CN117032591A

CN117032591A - Application method, device, computer equipment and storage medium of direct access channel

Info

Publication number: CN117032591A
Application number: CN202311289315.8A
Authority: CN
Inventors: 李树青; 王江; 孙华锦
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-10-08
Filing date: 2023-10-08
Publication date: 2023-11-10
Anticipated expiration: 2043-10-08
Also published as: CN117032591B

Abstract

The disclosure relates to the technical field of computer storage, and discloses an application method, a device, computer equipment and a storage medium of a direct access channel, wherein the method comprises the following steps: issuing a moving instruction to the direct memory access channel so as to move the data page list stored in the host into the external memory through the direct memory access channel; according to a read operation instruction executed on the hard disk, performing address conversion on a host data address and a host list address in a data page list in a host to obtain a converted new data page list, and writing the new data page list into an external memory; determining data to be read in the hard disk according to the read operation instruction; the hard disk obtains a new data page list from an external memory, and converts a system chip address corresponding to the data to be read in the new data page list into a host target address through a quick data path direct access channel in a high-speed serial computer expansion bus standard controller, and sends the data to be read to the host target address.

Description

Application method, device, computer equipment and storage medium of direct access channel

Technical Field

The present disclosure relates to the field of computer storage technologies, and in particular, to an application method and apparatus for a direct access channel, a computer device, and a storage medium.

Background

The bandwidth of external memory is often the bottleneck of a RAID (Redundant Arrays of Independent Disks, disk array) system. This is because the write operations of a RAID system can have a very significant write amplification effect on external storage. Taking the basic RAID5 system as an example, a write operation with a size of one block (the storage system is in units of blocks, and the typical size is 4 KB) issued by the host to the RAID system will cause 9 read and write operations to the external memory, which are respectively: reading host data to write to external memory (1 write); reading data corresponding to the position of the magnetic disk and writing the data into an external memory (1 time of writing); reading the redundant check data of the magnetic disk and writing the redundant check data into an external memory (1 write); reading host data, disk corresponding data and redundancy check data from an external memory to perform RAID calculation (3 reads); writing the new redundancy check calculation result into an external memory (1 write); reading host data from an external memory and writing the host data into a disk (1 reading); new redundancy check data is read from the external memory and written to the disk (1 read).

In a conventional RAID system, the read operation is divided into two steps as shown in fig. 1, in which control flow 1: first, a DMA (Direct Memory Access ) engine of a hard disk (typically found in NVMe (Non Volatile Memory Express, nonvolatile memory host controller interface specification) hard disk) or a DMA engine in a hard disk controller (typically found in SATA (Serial ATA) hard disk) writes hard disk data to an external memory; then, control flow 2 in the figure: and the DMA engine of the PCIE controller in the RAID chip reads the data from the external memory and writes the data into the memory space of the host. Therefore, it can be known that, the data entering and exiting the external memory is essentially only due to the fact that the storage space of the RAID chip accessible by the hard disk and the host address space accessible by the RAID chip belong to two address domains, and the external memory is required to realize the bridging function in the data cross-address domain transmission, but with the rapid development of PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) technology, the bandwidth of the host interface is continuously improved, and the external memory cannot provide the bandwidth required by the matching host interface, which becomes a bottleneck of the whole RAID system.

Therefore, how to improve the read-write operation performance of the RAID system, so that the RAID system is not dependent on the bridging function of the external memory, becomes the current urgent problem to be solved.

Disclosure of Invention

In view of this, the disclosure provides an application method, an apparatus, a computer device and a storage medium for a direct access channel, so as to solve the problem that when the related art realizes a read operation, the related art needs to rely on a bridging function of an external memory, but the external memory cannot provide a bandwidth required by matching a host interface, so that the read-write operation performance of a RAID system is often affected.

In a first aspect, the present disclosure provides a method for applying a direct access channel, where the method is applied to a disk array system, and the method includes:

issuing a moving instruction to the direct memory access channel so as to move the data page list stored in the host into the external memory through the direct memory access channel;

according to a read operation instruction executed on the hard disk, performing address conversion on a host data address and a host list address in a data page list in a host to obtain a system chip address of a converted new data page list, and writing the new data page list into an external memory;

Determining data to be read in the hard disk according to the read operation instruction;

the method comprises the steps of obtaining a new data page list from an external memory by using a hard disk, converting a system chip address corresponding to data to be read in the new data page list into a host target address by a direct access channel in a high-speed serial computer expansion bus standard controller, and sending the data to be read to the host target address of a host, wherein the host target address comprises: host data addresses and host list addresses.

In the embodiment of the disclosure, a direct memory access channel is utilized to move a data page list stored in a host into an external memory, address conversion is performed on a host data address and a host list address of the data page list in the host according to a read operation command to a hard disk, a new data page list is obtained, the new data page list is written into the external memory, then the hard disk obtains the new data page list from the external memory, the direct memory access channel in a high-speed serial computer expansion bus standard controller is utilized to convert data to be read in the hard disk from a system chip address into a host target address, and then the data to be read is sent to the host target address, so that when the host sends a read request to the disk array system, the data to be read in the hard disk is directly transmitted to the host target address of the host without entering and exiting the external memory, the burden of the read operation on the external memory is reduced, the write operation performance of the disk array system is improved, the read operation bandwidth and the write operation bandwidth of the disk array system are not dependent on the bandwidth of the external memory, the read operation bandwidth is not affected, the overall performance of the system is further improved, and the time delay caused by the data entering and exiting the external memory is reduced, and the data is particularly delayed.

In an alternative embodiment, performing address translation on a host data address and a host list address in a data page list in a host to obtain a translated new data page list includes:

executing a first conversion rule on a host data address in a data page list in the host to obtain a system chip address in a new data page list after conversion;

storing the address pointing to the next list position at the preset position of the host list address in the data page list in the host to obtain the target position corresponding to the head address of the next list page storing the system chip address list in the new data page list after conversion.

In the embodiment of the disclosure, address conversion of the host data address and the host list address is realized according to the data page list in the host, so that a direct access channel is convenient to realize subsequently.

In an alternative embodiment, performing a first translation rule on host data addresses in a list of data pages in a host to obtain system chip addresses in a list of new data pages after translation, includes:

acquiring the offset between the existing host data address and the existing system chip address;

And processing the host data address according to the offset to obtain a system chip address, and completing address conversion of the host data address.

In the embodiment of the disclosure, the system chip address in the accurate new data page list is conveniently determined according to the offset between the existing host data address and the existing system chip address.

In an alternative embodiment, storing an address pointing to a next list location at a preset location of a host list address in a data page list in the host, to obtain a target location corresponding to a first address of a next list page storing a system chip address list in a new data page list after conversion, includes:

determining a next list page according to the pointer pointing relationship between the preset position of the host list address and the address of the next list position;

and in the converted new data page list, the next list page is pointed to the target position of the head address of the next list page in the system chip address list memory, and the address conversion of the host list address is completed.

Executing a first conversion rule on a host data address in a data page list in the host to obtain a system chip address in a new data page list after conversion, wherein the system chip address comprises:

Acquiring a mapping phase difference table entry between an existing host data address and an existing system chip address;

and processing the host data address according to the mapping phase difference table entry to obtain a system chip address, and completing address conversion of the host data address.

In the embodiment of the disclosure, the system chip address in the accurate new data page list is conveniently determined according to the mapping phase difference table entry quantity between the existing host data address and the existing system chip address.

In an alternative embodiment, before issuing the move instruction to the direct memory access channel, the method further includes:

storing a pointer to a next list page in a last space of each list page in the case where there is a concatenation of a plurality of consecutive list pages in a list of data pages in the host;

and connecting a plurality of continuous list pages according to the pointers to obtain a data page list.

In the disclosed embodiment, when there is a concatenation of multiple consecutive list pages in a list of data pages in a host, a pointer to the next list page needs to be stored in the last space of each list page to generate a list of data pages of consecutive list pages.

Storing a pointer to a next list page in a last space of each list page in the case where there is a concatenation of a plurality of discrete list pages in a list of data pages in the host;

and connecting a plurality of discontinuous list pages according to the pointers to obtain a data page list.

In the disclosed embodiment, when there is a concatenation of multiple discrete list pages in the list of data pages in the host, a pointer to the next list page is also stored in the last space of each list page to generate a list of data pages of the discrete list pages.

and under the condition that one list page exists in the data page list in the host, storing corresponding data pointers in a plurality of spaces of the data page list in the host respectively to obtain the data page list.

In the embodiment of the disclosure, when only one list page exists in the data page list in the host, the data page list is generated according to the data pointers stored in the plurality of spaces.

In an alternative embodiment, converting, by a direct access channel in a high-speed serial computer expansion bus standard controller, a system chip address corresponding to data to be read in a new data page list to a host target address includes:

And processing the system chip address according to the offset by expanding a direct access channel in the bus standard controller by the high-speed serial computer to obtain a host target address.

In an alternative embodiment, processing the system chip address according to the offset to obtain the host target address includes:

determining a first mode of processing the system chip address by the offset according to a reverse rule of processing the host data address by the offset;

and obtaining the target address of the host according to the first mode.

In the embodiment of the disclosure, the host target address can be obtained by processing the host data address with the reverse rule of the offset, so that the offset is counteracted to obtain the accurate host target address.

and (3) expanding a direct access channel in the bus standard controller through the high-speed serial computer, and processing the system chip address according to the mapping phase difference table entry to obtain the host target address.

In an alternative embodiment, processing the system chip address according to the mapping phase difference table entry to obtain the host target address includes:

determining a second mode of processing the system chip address by the mapping phase difference table item according to the reverse rule of processing the host data address by the mapping phase difference table item;

and obtaining the target address of the host according to the second mode.

In the embodiment of the disclosure, the host target address can be obtained by using the reverse rule that the mapping phase difference table entry processes the host data address, so that the accurate host target address is obtained by counteracting the mapping phase difference table entry.

In an alternative embodiment, performing address conversion on a host data address in a data page list in a host and a host list address to obtain a system chip address of a new data page list after conversion, including:

reading a data page list in the host from the external memory, and remapping and arranging the data page list in the host according to the positions of the data pointers of the hard disk in all areas in the data page list in the host, so that the data page list in the host required by the hard disk is continuously stored in the external memory;

and obtaining a remapped data page list, and performing address conversion on the host data address and the host list address in the remapped data page list to obtain a converted new data page list and a system chip address of the new data page list.

In the embodiment of the disclosure, when the positions of the data pointers of the hard disk in the respective areas of the data page list in the host are discontinuous, the data page list in the host needs to be remapped, and then a new converted data page list is obtained according to the remapped data page list, so that the data page list required by the hard disk is ensured to be continuously stored in the memory, and the system performance is improved.

In an alternative embodiment, remapping the list of data pages in the host according to the locations of the data pointers of the hard disk in respective areas of the list of data pages in the host, includes:

acquiring a system level of a disk array system, a data layout of the disk array system and data to be read according to the positions of the data pointers of the hard disk in each region in a data page list in a host;

and remapping and arranging a data page list in the host according to the system level of the disk array system, the data layout of the disk array system and the data to be read.

In an alternative embodiment, remapping and arranging the data page list in the host according to a system level of the disk array system, a data layout of the disk array system, and data to be read, includes:

Predicting a hard disk data page list according to the system level of the disk array system, the data layout of the disk array system and the data to be read;

allocating continuous storage space for the hard disk data page list;

and reading the data page list in the host according to a preset sequence, storing the list item with the read label as the target label in the corresponding position with the label as the target label in the hard disk data page list, and remapping and arranging the data page list in the host.

In the embodiment of the disclosure, the data page lists in the host are respectively placed in the corresponding continuous storage space hard disk data page lists according to the reading sequence, so that the remapping arrangement of the data page lists in the host is completed, the continuous storage of the data page lists in the host required by the hard disk in the memory is ensured, and the system performance is improved.

In a second aspect, the present disclosure provides a disk array system including a direct access channel, the disk array system comprising: the system comprises a disk array chip, an external memory, a hard disk and a host, wherein the disk array chip comprises a high-speed serial computer expansion bus standard controller, a memory controller, a hard disk controller and an address first conversion module, and a direct access channel and a direct memory access channel are arranged in the high-speed serial computer expansion bus standard controller;

Under the condition that the direct memory access channel receives a moving instruction, the direct memory access channel is utilized to move the data page list stored in the host into the external memory;

under the condition that a hard disk receives a read operation instruction, an address first conversion module reads a data page list in a host from an external memory according to the read operation instruction, and performs address conversion on a host data address and a host list address in the data page list in the host to obtain a system chip address of a new data page list after conversion, and writes the new data page list into the external memory;

the method comprises the steps of obtaining a new data page list from an external memory by using a hard disk or a hard disk controller, converting a system chip address corresponding to data to be read in the new data page list into a host target address by a direct access channel in a high-speed serial computer expansion bus standard controller, and sending the data to be read to the host target address of the host, wherein the host target address comprises: host data addresses and host list addresses.

In an alternative embodiment, the disk array system further comprises: an on-chip interconnect module;

the on-chip interconnection module is used for communicating the high-speed serial computer expansion bus standard controller, the storage controller, the hard disk controller, the address first conversion module, the external memory, the hard disk and the data page list module to complete communication, wherein the data page list module is an independent module formed by independently extracting a data page list in a host through a direct memory access channel.

In a third aspect, the present disclosure provides an application apparatus for a fast data path, the apparatus being a disk array system, the apparatus comprising:

the first sending module is used for sending a moving instruction to the direct memory access channel so as to move the data page list stored in the host into the external memory through the direct memory access channel;

the first conversion module is used for carrying out address conversion on a host data address and a host list address in a data page list in a host according to a read operation instruction executed on the hard disk, obtaining a system chip address of a new data page list after conversion, and writing the new data page list into an external memory;

the determining module is used for determining data to be read in the hard disk according to the reading operation instruction;

The second sending module is configured to obtain a new data page list from the external memory by using the hard disk, convert a system chip address corresponding to the data to be read in the new data page list into a host target address through a direct access channel in the high-speed serial computer expansion bus standard controller, and send the data to be read to the host target address of the host, where the host target address includes: host data addresses and host list addresses.

In a fourth aspect, the present disclosure provides a computer device comprising: the external memory is in communication connection with the processor, the external memory stores computer instructions, and the processor executes the computer instructions, thereby executing the application method of the direct access channel according to the first aspect or any implementation manner corresponding to the first aspect.

In a fifth aspect, the present disclosure provides a computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the method of applying a direct access channel of the first aspect or any of its corresponding embodiments.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the prior art, the drawings that are required in the detailed description or the prior art will be briefly described, it will be apparent that the drawings in the following description are some embodiments of the present disclosure, and other drawings may be obtained according to the drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a control flow diagram of a conventional disk array system performing a read operation;

FIG. 2 is a flow diagram of a method of direct access channel application according to some embodiments of the present disclosure;

FIG. 3 is a control flow and data flow diagram of a disk array system provided with a direct access channel performing a read operation according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of address translation rules of an address translation module according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of address translation of a direct access channel according to some embodiments of the present disclosure;

FIG. 6 is a diagram of data page list generation according to some embodiments of the present disclosure;

FIG. 7 is a schematic diagram of a host access data overlay hard disk stripe according to some embodiments of the present disclosure;

FIG. 8 is a diagram of remapping a host data page list to a hard disk data page list, according to some embodiments of the present disclosure;

FIG. 9 is a block diagram of an application device for direct access channels according to some embodiments of the present disclosure;

fig. 10 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present disclosure.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

In a traditional RAID system, an external memory is required to realize bridging function in data cross-address-domain transmission during read operation, but with rapid development of PCIE technology, host interface bandwidth is continuously improved, and the external memory often cannot provide bandwidth required by matching with a host interface, which becomes a bottleneck of the whole RAID system. In order to improve the read-write operation performance of the system, the bridging function of the system which is not dependent on an external memory is a problem which needs to be solved currently.

In order to solve the above-described problems, according to an embodiment of the present disclosure, there is provided an application method embodiment of a direct access channel, it should be noted that the steps illustrated in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order different from that herein.

In this embodiment, an application method of a direct access channel is provided, fig. 2 is a flowchart of an application method of a direct access channel according to an embodiment of the disclosure, and as shown in fig. 2, the method is applied to a disk array system, i.e. a RAID system, and includes the following steps:

Step S201, a moving instruction is issued to a direct memory access channel so as to move a data page list stored in a host into an external memory by utilizing the direct memory access channel;

step S202, according to a read operation instruction executed on a hard disk, performing address conversion on a host data address and a host list address in a data page list in a host to obtain a system chip address of a new data page list after conversion, and writing the new data page list into an external memory;

step S203, determining data to be read in the hard disk according to the read operation instruction;

step S204, a new data page list is obtained from an external memory by using a hard disk, a system chip address corresponding to the data to be read in the new data page list is converted into a host target address by a direct access channel in a high-speed serial computer expansion bus standard controller, and the data to be read is sent to the host target address of the host, wherein the host target address comprises: host data addresses and host list addresses.

Optionally, as shown in fig. 3, the disk array system includes: the system comprises a disk array chip, an external memory, a hard disk and a host, wherein the disk array chip comprises a high-speed serial computer expansion bus standard controller, a memory controller, a hard disk controller and an address first conversion module, and a direct access channel and a direct memory access channel are arranged in the high-speed serial computer expansion bus standard controller; in addition, the host is connected with the disk array chip.

As can be seen in FIG. 3, embodiments of the present disclosure devise a "fast data path" in a RAID system for bypassing external memory bridging when a host initiates a read access, directly to the host.

As can be seen from fig. 3, a "direct access channel" is added to the PCIe controller of the RAID chip, and the direct access channel has two key functions:

1. a "slave" interface is provided which refers to an interface for receiving and responding to write requests and write data sent by the "master" interface, or receiving read requests sent by the "master" interface and returning read data to the "master" interface.

2. The direct access channel may support address translation, which means that when a read-write request from the host interface is received, the requested address may be translated into a PCIe bus domain address (i.e., a host target address) according to rules, then a write request and write data are sent to the host through PCIe, or a read request is sent, and data returned by the host is returned to the host interface.

The specific flow of fig. 3 is: control flow 1: when the host initiates a read access, a move instruction is issued to the direct memory access channel (i.e., the DMA channel in fig. 3) (the DMA channel may also be configured by the data page list acquisition module in fig. 3), and control flow 2 is executed: so that the list of data pages stored in the host (i.e., the host data page list) is moved to the external memory using the direct memory access channel.

According to the read operation instruction executed on the hard disk, control flow 3 is executed: the address first conversion module reads the data page list from the external memory, performs address conversion on the host data address and the host list address in the data page list to obtain a converted new data page list, and writes the new data page list into the external memory;

executing control flow 4: the hard disk or the hard disk controller obtains a new data page list from the external memory and executes the data stream 5: the hard disk sends data to be read according to the address appointed by the data page list, the data to be read finally hits the direct access channel, the system chip address corresponding to the data to be read in the new data page list is converted into a host target address (namely a host real address) through the direct access channel, and the data to be read is sent to the host target address of the host.

After all the control flows are executed, the data flow that the hard disk sends data to the designated position of the host computer according to the address designated by the data page list is completed.

In the embodiment of the disclosure, a direct memory access channel is utilized to move a data page list stored in a host into an external memory, address conversion is performed on a host data address and a host list address of the data page list in the host according to a read operation command to a hard disk, a new data page list is obtained, the new data page list is written into the external memory, then the hard disk obtains the new data page list from the external memory, a quick data path direct access channel in a bus standard controller is expanded by a high-speed serial computer, data to be read in the hard disk is converted from a system chip address into a host target address, and then the data to be read is sent to the host target address, so that when the host issues a read request to the disk array system, the data to be read in the hard disk is directly transmitted to the host target address of the host without entering and exiting the external memory, the load of the read operation to the external memory is reduced, the write operation performance of the disk array system is improved, the read operation bandwidth and the write operation bandwidth of the disk array system are not dependent on the bandwidth of the external memory, the read operation bandwidth and the read operation bandwidth of the disk array system is not affected each other, and the overall performance of the system is further improved, and the read operation bandwidth is reduced, and the read operation is delayed in a large block of the data entering and exiting the external memory is particularly advantageous.

In some alternative embodiments, address translation is performed on a host data address and a host list address in a data page list in a host, to obtain a translated new data page list, including:

Optionally, since the data page list is recorded with the host data address and the host list address, at this time, a first conversion rule is executed on the host data address in the data page list in the host to obtain a system chip address (i.e., SOC address) corresponding to the new data page list after conversion, and then an address pointing to the next list position is stored at a preset position (usually the last space of the current list page) of the host list address in the data page list, see host list address 0 filled in the last space of the original data page list shown in fig. 4, and the list page 1 is pointed to according to the list pointer, where the list page 1 is the next list.

For the new data page list after address conversion, the first address of the next page list (i.e., list page 1) of the system chip address list is deposited at the target location of list page 0 (which is also the last space of the new data page list).

The dashed arrows in fig. 3 represent pointing relationships, and the solid arrows represent data content sources.

In the embodiment of the disclosure, address conversion of the host data address and the host list address is realized according to the data page list, so that a fast data path direct access channel is conveniently realized subsequently.

In some alternative embodiments, performing a first translation rule on host data addresses in a list of data pages in a host resulting in system chip addresses in a list of new data pages that correspond to the translation, includes:

Alternatively, the offset may be determined by determining an existing host data address and an existing system chip address, that is, a difference between the existing host data address and the existing system chip address, that is, the offset.

The SOC address is then obtained by way of a source address (i.e., address before translation, i.e., host data address) -offset. I.e. destination address (i.e. SOC address after conversion) =source address (host data address) -offset.

In some alternative embodiments, processing the system chip address according to the offset to obtain the host target address includes:

and obtaining the target address of the host according to the first mode.

Alternatively, as shown in fig. 5, the conversion from the SOC address to the host target address (corresponding to the host address space of fig. 5) is performed by a direct conversion channel, which obtains the host target address according to the offset and then adopts the reverse rule of the address conversion mode.

Such as host destination address = source address (i.e., SOC address) +offset.

In some alternative embodiments, performing a first translation rule on host data addresses within a list of data pages to obtain system chip addresses within a list of new data pages corresponding to the translation, includes:

Alternatively, mapping table implementations may be used when the conversion rules are complex or the addresses are discontinuous. Because the mapping table is recorded with some entries, the host data address is processed according to the mapping phase difference table entry between the existing host data address and the existing system chip address to obtain the system chip address, where the mapping phase difference table entry is actually the offset in the above embodiment. The address conversion mode is consistent with the foregoing embodiment, and the offset is only required to be mapped to the phase difference table entry, which is not described again.

In some alternative embodiments, processing the system chip address according to the mapping phase difference table entry to obtain the host target address includes:

and obtaining the target address of the host according to the second mode.

Alternatively, as shown in fig. 5, the conversion from the SOC address to the host target address (corresponding to the host address space of fig. 5) is performed by a direct conversion channel, and the host target address is obtained by adopting a conversion mode reverse rule according to the offset address.

The mapped phase difference table entry here is actually the offset in the above embodiment. The address conversion mode is consistent with the foregoing embodiment, and the offset is only required to be mapped to the phase difference table entry, which is not described again.

In some alternative embodiments, before issuing the move instruction to the direct memory access channel, the method further comprises:

Alternatively, as shown in fig. 3, the embodiment of the present disclosure extracts the data page list acquisition module from the DMA engine of the conventional method as a separate module. The data page list refers to a list for placing a plurality of data page pointers. Since the host memory is typically managed page by page, each page is a continuous block of memory space, and when a larger space is required, a plurality of data pages are required, and the data pages are not address-continuous, the above-mentioned data page list is required for storing pointers (typically, first addresses) of each data page. It should be noted that, in general, the data page list is also managed by pages, so if too many data pages are needed, a problem occurs that one data page list page cannot be stored.

At this time, the embodiment of the present disclosure uses a pointer to cascade a plurality of consecutive list pages, so that the number of list pages is not limited. As shown in fig. 6, the last space of each list page stores a pointer to the next list page, so that a plurality of consecutive list pages can be connected to obtain a list of data pages.

Alternatively, when there are a cascade of a plurality of discontinuous list pages in the list of data pages in the host, the discontinuous list pages may be connected by pointing a pointer, and then a pointer pointing to the next list page is stored in the last space of each list page, so that a list of stored continuous data pages can be obtained even if there are a plurality of discontinuous list pages.

Optionally, when a list page exists in the data page list in the host, no paging condition exists at present, and then only the corresponding data pointers are stored in each space of the list page, and each data pointer is pointed to the data page item of the data page, so that the data page list can be obtained.

In the embodiment of the disclosure, when only one list page exists in the data page list, the data page list is generated according to the data pointers stored in the plurality of spaces.

In some alternative embodiments, performing address conversion on a host data address in a data page list in a host and a host list address to obtain a system chip address of a new data page list after conversion, including:

And obtaining the remapped data page list, and performing address conversion on the host data address and the host list address in the remapped data page list to obtain a new data page list after conversion and a system chip address of the new data page list.

Optionally, in order to avoid repeated access to the external memory, when the address remapping is required, the remapping and the address first conversion module may be combined into one, and then the remapped and arranged data page list needs to be obtained, and address conversion is performed on the host data address and the host list address in the remapped and arranged data page list, so as to obtain a converted new data page list.

After the list of data pages in the host is read from the external memory, if the data involved in the host's access to the RAID's system is present, as shown in FIG. 7, it may result in the list of hosts needing to be reordered when the 2 stripes of the hard disk are covered. Wherein the data pointers referred to by the hard disk 1 are located in the host list area 1 and area 4, respectively, and are not contiguous in the host list. When issuing a read/write command to the hard disk 1, the list of data pages within the host that is required for the hard disk must be stored continuously (the list pages are also considered to be continuous across) in the external memory of the RAID chip, and thus the list of data pages within the host needs to be reordered.

And then acquiring a data page list after remapping arrangement, and performing address conversion on the host data address and the host list address in the data page list after remapping arrangement to obtain a new data page list after conversion.

In the embodiment of the disclosure, when the positions of the data pointers of the hard disk in the areas in the data page list are discontinuous, the data page list in the host needs to be remapped, and then a new converted data page list is obtained according to the remapped data page list, so that the data page list in the host required by the hard disk is ensured to be continuously stored in the memory, and the system performance is improved.

In some alternative embodiments, remapping the list of data pages within the host according to the locations of the data pointers of the hard disk in respective regions within the list of data pages within the host, includes:

Optionally, remapping refers to reordering the host's list of data pages to generate a list of data pages that fit into the hard disk. And at this time, according to the positions of the data pointers of the hard disk in each region in the data page list, if the data pointers of the hard disk are positioned in the discontinuous regions of the data page list of the host, acquiring the system level of the disk array system, the data layout of the disk array system and the data to be read.

The list of data pages is then remapped based on the system level of the disk array system (e.g., RAID 5/6), the data layout of the disk array system (e.g., left/right handed and aligned/unaligned), and the data to be read.

In some alternative embodiments, remapping the list of data pages in the host according to a system level of the disk array system, a data layout of the disk array system, and data to be read, includes:

allocating continuous storage space for the hard disk data page list;

Optionally, the length of the data page list of each hard disk is calculated in advance according to the data layout of the RAID which is currently used, the system level of the disk array system and the starting position of the data to be read related to the current read command, so as to obtain a hard disk data page list. Each hard disk data page list is then allocated contiguous memory space in the RAID chip local memory space, such as the "hard disk data page list" in fig. 8. And then reading the data page list of the host according to a preset sequence, such as a sequence from front to back, and placing the data page list in a corresponding chip local storage space, such as placing a list item with a target number of 1 in the data page list of the host in a position with a target number of 1 in the data page list of the hard disk, so as to remap and arrange the data page list in the host.

In the embodiment of the disclosure, the data page lists in the host are respectively placed in the corresponding continuous storage space hard disk data page lists according to the reading sequence, so that the remapping arrangement of the data page lists in the host is completed, the continuous storage of the data page lists required by the hard disk in the memory is ensured, and the system performance is improved.

In this embodiment, there is also provided a disk array system of a direct access channel, the disk array system including: the system comprises a disk array chip, an external memory, a hard disk and a host, wherein the disk array chip comprises a high-speed serial computer expansion bus standard controller, a memory controller, a hard disk controller and an address first conversion module, and a fast data path direct access channel and a direct memory access channel are arranged in the high-speed serial computer expansion bus standard controller;

the method comprises the steps of obtaining a new data page list from an external memory by using a hard disk or a hard disk controller, converting a system chip address corresponding to data to be read in the new data page list into a host target address by a fast data path direct access channel in a high-speed serial computer expansion bus standard controller, and sending the data to be read to the host target address of the host, wherein the host target address comprises: host data addresses and host list addresses.

Optionally, in the embodiment of the present disclosure, a disk array system including a direct access channel is disclosed, and referring to the schematic diagram shown in fig. 3, a specific communication process of a control flow and a data flow has been described in the foregoing embodiment, which is not described herein.

In some alternative embodiments, the disk array system further comprises: an on-chip interconnect module;

Optionally, as shown in fig. 3, the RAID chip further includes an on-chip interconnection module for connecting and communicating with each hardware, as shown in fig. 3, where the on-chip interconnection module is configured to connect to the hardware, such as the high-speed serial computer expansion bus standard controller, the storage controller, the hard disk controller, the address first conversion module, the external memory, the hard disk, and the data page list module, to complete communication between the hardware.

It should be noted that, in fig. 3, the data page list module included in the RAID chip is an independent module formed by extracting the data page list in the host separately by using the direct memory access channel, which may be shown in fig. 3, or may be omitted, and the meaning of moving the data page list is completed by moving the data page list stored in the host to the external memory by using the direct memory access channel.

The embodiment also provides an application device of the direct access channel, which is used for implementing the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present embodiment provides an application apparatus for a direct access channel, as shown in fig. 9, including:

the first sending module 901 is configured to send a move instruction to the direct memory access channel, so that a data page list stored in the host is moved to the external memory through the direct memory access channel;

a first conversion module 902, configured to perform address conversion on a host data address and a host list address in a data page list in a host according to a read operation instruction executed on a hard disk, obtain a system chip address of a new data page list after conversion, and write the new data page list into an external memory;

a determining module 903, configured to determine data to be read in the hard disk according to the read operation instruction;

The second sending module 904 is configured to obtain a new data page list from the external memory by using the hard disk, convert, through a direct access channel in the high-speed serial computer expansion bus standard controller, a system chip address corresponding to data to be read in the new data page list into a host target address, and send the data to be read to the host target address of the host, where the host target address includes: host data addresses and host list addresses.

In some alternative embodiments, the first conversion module 902 includes:

a first obtaining unit, configured to execute a first conversion rule on a host data address in a data page list in a host, to obtain a system chip address in a new data page list after conversion;

and the second obtaining unit is used for storing the address pointing to the next list position at the preset position of the host list address in the data page list in the host to obtain the target position corresponding to the head address of the next list page storing the system chip address list in the converted new data page list.

In some alternative embodiments, the first deriving unit comprises:

the first acquisition sub-module is used for acquiring the offset between the existing host data address and the existing system chip address;

The first obtaining submodule is used for processing the host data address according to the offset to obtain a system chip address and complete address conversion of the host data address.

In some alternative embodiments, the second deriving unit comprises:

the first determining submodule is used for determining a next list page according to the pointer pointing relation between the preset position of the host list address and the address of the next list position;

and the storage sub-module is used for pointing the next list page to the target position of the head address of the next list page in the system chip address list memory in the converted new data page list, and finishing the address conversion of the host list address.

In some alternative embodiments, the first deriving unit comprises:

the second acquisition sub-module is used for acquiring a mapping phase difference table entry between the existing host data address and the existing system chip address;

and the second obtaining submodule is used for processing the host data address according to the mapping phase difference table entry to obtain a system chip address and complete address conversion of the host data address.

In some alternative embodiments, the apparatus further comprises:

the first storage module is used for storing a pointer pointing to the next list page in the last space of each list page under the condition that a cascade of a plurality of continuous list pages exists in a data page list in the host before issuing a moving instruction to the direct memory access channel;

The first obtaining module is used for connecting a plurality of continuous list pages according to the pointers to obtain a data page list.

In some alternative embodiments, the apparatus further comprises:

the second storage module is used for storing a pointer pointing to the next list page in the last space of each list page under the condition that a plurality of discontinuous list pages are cascaded in a data page list in the host before issuing a moving instruction to the direct memory access channel;

and the second obtaining module is used for connecting a plurality of discontinuous list pages according to the pointers to obtain a data page list.

In some alternative embodiments, the apparatus further comprises:

and the third storage module is used for respectively storing corresponding data pointers in a plurality of spaces of the data page list in the host under the condition that one list page exists in the data page list in the host before issuing a moving instruction to the direct memory access channel, so as to obtain the data page list.

In some alternative embodiments, the second transmitting module 904 includes:

and the third obtaining unit is used for processing the system chip address according to the offset by the direct access channel in the high-speed serial computer expansion bus standard controller to obtain the host target address.

In some alternative embodiments, the third deriving unit comprises:

the second determining submodule is used for determining a first mode of processing the system chip address by the offset according to a reverse rule of processing the host data address by the offset;

and a third obtaining sub-module, configured to obtain the target address of the host according to the first mode.

In some alternative embodiments, the second transmitting module 904 includes:

and the fourth obtaining unit is used for processing the system chip address according to the mapping phase difference table entry through a direct access channel in the high-speed serial computer expansion bus standard controller to obtain the host target address.

In some alternative embodiments, the fourth deriving unit comprises:

the third determining submodule is used for determining a second mode of processing the system chip address by the mapping phase difference table item according to the reverse rule of processing the host data address by the mapping phase difference table item;

and fourth obtaining a sub-module for obtaining the target address of the host according to the second mode.

In some alternative embodiments, the first conversion module 902 includes:

the remapping arrangement unit is used for reading the data page list in the host from the external memory, and remapping and arranging the data page list in the host according to the positions of the data pointers of the hard disk in all areas in the data page list in the host, so that the data page list in the host required by the hard disk is continuously stored in the external memory;

The address conversion unit is used for acquiring the remapped data page list, and performing address conversion on the host data address and the host list address in the remapped data page list to obtain a new data page list after conversion and a system chip address of the new data page list. In some alternative embodiments, the remapping arrangement unit includes:

the third acquisition sub-module is used for acquiring the system level of the disk array system, the data layout of the disk array system and the data to be read according to the positions of the data pointers of the hard disk in each region in the data page list in the host;

and the remapping arrangement sub-module is used for remapping and arranging the data page list in the host according to the system level of the disk array system, the data layout of the disk array system and the data to be read.

In some alternative embodiments, the remapping arrangement submodule includes:

the predicting subunit is used for predicting a hard disk data page list according to the system level of the disk array system, the data layout of the disk array system and the data to be read;

an allocation subunit, configured to allocate a continuous storage space for the hard disk data page list;

And the storage subunit is used for reading the data page list in the host according to a preset sequence, storing the list item with the read label as the target label in the corresponding position with the label as the target label in the hard disk data page list, and remapping and arranging the data page list in the host.

The application means of the direct access channel in this embodiment are presented in the form of functional units, where the units refer to ASIC circuits, processors and external memories executing one or more software or fixed programs, and/or other devices that can provide the above described functionality.

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The embodiment of the disclosure also provides a computer device, which is provided with the application device of the direct access channel shown in the figure 9.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a computer device according to an alternative embodiment of the disclosure, as shown in fig. 10, the computer device includes: one or more processors 10, an external memory 20, and interfaces for connecting the components, including a high-speed interface and a low-speed interface. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on an external memory to display graphical information of the GUI on an external input/output apparatus, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple external memories and multiple external memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 10.

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the external memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown to implement the above embodiments.

The external memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created from the use of the computer device of the presentation of a sort of applet landing page, and the like. In addition, the external memory 20 may include high-speed random access external memory, and may also include non-transitory external memory, such as at least one disk external memory device, flash memory device, or other non-transitory solid-state external memory device. In some alternative embodiments, external memory 20 may optionally include external memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The external memory 20 may include a volatile external memory, such as a random access external memory; the external memory may also include a nonvolatile external memory, such as a flash external memory, a hard disk, or a solid state disk; the external memory 20 may also comprise a combination of external memories of the kind described above.

The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

The presently disclosed embodiments also provide a computer readable storage medium, and the methods described above according to the presently disclosed embodiments may be implemented in hardware, firmware, or as recordable storage medium, or as computer code downloaded over a network that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and is to be stored in a local storage medium, such that the methods described herein may be stored on such software processes on a storage medium using a general purpose computer, special purpose processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, a compact disk, a read-only memory, a random access memory, a flash external memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of external memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although embodiments of the present disclosure have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the disclosure, and such modifications and variations are within the scope defined by the appended claims.

Claims

1. A method for applying a direct access channel, the method being applied to a disk array system, the method comprising:

issuing a moving instruction to a direct memory access channel so as to move a data page list stored in a host into an external memory through the direct memory access channel;

according to a read operation instruction executed on a hard disk, performing address conversion on a host data address and a host list address in a data page list in a host to obtain a system chip address of a new data page list after conversion, and writing the new data page list into the external memory;

the method comprises the steps of obtaining a new data page list from an external memory by using the hard disk, converting the system chip address corresponding to the data to be read in the new data page list into a host target address by a direct access channel in a high-speed serial computer expansion bus standard controller, and sending the data to be read to the host target address of the host, wherein the host target address comprises: the host data address and the host list address.

2. The method of claim 1, wherein performing address translation on the host data address and the host list address in the data page list in the host to obtain the translated new data page list comprises:

executing a first conversion rule on the host data address in a data page list in the host to obtain a system chip address in a new data page list after conversion;

storing an address pointing to the next list position at a preset position of the host list address in a data page list in the host to obtain a target position corresponding to the head address of the next list page storing the system chip address list in the converted new data page list.

3. The method of claim 2, wherein performing a first translation rule on the host data addresses in the list of data pages in the host results in system chip addresses in the list of new data pages that correspond to the translations, comprising:

and processing the host data address according to the offset to obtain the system chip address, and finishing address conversion of the host data address.

4. The method according to claim 2, wherein storing the address pointing to the next list location at the preset location of the host list address in the data page list in the host, and obtaining the target location corresponding to the first address of the next list page storing the system chip address list in the converted new data page list, includes:

and in the converted new data page list, the next list page is pointed to a target position in a system chip address list, in which the head address of the next list page is stored, so that the address conversion of the host list address is completed.

5. The method of claim 2, wherein performing a first translation rule on the host data addresses in the list of data pages in the host results in system chip addresses in the list of new data pages that correspond to the translations, comprising:

and processing the host data address according to the mapping phase difference table entry to obtain the system chip address, and finishing address conversion of the host data address.

6. The method of claim 1, wherein prior to issuing the move instruction to the direct memory access channel, the method further comprises:

and connecting a plurality of continuous list pages according to the pointer to obtain the data page list.

7. The method of claim 1, wherein prior to issuing the move instruction to the direct memory access channel, the method further comprises:

and connecting a plurality of discontinuous list pages according to the pointer to obtain the data page list.

8. The method of claim 1, wherein prior to issuing the move instruction to the direct memory access channel, the method further comprises:

9. The method of claim 3, wherein said translating the system chip address corresponding to the data to be read in the new data page list to a host target address via a direct access channel in a high speed serial computer expansion bus standard controller, comprises:

and processing the system chip address according to the offset by using a direct access channel in the high-speed serial computer expansion bus standard controller to obtain the host target address.

10. The method of claim 9, wherein said processing the system-on-chip address according to the offset to obtain the host target address comprises:

and obtaining the target address of the host according to the first mode.

11. The method of claim 5, wherein translating the system chip address corresponding to the data to be read in the new data page list to a host target address via a direct access channel in a high-speed serial computer expansion bus standard controller, comprises:

And processing the system chip address according to the mapping phase difference table entry by using a direct access channel in the high-speed serial computer expansion bus standard controller to obtain the host target address.

12. The method of claim 11, wherein said processing the system chip address according to the mapped phase difference table entry to obtain the host target address comprises:

determining a second mode of processing the system chip address by the mapping phase difference table entry according to a reverse rule of processing the host data address by the mapping phase difference table entry;

and obtaining the target address of the host according to the second mode.

13. The method of claim 1, wherein performing address translation on the host data address and the host list address in the data page list in the host to obtain a system chip address of the translated new data page list, comprises:

reading a data page list in a host from the external memory, and remapping and arranging the data page list in the host according to the positions of the data pointers of the hard disk in all areas in the data page list in the host, so that the data page list in the host required by the hard disk is continuously stored in the external memory;

And obtaining a remapped data page list, and performing address conversion on a host data address and a host list address in the remapped data page list to obtain a converted new data page list and a system chip address of the new data page list.

14. The method of claim 13, wherein remapping the list of data pages in the host based on the locations of the respective regions in the list of data pages in the host where the data pointers of the hard disk are located, comprises:

acquiring a system level of the disk array system, a data layout of the disk array system and the data to be read according to the positions of the data pointers of the hard disk in each region in a data page list in a host;

15. The method of claim 14, wherein remapping the list of data pages in the host according to the system level of the disk array system, the data layout of the disk array system, and the data to be read comprises:

allocating continuous storage space for the hard disk data page list;

16. A disk array system comprising direct access channels, the disk array system comprising: the system comprises a disk array chip, an external memory, a hard disk and a host, wherein the disk array chip comprises a high-speed serial computer expansion bus standard controller, a memory controller, a hard disk controller and an address first conversion module, and a direct access channel and a direct memory access channel are arranged in the high-speed serial computer expansion bus standard controller;

under the condition that the direct memory access channel receives a moving instruction, the direct memory access channel is utilized to move a data page list stored in a host into the external memory;

Under the condition that the hard disk receives a read operation instruction, according to the read operation instruction, the address first conversion module reads a data page list in a host from the external memory, performs address conversion on a host data address and a host list address in the data page list in the host, obtains a system chip address of a new data page list after conversion, and writes the new data page list into the external memory;

the hard disk or the hard disk controller is utilized to acquire the new data page list from the external memory, the system chip address corresponding to the data to be read in the new data page list is converted into a host target address through the direct access channel in the high-speed serial computer expansion bus standard controller, and the data to be read is sent to the host target address of a host, wherein the host target address comprises: the host data address and the host list address.

17. The disk array system of claim 16, wherein the disk array system further comprises: an on-chip interconnect module;

The on-chip interconnection module is used for communicating the high-speed serial computer expansion bus standard controller, the storage controller, the hard disk controller, the address first conversion module, the external memory, the hard disk and the data page list module, and completing communication, wherein the data page list module is an independent module formed by independently extracting a data page list in a host by a direct memory access channel.

18. An apparatus for direct access channel application, wherein the apparatus is a disk array system, the apparatus comprising:

the first conversion module is used for carrying out address conversion on a host data address and a host list address in a data page list in a host according to a read operation instruction executed on a hard disk, obtaining a system chip address of a new data page list after conversion, and writing the new data page list into the external memory;

The second sending module is configured to obtain the new data page list from the external memory by using the hard disk, convert, through a direct access channel in a high-speed serial computer expansion bus standard controller, the system chip address corresponding to the data to be read in the new data page list into a host target address, and send the data to be read to the host target address of the host, where the host target address includes: the host data address and the host list address.

19. A computer device, comprising:

an external memory and a processor, the external memory and the processor being communicatively connected to each other, the external memory having stored therein computer instructions, the processor executing the computer instructions to perform the method of applying a direct access channel according to any one of claims 1 to 15.

20. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the method of applying a direct access channel according to any one of claims 1 to 15.