CN117032166A

CN117032166A - System resetting method, device, equipment and storage medium

Info

Publication number: CN117032166A
Application number: CN202311013758.4A
Authority: CN
Inventors: 董沛君; 刘云波; 肖兆锋
Original assignee: Beijing Jizhijia Technology Co Ltd
Current assignee: Beijing Jizhijia Technology Co Ltd
Priority date: 2023-08-11
Filing date: 2023-08-11
Publication date: 2023-11-10

Abstract

The system resetting method provided by the embodiment of the application is applied to an emergency stop control system, and the emergency stop control system comprises a main control device and a plurality of controlled devices. After the emergency stop signal and the reset signal are generated, the main control equipment delays the reset signal according to a preset delay time length to obtain the delayed reset signal. Then, the main control equipment sends target scram signals to a plurality of controlled equipment, and the plurality of controlled equipment respectively performs scram control according to preset duration; and if the emergency stop signal meets the reset triggering condition, the main control equipment and the controlled equipment respond to the delayed reset signals to reset. According to the embodiment of the application, the reset signal is delayed, so that the control system can be reliably reset under the condition of maintaining the emergency stop control effect.

Description

System resetting method, device, equipment and storage medium

Technical Field

The embodiment of the application relates to the technical field of automatic control, in particular to a system resetting method, device, equipment and storage medium.

Background

Automated warehousing is an intelligent warehousing mode in which cargo handling and picking is performed by autonomous mobile robots (Autonomous Mobile Robot, AMR) (the present application is hereinafter simply referred to as "robots"). In a practical implementation scenario, hundreds or thousands of robots may be housed within a warehouse environment to collectively perform tasks. In order to maintain safety between the robots and to timely intervene in the expected states of the robots, in some cases, the robots may be controlled to enter an emergency stop (hereinafter referred to as emergency stop) state. Typically, the control system generates control signals in response to the triggering operation, and in turn, transmits the generated control signals to the robot end to control the behavior of the robot.

After the control system and the sudden stop function module at the robot end complete the sudden stop control once, the sudden stop should be relieved by resetting once, and then the next sudden stop control is executed. It can be seen that the control system and the scram function module at the robot end should trigger the scram operation preferentially and then reset. In some implementations, the control system generates the control signal including the scram signal and the reset signal in response to the triggering operation, and the time period during which a portion of the control system generates the scram signal and the time period during which a portion of the control system generates the reset signal have no longer time difference. In this way, the control system and the scram function module at the robot end cannot identify which operation control is executed preferentially, and there is a risk of failure in the scram control of the robot, so that the control effect on the robot is affected, and a certain potential safety hazard is generated.

In view of this, it is a study object in the art how to reliably reset the control system without affecting the sudden stop control effect of the robot.

Disclosure of Invention

The embodiment of the application provides a system resetting method, a device, equipment and a storage medium, which reserve time for a robot to execute scram by delaying a resetting signal, and can reliably reset a control system under the condition of maintaining the scram control effect. Specifically, the embodiment of the application discloses the following technical scheme:

in a first aspect, an embodiment of the present application provides a system reset method, which is applied to an emergency stop control system, where the emergency stop control system includes a master control device and a plurality of controlled devices, and the method includes:

after generating an emergency stop signal and a reset signal, the main control equipment delays the reset signal according to a preset delay time length to obtain a delayed reset signal;

the main control equipment sends target scram signals to the plurality of controlled equipment so that the plurality of controlled equipment can respectively carry out scram control according to preset duration, and the target scram signals are obtained according to the scram signals;

and if the signal value of the scram signal meets a reset triggering condition, the main control equipment and the controlled equipment respond to the delayed reset signals to reset.

With reference to the first aspect, in a possible implementation manner of the first aspect, the preset delay time is greater than or equal to 1 second.

With reference to the first aspect, in a possible implementation manner of the first aspect, for any one of the plurality of controlled devices, the performing emergency stop control according to a preset duration includes:

and the controlled equipment controls the effective execution time period of the target scram signal to reach the preset duration, wherein the preset duration is the sum of the duration of scram buffer delay and the duration of the controlled robot entering the scram state.

With reference to the first aspect, in a possible implementation manner of the first aspect, the controlled device makes the target scram signal execute effectively by controlling the target scram signal to maintain a low level state.

With reference to the first aspect, in a possible implementation manner of the first aspect, the emergency stop signal includes a first channel emergency stop signal and a second channel emergency stop signal, and a signal value of the emergency stop signal meets a reset triggering condition, including:

the first channel scram signal and the second channel scram signal are both high level signals.

With reference to the first aspect, in one possible implementation manner of the first aspect,

the emergency stop control system further comprises a plurality of signal generating devices connected in series, and the generation of the emergency stop signal and the reset signal comprises the following steps:

at least one of the plurality of signal generating devices responds to touch operation and generates a first initial scram signal, a second initial scram signal and an initial reset signal;

transmitting a first initial scram signal, a second initial scram signal and an initial reset signal to the main control equipment through three channels according to a serial sequence; the first channel scram signal includes a first initial scram signal generated by the at least one scram signal generating device, the second channel scram signal includes a second initial scram signal generated by the at least one scram signal generating device, and the reset signal includes an initial reset signal generated by the at least one scram signal generating device.

With reference to the first aspect, in a possible implementation manner of the first aspect, before performing delay processing on the reset signal according to a preset delay duration, the method further includes:

and determining that the rising edge or the falling edge of the first channel scram signal and the second channel scram signal are the same.

In a second aspect, an embodiment of the present application further provides a system reset device, which is applied to an emergency stop control system, where the emergency stop control system includes a master control device and a plurality of controlled devices, and the device includes:

the delay module is used for carrying out delay processing on the reset signal according to a preset delay time length after generating the emergency stop signal and the reset signal to obtain a delayed reset signal;

the sending module is used for sending target scram signals to the plurality of controlled devices so that the plurality of controlled devices can respectively carry out scram control according to preset duration, and the target scram signals are obtained according to the scram signals;

and the reset module is used for triggering the main control equipment and the controlled equipment to respond to the delayed reset signals for resetting if the signal value of the emergency stop signal meets a reset triggering condition.

In a third aspect, an embodiment of the present application provides an electronic device, including: a processor and a memory for storing computer executable instructions; a processor configured to read instructions from a memory and execute the instructions to implement the method of the first aspect and any implementation manner of the first aspect.

In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions for causing the computer to perform the method of the first aspect and any implementation manner of the first aspect.

In addition, an embodiment of the present application also provides a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the method in any implementation of the first aspect.

The system resetting method provided by the embodiment of the application is applied to an emergency stop control system, wherein the emergency stop control system comprises a main control device and a plurality of controlled devices. After the scram control system generates the scram signal and the reset signal, the main control equipment delays the reset signal according to a preset delay time length to obtain a delayed reset signal, and sends target scram signals to the controlled equipment, so that the controlled equipment performs scram control according to the preset duration time length respectively, and the target scram signals are obtained according to the scram signals. That is, in a scenario where the reset signal and the scram signal are generated at approximately the same time, the scram signal may be delayed and transmitted to the controlled device, so that a certain time interval is generated between the scram control and the reset, and thus the scram operation may be controlled to be performed first, and then the reset of the related device may be controlled. Further, the sending of the reset signal is controlled by the emergency stop signal, based on the emergency stop signal, if the emergency stop signal meets the reset triggering condition, the main control device and the plurality of controlled devices respond to the delayed reset signal to reset, so that after the emergency stop control is executed, relevant functional devices in the emergency stop control system can release the emergency stop state through reset to support the next emergency stop control. Therefore, in the embodiment of the application, under the condition that the emergency stop signal and the reset signal are almost generated at the same time, the control system can be reliably reset under the condition that the emergency stop control effect is maintained by delaying the reset signal.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an exemplary emergency stop control system according to an embodiment of the present application;

FIG. 2 is a method flow diagram of an exemplary system reset method provided by an embodiment of the present application;

fig. 3 is a schematic structural diagram of an exemplary programmable logic controller (Programmable Logic Controller, PLC) system according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an exemplary reset processing logic provided by an embodiment of the present application;

fig. 5 is a schematic structural diagram of a system reset device according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to better understand the technical solution in the embodiments of the present application and make the above objects, features and advantages of the embodiments of the present application more comprehensible, the technical solution in the embodiments of the present application is described in further detail below with reference to the accompanying drawings.

While exemplary implementations of embodiments of the present application are shown in the drawings, it should be understood that embodiments of the present application may be embodied in various forms and should not be limited to the implementations set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

It should be noted that unless otherwise indicated, technical or scientific terms used in the embodiments of the present application should be given the ordinary meanings as understood by those skilled in the art to which the embodiments of the present application belong.

The following describes an implementation scenario and related technology related to an embodiment of the present application.

The embodiment of the application relates to a robot scram control technology in an AMR scene, which can be applied to a scram control system.

As shown in fig. 1, the emergency stop control system according to the embodiment of the present application may include a master device and a plurality of controlled devices, where the master device is wirelessly connected to the plurality of controlled devices. The main control equipment is used for verifying, processing, detecting and the like signals generated by the control system, and further processing the signals meeting the conditions or responding to the triggering of the corresponding signals to operate. Each of the plurality of controlled devices controls a robot, and the plurality of controlled devices operates in response to signals from the master device. In some implementations, the control system according to the embodiments of the present application may be a PLC system.

In some implementations, the master device may verify the scram signal generated by the scram control system, and after the verification is passed, send the scram control signal to the plurality of controlled devices.

In other implementations, the master control device may further detect whether a reset trigger condition is reached, and if the reset trigger condition is reached, trigger the master control device and the plurality of controlled devices to reset, so as to release the scram state.

By way of example, the scram control system illustrated in fig. 1 may further include a plurality of signal generating devices, which may be in a serial configuration (not shown in the drawings), which may be connected in series with the master control device. At least one of the plurality of signal generating devices may generate the scram signal and the reset signal in response to an operation of a user pressing a button, and further transmit the generated scram signal and reset signal to the main control device in a serial structure.

It is noted that both the scram signal and the reset signal may be generated by a user trigger, i.e., it is understood that the scram signal and the reset signal may be generated equally simultaneously. The control logic of the technical scene may be that the scram control system should trigger execution of the scram control first, and then reset to eliminate triggering of the next scram control by the scram control state of the related device.

In view of this, the embodiment of the application provides a system reset method, in a scenario that a reset signal and an emergency stop signal are generated at the same time, by performing delay processing on the reset signal and sending the emergency stop signal to a controlled device, the emergency stop control operation is triggered to execute preferentially. Aiming at the delayed reset signal, under the condition that the trigger condition is met, the related equipment is triggered to respond to the delayed reset signal for resetting, and the control system can be reliably reset under the condition that the scram control effect is maintained.

The system reset method according to the embodiment of the application is described below.

Referring to fig. 2, fig. 2 is a flowchart of a system reset method according to an embodiment of the present application, where the system reset method may be applied to, for example, the scram control system illustrated in fig. 1. The system reset method comprises the following steps:

step S101, after generating an emergency stop signal and a reset signal, the main control equipment delays the reset signal according to a preset delay time length to obtain a delayed reset signal.

Wherein the preset delay time is greater than or equal to 1 second(s). Illustratively, the master device may delay the received reset signal for 1 s.

In some implementations, the master device may delay the received reset signal by a first timer. The delay processing of the reset signal by the first timer may be triggered by a falling edge, for example.

Therefore, in the scene that the reset signal and the scram signal are generated at the same time, the scram control operation is triggered to be executed preferentially by performing delay processing on the reset signal and sending the scram signal to the controlled device.

In connection with the corresponding implementation of fig. 1, the scram signal and the reset signal may be generated by a plurality of signal generating devices and transmitted to the master device. In some implementations, the scram signal may include a first channel scram signal and a second channel scram signal. For example, at least one of the plurality of signal generating devices may generate the first initial scram signal, the second initial scram signal, and the initial reset signal in response to a touch operation. Furthermore, the signal generating device that receives the touch operation may transmit the first initial scram signal, the second initial scram signal, and the initial reset signal to the master device through three channels in series, respectively. Correspondingly, the first channel scram signal comprises a first initial scram signal generated by the at least one scram signal generating device; the second channel scram signal includes a second initial scram signal generated by the at least one scram signal generating device; the reset signal includes an initial reset signal generated by the at least one scram signal generating device.

It is to be noted that, if at least two signal generating apparatuses (hereinafter, the signal generating apparatus 1 and the signal generating apparatus 2 are exemplified) respond to a trigger operation by a user, the signal generating apparatus 1 generates, for example, a first initial scram signal 1, a second initial scram signal 1, and an initial reset signal 1; the signal generating device 2 generates, for example, a first initial scram signal 2, a second initial scram signal 2, and an initial reset signal 2. Further, the signal generating device 1 and the signal generating device 2 sequentially transmit the generated signals according to a serial relationship, so that the signals of each channel of the signal generating device 1 and the signal generating device 2 are converged, that is, the first initial scram signal 1 and the first initial scram signal 2 are converged, and the first initial scram signal obtained after the convergence can be the first channel scram signal; the second initial scram signal 1 and the second initial scram signal 2 are converged, and the second initial scram signal obtained after the convergence can be a second channel scram signal; the initial reset signal 1 and the initial reset signal 2 are converged, and the initial reset signal obtained after the convergence can be a reset signal.

Further, the first channel emergency stop signal and the second channel emergency stop signal may be considered as the same signal transmitted through the two channels, based on which, before the reset signal is delayed according to the preset delay time, the master control device may verify consistency of the first channel emergency stop signal and the second channel emergency stop signal, so as to determine correctness of the first channel emergency stop signal and the second channel emergency stop signal.

For example, the master device may determine whether rising edges of the first channel scram signal and the second channel scram signal are identical, and/or determine whether falling edges of the first channel scram signal and the second channel scram signal are identical, and if so, may determine that the first channel scram signal and the second channel scram signal are identical, and then scram control may be performed based thereon. Otherwise, the first channel emergency stop signal and the second channel emergency stop signal are considered to have faults in the transmission process, and then the first channel emergency stop signal and the second channel emergency stop signal have the risk of correctness.

Step S102, the main control equipment sends target scram signals to the plurality of controlled equipment so that the plurality of controlled equipment can respectively carry out scram control according to preset duration.

The target scram signal is obtained according to the scram signal.

For example, if the first channel scram signal and the second channel scram signal are identical, the master device may transmit the first channel scram signal or the second channel scram signal as a target scram signal to the plurality of slave devices.

It should be noted that, the controlled device needs a certain buffering delay in response to the target scram signal, and the robot also needs a certain execution time from receiving the scram instruction of the controlled device to entering the scram state. In view of this, for any one of the plurality of controlled devices, the period in which the controlled device controls the effective execution of the target scram signal reaches a preset duration, which is the sum of the duration of the scram buffer delay and the duration of the controlled robot entering the scram state.

The scram control is triggered by a high level and is held this time by a low level, based on which, in some implementations, the controlled device causes the target scram signal to execute effectively by controlling the target scram signal to maintain a low level state.

In order to maintain the safety during the scram control and the scram behavior of the robot, the master control device does not respond to the triggering of any control signal within the preset duration range. After the preset duration range, the master device may resume the response and processing of the received signal.

For example, the buffering delay of the controlled device to the target scram signal is, for example, 7s, the duration required for the controlled robot to enter the scram state is, for example, 2s, and any controlled device can maintain a low level state of 9s after sending the target scram signal, so that the scram triggered by the target scram signal before resetting can be effectively executed.

For example, at the time of 10:00, the master control device receives a set of a first channel scram signal, a second channel scram signal and a reset signal, and delays the reset signal at the time by 1s, so that the master control device can respond to the first channel scram signal and the second channel scram signal at the time (in the case of passing safety verification), control the scram of the robot, and keep the scram control signal in a low level state for 9s at the time (for example, 10:00) when the scram control is started. At time 10:05, the master device receives a set of first channel scram signals, second channel scram signals, and reset signals again, for example, and then the master device does not respond to the signals at time 10:05. At a time of 10:11, the master device receives again a set of first channel scram signals, second channel scram signals and reset signals, for example, in which case the master device responds to the signals at the time of 10:11 and processes in accordance with the processing logic of the present application.

In some implementations, the controlled device may maintain a low level for the target scram signal via a second timer. Illustratively, the low level maintenance processing of the target scram signal by the second timer may be triggered by a falling edge.

Step S103, if the signal value of the scram signal meets the reset triggering condition, the main control equipment and the controlled equipment respond to the delayed reset signals to reset.

It should be noted that the condition for triggering the emission of the reset signal is that the scram signal is at a high level, and the reset signal is not active in the case that the scram signal is at a low level.

As can be seen from the foregoing description of the emergency stop signals, the emergency stop signals include a first channel emergency stop signal and a second channel emergency stop signal, and for example, in the case where the first channel emergency stop signal and the second channel emergency stop signal are both high level signals, the signal value of the emergency stop signal may be considered to satisfy the reset triggering condition, for example.

Further, when the first channel emergency stop signal and the second channel emergency stop signal are both high-level signals, the emergency stop (Estop) module corresponding to the main control equipment receives the delayed reset signal, and the main control equipment sends the delayed reset signal to the emergency stop (Estop O1) module corresponding to the controlled equipment so as to trigger the Estop module and the Estop O1 module to reset.

In summary, after the emergency stop control system generates the emergency stop signal and the reset signal, the main control device delays the reset signal according to the preset delay time length to obtain the delayed reset signal, and sends the target emergency stop signal to the plurality of controlled devices, so that the plurality of controlled devices respectively perform emergency stop control according to the preset duration time length, and the target emergency stop signal is obtained according to the emergency stop signal. That is, in a scenario where the reset signal and the scram signal are generated at approximately the same time, the scram signal may be delayed and transmitted to the controlled device, so that a certain time interval is generated between the scram control and the reset, and thus the scram operation may be controlled to be performed first, and then the reset of the related device may be controlled. Further, the sending of the reset signal is controlled by the emergency stop signal, based on the emergency stop signal, if the emergency stop signal meets the reset triggering condition, the main control equipment and the plurality of controlled equipment respond to the delayed reset signal to reset, so that after the emergency stop control is executed, related functional equipment in the emergency stop control system can release the emergency stop state through reset to support the next emergency stop control. Therefore, in the embodiment of the application, under the condition that the emergency stop signal and the reset signal are almost generated at the same time, the control system can be reliably reset under the condition that the emergency stop control effect is maintained by delaying the reset signal, so that the safety performance is optimized.

Embodiments of the present application are described below with reference to examples.

Taking a control system implemented as a PLC system as an example, fig. 3 is a schematic structural diagram of an exemplary PLC system provided in an embodiment of the present application, where the PLC system may include n front-end PLCs, a master station PLC, and a plurality of slave station PLCs deployed at a robot end. N and m are integers greater than or equal to 2. The front-end PLC may be, for example, an implementation of the foregoing signal generating device, the master station PLC may be, for example, an implementation of the foregoing master control device, and the slave station PLC may be, for example, an implementation of the foregoing slave control device. The master station PLC comprises an Estop module, and each slave station PLC comprises an Estop O1 module.

As shown in fig. 3, the n front end PLCs are connected in series and then connected in series with the master station PLC, which is connected with the m slave station PLCs wirelessly. Each front-end PLC in the n front-end PLCs comprises a button box, and the front-end PLC can respond to user trigger to generate a first initial scram signal, a second initial scram signal and an initial reset signal, and then the first initial scram signal, the second initial scram signal and the initial reset signal are transmitted to the master station PLC in series sequence through three channels. After receiving the reset signals, the scram signals 1 (i.e., the first channel scram signals) and the scram signals 2 (i.e., the first channel scram signals) generated and transmitted by the n front end PLCs, the master station PLCs process the reset signals, the scram signals 1 and the scram signals 2 to trigger the reset of the robot scram and scram functions.

Fig. 4 is a schematic diagram of a scenario of an exemplary reset processing logic according to an embodiment of the present application, in which, after the master station PLC receives, for example, the reset signal, the scram signal 1, and the scram signal 2 at time T0, and verifies that the scram signal 1 and the scram signal 2 agree, the master station PLC delays, for example, the reset signal for 1s, and obtains a reset signal to be transmitted.

Further, the Estop module in the master station PLC sends the scram signal 1 or the scram signal 2 as a target scram signal to m slave station PLCs at the time T1. In some implementations, the master station PLC may also detect signal values of the scram signal 1 and the scram signal 2 received after time T1, starting from time T1. Wherein time T1 is after time t0+1s.

For any one of the m slave station PLCs, the Estop O1 module in the slave station PLC may send the target scram signal to the corresponding robot at time T2, and further, for example, the target scram signal is forcedly maintained at a low level of 9s from time T2, so that the corresponding robot stably enters the scram state. Time T2 is later than time T1.

It should be noted that, in the period of t2+9s, the Estop module in the master station PLC and the Estop O1 module in the slave station PLC do not respond to the input scram signal and reset signal, and do not process.

If the master station PLC receives a set of emergency stop signals 1 and 2 again at time T3 after t2+9s, and detects that the emergency stop signals 1 and 2 are both high level signals, the master station PLC may send a reset signal to be sent to the Estop modules and the Estop O1 modules of the m slave station PLCs, and the Estop modules and the Estop O1 modules may respond to the reset signal to perform reset, and the reset state, that is, the state of performing emergency stop, is released.

In summary, the system resetting method provided by the embodiment of the application is applied to an emergency stop control system, wherein the emergency stop control system comprises a main control device and a plurality of controlled devices. After the scram control system generates the scram signal and the reset signal, the main control equipment delays the reset signal according to a preset delay time length to obtain a delayed reset signal, and sends target scram signals to the controlled equipment, so that the controlled equipment performs scram control according to the preset duration time length respectively, and the target scram signals are obtained according to the scram signals. That is, in a scenario where the reset signal and the scram signal are generated at approximately the same time, the reset signal may be delayed, and the scram signal may be sent to the controlled device, so that a certain time interval is generated between the scram control and the reset, so that the scram operation may be controlled to be performed first, and then the related device is controlled to be reset, so as to support the next scram control function. Further, the sending of the reset signal is controlled by the scram signal, based on the scram signal, if the scram signal meets the reset triggering condition, the main control device and the plurality of controlled devices respond to the delayed reset signal to reset, so that after the scram control is executed, relevant functional devices in the scram control system can release the scram state through reset. Therefore, in the embodiment of the application, under the condition that the emergency stop signal and the reset signal are almost generated at the same time, the control system can be reliably reset under the condition that the emergency stop control effect is maintained by delaying the reset signal.

Embodiments of the apparatus corresponding to the foregoing method embodiments are described below.

The embodiment of the application also provides a system resetting device, as shown in fig. 5, which comprises: a delay module 501, a send module 502, and a reset module 503. The system reset device can be applied to the system of fig. 1 or 3 for executing the system reset method in the embodiment illustrated in fig. 2 and 4.

For example, the delay module 501 is configured to delay the reset signal according to a preset delay time length after generating the scram signal and the reset signal, so as to obtain a delayed reset signal; the sending module 502 is configured to send a target scram signal to a plurality of controlled devices, so that the plurality of controlled devices respectively perform scram control according to a preset duration, and the target scram signal is obtained according to the scram signal; and the reset module 503 is configured to trigger the master control device and the plurality of controlled devices to respond to the delayed reset signals to perform reset if the signal value of the scram signal meets a reset triggering condition.

Optionally, the preset delay time is greater than or equal to 1 second.

Optionally, the system resetting device further comprises a scram control module, wherein the scram control module is applied to any controlled device and used for controlling the effective execution time period of the target scram signal to reach a preset duration, and the preset duration is the sum of the duration of scram buffer delay and the duration of the controlled robot entering the scram state.

Optionally, the scram control module is further configured to maintain the low level state of the target scram signal by controlling the target scram signal to effectively execute the target scram signal.

Optionally, the emergency stop signal includes a first channel emergency stop signal and a second channel emergency stop signal, and a signal value of the emergency stop signal meets a reset triggering condition, including: the first channel scram signal and the second channel scram signal are both high level signals.

Optionally, the system reset device further includes a signal generating module, applied to the plurality of signal generating devices connected in series, for generating a first initial scram signal, a second initial scram signal and an initial reset signal in response to a touch operation; transmitting the first initial emergency stop signal, the second initial emergency stop signal and the initial reset signal to the main control equipment through three channels respectively; the first channel scram signal includes a first initial scram signal generated by the at least one scram signal generating device, the second channel scram signal includes a second initial scram signal generated by the at least one scram signal generating device, and the reset signal includes an initial reset signal generated by the at least one scram signal generating device.

Optionally, the system resetting device further includes a determining module, where the determining module is configured to determine that a rising edge or a falling edge of the first channel scram signal and the second channel scram signal are the same.

The system resetting device provided by the embodiment of the application and the system resetting method provided by the embodiment of the application have the same beneficial effects as the method adopted, operated or realized by the application program stored by the system resetting device due to the same inventive concept.

In a specific implementation, the embodiment of the application further provides an electronic device, which may be the scram control system in the foregoing embodiment, for implementing all or part of the foregoing system reset method steps.

Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application. Comprising the following steps: a processor 600, a memory 601, a bus 602 and a communication interface 603, the processor 600, the communication interface 603 and the memory 601 being connected by the bus 602; the memory 601 stores a computer program executable on the processor 600, and the processor 600 executes the system reset method provided by any of the foregoing embodiments of the present disclosure when the computer program is executed.

The memory 601 may include a high-speed random access memory (RAM: random Access Memory), and may further include a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory. The communication connection between the system network element and at least one other network element is implemented via at least one communication interface 603 (which may be wired or wireless), the internet, a wide area network, a local network, a metropolitan area network, etc. may be used.

Bus 602 may be an ISA bus, a PCI bus, an EISA bus, or the like. The buses may be classified as address buses, data buses, control buses, etc. The memory 601 is configured to store a program, the processor 600 executes the program after receiving an execution instruction, and the system reset method disclosed in any one of the foregoing embodiments of the disclosure may be applied to the processor 600 or implemented by the processor 600.

The processor 600 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the methods described above may be performed by integrated logic circuitry in hardware or instructions in software in processor 600. The processor 600 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but may also be a Digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The various methods, steps and logic blocks of the disclosure in the embodiments of the disclosure may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present disclosure may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 601 and the processor 600 reads the information in the memory 601 and performs the steps of the method described above in combination with its hardware.

The electronic device provided by the embodiment of the present disclosure and the system reset method provided by the embodiment of the present disclosure are the same inventive concept, and have the same beneficial effects as the method adopted, operated or implemented by the same.

The present disclosure further provides a computer readable storage medium corresponding to the system reset method provided in the foregoing embodiment, where the computer readable storage medium may be, for example, an optical disc, and a computer program (i.e., a program product) stored thereon, where the computer program, when executed by a processor, performs the system reset method provided in any of the foregoing embodiments.

It should be noted that examples of the computer readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical or magnetic storage medium, which will not be described in detail herein.

In addition, the embodiment of the application also provides a computer program product for storing computer readable program instructions, which can realize a system reset method in the previous embodiment when the instructions are executed by a processor.

It is noted that in the present application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.

Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.

For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

The above embodiment of the present application does not limit the protection scope of the embodiment of the present application.

Claims

1. A system reset method, which is applied to a scram control system, wherein the scram control system comprises a master control device and a plurality of controlled devices, the method comprises:

2. The system reset method of claim 1, wherein the preset delay time is greater than or equal to 1 second.

3. The system resetting method according to claim 1, wherein for any one of the plurality of controlled devices, the scram control is performed according to a preset duration, including:

4. The system reset method of claim 3, wherein said controlled device causes said target scram signal to execute effectively by controlling said target scram signal to maintain a low state.

5. The system reset method of claim 1, wherein the scram signal comprises a first channel scram signal and a second channel scram signal, the signal value of the scram signal satisfying a reset trigger condition, comprising:

6. The system reset method of claim 5 wherein the scram control system further comprises a plurality of signal generating devices in series, the generating the scram signal and the reset signal comprising:

7. The system reset method of claim 6, further comprising, prior to delaying the reset signal by a predetermined delay time, the step of:

8. A system reset device, characterized by being applied to a scram control system, the scram control system including a master control device and a plurality of controlled devices, the device comprising:

9. An electronic device, comprising: a processor and a memory, wherein,

the memory is used for storing computer executable instructions;

the processor is configured to read the instructions from the memory and execute the instructions to implement the method of any one of claims 1 to 7.

10. A computer readable storage medium, characterized in that the storage medium stores computer program instructions, which, when read by a computer, perform the method according to any of claims 1 to 7.

11. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.