CN117016050A

CN117016050A - Ferroelectric memory, forming method thereof and electronic equipment

Info

Publication number: CN117016050A
Application number: CN202180095753.3A
Authority: CN
Inventors: 谭万良; 李宇星; 李维谷; 蔡佳林; 吕杭炳; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-08-27
Filing date: 2021-08-27
Publication date: 2023-11-07
Also published as: WO2023024100A1

Abstract

The embodiment of the application provides a ferroelectric memory, a forming method thereof and electronic equipment. The electrode layers on two sides of the ferroelectric layer are mainly used for inhibiting the electrode layers on two sides of the ferroelectric layer from affecting the crystal phase orientation of the ferroelectric layer. The ferroelectric memory includes: a substrate and a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric capacitor; the ferroelectric capacitor includes a first electrode and a second electrode, a ferroelectric layer formed between the first electrode and the second electrode; the ferroelectric capacitor further includes a first buffer layer formed between the first electrode and the ferroelectric layer, and a second buffer layer formed between the second electrode and the ferroelectric layer; the first buffer layer and the second buffer layer utilize an amorphous structure and/or an orthorhombic structure to inhibit the corresponding electrodes from affecting the crystal phase orientation of the ferroelectric layer, namely the first buffer layer and the second buffer layer enable the ferroelectric layer to be in an orthorhombic phase. That is, the first buffer layer and the second buffer layer are used as growth templates for the ferroelectric layer to prevent the influence of the electrodes on the crystal phase orientation of the ferroelectric layer.

Description

Ferroelectric memory, forming method thereof and electronic equipment

Technical Field

The present application relates to the field of semiconductor memory technology, and more particularly, to a ferroelectric memory, a method for forming a ferroelectric memory, and an electronic device including the ferroelectric memory.

Background

Ferroelectric random access memory (ferroelectric random access memory, feRAM) is a new type of memory, and is more widely used than conventional dynamic random access memory (dynamic random access memory, DRAM) or flash memory, because it has the advantages of non-volatility, high speed, low power consumption, multiple read/write times, and radiation resistance.

Fig. 1 shows a process structure diagram of the ferroelectric capacitor of the core part in FeRAM. Wherein the ferroelectric capacitor comprises a stacked first electrode 01 and second electrode 02, and a ferroelectric layer 03 formed between the first electrode 01 and second electrode 02.

The ferroelectric properties of the ferroelectric layer 03 in fig. 1 are closely related to the ferroelectric crystal phase, and fig. 2a, 2b and 2c show three common crystal phases of the ferroelectric layer 03 made of hafnium oxide based material, fig. 2a being a monoclinic phase, fig. 2b being a tetragonal phase, and fig. 2c being an orthorhombic phase, wherein the ferroelectric layer 03 can obtain better ferroelectric properties when the ferroelectric crystal phase is the orthorhombic phase shown in fig. 2 c.

In the formation of the ferroelectric capacitor structure shown in fig. 1, the material of the first electrode 01 located under the ferroelectric layer 03 has a very important influence on the crystal phase orientation of the ferroelectric layer 03, for example, as shown in fig. 3a to 3c, black circles in fig. 3a to 3c show the atomic arrangement in the ferroelectric layer 03, white circles show the atomic arrangement in the first electrode 01, and the ferroelectric material selected for the ferroelectric layer 03 in fig. 3a to 3c is the same, whereas the conductive material selected for the first electrode 01 in fig. 3a to 3c is different, and it can be seen from fig. 3a to 3c that the atomic arrangement of the ferroelectric layer 03 has a tendency substantially identical to the atomic arrangement of the first electrode 01, so that even though the material selected for the ferroelectric layer 03 is the same, the ferroelectric layer 03 has a different crystal phase orientation.

In addition, as shown in fig. 4a to 4c, the ferroelectric material selected for the ferroelectric layer 03 in fig. 4a to 4c is the same, and the conductive material selected for the first electrode 01 in fig. 4a to 4c is different. In this way, since the conductive materials selected for the first electrode 01 are different, different growth environments are provided for the ferroelectric layer 03, and the growth speed of the ferroelectric layer 03 is different, even if the materials of the ferroelectric layer 03 are the same, the grain size of the ferroelectric layer 03 is different, and the difference in grain size affects the crystal phase orientation as the grain size of the ferroelectric layer 03 shown in fig. 4a to 4c gradually decreases.

In order to obtain a desired specific crystal phase orientation of the ferroelectric layer 03 in fig. 1, the first electrode 01 is prepared by selecting a suitable material, for example, iridium oxide lead (Pb) ₂ Ir ₂ O ₇ PIO), bismuth oxyruthenium (Bi) ₂ Ru ₂ O ₇ BRO), lanthanum strontium oxymanganese (La) _0.67 Sr _0.33 MnO ₃ ) And the like as electrode materials, since these electrode materials have a suitable lattice constant, the crystalline phase of the grown ferroelectric layer 03 can be preferentially oriented. However, this results in limited choice of materials for the first electrode 01, and in addition, the ferroelectric layer 03 is grown under severe conditions and at a slow growth rate, which presents challenges to the ferroelectric capacitor formation process.

Disclosure of Invention

The application provides a ferroelectric memory, a forming method thereof and electronic equipment comprising the ferroelectric memory, and mainly aims to provide the ferroelectric memory which can inhibit electrode layers positioned at two sides of a ferroelectric layer from affecting the crystal phase orientation of the ferroelectric layer so as to enable the ferroelectric layer to present an orthorhombic phase with better ferroelectric characteristics.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

in a first aspect, the application provides a ferroelectric memory which is a ferroelectric random access memory (ferroelectric random access memory, feRAM). The ferroelectric memory includes: a substrate and a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric capacitor; the ferroelectric capacitor includes a first electrode and a second electrode, a ferroelectric layer as a storage medium formed between the first electrode and the second electrode; in addition, the ferroelectric capacitor further includes a first buffer layer formed between the first electrode and the ferroelectric layer, and a second buffer layer formed between the second electrode and the ferroelectric layer; wherein the ferroelectric layer comprises a hafnium oxide-based material, the first buffer layer comprises an amorphous structure and/or an orthorhombic structure, the second buffer layer comprises an amorphous structure and/or an orthorhombic structure, the first buffer layer inhibits the first electrode from affecting the crystal phase orientation of the ferroelectric layer by using the amorphous structure and/or the orthorhombic structure, the second buffer layer inhibits the second electrode from affecting the crystal phase orientation of the ferroelectric layer by using the amorphous structure and/or the orthorhombic structure, and the first buffer layer and the second buffer layer enable the ferroelectric layer to be in an orthorhombic phase.

In a memory cell of a ferroelectric memory according to the present application, a ferroelectric capacitor for storing electric charges includes not only a first electrode and a second electrode, and a ferroelectric layer stacked between the first electrode and the second electrode, but also a first buffer layer and a second buffer layer. And, the first buffer layer herein includes an amorphous structure and/or an orthorhombic structure, and the second buffer layer includes an amorphous structure and/or an orthorhombic structure. The ferroelectric layer is grown on the first buffer layer instead of the first electrode as a template, so that the first electrode does not influence the crystal phase orientation of the ferroelectric layer, and the selectable material range of the first electrode can be enlarged, correspondingly, because the material of the first electrode is not a specific material, the ferroelectric layer does not need severe growth process conditions, the process difficulty of the ferroelectric capacitor can be reduced, the manufacturing cost can be reduced, and the production efficiency can be improved.

The first buffer layer may include an amorphous structure and/or an orthorhombic structure, that is, the ferroelectric layer may be grown on the first buffer layer of amorphous material, so that the ferroelectric layer may be preferentially oriented and grown into an orthorhombic structure with better ferroelectric properties.

Similarly, since the second buffer layer containing an amorphous structure and/or an orthorhombic structure is arranged between the ferroelectric layer and the second electrode, the second buffer layer can inhibit the influence of the second electrode on the crystal phase orientation of the ferroelectric layer, so that the ferroelectric layer is orthorhombic under the action of the first buffer layer and the second buffer layer, and the storage performance of the memory is optimized.

In a possible implementation manner of the first aspect, the first buffer layer and/or the second buffer layer comprises at least one of an oxide and a semiconductor material.

In a possible implementation manner of the first aspect, the first buffer layer and/or the second buffer layer comprises an oxide dielectric material.

For example, at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, and silicon oxide may be contained.

When the first buffer layer and the second buffer layer are prepared using the above-described illustrated oxides, the first buffer layer and the second buffer layer may be formed using an amorphous structure, and after the ferroelectric capacitor is prepared, the oxides may include an amorphous structure, or may include an amorphous structure and an orthorhombic structure obtained by crystallization, or may include an orthorhombic structure obtained by crystallization.

In addition, although these oxides are dielectric materials, since the first buffer layer and the second buffer layer are relatively thin in practical processes, substantially in a few nanometers or even less than 1 nanometer, when voltages are applied to the first electrode and the second electrode, an electric field may still exist in the ferroelectric layer, and polarization of the ferroelectric layer is not affected.

In a possible implementation manner of the first aspect, the first buffer layer and/or the second buffer layer comprises an oxide conductive material.

For example, at least one of indium tin oxide, ruthenium oxide, and iridium oxide may be contained.

In a possible implementation manner of the first aspect, the first buffer layer and/or the second buffer layer includes at least one of silicon, germanium, silicon germanium, and silicon nitride.

In a possible implementation manner of the first aspect, the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer and the second electrode are stacked in a direction perpendicular to the substrate.

The ferroelectric capacitor thus formed may be referred to as a planar ferroelectric capacitor structure.

In a possible implementation manner of the first aspect, the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer and the second electrode are stacked in a direction parallel to the substrate.

The ferroelectric capacitor thus formed may be referred to as a vertical ferroelectric capacitor structure. The ferroelectric capacitor structure can realize three-dimensional integration on a substrate, and improves the storage density of the memory so as to adapt to the rapid operation requirement of electronic equipment.

In a possible implementation manner of the first aspect, the first electrode extends along a direction perpendicular to the substrate, and the first buffer layer, the ferroelectric layer, the second buffer layer and the second electrode sequentially surround the periphery of the first electrode along a direction parallel to the substrate.

In this way, the ferroelectric capacitor is formed in a columnar structure perpendicular to the substrate, and the cross section of the columnar structure may be circular, rectangular, or other shapes.

In a possible implementation manner of the first aspect, a thickness of the first buffer layer and/or the second buffer layer along a stacking direction of the first electrode and the second electrode is 0.5nm-5nm.

That is, the first buffer layer and the second buffer layer are thin enough, and when the first buffer layer and the second buffer layer are made of amorphous materials, the thin enough film layer structure makes the materials not crystallize as much as possible in the growth process so as to maintain the amorphous structure; in addition, in this way, the ferroelectric characteristics of the ferroelectric layer can be stabilized by utilizing the thermal expansion characteristics of the first electrode and the second electrode well without affecting the stress applied to the ferroelectric layer by the first electrode and the second electrode.

In a possible implementation manner of the first aspect, each memory cell further includes a first transistor, a second transistor, a control line, a write bit line, a read bit line, and a source line, and a word line; the control end of the first transistor is electrically connected with the control line, the first end of the first transistor is electrically connected with the first electrode, and the second end of the first transistor is electrically connected with the write bit line; the control end of the second transistor is electrically connected with the first electrode, the first end of the second transistor is electrically connected with the source line, and the second end of the second transistor is electrically connected with the read bit line; the second electrode is electrically connected to the word line.

In a possible implementation manner of the first aspect, each memory cell includes at least two ferroelectric capacitors. In the 2TnC memory cell thus formed, one memory cell may be used to store multi-bit data to increase the storage capacity of each memory cell.

In a second aspect, the application also provides a ferroelectric memory which is still a FeRAM. The ferroelectric memory includes: a substrate and a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric capacitor; the ferroelectric capacitor includes a first electrode and a second electrode, a ferroelectric layer as a storage medium formed between the first electrode and the second electrode; in addition, the ferroelectric capacitor further includes a first buffer layer formed between the first electrode and the ferroelectric layer, and a second buffer layer formed between the second electrode and the ferroelectric layer; wherein the ferroelectric layer comprises a hafnium oxide based material, the first buffer layer comprises an amorphous structure and/or an orthorhombic structure, the second buffer layer comprises an amorphous structure and/or an orthorhombic structure, and the first buffer layer and/or the second buffer layer comprises at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide, indium tin oxide, ruthenium oxide, iridium oxide, silicon, germanium, silicon germanium, and silicon nitride.

In the memory cell of the ferroelectric memory provided by the application, at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide, indium tin oxide, ruthenium oxide, iridium oxide, silicon, germanium, silicon germanium and silicon nitride is included, and the oxide or semiconductor material comprises at least one of an amorphous structure and an orthorhombic structure, so that the first buffer layer serving as a growth template of the ferroelectric layer can enable the crystal phase orientation of the ferroelectric layer to be free from the influence of the first electrode, and can be preferentially grown into the ferroelectric layer with an orthorhombic phase. Also, by employing these titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, indium tin oxide, ruthenium oxide, iridium oxide, or the like including at least one of an amorphous structure and an orthorhombic structure, the ferroelectric layer can be protected from the second electrode, that is, the ferroelectric layer can be made orthorhombic under the action of the first buffer layer and the second buffer layer.

In a possible implementation manner of the second aspect, the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer, and the second electrode are stacked in a direction perpendicular to the substrate.

In a possible implementation manner of the second aspect, the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer and the second electrode are stacked in a direction parallel to the substrate.

In a possible implementation manner of the second aspect, the first electrode extends along a direction perpendicular to the substrate, and the first buffer layer, the ferroelectric layer, the second buffer layer and the second electrode sequentially surround the periphery of the first electrode along a direction parallel to the substrate.

That is, when the first buffer layer and the second buffer layer are made of amorphous materials, the thin film layer structure is enough to prevent the materials from crystallizing as much as possible in the growth process, so that the amorphous structure is maintained, the stress applied to the ferroelectric layer by the first electrode and the second electrode is not influenced, and the ferroelectric property of the ferroelectric layer can be well stabilized by utilizing the thermal expansion property of the first electrode and the second electrode.

In a possible implementation manner of the second aspect, each memory cell further includes a first transistor, a second transistor, a control line, a write bit line, a read bit line, and a source line, and a word line; the control end of the first transistor is electrically connected with the control line, the first end of the first transistor is electrically connected with the first electrode, and the second end of the first transistor is electrically connected with the write bit line; the control end of the second transistor is electrically connected with the first electrode, the first end of the second transistor is electrically connected with the source line, and the second end of the second transistor is electrically connected with the read bit line; the second electrode is electrically connected to the word line.

In a possible implementation manner of the second aspect, each memory cell includes at least two ferroelectric capacitors. In the 2TnC memory cell thus formed, one memory cell may be used to store multi-bit data to increase the storage capacity of each memory cell.

In a third aspect, the present application also provides a method for forming a ferroelectric memory, the method comprising:

forming a first electrode, a second electrode, a ferroelectric layer, a first buffer layer and a second buffer layer on a substrate, wherein the ferroelectric layer is formed between the first electrode and the second electrode, the first buffer layer is formed between the first electrode and the ferroelectric layer, and the second buffer layer is formed between the second electrode and the ferroelectric layer, and wherein the first buffer layer and the second buffer layer are made of amorphous materials, and the ferroelectric layer is made of materials containing hafnium oxide-based materials;

Annealing the first electrode, the second electrode, the ferroelectric layer, the first buffer layer and the second buffer layer to obtain a ferroelectric capacitor comprising the first electrode, the second electrode, the ferroelectric layer, the first buffer layer and the second buffer layer; the first buffer layer is used for inhibiting the first electrode from affecting the crystal phase orientation of the ferroelectric layer, the second buffer layer is used for inhibiting the second electrode from affecting the crystal phase orientation of the ferroelectric layer, and the first buffer layer and the second buffer layer enable the ferroelectric layer to be in orthorhombic phases.

In the forming method of the ferroelectric memory, after the first electrode is finished, the ferroelectric layer is not directly formed on the first electrode, but the first buffer layer made of amorphous material is formed firstly, and then the ferroelectric layer is formed on the first buffer layer, when the ferroelectric layer grows on the first buffer layer made of amorphous material, the ferroelectric layer can preferentially grow into an orthorhombic phase structure with better ferroelectric characteristics due to the fact that particles of the first buffer layer are not periodically and repeatedly arranged; after the ferroelectric layer is formed, a second buffer layer is formed on the ferroelectric layer, and then a second electrode is formed on the second buffer layer, so that the crystal orientation of the second electrode does not influence the crystal orientation of the ferroelectric layer, and the ferroelectric layer can grow towards an orthorhombic crystal phase under the action of the second buffer layer.

In a possible implementation manner of the third aspect, when forming the first buffer layer and/or the second buffer layer, the method includes: the first buffer layer and the second buffer layer are made of at least one of an amorphous oxide and a semiconductor material.

In a possible implementation manner of the third aspect, the first buffer layer and/or the second buffer layer includes at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide, indium tin oxide, ruthenium oxide, iridium oxide, silicon, germanium, silicon germanium, and silicon nitride.

In a possible implementation manner of the third aspect, when forming the first buffer layer and/or the first buffer layer, the method includes: the first buffer layer and the second buffer layer are prepared by adopting a thin film deposition method.

In this way, the process method for preparing the first buffer layer and the second buffer layer can be compatible with the preparation process of other layer structures in the ferroelectric memory, and the complex process flow and the increase of the manufacturing cost caused by the need of adding the buffer layer structure are avoided.

In a possible implementation manner of the third aspect, when forming the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer, and the second electrode, the method includes: the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer, and the second electrode are stacked in this order in a direction perpendicular to the substrate.

In this way, a planar ferroelectric capacitor structure can be produced.

In a possible implementation manner of the third aspect, when forming the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer, and the second electrode, the method includes: the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer, and the second electrode are stacked in this order in a direction parallel to the substrate.

This produces a vertical ferroelectric capacitor structure.

In a fourth aspect, the present application provides a ferroelectric memory which is a ferroelectric field effect transistor memory (ferroelectric filed-effect-transistor, feFET). The ferroelectric memory includes: a substrate and a plurality of memory cells formed on the substrate, each memory cell comprising: a first doped region and a second doped region formed in the substrate, a channel region between the first doped region and the second doped region, a ferroelectric layer comprising a hafnium oxide-based material formed on the channel region, a gate electrode formed on a side of the ferroelectric layer remote from the substrate; each memory cell further includes a first buffer layer formed between the ferroelectric layer and the channel region, and a second buffer layer formed between the ferroelectric layer and the gate electrode, the first buffer layer including an amorphous structure and/or an orthorhombic structure, the second buffer layer including an amorphous structure and/or an orthorhombic structure, the first buffer layer for suppressing the channel region from affecting the crystalline phase orientation of the ferroelectric layer, the second buffer layer for suppressing the gate from affecting the crystalline phase orientation of the ferroelectric layer, the first buffer layer and the second buffer layer causing the ferroelectric layer to assume an orthorhombic phase.

In the memory cell of the ferroelectric memory according to the present application, one of the first doped region and the second doped region formed in the substrate may be a source and the other doped region may be a drain, and then the memory cell includes a first buffer layer disposed between the ferroelectric layer and the channel region, and a second buffer layer disposed between the ferroelectric layer and the gate, in addition to the source, the drain, the gate, and the channel structure. When forming the ferroelectric layer, the first buffer layer is used as a growth template instead of the channel region of the substrate, so that the ferroelectric layer is preferentially oriented without being influenced by the template effect of the substrate; also, since the second buffer layer is also present between the gate electrode and the ferroelectric layer, the second buffer layer including an amorphous structure and/or an orthorhombic structure can also protect the ferroelectric layer from the gate electrode to the crystal phase orientation, and eventually make the ferroelectric layer orthorhombic.

In a possible implementation manner of the fourth aspect, the first buffer layer and/or the second buffer layer comprises at least one of an oxide and a semiconductor material.

In a possible implementation manner of the fourth aspect, the first buffer layer and/or the second buffer layer comprises an oxide dielectric material.

In the practical process, the first buffer layer and the second buffer layer are relatively thin and basically are a few nanometers or even less than 1 nanometer, so when voltage is applied to the first electrode and the second electrode, an electric field can still exist in the ferroelectric layer, and the ferroelectric layer is not affected to be polarized.

In a possible implementation manner of the fourth aspect, the first buffer layer and/or the second buffer layer comprises an oxide conductive material.

In a possible implementation manner of the fourth aspect, the first buffer layer and/or the second buffer layer includes at least one of silicon, germanium, silicon germanium, and silicon nitride.

In a possible implementation manner of the fourth aspect, each storage unit further includes: word lines, bit lines, and source lines; the gate is electrically connected to the word line, the first doped region is electrically connected to the bit line, and the second doped region is electrically connected to the source line.

In a possible implementation manner of the fourth aspect, a thickness of the first buffer layer and/or the second buffer layer along a stacking direction of the ferroelectric layer and the gate electrode is 0.5nm to 5nm.

That is, the first buffer layer and the second buffer layer are thin enough, and when the first buffer layer and the second buffer layer are made of amorphous material, the thin enough film layer structure makes the material not crystallize as much as possible during the growth process so as to maintain the amorphous structure.

In a fifth aspect, the present application provides a ferroelectric memory which, as in the fourth aspect, is also a FeFET. The ferroelectric memory includes: a substrate and a plurality of memory cells formed on the substrate, each memory cell comprising: a first doped region and a second doped region formed in the substrate, a channel region between the first doped region and the second doped region, a ferroelectric layer comprising a hafnium oxide-based material formed on the channel region, a gate electrode formed on a side of the ferroelectric layer remote from the substrate; each memory cell further includes a first buffer layer formed between the ferroelectric layer and the channel region, and a second buffer layer formed between the ferroelectric layer and the gate electrode, the first buffer layer including an amorphous structure and/or an orthorhombic structure, the second buffer layer including an amorphous structure and/or an orthorhombic structure, the first buffer layer and/or the second buffer layer including at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide, indium tin oxide, ruthenium oxide, iridium oxide, silicon, germanium, silicon germanium, and silicon nitride.

In the memory cell of the ferroelectric memory provided by the application, at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, indium tin oxide, ruthenium oxide, iridium oxide, silicon, germanium, silicon germanium and silicon nitride is included, and the oxide or semiconductor material comprises at least one of an amorphous structure and an orthorhombic structure, so that the first buffer layer serving as a ferroelectric layer growth template can enable the crystal phase orientation of the ferroelectric layer to be free from the influence of the channel region of the substrate, and can be preferentially grown into the ferroelectric layer with the orthorhombic phase. Also, by employing these titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, indium tin oxide, ruthenium oxide, iridium oxide, or the like including at least one of an amorphous structure and an orthorhombic structure, the ferroelectric layer can be protected from the gate electrode, that is, the ferroelectric layer can be made orthorhombic under the action of the first buffer layer and the second buffer layer.

In a possible implementation manner of the fifth aspect, each storage unit further includes: word lines, bit lines, and source lines; the gate is electrically connected to the word line, the first doped region is electrically connected to the bit line, and the second doped region is electrically connected to the source line.

In a possible implementation manner of the fifth aspect, a thickness of the first buffer layer and/or the second buffer layer along a stacking direction of the ferroelectric layer and the gate electrode is 0.5nm to 5nm.

In a sixth aspect, the present application also provides a method for forming a ferroelectric memory, the method comprising:

forming a first doped region, a second doped region in a substrate, and forming a ferroelectric layer, a gate electrode, a first buffer layer and a second buffer layer on the substrate, wherein the ferroelectric layer is formed on a channel region between the first doped region and the second doped region, the gate electrode is formed on one side of the ferroelectric layer away from the substrate, the first buffer layer is formed between the ferroelectric layer and the channel region, and the second buffer layer is formed between the ferroelectric layer and the gate electrode, and wherein the first buffer layer and the second buffer layer are made of amorphous materials and the ferroelectric layer is made of materials containing hafnium oxide-based materials;

and annealing the gate electrode, the ferroelectric layer, the first buffer layer and the second buffer layer, wherein the first buffer layer is used for inhibiting the channel region from affecting the crystal phase orientation of the ferroelectric layer, the second buffer layer is used for inhibiting the gate electrode from affecting the crystal phase orientation of the ferroelectric layer, and the first buffer layer and the second buffer layer enable the ferroelectric layer to be in an orthorhombic phase.

In the method for forming the ferroelectric memory, the ferroelectric layer is not directly formed on the channel region, but the first buffer layer made of amorphous material is formed firstly, and then the ferroelectric layer is formed on the first buffer layer, when the ferroelectric layer grows on the first buffer layer made of amorphous material, the ferroelectric layer can preferentially grow into an orthorhombic phase structure with better ferroelectric characteristics due to the fact that particles of the first buffer layer are not periodically and repeatedly arranged; after the ferroelectric layer is formed, a second buffer layer is formed on the ferroelectric layer, and then a grid electrode is formed on the second buffer layer, so that the crystal orientation of the grid electrode does not influence the crystal phase orientation of the ferroelectric layer, and the ferroelectric layer can grow towards an orthorhombic phase under the action of the second buffer layer.

In a possible implementation manner of the sixth aspect, when forming the first buffer layer and/or the first buffer layer, the method includes: the first buffer layer and the second buffer layer are prepared by adopting a thin film deposition method.

In a possible implementation manner of the sixth aspect, when forming the first buffer layer and/or the second buffer layer, the method includes: the first buffer layer and the second buffer layer are made of at least one of an amorphous oxide and a semiconductor material.

In a possible implementation manner of the sixth aspect, the first buffer layer and/or the second buffer layer includes at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide, indium tin oxide, ruthenium oxide, iridium oxide, silicon, germanium, silicon germanium, and silicon nitride.

In a seventh aspect, the present application further provides an electronic device, including a processor and a ferroelectric memory in any one of the above first, second, third or fourth aspects, where the processor is electrically connected to the ferroelectric memory.

The electronic device provided by the embodiment of the application comprises the ferroelectric memory of the first aspect of the embodiment, the second aspect of the embodiment, the third aspect of the embodiment, the fourth aspect of the embodiment, the fifth aspect of the embodiment or the sixth aspect of the embodiment, so that the electronic device provided by the embodiment of the application and the ferroelectric memory of the technical scheme can solve the same technical problems and achieve the same expected effects.

Drawings

Fig. 1 is a process structure diagram of a ferroelectric capacitor of a FeRAM according to the prior art;

FIG. 2a is a diagram of a structural model of a monoclinic phase of a ferroelectric layer;

fig. 2b is a structural model diagram of a tetragonal phase of the ferroelectric layer;

FIG. 2c is a schematic diagram of a ferroelectric layer with an orthorhombic phase;

fig. 3a is a schematic diagram of an atomic arrangement of a ferroelectric layer and a first electrode;

fig. 3b is a schematic diagram of another atomic arrangement of the ferroelectric layer and the first electrode;

fig. 3c is a schematic diagram of an atomic arrangement of a ferroelectric layer and a first electrode;

fig. 4a is a block diagram of a substrate, ferroelectric layer and first electrode;

fig. 4b is a block diagram of another substrate, ferroelectric layer and first electrode;

fig. 4c is a block diagram of a further substrate, ferroelectric layer and first electrode;

fig. 5 is a circuit diagram of an electronic device according to an embodiment of the present application;

fig. 6 is a circuit diagram of a ferroelectric memory according to an embodiment of the present application;

fig. 7 is a circuit diagram of a memory cell in a ferroelectric memory according to an embodiment of the present application;

FIG. 8 is a circuit diagram of a memory array formed by a plurality of memory cells in a ferroelectric memory according to an embodiment of the present application;

fig. 9 is a circuit diagram of a memory cell in a ferroelectric memory according to an embodiment of the present application;

Fig. 10 is a circuit diagram of a memory array formed by a plurality of memory cells in a ferroelectric memory according to an embodiment of the present application;

FIG. 11 is a block diagram illustrating a process for fabricating a ferroelectric capacitor in a ferroelectric memory according to an embodiment of the present application;

fig. 12a to 12e are corresponding process structure diagrams in the preparation process of a ferroelectric capacitor according to the present application;

fig. 13a is a schematic diagram of an atomic arrangement of a ferroelectric layer and a first electrode according to an embodiment of the present application;

fig. 13b is a schematic diagram of another atomic arrangement of a ferroelectric layer and a first electrode according to an embodiment of the present application;

fig. 13c is a schematic diagram of an atomic arrangement of a ferroelectric layer and a first electrode according to an embodiment of the present application;

fig. 14a is a block diagram of a substrate, a ferroelectric layer, and a first electrode according to an embodiment of the present application;

fig. 14b is a block diagram of another substrate, ferroelectric layer, and first electrode provided in an embodiment of the present application;

fig. 14c is a block diagram of a further substrate, ferroelectric layer and first electrode provided in accordance with an embodiment of the present application;

FIG. 15a is a graph showing the polarization contrast of a ferroelectric memory according to the prior art and an embodiment of the present application;

FIG. 15b is a graph showing the polarization contrast of a ferroelectric memory according to the prior art and an embodiment of the present application;

Fig. 16 is a schematic diagram showing a positional relationship between a ferroelectric capacitor and a substrate in a ferroelectric memory according to an embodiment of the present application;

FIG. 17 is a schematic diagram showing a positional relationship between a ferroelectric capacitor and a substrate in a ferroelectric memory according to an embodiment of the present application;

FIG. 18 is a view in the B direction of FIG. 17;

fig. 19 is a process structure diagram of a memory cell in a ferroelectric memory according to an embodiment of the present application;

FIG. 20 is a circuit diagram of a memory array formed by a plurality of memory cells in a ferroelectric memory according to an embodiment of the present application;

fig. 21 is a block flow diagram of a memory cell fabricated in a ferroelectric memory according to an embodiment of the present application.

Reference numerals:

01-a first electrode; 02-a second electrode; 03-a ferroelectric layer; 04-a first buffer layer; 05-a second buffer layer; 06-gate;

100-a substrate; 100 a-a first doped region; 100 b-a second doped region; 100 c-channel region.

Detailed Description

Before describing the embodiments of the present application, technical terms related to the present application are described, specifically as follows:

amorphous: refers to an irregular shape and a fixed melting point, and the internal structure does not have long range order, but there is a structural ordered arrangement of matter in a small range of atomic distances. That is, amorphous is a material in which the internal particles do not have periodic repeating arrangements in three dimensions, have short range order, but do not have long range order.

A crystal: since a large number of microscopic substance units (atoms, ions, molecules, etc.) are orderly arranged according to a certain rule, the arrangement rule and crystal morphology can be studied and judged from the size of the structural units. That is, the crystal is a substance in which internal particles are periodically and repeatedly arranged in three-dimensional space.

Orientation of crystalline phases: generally refers to the directionality of covalent crystals, i.e. covalent bonds are formed in a specific direction, and according to the quantum theory of covalent bonds, the strength of covalent bonds depends on the degree of overlap of electron clouds, and due to the asymmetry of the electron distribution of non-full shells, bonds are always formed in the direction of the greatest electron cloud density. For example, the crystal phase orientation morphology includes monoclinic phase, tetragonal phase, orthorhombic phase, and the like.

Lattice constant: or lattice parameter, refers to the side length of the unit cell, i.e. the side length of each parallelepiped element, which is an important fundamental parameter of the crystal structure.

Crystallization temperature: at a certain temperature atoms will rearrange to reduce their chemical sites and convert to stable crystals, the process is called crystallization and the temperature at which crystallization occurs is called crystallization temperature.

Ferroelectric memories store data based on the ferroelectric effect of ferroelectric materials. Ferroelectric memories are expected to be a major competitor to DRAM due to their ultra-high memory density, low power consumption, and high speed. The memory cell in a ferroelectric memory comprises a ferroelectric capacitor comprising two electrodes and a ferroelectric material, such as a ferroelectric film layer, arranged between the two electrodes. Due to the non-linear nature of the ferroelectric material, the dielectric constant of the ferroelectric material can be adjusted, and the difference between before and after the polarization state of the ferroelectric film layer is reversed is very large, which makes the ferroelectric capacitor have a smaller volume compared with other capacitors, for example, the capacitor for storing charges in the DRAM is much smaller.

In ferroelectric memories, the ferroelectric layer may be formed using a common ferroelectric material. When an electric field is applied to the ferroelectric layer of the memory cell, the central atoms are stopped in a low energy state along the electric field, whereas when an electric field reversal is applied to the ferroelectric layer, the central atoms move in the crystal along the direction of the electric field and are stopped in another low energy state. A large number of central atoms are mobile-coupled in the crystal unit cell to form ferroelectric domains (ferroelectric domains), which form polarized charges under the action of an electric field. The ferroelectric domain has higher polarized charge formed by inversion under the electric field, the ferroelectric domain has lower polarized charge formed by non-inversion under the electric field, and the binary stable state of the ferroelectric material enables the ferroelectric to be used as a memory.

The embodiment of the application provides an electronic device comprising a ferroelectric memory. Fig. 5 shows an electronic device 200 according to an embodiment of the present application, where the electronic device 200 may be a terminal device, such as a mobile phone, a tablet computer, a smart band, or a personal computer (personal computer, PC), a server, a workstation, etc. The electronic device 200 includes a bus 205, a System On Chip (SOC) 210 and a read-only memory (ROM) 220 connected to the bus 205. The SOC210 may be used to process data, such as data of processing applications, process image data, and buffer temporary data. The ROM220 may be used to hold non-volatile data such as audio files, video files, and the like. ROM220 may be a PROM (programmable read-only memory), EPROM (erasable programmable read-only memory ), flash memory (flash memory), or the like.

In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240. The communication chip 230 may be used for processing the protocol stack, amplifying, filtering, etc. the analog radio frequency signal, or simultaneously implementing the above functions. The power management chip 240 may be used to power other chips.

In one embodiment, the SOC210 may include an application processor (application processor, AP) 211 for processing applications, an image processing unit (graphics processing unit, GPU) 212 for processing image data, and a random access memory (random access memory, RAM) 213 for caching data.

The AP211, GPU212, and RAM213 may be integrated into one die (die), or may be integrated into multiple dies (die), respectively, and packaged in a package structure, for example, using 2.5D (dimension), 3D packaging, or other advanced packaging techniques. In one embodiment, the AP211 and the GPU212 are integrated in one die, the RAM213 is integrated in another die, and the two die are packaged in a package structure, so as to obtain a faster inter-die data transmission rate and a higher data transmission bandwidth.

Fig. 6 is a schematic structural diagram of a ferroelectric memory 300 according to an embodiment of the present application. The ferroelectric memory 300 may be a RAM213 as shown in fig. 5, belonging to FeRAM. In one embodiment, ferroelectric memory 300 may also be a RAM disposed external to SOC 210. The present application does not limit the location of ferroelectric memory 300 in the device and the positional relationship with SOC 210.

Continuing with fig. 6, ferroelectric memory 300 includes memory array 310, decoder 320, driver 330, timing controller 340, buffer 350, and input-output driver 360. The memory array 310 includes a plurality of memory cells 400 arranged in an array, wherein each memory cell 400 may be used to store 1bit or more of data. The memory array 310 further includes Word Line (WL), bit Line (BL), and other signal lines. Each memory cell 400 is electrically connected to a corresponding word line WL, bit line BL. One or more of the word lines WL and the bit lines BL are used for selecting the memory cell 400 to be read and written in the memory array by receiving the control level output by the control circuit, so as to change the polarization direction of the ferroelectric capacitor in the memory cell 400, thereby realizing the data read and write operation.

In the ferroelectric memory 300 structure shown in fig. 6, the decoder 320 is used for decoding according to the received address to determine the memory cell 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby realizing access to the designated memory cell 400. The buffer 350 is used for buffering the read data, and may be, for example, a first-in first-out (FIFO) buffer. The timing controller 330 is used for controlling the timing of the buffer 350 and controlling the driver 330 to drive the signal lines in the memory array 310. The input-output driver 360 is used to drive transmission signals, such as to drive received data signals and to drive data signals to be transmitted, so that the data signals can be transmitted over a long distance.

The memory array 310, the decoder 320, the driver 330, the timing controller 340, the buffer 350, and the input/output driver 360 may be integrated into one chip or may be integrated into a plurality of chips.

The ferroelectric memory 300 according to the present application may be a ferroelectric random access memory (ferroelectric random access memory, feRAM) or a ferroelectric field effect transistor memory (ferroelectric filed-effect-transistor, feFET). For example, fig. 7 shows a circuit configuration diagram of one of the memory cells 400 of the FeRAM, as in fig. 7, the memory cell 400 includes at least two ferroelectric capacitors C and one transistor Tr, for example, fig. 7 exemplarily shows three ferroelectric capacitors (e.g., ferroelectric capacitor C1, ferroelectric capacitor C2, and ferroelectric capacitor C3 of fig. 7), and such a memory cell may be referred to as a 1TnC memory cell. The transistor Tr here may be a metal-oxide-semiconductor field-effect transistor (MOSFET).

In addition, the memory cell 400 further includes Word Line (WL), bit Line (BL), and Plate Line (PL) signal lines, and in the memory cell 400, a first terminal of the transistor Tr is electrically connected to the bit line BL, a control terminal of the transistor Tr is electrically connected to the word line WL, a second terminal of the transistor Tr is electrically connected to a first electrode of the ferroelectric capacitor C, and a second electrode of the ferroelectric capacitor C is electrically connected to the plate line PL.

In the present application, one of the drain (drain) or source (source) of the transistor Tr is referred to as a first terminal, the other is referred to as a second terminal, and the control terminal of the transistor Tr is a gate. The drain and source of the transistor Tr may be determined according to the flow direction of current, for example, in fig. 7, when the current is from left to right, the left end is the drain, the right end is the source, and conversely, when the current is from right to left, the right end is the drain, and the left end is the source.

It will be understood that the transistor Tr herein is a transistor device having three terminals, and then the transistor Tr may be selected from NMOS (N-channel metal oxide semiconductor ) transistors, or may be selected from PMOS (P-channel metal oxide semiconductor ) transistors.

One memory cell 400 shown in fig. 7 may be used to store multi-bit data to increase the storage capacity of each memory cell. In particular, the ferroelectric capacitors C share one transistor Tr, and thus, the number of transistors per memory cell 400 can be reduced to increase the memory density.

The memory array 310 may be obtained by arranging the memory cells 400 shown in fig. 7 according to an array configuration, where the circuit structure of each memory cell 400 is the same, for example, in the memory array 310 shown in fig. 8, a memory array including four memory cells of the memory cell 401, the memory cell 402, the memory cell 403 and the memory cell 404 is exemplarily shown. One skilled in the art can design the arrangement of the memory cells 400 and the number of memory cells 400 in the memory array 310 according to the storage capacity requirements of the ferroelectric memory. In one embodiment, the memory array 310 may further include more memory cells 400, and the memory cells 400 may be arranged in an X direction, a Y direction, and a Z direction perpendicular to each other to form a three-dimensional memory array.

In an alternative embodiment, in the memory array 310 shown in fig. 8, the word line WL extends in the X direction, and further, the control terminals of the transistors Tr of the plurality of memory cells arranged in the X direction are electrically connected to the same word line WL. The bit line BL extends in the Y direction perpendicular to the X direction, and thus the first ends of the transistors Tr of the plurality of memory cells arranged in the Y direction are electrically connected to the same bit line BL.

Fig. 9 shows a circuit configuration diagram of another memory cell 400 of FeRAM. In this memory cell 400, a first transistor Tr1 and a second transistor Tr2 are included, and at least two ferroelectric capacitors, for example, fig. 9 exemplarily shows that one memory cell 400 includes two ferroelectric capacitors, namely, a ferroelectric capacitor C1 and a ferroelectric capacitor C2. The ferroelectric capacitor C2 and the ferroelectric capacitor C1 have the same structure and each include two electrodes and a ferroelectric layer between the two electrodes. In order to facilitate the following description of the electrical connection relationship between the ferroelectric capacitor C2 and the ferroelectric capacitor C1 and other structures, one electrode of the ferroelectric capacitor C1 may be called a first electrode, the other electrode may be called a second electrode, and one electrode of the ferroelectric capacitor C2 may be called a third electrode, and the other electrode may be called a fourth electrode.

Referring again to fig. 9, the memory cell 400 further includes Word Lines (WL), write Bit Lines (WBL), read Bit Lines (RBL), source Lines (SL), and Control Lines (CL). The control terminal of the first transistor Tr1 is electrically connected to the control line CL, the first terminal of the first transistor Tr1 is electrically connected to the first electrode of the ferroelectric capacitor C1 and the third electrode of the ferroelectric capacitor C2, respectively, the second terminal of the first transistor Tr1 is electrically connected to the write bit line WBL, and the second electrode of the ferroelectric capacitor C1 and the fourth electrode of the ferroelectric capacitor C2 are electrically connected to the corresponding word line WL.

After a certain voltage difference is formed between the first electrode of the ferroelectric capacitor C1 and the word line WL1, that is, after a voltage difference is formed between the two ends of the ferroelectric capacitor C1, the polarization direction of the ferroelectric material in the ferroelectric capacitor is changed, so as to implement the read-write operation of data. Similarly, after a certain voltage difference is formed between the third electrode of the ferroelectric capacitor C2 and the word line WL2, that is, after a voltage difference is formed between the two ends of the ferroelectric capacitor C2, the polarization direction of the ferroelectric material in the ferroelectric capacitor is changed, so as to implement the read-write operation of data.

As shown in fig. 9, the first terminal of the second transistor Tr2 is electrically connected to the source line SL, the second terminal is electrically connected to the read bit line RBL, and the control terminal of the second transistor T2 is electrically connected to the first electrode of the ferroelectric capacitor C1 and the third electrode of the ferroelectric capacitor C2, respectively.

In an alternative embodiment, the memory array 310 shown in fig. 10 may be obtained by arranging the memory cells 400 shown in fig. 9 according to an array, for example, in the memory array 310 shown in fig. 10, a memory array including four memory cells, that is, a memory cell 401, a memory cell 402, a memory cell 403, and a memory cell 404 is exemplarily shown.

In the memory array 310 shown in fig. 10, two control lines, respectively, control line CL0 and control line CL1, are included, and each control line extends along the Y direction, and when the memory array 310 further includes more memory cells, then the corresponding memory array further includes more control lines CL, which are disposed in parallel along the X direction perpendicular to the Y direction, and further, the plurality of memory cells disposed along the Y direction may share one control line, for example, the memory cell 401 and the memory cell 404 share the selected control line CL0, and the memory cell 402 and the memory cell 403 share the control line CL1.

With continued reference to fig. 10, the memory array 310 includes two write bit lines, write bit line WBL0 and write bit line WBL1, respectively, and each write bit line extends along the X-direction, while further including more write bit lines WBL, the write bit lines WBL may be arranged in parallel along the Y-direction perpendicular to the X-direction, and further, a plurality of memory cells arranged along the X-direction may share one write bit line WBL, for example, memory cell 401 and memory cell 402 share write bit line WBL1, and memory cell 403 and memory cell 404 share write bit line WBL0.

Similarly, the read bit line RBL and the write bit line WBL are arranged in the same manner, and will not be described herein.

Note that, regarding the source line SL in this memory array, not only the source line SL of a plurality of memory cells laid in the X direction but also the source line SL of a plurality of memory cells laid in the Y direction are shared, for example, the source line SL of the memory cell 401 and the source line SL of the memory cell 404 here are shared, and the source line SL of the memory cell 401 and the source line SL of the memory cell 402 are also shared, that is, the source lines SL of the memory cell 401, the memory cell 402, the memory cell 403, and the memory cell 404 here are connected to each other. In an achievable process structure, a source line SL layer structure parallel to the substrate may be formed to electrically connect the source lines parallel to the substrate to each other.

Note that, regarding the word lines WL in this memory array, not only the word lines WL of a plurality of memory cells laid in the X direction but also the word lines WL of a plurality of memory cells laid in the Y direction are shared, for example, the word line WL0 connected to the ferroelectric capacitor C0 of the memory cell 401 and the word line WL0 connected to the ferroelectric capacitor C0 of the memory cell 402 are shared, and the word line WL0 connected to the ferroelectric capacitor C0 of the memory cell 401 and the word line WL0 connected to the ferroelectric capacitor C0 of the memory cell 404 are shared, that is, the word lines WL0 connected to the four ferroelectric capacitors C0 of the memory cell 401, the memory cell 402, the memory cell 403 and the memory cell 404 are connected to each other, that is, the word lines WL1 connected to the four ferroelectric capacitors C1 of the memory cell 401, the memory cell 402, the memory cell 403 and the memory cell 404 are connected to each other. Similarly, in an achievable process structure, a word line layer structure parallel to the substrate may be provided to interconnect word lines located in the same layer.

In the ferroelectric capacitors shown in fig. 7, 8, 9 and 10 described above, the stacked first and second electrodes are mainly included, and a ferroelectric layer as a memory medium is formed between the first and second electrodes.

In some alternative embodiments, the ferroelectric layer is made of a hafnium oxide based material. Compared with other ferroelectric materials, the thickness of the hafnium oxide-based ferroelectric capacitor can be reduced to ten nanometers or even subten nanometers, so that high-density integration or even three-dimensional integration can be realized, and the method has great advantages in the aspect of constructing an ultra-high density memory chip. In addition, the preparation process of the hafnium oxide-based ferroelectric capacitor can have good compatibility with a silicon-based semiconductor process, so that the ferroelectric capacitor can be prepared by using a mature manufacturing process without increasing the manufacturing cost.

The hafnium oxide-based material according to the present application refers to ferroelectric materials based on a hafnium oxide material system, such as silicon (Si) doped hafnium dioxide (HfO) ₂ ) Aluminum (Al) doped HfO ₂ Lanthanum (La) -doped HfO ₂ Yttrium (Y) doped HfO ₂ Gadolinium (Gd) -doped HfO ₂ Strontium (Sr) -doped HfO ₂ Etc.; or may be a hafnium zirconium oxide (hafnium zirconium oxide, HZO) system, for example, lanthanum (La) -doped HZO, yttrium (Y) -doped HZO, strontium (Sr) -doped HZO, gadolinium (Gd) -doped HZO, gadolinium lanthanum (Gd/La) -co-doped HZO, and the like.

When the crystal phase orientation of the ferroelectric layer made of the hafnium oxide base material is orthorhombic, the ferroelectric capacitor can show good ferroelectric property, and the storage performance of the ferroelectric memory can be better. In order to make the ferroelectric layer an orthorhombic phase, in some possible designs, the materials of the first electrode and the second electrode may be selected, for example, to be selected to have specific parameters of lattice structure, lattice constant, surface chemical property, etc. to promote the growth of the ferroelectric layer with an orthorhombic phase, but this may result in limited materials of the first electrode and the second electrode that may be selected, and may also present challenges to the ferroelectric layer growth process because the materials of the first electrode and the second electrode are both specific materials; the application provides a method for preparing a ferroelectric capacitor, when the ferroelectric capacitor is prepared by the method, a first electrode and a second electrode which are made of specific materials are not required to be selected, the ferroelectric capacitor with an orthorhombic phase can still be prepared without specific process conditions, and the ferroelectric layer is ensured to have better ferroelectric characteristics.

Fig. 11 shows a flowchart of one implementation of the ferroelectric capacitor forming method, and fig. 12a to 12e are block diagrams corresponding to each step in the ferroelectric capacitor forming method. The method comprises the following specific steps:

As in step S01 in fig. 11: forming a first electrode, a second electrode, a ferroelectric layer, a first buffer layer, and a second buffer layer on the substrate, with the ferroelectric layer formed between the first electrode and the second electrode, the first buffer layer formed between the first electrode and the ferroelectric layer, and the second buffer layer formed between the second electrode and the ferroelectric layer; wherein the first buffer layer and the second buffer layer are made of amorphous material, and the ferroelectric layer is made of material containing hafnium oxide-based material.

The first electrode, the second electrode, the ferroelectric layer, the first buffer layer and the second buffer layer herein may be fabricated on the substrate by a front-end-of-line process (front end of line, FEOL), for example, as shown in fig. 12a to 12 e; in other designs, the substrate may also be fabricated by back end of line (BEOL).

As in step S02 in fig. 11: annealing the first electrode, the second electrode, the ferroelectric layer, the first buffer layer and the second buffer layer to obtain a ferroelectric capacitor comprising the first electrode, the second electrode, the ferroelectric layer, the first buffer layer and the second buffer layer; the first buffer layer is used for inhibiting the first electrode from affecting the crystal phase orientation of the ferroelectric layer, the second buffer layer is used for inhibiting the second electrode from affecting the crystal phase orientation of the ferroelectric layer, and the first buffer layer and the second buffer layer enable the ferroelectric layer to be in orthorhombic phases.

The following describes the process flow that can be implemented in steps S01 and S02 of fig. 11 by taking the previous process as an example.

As shown in fig. 12a, a first electrode 01 is formed on a substrate 100.

The first electrode 01 may be made of more kinds of materials than the prior art, for example, titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), tungsten (W), ruthenium (Ru), molybdenum (Mo), iridium (Ir), nickel (Ni), platinum (Pt), tungsten (W), gold (Au), ruthenium oxide (RuO), iridium oxide (IrO), indium TiN Oxide (ITO), etc. may be selected instead of being limited to a specific material range as in the prior art.

The thickness dimension of the first electrode 01 in the stacking direction may be, but is not limited to, 1nm to 100nm, for example, 50nm may be selected.

As shown in fig. 12b, a first buffer layer 04 is formed on the side of the first electrode 01 remote from the substrate 100.

In forming the first buffer layer 04, the first buffer layer 04 is prepared using an amorphous structural material.

The first buffer layer 04 of amorphous structure may be made of various materials. By way of example, at least one of an amorphous oxide or a semiconductor material may be selected.

The amorphous oxide may be an oxide dielectric material. For example, titanium oxide (TiO ₂ ) Tungsten oxide (WO) ₃ ) Zirconium oxide (ZrO) ₂ ) Hafnium oxide (HfO) ₂ ) Alumina (Al) ₂ O ₃ ) Silicon oxide (SiO) ₂ ) At least one of (a) and (b);

the amorphous oxide may be an oxide conductive material. For example, at least one of Indium Tin Oxide (ITO), ruthenium oxide (RuO), iridium oxide (IrO) may be selected.

In some embodiments, the first electrode 01 and the first buffer layer 04 adjacent to each other may each be at least one of Indium Tin Oxide (ITO), ruthenium oxide (RuO), and iridium oxide (IrO). However, in a specific realizable process, when the first electrode 01 selects one of Indium Tin Oxide (ITO), ruthenium oxide (RuO), iridium oxide (IrO), the first buffer layer 04 may select the other one of Indium Tin Oxide (ITO), ruthenium oxide (RuO), iridium oxide (IrO), or a combination of the other two.

The amorphous semiconductor material may be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon nitride (Si) ₃ N ₄ ) At least one of them.

The thickness dimension of the first buffer layer 04 in the stacking direction may be, but is not limited to, 0.5nm to 50nm, for example, 1nm may be selected. That is, the first buffer layer 04 needs to be thin enough so that the amorphous material does not crystallize easily.

As shown in fig. 12c, the ferroelectric layer 03 is formed on the side of the first buffer layer 04 remote from the first electrode 01.

The ferroelectric layer 03 is made of a material containing a hafnium oxide based material, and the above description of the specific materials selected for the hafnium oxide based material has been omitted herein.

The thickness dimension of the ferroelectric layer 03 in the stacking direction may be, but is not limited to, 1nm to 20nm, for example, 10nm may be selected.

As shown in fig. 12d, a second buffer layer 05 is formed on the side of the ferroelectric layer 03 remote from the first buffer layer 04.

The optional material of the second buffer layer 05 may refer to the material of the first buffer layer 04 described above, and the materials of the first buffer layer 05 and the second buffer layer 04 may be the same or different. The thickness of the second buffer layer 05 may be equal to or different from the thickness of the first buffer layer 04.

As shown in fig. 12e, a second electrode 02 is formed on the side of the second buffer layer 05 remote from the ferroelectric layer 03.

The optional material of the second electrode 02 may be the same as or different from the material of the first electrode 01, and the materials of the second electrode 02 and the first electrode 01 may be the same. The thickness dimension of the second electrode 02 and the thickness dimension of the first electrode 01 may be equal or unequal.

As can be seen from fig. 12b and 12c, before forming the ferroelectric layer 03, the first buffer layer 04 is formed on the first electrode 01, and then the ferroelectric layer 03 is formed on the first buffer layer 04, instead of directly growing the ferroelectric layer 03 on the first electrode 01, and in addition, the first buffer layer 04 is made of amorphous material. That is, the ferroelectric layer 02 is grown on the amorphous structure as a template, so that the atomic arrangement and crystal phase orientation of the ferroelectric layer 02 are not affected by the material of the first electrode 01, so that the phenomenon that the crystal phase orientation of the ferroelectric layer 02 is consistent with that of the first electrode 01 and cannot be preferentially oriented is caused, and instead, an orthorhombic crystal phase with better ferroelectric property is preferentially selected on the template of the first buffer layer 04 with the amorphous structure.

Fig. 13a, 13b and 13c show three atomic arrangement model diagrams of the present application including the first electrode 01, the first buffer layer 04 and the ferroelectric layer 03, black circles show the atomic arrangement in the ferroelectric layer 03, and white circles show the atomic arrangement in the first electrode 01. The three model diagrams are merely exemplary illustrations, and do not constitute a specific limitation on the atomic arrangement of the first electrode 01, the first buffer layer 04, and the ferroelectric layer 03 of the present application. Wherein the ferroelectric layer 03 of fig. 13 a-13 c is selected from the same ferroelectric materials, e.g., lanthanum (La) -doped HfO ₂ The method comprises the steps of carrying out a first treatment on the surface of the The first electrode 01 in fig. 13a to 13c is made of a different conductive material; the first buffer layer 04 in fig. 13a to 13c may be made of different amorphous materials.

Since the first electrode 01 in fig. 13a to 13c is made of different conductive materials, the phenomenon that the atomic arrangement of the first electrode 01 in fig. 13a to 13c is different occurs, but since the first buffer layer 04 exists between the first electrode 01 and the ferroelectric layer 03, even though the materials of the first electrode 01 are different, different growth templates are provided, the atomic arrangement of the ferroelectric layer 03 is substantially uniform and is an orthorhombic crystal. It can be said that the first buffer layer 04 provides the ferroelectric layer 03 with a growth template by its amorphous structure, suppressing the influence of the first electrode 01 on the crystal phase orientation of the ferroelectric layer 03.

Fig. 14a, 14b and 14c show structural diagrams of the present application including a substrate 100, a first electrode 01, a first buffer layer 04 and a ferroelectric layer 03, and show grain sizes of the ferroelectric layer 03. The size of the grain size of the ferroelectric layer 03 here is also an exemplary illustration and does not constitute an absolute limitation of the grain size. The substrate 100 in fig. 14a to 14c is made of the same material, for example, a SrTiO3 substrate with 001 orientation; the ferroelectric materials selected for the ferroelectric layer 03 are also the same, for example, lanthanum (La) -doped HfO2 is selected; the conductive materials selected for the first electrode 01 are different; the first buffer layer 04 may be made of different amorphous structural materials.

Since the first buffer layer 04 exists between the first electrode 01 and the ferroelectric layer 03, even though the material of the first electrode 01 is different, no influence is given to the initial growth environment of the ferroelectric layer 03, and thus, as can be seen from comparison of fig. 14a, 14b and 14c, the grain size of the ferroelectric layer 03 is substantially uniform, and a phenomenon that the grain size in the ferroelectric layer 03 in fig. 14a is large or the grain size in the ferroelectric layer 03 in fig. 14b is small due to the difference of the material of the first electrode 01 does not occur. Therefore, the grain size of the ferroelectric layer 03 is comparable despite the material of the first electrode 01, and the crystal phase orientation of the ferroelectric layer is substantially uniform. It will also be appreciated that the introduction of the first buffer layer 04 may provide a similar initial growth environment for the growth of the hafnium oxide based ferroelectric layer 03 on the different first electrode 01 materials, thereby reducing uncertainty in the growth of the hafnium oxide based ferroelectric layer 03.

Based on the above description of the effect of the first buffer layer 04, it can be obtained that the material of the first electrode 01 does not affect the crystal phase orientation of the ferroelectric layer 03, so that the selection range can be enlarged when the material of the first electrode 01 is selected, and correspondingly, because the material of the first electrode 01 is not a specific material, the ferroelectric layer 04 does not need severe growth process conditions, thereby reducing the process difficulty of the ferroelectric capacitor, reducing the manufacturing cost and improving the production efficiency.

Also, when the ferroelectric capacitor is integrated on the substrate using the previous process shown in fig. 14a, 14b and 14c, there is no need to select a specific substrate 100, and thus the process of forming the ferroelectric capacitor can be well compatible with the silicon-based semiconductor manufacturing process.

In some embodiments, for example, the first buffer layer 04 employs amorphous titanium oxide (TiO ₂ ) When prepared, titanium oxide (TiO ₂ ) The crystallization temperature of the first buffer layer 04 is still in the form of an amorphous structure after the ferroelectric capacitor is formed by annealing, that is, the first buffer layer 04 still includes an amorphous structure after the ferroelectric capacitor is formed. In this way, in this embodiment, titanium oxide (TiO ₂ ) The amorphous structure of (a) suppresses the influence of the first electrode 01 on the crystal phase orientation of the ferroelectric layer 03, so that the hafnium oxide-based material ferroelectric layer03 implements an orthorhombic orientation.

In other embodiments, for example, the first buffer layer 04 employs amorphous zirconia (ZrO ₂ ) Hafnium oxide (HfO) ₂ ) Alumina (Al) ₂ O ₃ ) When at least one of the iso-oxides is formed, after the ferroelectric capacitor is formed by annealing, the first buffer layer 04 is partially crystallized, so that the first buffer layer 04 includes both amorphous structures and orthorhombic structures, and in this embodiment, the orthorhombic crystal structure can better assist the preferred orientation of the hafnium oxide-based material ferroelectric layer 03 to realize orthorhombic phases in addition to inhibiting the first electrode 01 from affecting the crystal phase orientation of the ferroelectric layer 03 by using the amorphous structures of these materials.

In other embodiments, for example, the first buffer layer 04 employs amorphous tungsten oxide (WO ₃ ) When prepared, titanium oxide (TiO ₂ ) The crystallization temperature of the first buffer layer 04 is lower than the highest process temperature of the formation of the ferroelectric capacitor, and after the ferroelectric capacitor is formed by annealing or the like, the first buffer layer 04 is crystallized such that the first buffer layer 04 includes a crystal structure of an orthorhombic phase, so that in this embodiment, tungsten oxide (WO ₃ ) The orthorhombic phase of the hafnium oxide-based material ferroelectric layer 03 is assisted to perform preferred orientation to realize orthorhombic phase.

Based on the above description of the optional different materials of the first buffer layer 04, it can be seen that, in the present application, the influence of the first electrode 01 on the crystal phase orientation of the ferroelectric layer 03 can be suppressed by using the amorphous structure and/or the orthorhombic structure of the first buffer layer 04, so that the ferroelectric layer 03 has the crystal structure of the orthorhombic phase.

In addition, as can be seen from fig. 12d and 12e, before forming the second electrode 02, the second buffer layer 05 is formed on the ferroelectric layer 03, and then the second electrode 02 is grown with the second buffer layer 05 of amorphous structure as a growth template, that is, the second electrode 02 is not directly grown on the ferroelectric layer 03. In this way, the crystal phase orientation of the ferroelectric layer 03 is not affected by the crystal structure of the second electrode 02 when the second electrode 02 is manufactured under high temperature process conditions, and by subsequent high temperature processes, such as annealing. Also, the second buffer layer 05 includes an amorphous structure and/or an orthorhombic phase structure, and the second buffer layer 05 suppresses the influence of the second electrode 02 on the crystal phase orientation of the ferroelectric layer 03 using the amorphous structure and/or the orthorhombic phase structure. That is, the ferroelectric layer 03 has an orthorhombic phase with good ferroelectric properties by the combined action of the first buffer layer 04 and the second buffer layer 05.

In the above-described process of manufacturing the ferroelectric capacitor, when forming the first electrode 01, the second electrode 02, or the ferroelectric layer 03, a magnetron sputtering method may be used for deposition, or a thin film deposition method, such as a deposition process of chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapour deposition, PVD), or atomic layer deposition (atomic layer deposition, ALD), may be used.

In forming the first buffer layer 04 or the second buffer layer 05, a thin film deposition method, such as a deposition process including chemical vapor deposition CVD, physical vapor deposition PVD, or atomic layer deposition ALD, may be used. Magnetron sputtering may also be used for deposition.

That is, the fabrication process of the first buffer layer 04 or the second buffer layer 05 herein may be compatible with the fabrication process of the first electrode 01, the second electrode 02, or the ferroelectric layer 03, so that other complicated fabrication processes are not introduced due to the addition of the two-layer structure of the first buffer layer 04 and the second buffer layer 05.

FIG. 15a shows a comparison of polarization intensity of a conventional FeRAM and a FeRAM according to the present application, wherein the left bar chart is a graph obtained by using no titanium oxide (TiO ₂ ) Polarization intensity of FeRAM in buffer layer, right bar chart shows that titanium oxide (TiO) is used in the present application ₂ ) The polarization of FeRAM when the first buffer layer 04 and the second buffer layer 05 are compared with each other, as can be seen from the two bar graphs, when titanium oxide (TiO ₂ ) When the first buffer layer 04 and the second buffer layer 05 are used, the polarization intensity is obviously improved, and the ferroelectric property is correspondingly improved.

In addition, FIG. 15b also shows the prior FeRAM and the pole of FeRAM provided by the present applicationThe intensity contrast graph, wherein the left bar graph is a graph of the prior art without tungsten oxide (WO ₃ ) Polarization intensity of FeRAM in buffer layer, the right bar chart shows that tungsten oxide is used in the present application (WO ₃ ) The polarization of FeRAM when the first buffer layer 04 and the second buffer layer 05 are similar to those of fig. 15a, when tungsten oxide is contained (WO ₃ ) When the first buffer layer 04 and the second buffer layer 05 are used, the polarization intensity is obviously improved, and the ferroelectric property is correspondingly improved.

In addition to the ability of the first buffer layer 04 to inhibit the first electrode 04 from affecting the crystal phase orientation of the ferroelectric layer 03, in some embodiments, the first buffer layer 04 may inhibit the diffusion of oxygen in the ferroelectric layer 03 into the first electrode 01, for example, when the first buffer layer 04 employs titanium oxide (TiO ₂ ) Tungsten oxide (WO) ₃ ) Alumina (Al) ₂ O ₃ ) The first buffer layer 04 can prevent oxygen in the ferroelectric layer 03 from diffusing into the first electrode 01, so as to avoid oxygen vacancies in the ferroelectric layer 03 and even leakage channels in the ferroelectric layer 03.

Similarly, the second buffer layer 05 may inhibit diffusion of oxygen element in the ferroelectric layer 03 into the second electrode 02 in some embodiments, in addition to the function of inhibiting the second electrode 02 from affecting the crystal phase orientation of the ferroelectric layer 03.

The ferroelectric capacitor according to the present application may be arranged on the substrate in various manners, for example, fig. 16 shows one of the ferroelectric capacitor arranged on the substrate 100, specifically, the first electrode 01, the first buffer layer 04, the ferroelectric layer 03, the second buffer 05 and the second electrode 02 are stacked in a direction perpendicular to the substrate 100. That is, each of the structures of the first electrode 01, the first buffer layer 04, the ferroelectric layer 03, the second buffer layer 05, and the second electrode 02 is arranged parallel to the substrate 100, such ferroelectric capacitor may be referred to as a planar ferroelectric capacitor structure. As another example, fig. 17 shows another arrangement manner of the ferroelectric capacitor on the substrate 100, and fig. 17 is a B-direction view in fig. 17, that is, the first electrode 01 extends along a direction perpendicular to the substrate 100, and the first buffer layer 04, the ferroelectric layer 03, the second buffer layer 05 and the second electrode 02 sequentially surround the periphery of the first electrode 01 along a direction parallel to the substrate 100, so that a columnar ferroelectric capacitor is formed, and a cross section of the columnar ferroelectric capacitor may be circular as shown in fig. 18, or may be rectangular, or may be other shapes.

As shown in fig. 19, fig. 19 is a process configuration diagram showing a memory cell in a ferroelectric field effect transistor memory (FeFET) in a ferroelectric memory according to the present application. Wherein the memory cell comprises a first doped region 100a and a second doped region 100b formed in a substrate 100, a channel region 100c located between the first doped region 100a and the second doped region 100b, a ferroelectric layer 03 formed on the channel region 100c, and a gate 06 formed on a side of the ferroelectric layer 03 remote from the substrate 100, and wherein the ferroelectric layer 03 comprises a hafnium oxide based material.

In addition, continuing with fig. 19, the memory cell further includes a first buffer layer 04 formed between the ferroelectric layer 03 and the channel region 100c, and a second buffer layer 05 formed between the ferroelectric layer 03 and the gate electrode 06; here, the first buffer layer 04 and the second buffer layer 05 are the same as the first buffer layer 04 and the second buffer layer 05 in the ferroelectric capacitor of the FeRAM described above, that is, the first buffer layer 04 also includes an amorphous structure and/or an orthorhombic structure, the second buffer layer 05 also includes an amorphous structure and/or an orthorhombic structure, the first buffer layer 04 in fig. 19 suppresses the channel region 100c from affecting the crystal phase orientation of the ferroelectric layer 03 by using the amorphous structure and/or the orthorhombic structure thereof, and the second buffer layer 05 suppresses the gate 06 from affecting the crystal phase orientation of the ferroelectric layer 03 by using the amorphous structure and/or the orthorhombic structure thereof, that is, the first buffer layer 04 and the second buffer layer 05 make the ferroelectric layer 03 in an orthorhombic phase.

In some alternative embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate in the form of a P-type.

In the substrate 100, the first doped region 100a and the second doped region 100b having the same doping type may be formed by a doping process, for example, the first doped region 100a and the second doped region 100b may each be N-type. One of the first and second doped regions 100a and 100b forms a Source (Source) and the other one forms a Drain (Drain).

The hafnium oxide-based material for the ferroelectric layer 03 in fig. 19 may be the material that is selectable for the ferroelectric layer 03 in the FeRAM described above, and will not be described here.

In some designs, the gate 06 may be made of polysilicon (poly-Si, p-Si) or may be made of a metal material.

The optional materials of the first buffer layer 04 and the second buffer layer 05 in fig. 19 may refer to the optional materials of the above FeRAM for the buffer layer, and will not be described herein.

In the memory cell shown in fig. 19, the memory cell further includes a word line WL, a bit line BL, and a source line SL, wherein the gate 07 is electrically connected to the word line WL, the first doped region 100a is electrically connected to the bit line BL, and the second doped region 100b is electrically connected to the source line SL.

Fig. 20 shows a circuit diagram of a memory array 310 including the memory cells shown in fig. 19, and in the memory array 310 shown in fig. 20, four memory cells, that is, a memory cell 401, a memory cell 402, a memory cell 403, and a memory cell 404, are exemplarily shown, and a word line WL extends in the X direction, and further, gates of a plurality of memory cells arranged in the X direction are electrically connected to the same word line WL. The bit line BL extends in the Y direction perpendicular to the X direction, and thus the first doped regions 100a of the plurality of memory cells arranged in the Y direction are electrically connected to the same bit line BL. The source line SL extends in a Y direction perpendicular to the X direction, and the second doped regions 100b of the plurality of memory cells arranged in the Y direction are electrically connected to the same source line SL.

The application also provides a forming method for forming the memory cell shown in fig. 19, and fig. 21 shows a flowchart which can be implemented in the forming method. The method comprises the following specific steps:

step S11: forming a first doped region, a second doped region in the substrate, and forming a ferroelectric layer, a gate electrode, a first buffer layer and a second buffer layer on the substrate, wherein the ferroelectric layer is formed on a channel region between the first doped region and the second doped region, the gate electrode is formed on one side of the ferroelectric layer away from the substrate, the first buffer layer is formed between the ferroelectric layer and the channel region, and the second buffer layer is formed between the ferroelectric layer and the gate electrode; wherein the first buffer layer and the second buffer layer are made of amorphous material, and the ferroelectric layer is made of material containing hafnium oxide-based material.

Step S12: and annealing the gate electrode, the ferroelectric layer, the first buffer layer and the second buffer layer, wherein the first buffer layer is used for inhibiting the channel region from affecting the crystal phase orientation of the ferroelectric layer, the second buffer layer is used for inhibiting the gate electrode from affecting the crystal phase orientation of the ferroelectric layer, and the first buffer layer and the second buffer layer enable the ferroelectric layer to be in an orthorhombic phase.

Similar to the ferroelectric capacitor of the FeRAM prepared as described above, the ferroelectric layer 03 is not grown directly over the channel region 100c of the substrate 100, but the first buffer layer 04 of amorphous material is grown over the channel region 100c first, and the ferroelectric layer 03 is grown thereon using the amorphous first buffer layer 04 as a template. By such design, the atomic arrangement of the channel region 100c does not affect the atomic arrangement of the ferroelectric layer 03, and thus the ferroelectric layer 03 does not grow in a direction similar to the atomic arrangement of the channel region 100c, but an orthorhombic phase with better ferroelectric properties is preferentially selected by taking an amorphous structure as a template.

The crystal phase orientation based on the ferroelectric layer 03 is not affected by the substrate 100, so that a specific substrate 100 material is not required to be selected, and the selection range of the substrate 100 can be expanded to meet different application scenes.

Also, when the materials for preparing the first buffer layer 04 are different in amorphous structure, the first buffer layer 04 may still exist in amorphous structure after the preparation of the memory cell is completed, for example, the first buffer layer 04 adopts titanium oxide (TiO ₂ ) When in preparation; in some alternative embodiments, the first buffer layer 04 may include not only an amorphous structure but also a crystal structure of an orthorhombic phase, for example, the first buffer layer 04 employs zirconium oxide (ZrO ₂ ) Hafnium oxide (HfO) ₂ ) Alumina (Al) ₂ O ₃ ) When in preparation; in other alternative embodiments, the first buffer layer 04 includes orthogonalThe crystal structure of the crystal phase, for example, the first buffer layer 04 adopts tungsten oxide of amorphous structure (WO ₃ ) When in preparation.

In summary, the first electrode 01 can be isolated regardless of the amorphous structure of the first buffer layer 04 or the orthorhombic phase of the first buffer layer 04, and the influence of the first electrode 01 on the crystal phase orientation of the ferroelectric layer 03 can be suppressed, but the ferroelectric layer 03 can be caused to grow into an orthorhombic phase having a better ferroelectric property.

Before forming the gate 06, the gate 06 is not grown directly on the ferroelectric layer 03, but the second buffer layer 05 is grown on the ferroelectric layer 03, and then the gate 06 is grown on the second buffer layer 05. In this way, the crystal phase orientation of the ferroelectric layer 03 is not affected by the crystal structure of the gate electrode 06 when the gate electrode 06 is manufactured under high temperature process conditions, and by subsequent high temperature processes, such as annealing.

In the process of manufacturing the memory cell, the ferroelectric layer 03 and the gate 06 may be manufactured by using a magnetron sputtering method, or may be manufactured by using a chemical vapor deposition, a physical vapor deposition, or an atomic layer deposition. The first buffer layer 04 and the second buffer layer 05 can be manufactured by adopting a process compatible with the ferroelectric layer 03 and the gate 06, so that the process difficulty of the memory cell can be reduced, and the manufacturing efficiency can be improved.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. The scope of the application should therefore be determined by the scope of the claims.

Claims

A ferroelectric memory, comprising:

a substrate;

a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric capacitor;

wherein the ferroelectric capacitor comprises:

a first electrode and a second electrode;

a ferroelectric layer formed between the first electrode and the second electrode, the ferroelectric layer comprising a hafnium oxide based material;

a first buffer layer formed between the first electrode and the ferroelectric layer, the first buffer layer including an amorphous structure and/or an orthorhombic structure;

a second buffer layer formed between the second electrode and the ferroelectric layer, the second buffer layer including an amorphous structure and/or an orthorhombic structure;

the first buffer layer is used for inhibiting the first electrode from affecting the crystal phase orientation of the ferroelectric layer, the second buffer layer is used for inhibiting the second electrode from affecting the crystal phase orientation of the ferroelectric layer, and the first buffer layer and the second buffer layer enable the ferroelectric layer to be in an orthorhombic phase.
The ferroelectric memory of claim 1, wherein the first buffer layer and/or the second buffer layer comprises at least one of an oxide and a semiconductor material.
The ferroelectric memory of claim 2, wherein the first buffer layer and/or the second buffer layer comprises an oxide dielectric material.
The ferroelectric memory according to claim 3, wherein the first buffer layer and/or the second buffer layer comprises at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide.
The ferroelectric memory of claim 2, wherein the first buffer layer and/or the second buffer layer comprises an oxide conductive material.
The ferroelectric memory according to claim 5, wherein the first buffer layer and/or the second buffer layer comprises at least one of indium tin oxide, ruthenium oxide, iridium oxide.
The ferroelectric memory according to claim 2, wherein the first buffer layer and/or the second buffer layer comprises at least one of silicon, germanium, silicon nitride.
The ferroelectric memory of any one of claims 1-6, wherein the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer, and the second electrode are stacked in a direction parallel to the substrate.
The ferroelectric memory of any one of claims 1-8, wherein each of the memory cells further comprises a first transistor, a second transistor, a control line, a write bit line, a read bit line, and a source line, and a word line;

the control end of the first transistor is electrically connected with the control line, the first end of the first transistor is electrically connected with the first electrode, and the second end of the first transistor is electrically connected with the write bit line;

the control end of the second transistor is electrically connected with the first electrode, the first end of the second transistor is electrically connected with the source line, and the second end of the second transistor is electrically connected with the read bit line;

the second electrode is electrically connected to the word line.
The ferroelectric memory according to any one of claims 1 to 9, wherein a thickness of the first buffer layer and/or the second buffer layer in a stacking direction of the first electrode and the second electrode is 0.5nm to 5nm.
A ferroelectric memory, comprising:

a substrate;

a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric capacitor;

wherein the ferroelectric capacitor comprises:

A first electrode and a second electrode;

a ferroelectric layer formed between the first electrode and the second electrode, the ferroelectric layer comprising a hafnium oxide based material;

a first buffer layer formed between the first electrode and the ferroelectric layer, the first buffer layer including an amorphous structure and/or an orthorhombic structure;

a second buffer layer formed between the second electrode and the ferroelectric layer, the second buffer layer including an amorphous structure and/or an orthorhombic structure;

the first buffer layer and/or the second buffer layer comprises at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide, indium tin oxide, ruthenium oxide, iridium oxide, silicon, germanium, silicon germanium, and silicon nitride.
The ferroelectric memory of claim 11, wherein the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer, and the second electrode are stacked in a direction perpendicular to the substrate.
The ferroelectric memory of claim 11, wherein the first electrode, the first buffer layer, the ferroelectric layer, the second buffer layer, and the second electrode are stacked in a direction parallel to the substrate.
The ferroelectric memory according to any one of claims 11 to 13, wherein a thickness of the first buffer layer and/or the second buffer layer in a stacking direction of the first electrode and the second electrode is 0.5nm to 5nm.
A method of forming a ferroelectric memory, the method comprising:

forming a first electrode, a second electrode, a ferroelectric layer, a first buffer layer, and a second buffer layer on a substrate, wherein the ferroelectric layer is formed between the first electrode and the second electrode, the first buffer layer is formed between the first electrode and the ferroelectric layer, and the second buffer layer is formed between the second electrode and the ferroelectric layer, wherein the first buffer layer and the second buffer layer are made of an amorphous material, and the ferroelectric layer is made of a material containing a hafnium oxide-based material;

annealing the first electrode, the second electrode, the ferroelectric layer, the first buffer layer and the second buffer layer to obtain a ferroelectric capacitor comprising the first electrode, the second electrode, the ferroelectric layer, the first buffer layer and the second buffer layer; the first buffer layer is used for inhibiting the first electrode from affecting the crystal phase orientation of the ferroelectric layer, the second buffer layer is used for inhibiting the second electrode from affecting the crystal phase orientation of the ferroelectric layer, and the first buffer layer and the second buffer layer enable the ferroelectric layer to be in an orthorhombic phase.
The method of forming a ferroelectric memory according to claim 15, wherein forming the first buffer layer and/or the second buffer layer comprises: the first buffer layer and the second buffer layer are made of at least one of an amorphous oxide and a semiconductor material.
The method of forming a ferroelectric memory according to claim 15 or 16, wherein the first buffer layer and/or the second buffer layer comprises at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide, indium tin oxide, ruthenium oxide, iridium oxide, silicon, germanium, silicon nitride.
A ferroelectric memory, comprising:

a substrate;

a plurality of memory cells formed on the substrate, each of the memory cells comprising:

a first doped region and a second doped region formed in the substrate;

a channel region between the first doped region and the second doped region;

a ferroelectric layer formed on the channel region, the ferroelectric layer comprising a hafnium oxide based material;

a gate electrode formed on a side of the ferroelectric layer remote from the substrate;

a first buffer layer formed between the ferroelectric layer and the channel region, the first buffer layer including an amorphous structure and/or an orthorhombic structure;

A second buffer layer formed between the ferroelectric layer and the gate electrode, the second buffer layer including an amorphous structure and/or an orthorhombic structure;

the first buffer layer is used for inhibiting the channel region from affecting the crystal phase orientation of the ferroelectric layer, the second buffer layer is used for inhibiting the grid from affecting the crystal phase orientation of the ferroelectric layer, and the first buffer layer and the second buffer layer enable the ferroelectric layer to be in an orthorhombic phase.
The ferroelectric memory of claim 18, wherein the first buffer layer and/or the second buffer layer comprises at least one of an oxide and a semiconductor material.
The ferroelectric memory of claim 19, wherein the first buffer layer and/or the second buffer layer comprises an oxide dielectric material.
The ferroelectric memory of claim 20, wherein the first buffer layer and/or the second buffer layer comprises at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide.
The ferroelectric memory of claim 19, wherein the first buffer layer and/or the second buffer layer comprises an oxide conductive material.
The ferroelectric memory of claim 22, wherein the first buffer layer and/or the second buffer layer comprises at least one of indium tin oxide, ruthenium oxide, iridium oxide.
The ferroelectric memory of claim 19, wherein the first buffer layer and/or the second buffer layer comprises at least one of silicon, germanium, silicon nitride.
The ferroelectric memory of any one of claims 18-24, wherein each of the memory cells further comprises: word lines, bit lines, and source lines;

the gate is electrically connected with the word line, the first doped region is electrically connected with the bit line, and the second doped region is electrically connected with the source line.
The ferroelectric memory of any one of claims 18-25, wherein a thickness of the first buffer layer and/or the second buffer layer in a stacking direction of the ferroelectric layer and the gate electrode is 0.5nm-5nm.
A ferroelectric memory, comprising:

a substrate;

a plurality of memory cells formed on the substrate, each of the memory cells comprising:

a first doped region and a second doped region formed in the substrate;

A channel region between the first doped region and the second doped region;

a ferroelectric layer formed on the channel region, the ferroelectric layer comprising a hafnium oxide based material;

a gate electrode formed on a side of the ferroelectric layer remote from the substrate;

a first buffer layer formed between the ferroelectric layer and the channel region, the first buffer layer including an amorphous structure and/or an orthorhombic structure;

a second buffer layer formed between the ferroelectric layer and the gate electrode, the second buffer layer including an amorphous structure and/or an orthorhombic structure;

the first buffer layer and/or the second buffer layer comprises at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide, indium tin oxide, ruthenium oxide, iridium oxide, silicon, germanium, silicon germanium, and silicon nitride.
The ferroelectric memory of claim 27, wherein each of said memory cells further comprises: word lines, bit lines, and source lines;

the gate is electrically connected with the word line, the first doped region is electrically connected with the bit line, and the second doped region is electrically connected with the source line.
The ferroelectric memory according to claim 27 or 28, wherein a thickness of the first buffer layer and/or the second buffer layer in a stacking direction of the ferroelectric layer and the gate electrode is 0.5nm to 5nm.
A method of forming a ferroelectric memory, the method comprising:

forming a first doped region, a second doped region in a substrate, and forming a ferroelectric layer, a gate electrode, a first buffer layer and a second buffer layer on the substrate, wherein the ferroelectric layer is formed on a channel region between the first doped region and the second doped region, the gate electrode is formed on a side of the ferroelectric layer away from the substrate, a first buffer layer is formed between the ferroelectric layer and the channel region, and a second buffer layer is formed between the ferroelectric layer and the gate electrode, wherein the first buffer layer and the second buffer layer are made of an amorphous material, and the ferroelectric layer is made of a material containing a hafnium oxide-based material;

and annealing the grid electrode, the ferroelectric layer, the first buffer layer and the second buffer layer, wherein the first buffer layer is used for inhibiting the channel region from affecting the crystal phase orientation of the ferroelectric layer, the second buffer layer is used for inhibiting the grid electrode from affecting the crystal phase orientation of the ferroelectric layer, and the first buffer layer and the second buffer layer enable the ferroelectric layer to be in an orthorhombic phase.
The method of forming a ferroelectric memory according to claim 30, wherein forming the first buffer layer and/or the second buffer layer comprises: the first buffer layer and the second buffer layer are made of at least one of an amorphous oxide and a semiconductor material.
The method of claim 30 or 31, wherein the first buffer layer and/or the second buffer layer comprises at least one of titanium oxide, tungsten oxide, zirconium oxide, hafnium oxide, aluminum oxide, silicon oxide, indium tin oxide, ruthenium oxide, iridium oxide, silicon, germanium, silicon germanium, and silicon nitride.
An electronic device, comprising:

a processor; and

ferroelectric memory according to any one of claims 1 to 14, ferroelectric memory manufactured by a method of forming a ferroelectric memory according to any one of claims 15 to 17, ferroelectric memory according to any one of claims 18 to 29, or ferroelectric memory manufactured by a method of forming a ferroelectric memory according to any one of claims 30 to 32;

wherein the processor and the ferroelectric memory are electrically connected.