CN117012815A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN117012815A
CN117012815A CN202211083313.9A CN202211083313A CN117012815A CN 117012815 A CN117012815 A CN 117012815A CN 202211083313 A CN202211083313 A CN 202211083313A CN 117012815 A CN117012815 A CN 117012815A
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China
Prior art keywords
well
diffusion region
semiconductor structure
doping concentration
diffusion
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Chinese (zh)
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陈柏安
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Nuvoton Technology Corp
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Nuvoton Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application discloses a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a substrate, a first well, a second well, a third well, a fourth well, a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region and a grid structure. The first well and the second well are formed on the substrate and are in contact. The third well is formed in the second well. The fourth well is formed in the third well. The first diffusion region and the second diffusion region are far away from each other and are formed in the fourth well. The third diffusion region and the fourth diffusion region are far away from each other and are formed in the third well. The fifth diffusion region and the sixth diffusion region are formed in the first well. The gate structure is formed over the first well and the second well. The application can obviously improve the efficiency of the transverse insulated gate bipolar transistor.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present application relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor structure of a lateral igbt and a method for fabricating the same.
Background
A lateral insulated gate bipolar transistor (Lateral Insulated Gate Bipolar Transistor, LIGBT) is a minority carrier component with high input impedance and high current drive capability. Many designers consider lateral igbt as a voltage controlled bipolar device having both the input characteristics of Metal Oxide Semiconductor (MOS) and the output characteristics of bipolar junction transistors (bipolar junction transistor, BJT). The lateral igbt integrates the functions of a power mos and a bipolar junction transistor device, and combines the best advantages of both to achieve the best device characteristics.
Disclosure of Invention
The application discloses a semiconductor structure and a manufacturing method thereof, which are used for forming a transverse insulated gate bipolar transistor. The lateral insulated gate bipolar transistor provided by the application can effectively inhibit rebound phenomenon when the voltage of the collector terminal is greater than that of the emitter terminal, and provide a path for discharging charges of the emitter terminal to the collector terminal when the voltage of the emitter terminal is greater than that of the collector terminal, so that the efficiency of the lateral insulated gate bipolar transistor is obviously improved.
In view of the above, the present application provides a semiconductor structure including a substrate, a first well, a second well, a third well, a fourth well, a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, and a gate structure. The first well is formed on the substrate. The second well is formed on the substrate and is in contact with the first well. The third well is formed in the second well. The fourth well is formed in the third well. The first diffusion region is formed in the fourth well. The second diffusion region is formed in the fourth well and is away from the first diffusion region. The third diffusion region is formed in the third well. The fourth diffusion region is formed in the third well and is away from the third diffusion region. The fifth diffusion region is formed in the first well. The sixth diffusion region is formed in the first well, and the sixth diffusion region is in contact with the fifth diffusion region. The gate structure is formed on the first well and the second well.
According to an embodiment of the present application, the first well, the fourth well, the first diffusion region, the fourth diffusion region, the fifth diffusion region, and the substrate have a first conductivity type, and the second well, the third well, the second diffusion region, the third diffusion region, and the sixth diffusion region have a second conductivity type.
According to an embodiment of the present application, the first conductivity type is P-type, and the second conductivity type is N-type.
According to an embodiment of the present application, the doping concentration of the first well is similar to the doping concentration of the fourth well and is greater than the doping concentration of the substrate; the doping concentration of the first well is similar to that of the fourth well, and the method comprises the following steps: the doping concentration of the fourth well is similar to that of the first well.
According to an embodiment of the present application, a doping concentration of the second well is smaller than a doping concentration of the third well.
According to an embodiment of the present application, the first diffusion region and the second diffusion region are arranged along a first direction, the third diffusion region and the fourth diffusion region are arranged along the first direction, and the fifth diffusion region and the sixth diffusion region are arranged along the first direction. The first diffusion region and the third diffusion region are arranged along a second direction, and the second diffusion region and the fourth diffusion region are arranged along the second direction. The first direction is different from the second direction.
According to an embodiment of the present application, the semiconductor structure further includes an isolation structure. The isolation structure is formed between the first diffusion region and the second diffusion region and between the third diffusion region and the fourth diffusion region.
According to an embodiment of the present application, the first diffusion region and the third diffusion region are electrically connected to each other and are in a floating state.
According to an embodiment of the present application, the semiconductor structure is used to form a lateral igbt. The second diffusion region and the fourth diffusion region are electrically connected to each other to form a collector terminal, the fifth diffusion region and the sixth diffusion region are electrically connected to each other to form an emitter terminal, and the gate structure forms a gate terminal.
According to an embodiment of the present application, when the voltage of the collector is greater than the voltage of the emitter, the second diffusion region and the fourth well are reverse biased to suppress a snapback (snapback) phenomenon generated by the lateral igbt.
According to an embodiment of the present application, when the voltage of the collector is smaller than the voltage of the emitter, the charge of the emitter is discharged to the collector through the path from the first well to the second diffusion region.
The application further provides a manufacturing method for forming a semiconductor structure. The manufacturing method comprises providing a substrate; forming a first well on the substrate; forming a second well on the substrate. The first well and the second well are in contact; forming a third well in the second well; forming a fourth well in the third well; forming a first diffusion region in the fourth well; forming a second diffusion region in the fourth well. The second diffusion region and the first diffusion region are far away from each other; forming a third diffusion region in the third well; and forming a fourth diffusion region in the third well. The fourth diffusion region and the third diffusion region are far away from each other; forming a fifth diffusion region in the first well; a sixth diffusion region is formed in the first well. The sixth diffusion region is in contact with the fifth diffusion region; and forming a gate structure on the first well and the second well.
According to an embodiment of the present application, the first well, the fourth well, the first diffusion region, the fourth diffusion region, the fifth diffusion region, and the substrate have a first conductivity type, and the second well, the third well, the second diffusion region, the third diffusion region, and the sixth diffusion region have a second conductivity type.
According to an embodiment of the present application, the doping concentration of the first well is similar to the doping concentration of the fourth well and is greater than the doping concentration of the substrate; the doping concentration of the first well is similar to that of the fourth well, and the method comprises the following steps: the doping concentration of the fourth well is similar to that of the first well.
According to an embodiment of the present application, a doping concentration of the second well is smaller than a doping concentration of the third well.
According to an embodiment of the present application, the first diffusion region and the second diffusion region are arranged along a first direction, the third diffusion region and the fourth diffusion region are arranged along the first direction, and the fifth diffusion region and the sixth diffusion region are arranged along the first direction. The first diffusion region and the third diffusion region are arranged along a second direction, and the second diffusion region and the fourth diffusion region are arranged along the second direction. The first direction is different from the second direction.
According to an embodiment of the present application, the manufacturing method further includes forming an isolation structure. The isolation structure is located between the first diffusion region and the second diffusion region and between the third diffusion region and the fourth diffusion region.
According to an embodiment of the present application, the first diffusion region and the third diffusion region are electrically connected to each other and are in a floating state.
According to an embodiment of the present application, the semiconductor structure is used to form a lateral igbt. The second diffusion region and the fourth diffusion region are electrically connected to each other to form a collector terminal, the fifth diffusion region and the sixth diffusion region are electrically connected to each other to form an emitter terminal, and the gate structure forms a gate terminal.
According to an embodiment of the present application, when the voltage of the collector is greater than the voltage of the emitter, the second diffusion region and the fourth well are reverse biased to suppress a snapback (snapback) phenomenon generated by the lateral igbt. When the voltage of the collector is smaller than the voltage of the emitter, the charge of the emitter is discharged to the collector through the path from the first well to the second diffusion region.
Drawings
FIG. 1 shows a top view of a semiconductor structure according to an embodiment of the present application;
fig. 2 shows a cross-sectional view of the semiconductor structure of fig. 1 along the dashed line A-A' in accordance with the present application;
fig. 3 shows a top view of a semiconductor structure according to another embodiment of the application;
FIG. 4 illustrates a cross-sectional view of the semiconductor structure of FIG. 3 along the dashed line B-B' in accordance with the present application;
fig. 5 shows a cross-sectional view of the semiconductor structure of fig. 3 along the dashed line D-D' in accordance with the present application;
FIGS. 6A-6G are flow charts illustrating a method of fabricating a semiconductor structure according to one embodiment of the present application; and
fig. 7 shows a top view of a semiconductor structure according to another embodiment of the application.
Reference numerals
100,300 semiconductor structure
110 grid structure
SUB substrate
BOX buried oxide layer
W1 first well
W2 second well
W3:third well
W4 fourth well
DF1 first diffusion region
DF2 second diffusion region
DF3 third diffusion region
DF4 fourth diffusion zone
DF5 fifth diffusion region
DF6 sixth diffusion region
DF7 seventh diffusion region
DF8 eighth diffusion region
ISO isolation structure
Collector terminal
G: gate terminal
E emitter end
BJT1 first parasitic bipolar junction transistor
BJT2 second parasitic bipolar junction transistor
Detailed Description
The component substrate, the semiconductor device, and the method of manufacturing the semiconductor device according to some embodiments of the present application are described in detail below. It is to be understood that the following description provides many different embodiments, or examples, for implementing different aspects of some embodiments of the application. The specific components and arrangements described below are only for simplicity and clarity in describing some embodiments of the present application. These are, of course, merely examples and are not intended to be limiting. Furthermore, repeated reference numerals or designations may be used in the various embodiments. These repetition are for the purpose of simplicity and clarity in connection with the description of some embodiments of the application and do not in itself represent any relationship between the various embodiments and/or configurations discussed. Furthermore, when a first material layer is described as being on or over a second material layer, this includes situations where the first material layer is in direct contact with the second material layer. Alternatively, one or more other material layers may be spaced apart, in which case there may not be direct contact between the first material layer and the second material layer.
Moreover, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in embodiments to describe one component's relative relationship to another component of the drawing. It will be appreciated that if the device of the drawings is turned upside down, the components recited on the "lower" side will be components on the "upper" side.
The terms "about", "approximately" and "approximately" herein generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The amounts given herein are about amounts, i.e., where "about", "about" or "approximately" is not specifically recited, the meaning of "about", "about" or "approximately" may still be implied.
It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms, and these terms are used solely to distinguish between different elements, components, regions, layers, and/or sections. Thus, a first element, component, region, layer, and/or section discussed below could be termed a second element, component, region, layer, and/or section without departing from the teachings of some embodiments of the present application.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be appreciated that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present application and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Some embodiments of the application may be understood together with the drawings, which form a part of the description of embodiments of the application. It should be understood that the drawings of embodiments of the present application are not drawn to scale from actual devices and components. The shapes and thicknesses of embodiments may be exaggerated in the drawings in order to clearly show features of embodiments of the present application. Furthermore, the structures and devices are schematically depicted in the drawings in order to clearly demonstrate the features of the embodiments of the present application.
In some embodiments of the application, relative terms such as "lower," "upper," "horizontal," "vertical," "below," "over," "top," "bottom," and the like are to be construed as referring to the orientation depicted in this section and the associated drawings. This relative term is for convenience of description only and is not intended to represent that the device described is manufactured or operated in a particular orientation. In contrast, terms such as "connected," "interconnected," and the like, refer to two structures as being in direct contact, or to two structures as not being in direct contact, unless otherwise specified, wherein other structures are provided between the two structures. And the term coupled, connected, may also include situations where both structures are movable, or where both structures are fixed.
Embodiments of the present application disclose semiconductor device embodiments, and may be included in integrated circuits (integrated circuit, ICs) such as microprocessors, memory elements, and/or other components. The integrated circuits may also include various passive and active microelectronic components such as thin film resistors (thin film resistors), other types of capacitors such as Metal-insulator-Metal capacitors (MIMCAP), inductors, diodes, metal-Oxide-semiconductor field effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (bipolar junction transistors, BJTs), laterally diffused MOS transistors, high power MOS transistors, or other types of transistors. Those skilled in the art will appreciate that semiconductor devices may also be used to include other types of semiconductor components in integrated circuits.
Fig. 1 shows a top view of a semiconductor structure according to an embodiment of the application. Fig. 2 shows a cross-sectional view of the semiconductor structure of fig. 1 along the dashed line A-A' in accordance with the present application. As shown in fig. 1 and 2, the semiconductor structure 100 includes a substrate SUB, a first well W1, a second well W2, and a third well W3. The substrate SUB has a first conductivity type. According to an embodiment of the application, the substrate SUB is a silicon substrate. According to another embodiment of the present application, the substrate SUB may also be a lightly doped substrate having the first conductivity type.
The first well W1 is formed in the substrate SUB and has a first conductivity type. According to an embodiment of the present application, the first conductivity type is P-type and the second conductivity type is N-type. According to an embodiment of the present application, the first well W1 may be formed by an ion implantation step. For example, boron ions or indium ions may be implanted in a region where the first well W1 is predetermined to be formed to form the first well W1. In the present embodiment, the doping concentration of the first well W1 is higher than the doping concentration of the substrate SUB.
The second well W2 is formed in the substrate SUB and has a second conductivity type. According to an embodiment of the application, the second well W2 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions may be implanted in a region of the predetermined second well W2 to form the second well W2. According to an embodiment of the present application, the second well W2 is also called a drift region (drift region).
The third well W3 is formed in the second well W2 and has the second conductivity type, wherein the doping concentration of the third well W3 is higher than the doping concentration of the second well W2. According to an embodiment of the application, the third well W3 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions may be implanted in a region of the predetermined third well W3 to form the third well W3. According to an embodiment of the application, the third well W3 is also called a buffer (buffer).
As shown in fig. 2, the semiconductor structure 100 may further include a buried oxide layer (Buried Oxide Layer, BOX) BOX, wherein the buried oxide layer BOX is formed in the substrate SUB, and the first well W1 and the second well W2 are formed over and in contact with the buried oxide layer BOX. According to some embodiments of the present application, semiconductor structure 100 may or may not include a buried oxide BOX, and semiconductor structure 100 including a buried oxide BOX is herein explained as an illustration and is not limited in any way.
As shown in fig. 1 and 2, the semiconductor structure 100 further includes a first diffusion region DF1, a second diffusion region DF2, a third diffusion region DF3, and a fourth diffusion region DF4. The first diffusion region DF1 and the second diffusion region DF2 are formed in the third well W3, wherein the first diffusion region DF1 has the second conductivity type and the second diffusion region DF2 has the first conductivity type. According to an embodiment of the present application, the doping concentration of the first diffusion region DF1 is greater than the doping concentration of the third well W3.
As shown in fig. 1 and 2, a third diffusion region DF3 and a fourth diffusion region DF4 are formed in the first well W1, and the fourth diffusion region DF4 is located between the third diffusion region DF3 and the second well W2. The third diffusion region DF3 has a first conductivity type, and the fourth diffusion region DF4 has a second conductivity type. According to an embodiment of the present application, the doping concentration of the third diffusion region DF3 is greater than the doping concentration of the first well W1.
As shown in fig. 1, the arrangement direction of the first and second doped regions DF1 and DF2 is different from the arrangement direction of the third and fourth doped regions DF3 and DF4. As shown in the embodiment of fig. 1, the first direction is the Y direction and the second direction is the X direction. As shown in fig. 1 and 2, the semiconductor structure 100 further includes a gate structure 110. The gate structure 110 is formed on the first well W1 and the second well W2, and covers the first well W1 and the second well W2. In accordance with some embodiments of the present application, in fig. 1, the gate structure 110 may exceed the upper and lower edges of the first well W1 and the second well W2 to effectively block the current, and the upper and lower edges of the first well W1 and the second well W2 are illustrated by the gate structure 110 being cut off, but are not limited thereto in any way.
According to an embodiment of the present application, the semiconductor structure 100 of fig. 1 and 2 forms a lateral insulated gate bipolar transistor, wherein the first diffusion region DF1 and the second diffusion region DF2 are electrically connected to each other to form a collector terminal C of the lateral insulated gate bipolar transistor, the gate structure 110 forms a gate terminal G of the power semiconductor device, and the third diffusion region DF3 and the fourth diffusion region DF4 are electrically connected to each other to form an emitter terminal E of the power semiconductor device.
According to an embodiment of the present application, the gate structure 110 may cover the fourth diffusion region DF4. As shown in the embodiment of fig. 1, the gate structure 110 is illustrated herein as covering the fourth diffusion region DF4, but is not limited thereto in any way.
According to an embodiment of the present application, when the voltage at the collector terminal C of the power semiconductor device of the semiconductor structure 100 exceeds the voltage at the emitter terminal E and the parasitic bipolar junction transistor formed by the second diffusion region DF2, the third well W3 and the first well W1 is turned on, the lateral igbt will generate a spring back (snapback) phenomenon, which reduces the performance.
When the lateral insulated gate bipolar transistor is turned on in the forward direction, at the beginning, due to the existence of an N-type portion (N-collector) of the collector, electrons injected into the drift region from the emitter flow out of the collector through the N-type portion (N-collector), and at this time, only electrons are conductive, which is called a unipolar conductive mode. As the current flowing through the P-type portion (P-collector) of the collector increases, the voltage between the P-type portion (P-collector) and the PN junction formed by the N-type drift region increases. When the threshold voltage (e.g., 0.7V) is exceeded, the PN junction is turned on, a large number of holes (Hole) are injected into the N-type drift region from the P-type portion (P-collector), a conductivity modulation effect occurs, so that the transistor enters a bipolar conduction mode, a voltage rebound phenomenon is generated when the transistor is reflected on the forward conduction curve, the voltage and current on the curve suddenly change, i.e., a negative resistance effect, also called a rebound (snapback) effect, occurs, and the phenomenon causes a series of problems to influence the reliability of the lateral insulated gate bipolar transistor, such as local current is excessively large, so that the device cannot work normally or even burn out, and the whole circuit is collapsed.
Fig. 3 shows a top view of a semiconductor structure according to another embodiment of the application. Comparing the semiconductor structure 300 of fig. 3 with the semiconductor structure 100 of fig. 1, the semiconductor structure 300 further includes a fourth well W4, a fifth diffusion region DF5, a sixth diffusion region DF6, a seventh diffusion region DF7, and an eighth diffusion region DF8.
As shown in fig. 3, a fourth well W4 is formed in the third well W3 and has the first conductivity type. According to an embodiment of the application, the fourth well W4 may be formed by an ion implantation step. For example, boron ions or indium ions may be implanted in a region where the fourth well W4 is predetermined to be formed to form the fourth well W4. According to some embodiments of the application, the doping concentration of the fourth well W4 is similar to the doping concentration of the first well W1.
Fig. 4 shows a cross-sectional view of the semiconductor structure of fig. 3 along the dashed line B-B' in accordance with the present application. As shown in fig. 3 and 4, a fifth diffusion region DF5 and a sixth diffusion region DF6 are formed in the fourth well W4, wherein the fifth diffusion region DF5 has a first conductivity type and the sixth diffusion region DF6 has a second conductivity type. Further, the fifth diffusion region DF5 and the sixth diffusion region DF6 are distant from each other.
Fig. 5 shows a cross-sectional view of the semiconductor structure of fig. 3 along the dashed line D-D' in accordance with the present application. As shown in fig. 3 and 5, a seventh diffusion region DF7 and an eighth diffusion region DF8 are formed in the third well W3, wherein the seventh diffusion region DF7 has the second conductivity type and the eighth diffusion region has the first conductivity type. Further, the seventh diffusion region DF7 and the eighth diffusion region DF8 are distant from each other.
As shown in fig. 3, the third and fourth diffusion regions DF3 and DF4, the fifth and sixth diffusion regions DF5 and DF6, and the seventh and eighth diffusion regions DF7 and DF8 are arranged along a first direction, and the fifth and seventh diffusion regions DF5 and DF7, and the sixth and eighth diffusion regions DF6 and DF8 are arranged along a second direction, wherein the first and second directions are different. As shown in the embodiment of fig. 3, the first direction is the X direction and the second direction is the Y direction.
As shown in fig. 3, 4 and 5, the semiconductor structure 300 further includes an isolation structure ISO. The isolation structures ISO are formed in the third well W3 and the fourth well W4, and are located between the fifth diffusion region DF5 and the sixth diffusion region DF6 and between the seventh diffusion region DF7 and the eighth diffusion region DF8. As shown in fig. 3, 4 and 5, the isolation structure ISO directly contacts the fifth, sixth, seventh and eighth diffusion regions DF5, DF6, DF7 and DF8, but is not intended to limit the present application. According to other embodiments of the present application, the isolation structure ISO does not contact at least one of the fifth, sixth, seventh and eighth diffusion regions DF5, DF6, DF7, DF8.
According to an embodiment of the present application, the semiconductor structure 300 forms a lateral igbt, the third diffusion region DF3 and the fourth diffusion region DF4 are electrically connected to each other to form an emitter terminal E of the lateral igbt, the fifth diffusion region DF5 and the seventh diffusion region DF7 are electrically connected to each other to be in a floating state, the sixth diffusion region DF6 and the eighth diffusion region DF8 are electrically connected to each other to be a collector terminal C of the lateral igbt, and the gate structure 110 forms a gate terminal G of the lateral igbt. According to an embodiment of the present application, the third diffusion region DF3 and the fourth diffusion region DF4 are electrically connected together to have the same potential during operation, so that the size of the lateral igbt can be reduced.
As shown in fig. 4, the first well W1 (including the third diffusion region DF 3), the second well W2 (including the third well W3), and the fourth well W4 (including the fifth diffusion region DF 5) form a first parasitic bipolar junction transistor BJT1, and the second well W2 (including the third well W3), the fourth well W4, and the sixth diffusion region DF6 form a second parasitic bipolar junction transistor BJT2. According to an embodiment of the present application, the first parasitic bipolar junction transistor BJT1 is PNP and the second parasitic bipolar junction transistor BJT2 is NPN.
In addition, since the fifth diffusion region DF5 and the seventh diffusion region DF7 are electrically connected to each other, the first parasitic bipolar junction transistor BJT1 and the second parasitic bipolar junction transistor BJT2 are electrically connected to each other in a diode form, which is equivalent to the second well W2, the third well W3, the fourth well W4 and the fifth diffusion region DF 5. Therefore, the first parasitic bipolar junction transistor BJT1 and the second parasitic bipolar junction transistor BJT2, which are coupled in the form of diodes, are connected in series between the emitter terminal E and the collector terminal C. In other words, when the voltage at the emitter terminal E exceeds the voltage at the collector terminal C, the first parasitic bipolar junction transistor BJT1 and the second parasitic bipolar junction transistor BJT2, which are coupled in the form of diodes, are both turned on.
According to an embodiment of the present application, when the voltage at the collector terminal C of the lateral igbt of the semiconductor structure 300 is greater than the voltage at the emitter terminal E, the first parasitic BJT1 and the second parasitic BJT2 of fig. 4 are non-conductive, and the current flows from the collector terminal C to the emitter terminal E through the eighth diffusion region DF8, the third well W3, the second well W2, the first well W1, the third diffusion region DF3 and the fourth diffusion region DF4 shown in fig. 5.
According to another embodiment of the present application, when the voltage at the emitter terminal E of the lateral igbt of the semiconductor structure 300 is greater than the voltage at the collector terminal C, the first parasitic BJT1 and the second parasitic BJT2 of fig. 4 are turned on, thereby clamping the voltage across the emitter terminal E to the collector terminal C. In addition, the charge at the emitter terminal E is discharged to the collector terminal C through the first parasitic bipolar junction transistor BJT1 and the second parasitic bipolar junction transistor BJT2.
Comparing the lateral igbt formed by the semiconductor structure 300 of fig. 3-5 with the lateral igbt formed by the semiconductor structure 100 of fig. 1-2, the semiconductor structure 300 has more floating fourth well W4, fifth diffusion region DF5 and seventh diffusion region DF7 to suppress the spring back, thereby improving the performance of the lateral igbt formed by the semiconductor structure 300.
Fig. 6A-6G are flowcharts illustrating a method of fabricating a semiconductor structure according to an embodiment of the application. As shown in fig. 6A, a substrate SUB is first provided. According to some embodiments of the application, the substrate SUB may comprise a buried oxide layer. In the embodiments of fig. 6A-6F, the explanation is given by taking the example of excluding the buried oxide layer, and is not limited thereto in any way.
Next, a first well W1 and a second well W2 are formed on the substrate SUB, wherein the first well W1 has a first conductivity type and the second well W2 has a second conductivity type. According to an embodiment of the present application, the first well W1 and the second well W2 are in contact with each other. According to an embodiment of the present application, the first conductivity type is P-type and the second conductivity type is N-type.
As shown in fig. 6B, a third well W3 is formed in the second well W2, wherein the third well W3 has the second conductivity type. According to an embodiment of the present application, the doping concentration of the third well W3 is higher than the doping concentration of the second well W2.
As shown in fig. 6C, a fourth well W4 is formed in the third well W3, wherein the fourth well W4 has the first conductivity type. According to an embodiment of the present application, the doping concentration of the fourth well W4 is similar to the doping concentration of the first well W1. According to an embodiment of the application, the substrate SUB has a first conductivity type, and the doping concentrations of the fourth well W4 and the first well W1 are higher than the doping concentration of the substrate SUB.
As shown in fig. 6D, a region in which the third diffusion region DF3 and the fourth diffusion region DF4 are formed is defined in the first well W1, a region in which the fifth diffusion region DF5 and the sixth diffusion region DF6 are formed in the fourth well W4, a region in which the seventh diffusion region DF7 and the eighth diffusion region DF8 are formed in the third well W3, and a region in which the gate structure 110 is formed are defined. The third and fourth diffusion regions DF3 and DF4 are in contact with each other, the fifth and sixth diffusion regions DF5 and DF6 are distant from each other, the seventh and eighth diffusion regions DF7 and DF8 are distant from each other, and the gate structure 110 covers the fourth diffusion region DF4.
As shown in fig. 6E, an isolation structure ISO is formed between the fifth and sixth diffusion regions DF5 and DF6 and between the seventh and eighth diffusion regions DF7 and DF8, and is in direct contact with the fifth, sixth, seventh and eighth diffusion regions DF5, DF6, DF7 and DF8. According to other embodiments of the present application, the isolation structure ISO does not contact at least one of the fifth, sixth, seventh and eighth diffusion regions DF5, DF6, DF7, DF8. According to another embodiment of the present application, the isolation structure ISO is not required, and the fifth diffusion region DF5, the sixth diffusion region DF6, the seventh diffusion region DF7 and the eighth diffusion region DF8 are not in contact with each other.
As shown in fig. 6F, a gate structure 110 is formed on the region of the gate structure 110 defined in fig. 6D, wherein the gate structure 110 may cover the fourth diffusion region DF4 and be formed over the first well W1 and the second well W2.
After the gate structure 110 is formed, the regions of the third, fourth, fifth, sixth, seventh, and eighth diffusion regions DF3, DF4, DF5, DF6, DF7, and DF8 defined in fig. 6D are implanted to form the third, fourth, fifth, sixth, seventh, and eighth diffusion regions DF3, DF4, DF5, DF6, DF7, and DF8, respectively.
As shown in fig. 6F, the fourth diffusion region DF4 is located between the third diffusion region DF3 and the second well W2. According to an embodiment of the present application, the third, fifth and eighth diffusion regions DF3, DF5 and DF8 have a first conductivity type, and the fourth, sixth and seventh diffusion regions DF4, DF6 and DF7 have a second conductivity type.
Further, the doping concentrations of the third, fifth, and eighth diffusion regions DF3, DF5, and DF8 are higher than those of the first and fourth wells W1 and W4, and the doping concentrations of the fourth, sixth, and seventh diffusion regions DF4, DF6, and DF7 are higher than those of the third well W3.
The third and fourth diffusion regions DF3 and DF4, the fifth and sixth diffusion regions DF5 and DF6, and the seventh and eighth diffusion regions DF7 and DF8 are aligned along the first direction, and the fifth and seventh diffusion regions DF5 and DF7, and the sixth and eighth diffusion regions DF6 and DF8 are aligned along the second direction, wherein the first and second directions are different. As shown in fig. 6F, the first direction is the X direction, and the second direction is the Y direction.
As shown in fig. 6G, the sixth diffusion region DF6 is electrically connected to the eighth diffusion region DF8, the fifth diffusion region DF5 is electrically connected to the seventh diffusion region DF7, and the third diffusion region DF3 is electrically connected to the fourth diffusion region DF4 by means of an interconnection structure. According to one embodiment of the present application, the interconnect structure is at least one metal interconnect layer.
According to an embodiment of the present application, the semiconductor structure 300 shown in fig. 6G is a lateral insulated gate bipolar transistor, the sixth diffusion region DF6 is electrically connected to the eighth diffusion region DF8 and is a collector terminal C of the lateral insulated gate bipolar transistor, the fifth diffusion region DF5 is electrically connected to the seventh diffusion region DF7 and is in a floating state, the third diffusion region DF3 is electrically connected to the fourth diffusion region DF4 and is an emitter terminal E of the lateral insulated gate bipolar transistor, and the gate structure 110 is used as a gate terminal G of the lateral insulated gate bipolar transistor.
Fig. 7 shows a top view of a semiconductor structure according to another embodiment of the application. Comparing the semiconductor structure 700 shown in fig. 7 with the semiconductor structure 300 of fig. 3, the third well W3 includes a plurality of groups of fourth well W4, fifth diffusion region DF5, sixth diffusion region DF6, seventh diffusion region DF7, and eighth diffusion region DF8.
As shown in fig. 7, a plurality of fourth wells W4 are formed in the third well W3 and have the first conductivity type. A fifth diffusion region DF5 and a sixth diffusion region DF6 are formed in the fourth well W4, wherein the fifth diffusion region DF5 has a first conductivity type and the sixth diffusion region DF6 has a second conductivity type. A seventh diffusion region DF7 and an eighth diffusion region DF8 are formed in the third well W3, wherein the seventh diffusion region DF7 has the second conductivity type and the eighth diffusion region has the first conductivity type.
As shown in fig. 7, the fifth and sixth diffusion regions DF5 and DF6 and the seventh and eighth diffusion regions DF7 and DF8 are aligned along a first direction, and the fifth and seventh diffusion regions DF5 and DF7 and the sixth and eighth diffusion regions DF6 and DF8 are aligned along a second direction, wherein the first and second directions are different. As shown in the embodiment of fig. 7, the first direction is the X direction and the second direction is the Y direction.
As shown in fig. 7, the semiconductor structure 300 further includes an isolation structure ISO. The isolation structures ISO are formed in the third and fourth wells W3 and W4 and are located between the fifth and sixth diffusion regions DF5 and DF6 and between the seventh and eighth diffusion regions DF7 and DF8 such that the fifth and sixth diffusion regions DF5 and DF6 are distant from each other and the seventh and eighth diffusion regions DF7 and DF8 are distant from each other.
The application discloses a semiconductor structure and a manufacturing method thereof, which are used for forming a transverse insulated gate bipolar transistor. The lateral insulated gate bipolar transistor provided by the application can effectively inhibit rebound phenomenon when the voltage of the collector terminal is greater than that of the emitter terminal, and provide a path for discharging charges of the emitter terminal to the collector terminal when the voltage of the emitter terminal is greater than that of the collector terminal, so that the efficiency of the lateral insulated gate bipolar transistor is obviously improved.
Although embodiments of the present application and their advantages have been disclosed above, it should be understood that those skilled in the art may make modifications, substitutions and alterations herein without departing from the spirit and scope of the application. Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather should be understood to correspond to the particular embodiments of the present application or to the particular embodiments of the present application. Accordingly, the scope of the present application includes such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim scope constitutes a separate embodiment, and the scope of the application also includes combinations of the individual claims and embodiments.

Claims (15)

1. A semiconductor structure, comprising:
a substrate;
a first well formed on the substrate;
a second well formed on the substrate and contacting the first well;
a third well formed in the second well;
a fourth well formed in the third well;
a first diffusion region formed in the fourth well;
a second diffusion region formed in the fourth well and separated from the first diffusion region;
a third diffusion region formed in the third well;
a fourth diffusion region formed in the third well and spaced apart from the third diffusion region;
a fifth diffusion region formed in the first well;
a sixth diffusion region formed in the first well, wherein the sixth diffusion region is in contact with the fifth diffusion region; and
and a gate structure formed on the first well and the second well.
2. The semiconductor structure of claim 1, wherein said first well, said fourth well, said first diffusion region, said fourth diffusion region, said fifth diffusion region, and said substrate have a first conductivity type, and said second well, said third well, said second diffusion region, said third diffusion region, and said sixth diffusion region have a second conductivity type.
3. The semiconductor structure of claim 2, wherein a doping concentration of said first well is similar to a doping concentration of said fourth well and is greater than a doping concentration of said substrate; the doping concentration of the first well is similar to that of the fourth well, and the method comprises the following steps: the doping concentration of the fourth well is similar to that of the first well.
4. The semiconductor structure of claim 2, wherein a doping concentration of said second well is less than a doping concentration of said third well.
5. The semiconductor structure of claim 1, further comprising:
an isolation structure is formed between the first diffusion region and the second diffusion region and between the third diffusion region and the fourth diffusion region.
6. The semiconductor structure of claim 1, wherein said first diffusion region and said third diffusion region are electrically connected to each other and are floating.
7. The semiconductor structure of claim 1, wherein said semiconductor structure is used to form a lateral igbt, wherein said second diffusion region and said fourth diffusion region are electrically connected to each other to form a collector, wherein said fifth diffusion region and said sixth diffusion region are electrically connected to each other to form an emitter, and wherein said gate structure forms a gate.
8. A method of forming a semiconductor structure, the method comprising:
providing a substrate;
forming a first well on the substrate;
forming a second well on the substrate, wherein the first well and the second well are contacted;
forming a third well in the second well;
forming a fourth well in the third well;
forming a first diffusion region in the fourth well;
forming a second diffusion region in the fourth well, wherein the second diffusion region is far away from the first diffusion region;
forming a third diffusion region in the third well;
forming a fourth diffusion region in the third well, wherein the fourth diffusion region is far away from the third diffusion region;
forming a fifth diffusion region in the first well;
forming a sixth diffusion region in the first well, wherein the sixth diffusion region is in contact with the fifth diffusion region; and
a gate structure is formed over the first well and the second well.
9. The method of claim 8, wherein the first well, the fourth well, the first diffusion region, the fourth diffusion region, the fifth diffusion region, and the substrate have a first conductivity type, and the second well, the third well, the second diffusion region, the third diffusion region, and the sixth diffusion region have a second conductivity type.
10. The method of claim 9, wherein the doping concentration of the first well is similar to the doping concentration of the fourth well and is greater than the doping concentration of the substrate; the doping concentration of the first well is similar to that of the fourth well, and the method comprises the following steps: the doping concentration of the fourth well is similar to that of the first well.
11. The method of claim 9, wherein the second well has a doping concentration less than the doping concentration of the third well.
12. The method of manufacturing as set forth in claim 8, further comprising:
forming an isolation structure, wherein the isolation structure is located between the first diffusion region and the second diffusion region and between the third diffusion region and the fourth diffusion region.
13. The method of claim 8, wherein the first diffusion region and the third diffusion region are electrically connected to each other and are floating.
14. The method of claim 8 wherein the semiconductor structure is used to form a lateral igbt, wherein the second diffusion region and the fourth diffusion region are electrically connected to each other to form a collector, wherein the fifth diffusion region and the sixth diffusion region are electrically connected to each other to form an emitter, and wherein the gate structure forms a gate.
15. The method of claim 14, wherein the second diffusion region and the fourth well are reverse biased to inhibit the lateral igbt from springback when the voltage at the collector is greater than the voltage at the emitter, and wherein the charge at the emitter is removed from the collector through the path from the first well to the second diffusion region when the voltage at the collector is less than the voltage at the emitter.
CN202211083313.9A 2022-04-27 2022-09-06 Semiconductor structure and manufacturing method thereof Pending CN117012815A (en)

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