CN117012792A

CN117012792A - Image Sensor

Info

Publication number: CN117012792A
Application number: CN202310456735.4A
Authority: CN
Inventors: 朴惠涓; 权炯根; 金范锡; 金智恩; 朴巨成; 李允基; 林夏珍; 全宅洙; 许在成
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-05-03
Filing date: 2023-04-25
Publication date: 2023-11-07

Abstract

Disclosed is an image sensor including: a first substrate having a first surface and a second surface opposite to the first surface, and including a pixel array region and an edge region; an anti-reflective structure on the second surface; a pixel separation section in the first substrate and separating pixels from each other; and a microlens array on the anti-reflective structure. The anti-reflective structure includes a first dielectric layer, a titanium oxide layer, a second dielectric layer, and a third dielectric layer stacked in sequence. The first dielectric layer, the second dielectric layer, and the third dielectric layer comprise different materials from one another. On the edge region, the third dielectric layer penetrates the second dielectric layer and the titanium oxide layer to be in contact with the first dielectric layer.

Description

Image sensor

Technical Field

The present inventive concept relates to an image sensor.

Background

An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors can be classified into a Charge Coupled Device (CCD) type and a Complementary Metal Oxide Semiconductor (CMOS) type. CIS (CMOS image sensor) is an abbreviation for CMOS image sensor. The CIS may include a plurality of pixels arranged in two dimensions. Each pixel includes a Photodiode (PD). Photodiodes are used to convert incident light into electrical signals.

Disclosure of Invention

Some example embodiments of the inventive concepts provide an image sensor capable of realizing a clear image.

The objects of the inventive concept are not limited to the above, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

According to some example embodiments of the inventive concepts, an image sensor may include: a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a pixel array region and an edge region; an anti-reflective structure on the second surface; a pixel separation portion in the first substrate, the pixel separation portion separating pixels from each other; and a microlens array on the anti-reflective structure. The anti-reflective structure may include a first dielectric layer, a titanium oxide layer, a second dielectric layer, and a third dielectric layer sequentially stacked. The first dielectric layer, the second dielectric layer, and the third dielectric layer may include materials different from each other. On the edge region, the third dielectric layer may penetrate the second dielectric layer and the titanium oxide layer to be in contact with the first dielectric layer.

According to some example embodiments of the inventive concepts, an image sensor may include: a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a pixel array region and an edge region; an anti-reflective structure on the second surface; a pixel separation portion on the first substrate, the pixel separation portion separating pixels from each other; a color filter on the anti-reflective structure; a microlens array on the color filter; a first interlayer dielectric layer on the first surface of the first substrate; a first interconnect layer in the first interlayer dielectric layer; a second interlayer dielectric layer under the first interlayer dielectric layer; a second interconnect layer in the second interlayer dielectric layer; a second substrate under the second interlayer dielectric layer; a first contact on the second surface of the first substrate on the edge region; and a second contact on the edge region, the second contact penetrating the first substrate, the first interlayer dielectric layer, and a portion of the second interlayer dielectric layer to contact the second interconnect layer. The anti-reflective structure may include a first dielectric layer, a titanium oxide layer, a second dielectric layer, and a third dielectric layer sequentially stacked. The first dielectric layer, the second dielectric layer, and the third dielectric layer may include materials different from each other. Between the first contact and the second contact, the third dielectric layer may penetrate the second dielectric layer and the titanium oxide layer to contact the first dielectric layer.

According to some example embodiments of the inventive concepts, an image sensor may include: a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a pixel array region and an edge region; an anti-reflective structure on the second surface; a pixel separation portion in the first substrate, the pixel separation portion separating pixels from each other; and a microlens array on the anti-reflective structure. The anti-reflective structure may include a first dielectric layer, a titanium oxide layer, a second dielectric layer, and a third dielectric layer sequentially stacked. The first dielectric layer, the second dielectric layer, and the third dielectric layer may include materials different from each other. The recess may be on the edge region in the titanium oxide layer and the second dielectric layer. The first dielectric layer may be exposed on a bottom surface of the recess. The third dielectric layer may conformally cover side surfaces and bottom surfaces of the recess. The groove may surround the pixel array area when viewed in plan.

Drawings

Fig. 1 illustrates a block diagram showing an image sensor according to some example embodiments of the inventive concepts.

Fig. 2 illustrates a circuit diagram showing an active pixel sensor array of an image sensor according to some example embodiments of the inventive concepts.

Fig. 3 illustrates a plan view showing an image sensor according to some example embodiments of the inventive concepts.

Fig. 4 shows a cross-sectional view taken along line A-A' of fig. 3.

Fig. 5 shows a partial plan view showing the image sensor of fig. 3.

Fig. 6 shows a plan view of a via array disposed on the via area of fig. 3.

Fig. 7A shows an enlarged view showing a portion P2 of fig. 4.

Fig. 7B shows an enlarged view showing the P1 portion of fig. 4.

Fig. 8A to 8H illustrate cross-sectional views showing a method of manufacturing an image sensor having the cross-section of fig. 4.

Fig. 9 shows a cross-sectional view taken along line A-A' of fig. 3.

Fig. 10 illustrates a cross-sectional view of an image sensor according to some example embodiments of the inventive concepts.

Fig. 11A shows an enlarged view showing a portion P2 of fig. 10.

Fig. 11B shows an enlarged view showing a portion P1 of fig. 10.

Fig. 12 illustrates a cross-sectional view showing an image sensor according to some example embodiments of the inventive concepts.

Detailed Description

Some example embodiments of the inventive concepts will now be described in detail with reference to the accompanying drawings to help clearly explain the inventive concepts.

Fig. 1 illustrates a block diagram of an image sensor according to some example embodiments of the inventive concepts.

Referring to fig. 1, an image sensor may include an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a Correlated Double Sampler (CDS) 1006, an analog-to-digital converter (ADC) 1007, and an input/output (I/O) buffer 1008.

The active pixel sensor array 1001 may include a plurality of unit pixels arranged in two dimensions, each configured to convert an optical signal into an electrical signal. The active pixel sensor array 1001 may be driven by a plurality of drive signals, such as a pixel select signal, a reset signal, and a charge transfer signal from the row driver 1003. The converted electrical signal may be provided to correlated double sampler 1006.

The row driver 1003 may supply a number of driving signals for driving a number of unit pixels to the active pixel sensor array 1001 according to a decoding result obtained from the row decoder 1002. When the unit pixels are arranged in a matrix shape, a driving signal may be supplied to each row.

The timing generator 1005 may provide timing and control signals to the row decoder 1002 and the column decoder 1004.

The correlated double sampler 1006 may receive electrical signals generated from the active pixel sensor array 1001 and may hold and sample the received electrical signals. The correlated double sampler 1006 may perform a double sampling operation to sample a specific noise level and signal level of the electrical signal, and then may output a difference level corresponding to a difference between the noise level and the signal level.

The analog-to-digital converter 1007 may convert an analog signal corresponding to the difference level received from the correlated double sampler 1006 into a digital signal and then output the converted digital signal.

The input/output buffer 1008 may latch digital signals and then sequentially output the latched digital signals to an image signal processing unit (not shown) in response to a decoding result obtained from the column decoder 1004.

Referring to fig. 1 and 2, the active pixel sensor array 1001 may include a plurality of unit pixels PX, and the unit pixels PX may be arranged in a matrix shape. Each unit pixel UP may include a transfer transistor TX. Each unit pixel UP may further include logic transistors RX, SX, and DX. The logic transistors RX, SX, and DX may include a reset transistor RX, a selection transistor SX, and a source follower transistor DX. The transfer transistor TX may include a transfer gate electrode TG. Each unit pixel PX may further include a photoelectric conversion element PD and a floating diffusion FD. The logic transistors RX, SX, and DX may be shared by a plurality of unit pixels UP.

The photoelectric conversion element PD can generate and accumulate a photo-charge in proportion to the amount of externally incident light. The photoelectric conversion element PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX may transfer charges generated in the photoelectric conversion element PD into the floating diffusion FD. The floating diffusion FD can accumulate and store charges generated and transferred from the photoelectric conversion element PD. The source follower transistor DX may be controlled by the amount of photo-charges accumulated in the floating diffusion FD.

The reset transistor RX may periodically reset the charge accumulated in the floating diffusion FD. The reset transistor RX may have a drain electrode connected to the floating diffusion region FD and a source voltage V _DD Is provided. When the reset transistor RX is turned on, a power supply voltage V connected to the source electrode of the reset transistor RX may be supplied to the floating diffusion FD _DD . Accordingly, when the reset transistor RX is turned on, the charge accumulated in the floating diffusion FD can be depleted, and thus the floating diffusion FD can be reset.

The source follower transistor DX including the source follower gate electrode SF may function as a source follower buffer amplifier. The source follower transistor DX can amplify the variation in the potential of the floating diffusion FD and can output the amplified potential to the output line V _OUT 。

The selection transistor SX including the selection gate electrode SEL may select each row of the unit pixels P to be read. When the selection transistor SX is turned on, the power supply voltage V _DD Can be applied to a sourceThe drain of the polar follower transistor DX.

Fig. 3 illustrates a plan view of an image sensor according to some example embodiments of the inventive concepts. Fig. 4 shows a cross-sectional view taken along line A-A' of fig. 3. Fig. 5 shows a partial plan view showing the image sensor of fig. 3. Fig. 6 shows a plan view showing a via array disposed on the via area of fig. 3. Fig. 7A shows an enlarged view showing a portion P1 of fig. 4. Fig. 7B shows an enlarged view showing the P2 portion of fig. 4.

Referring to fig. 3 and 4, an image sensor 500 according to some example embodiments of the inventive concepts may have a structure in which a first sub-chip CH1 and a second sub-chip CH2 are bonded to each other. The first sub-chip CH1 may be disposed on the second sub-chip CH 2. The first sub-chip CH1 may include a first substrate 1. The first substrate 1 may be, for example, a monocrystalline silicon wafer, a silicon epitaxial layer substrate, and/or a silicon-on-insulator (SOI) substrate. The first substrate 1 may be doped with impurities having the first conductivity type. For example, the first conductivity type may be p-type. The first substrate 1 may have a front surface 1a and a rear surface 1b opposite to each other. In this specification, the front surface 1a may be referred to as a first surface, and the rear surface 1b may be referred to as a second surface. The first substrate 1 may include a pixel array area APS, an optical black area OB, and an edge area ER.

The pixel array area APS and the optical black area OB may each include a plurality of unit pixels UP. The optical black area OB may surround the pixel array area APS. The edge region ER may surround the pixel array region APS and the optical black region OB. The edge region ER may include a contact region BR1, a via region BR2, and a pad region PR. The via region BR2 may be located between the contact region BR1 and the pad region PR. The pad region PR may be located at an outermost portion of the edge region ER. In this specification, the term "via" may be referred to as "contact". Alternatively, the term "contact" may be referred to as a "via".

On the pixel array area APS and the optical black area OB, the first substrate 1 may have therein a first pixel separation portion DTI1, which is provided to separate and/or restrict the unit pixels UP. The first pixel separation portion DTI1 may extend to a contact region BR1 of the edge region ER. The first pixel separation section DTI1 may have a mesh shape when viewed in a plan view.

On the edge region ER, the first substrate 1 may be provided with a back contact BCA, a back via BVS, and a back conductive PAD on its back surface 1 b. Referring to fig. 4 and 6, the second pixel separation portion DTI2 may surround each of the back surface vias BVS when viewed in a plan view. The backside via BVS may include a first backside via BVS (1) and a second backside via BVS (2). One or more column signals and row signals may be transmitted through the back side path BVS between the first sub-chip CH1 and the second sub-chip CH 2.

Each of the first and second pixel separation portions DTI1 and DTI2 may be located in a deep trench 22, the deep trench 22 being formed to extend from the front surface 1a to the rear surface 1b of the first substrate 1. Each of the first and second pixel separation portions DTI1 and DTI2 may be front side deep trench isolation (FDTI). Each of the first and second pixel separation portions DTI1 and DTI2 may include a buried dielectric pattern 12, a separation dielectric pattern 14, and a separation conductive pattern 16. The buried dielectric pattern 12 may be interposed between the separation conductive pattern 16 and the first interlayer dielectric layer IL1, which will be discussed below. The separation dielectric pattern 14 may be interposed between the separation conductive pattern 16 and the first substrate 1 and between the buried dielectric pattern 12 and the first substrate 1.

The buried dielectric pattern 12 and the separation dielectric pattern 14 may be formed of a dielectric material having a refractive index different from that of the first substrate 1. The buried dielectric pattern 12 and the separation dielectric pattern 14 may include, for example, silicon oxide. The separation conductive pattern 16 may be spaced apart from the first substrate 1. The separation conductive pattern 16 may include a doped polysilicon layer or a doped silicon germanium layer. For example, one of boron, phosphorus, and arsenic may be employed as an impurity doped into a polysilicon or silicon germanium layer. Alternatively, the separation conductive pattern 16 may include a metal layer.

As shown in fig. 4, each of the first and second pixel separation portions DTI1 and DTI2 may have a width decreasing in a direction from the front surface 1a toward the rear surface 1b of the first substrate 1. For example, the first and second pixel separation portions DTI1 and DTI2 may have a larger width at the front surface 1a than at the rear surface 1b, and the reduced width may be linear, curved, or the like. In this specification, the term "width" may be replaced with the term "thickness". The second pixel separation portion DTI2 may be referred to as a "substrate separation portion".

The first substrate 1 may have photoelectric conversion elements PD on the respective unit pixels UP. The photoelectric conversion element PD may be doped with impurities having a second conductivity type opposite to the first conductivity type. The second conductivity type may be, for example, n-type. The n-type impurity doped in the photoelectric conversion element PD and the p-type impurity doped in the first substrate 1 therearound may constitute a PN junction to provide a photodiode.

The first substrate 1 may have a device isolation portion STI adjacent to the front surface 1a therein. The first pixel separation portion DTI1 may penetrate the device isolation portion STI. The device isolation portion STI may limit an active portion adjacent to the front surface 1a on each unit pixel UP (see ACT of fig. 5). The active part ACT may be provided for the transistors TX, RX, DX and SX of fig. 2.

Referring to fig. 4, on each unit pixel UP, a transfer gate electrode TG may be disposed on the front surface 1a of the first substrate 1. A portion of the transfer gate electrode TG may extend into the first substrate 1. The transfer gate electrode TG may have a vertical shape. Alternatively, the transfer gate electrode TG may be flat planar without extending into the first substrate 1. A gate dielectric layer Gox may be interposed between the transfer gate electrode TG and the first substrate 1. The floating diffusion FD may be disposed in the first substrate 1 at a side of the transfer gate electrode TG. The floating diffusion FD may be doped with, for example, an impurity having the second conductivity type.

The image sensor 500 may be a back-illuminated image sensor. The first substrate 1 may receive light incident through the rear surface 1b of the first substrate 1. The PN junction may generate electron-hole pairs from incident light. These generated electrons can move toward the photoelectric conversion element PD. When a voltage is applied to the transfer gate electrode TG, electrons can move toward the floating diffusion FD.

As shown in fig. 5, on one of the unit pixels UP, the front surface 1a may be provided thereon with a reset gate electrode RG adjacent to the transfer gate electrode TG. On the other one of the unit pixels UP, the front surface 1a may be provided thereon with a source follower gate SF and a selection gate electrode SEL adjacent to the transfer gate electrode TG. The gate electrodes TG, RG, SF, and SEL may correspond to gate electrodes of the transistors TX, RX, DX, and SX of fig. 2, respectively. The gate electrodes TG, RG, SF, and SEL may overlap the active portion ACT. In some example embodiments, the reset transistor RX, the selection transistor SX, and the source follower transistor DX may be shared by two adjacent unit pixels UP.

The first unit pixel UP (1) and the second unit pixel UP (2) may be disposed on the optical black area OB of the first substrate 1. On the first unit pixel UP (1), a black photoelectric conversion element PD' may be provided in the first substrate 1. On the second unit pixel UP (2), a dummy region pd″ may be provided in the first substrate 1. The black photoelectric conversion element PD' may be doped with, for example, an impurity having a second conductivity type different from the first conductivity type. The second conductivity type may be, for example, n-type. The pixel array area APS may include a plurality of unit pixels UP. The black photoelectric conversion element PD' may have a similar structure to the photoelectric conversion element PD, but may not perform the same operation as the photoelectric conversion element PD (for example, convert light into an electric signal). The dummy region pd″ may not be doped with impurities. The dummy region pd″ may generate a signal serving as information for removing the subsequent process noise.

The first sub-chip CH1 may further include a first interlayer dielectric layer IL1 disposed on the front surface 1 a. The first interlayer dielectric layer IL1 may be formed of a plurality of layers including at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous low-k dielectric layer. The first interlayer dielectric layer IL1 may be provided with the first wiring 15 therebetween or therein. The floating diffusion FD may be connected to the first wiring 15 through the first contact plug 17. On the pixel array area APS, the first contact plug 17 may penetrate one (e.g., the lowermost one) of the first interlayer dielectric layers IL1 closest to the front surface 1 a.

The second sub-chip CH2 may include a second substrate SB2, peripheral transistors PTR disposed on the second substrate SB2, and a second interlayer dielectric layer IL2 covering the peripheral transistors PTR. The second interlayer dielectric layer IL2 may be provided therein with a second wiring 217. The second sub-chip CH2 may include a circuit for storing an electrical signal generated from the first sub-chip CH 1.

Referring to fig. 4, 7A and 7B, an anti-reflection structure AL may be disposed on the rear surface 1B of the first substrate 1. The anti-reflection structure AL may include a first dielectric layer A1, a titanium oxide layer A2, a second dielectric layer A3, and a third dielectric layer A4, which are sequentially stacked. The first, second and third dielectric layers A1, A3 and A4 may include materials different from each other. For example, the first dielectric layer A1 may include aluminum oxide, the second dielectric layer A3 may include silicon oxide, and the third dielectric layer A4 may include hafnium oxide.

In this specification, the first dielectric layer A1 may be referred to as a "first antireflection layer", the titanium oxide layer A2 may be referred to as a "second antireflection layer", the second dielectric layer A3 may be referred to as a "third antireflection layer", and the third dielectric layer A4 may be referred to as a "fourth antireflection layer"

The first substrate 1 may have a first refractive index n1, the first dielectric layer A1 may have a second refractive index n2, the titanium oxide layer A2 may have a third refractive index n3, and the second dielectric layer A3 may have a fourth refractive index n4. The average value (n2+n3)/2 of the second refractive index n2 and the third refractive index n3 may be smaller than the first refractive index n1 and larger than the fourth refractive index n4. For example, the first refractive index n1 may range from about 4.0 to about 4.4. The second refractive index n2 may range from about 2.0 to about 3.0. The third refractive index n3 may range from about 2.2 to about 2.8. The fourth refractive index n4 may range from about 1.0 to about 1.9.

As shown in fig. 7B, the first dielectric layer A1 may have a first thickness T1, the titanium oxide layer A2 may have a second thickness T2, the second dielectric layer A3 may have a third thickness T3, and the third dielectric layer A4 may have a fourth thickness T4. In some example embodiments, thicknesses T1, T2, T3, and T4 may be different from one another, and in some example embodiments, thicknesses T1, T2, T3, and T4, or some subset thereof, may be the same or similar, e.g., all thicknesses T1, T2, T3, and T4, or only thicknesses T1 and T4. In some example embodiments, the second thickness T2 may be less than the third thickness T3 and greater than each of the first thickness T1 and the fourth thickness T4.

For example, the first thickness T1 may range from aboutTo about->The second thickness T2 may range from aboutTo about->The third thickness T3 may range from about +.>To about->The fourth thickness T4 may range from about +.>To about->

As shown in fig. 7B, the relationship between the refractive index and/or the thickness may cause the light L1 incident on the microlens ML described later to be refracted, and pass through the multilayer structure of the antireflection structure AL, and then be appropriately incident on the photoelectric conversion element PD. Accordingly, the image sensor 500 may have increased light receiving efficiency and clear image quality.

In addition, in the image sensor 500 according to the inventive concept, the anti-reflection structure AL may include a titanium oxide layer A2. The titanium oxide layer A2 can completely reduce the reflectance of all colors, and in particular, can further reduce the reflectance of blue light. Accordingly, the Quantum Efficiency (QE) of the blue pixel may be increased.

The first dielectric layer A1 may serve as a negative fixed charge layer. Thus, it is possible to reduce dark current and white spots.

Referring to fig. 3, 4 and 7A, on the edge region ER, the third dielectric layer A4 may penetrate the second dielectric layer A3 and the titanium oxide layer A2 to be in contact with the first dielectric layer A1. The second dielectric layer A3 and the titanium oxide layer A2 may have grooves GR formed therein. The third dielectric layer A4 may conformally cover side surfaces and bottom surfaces of the groove GR. The groove GR may surround the pixel array area APS and the optical black area OB when viewed in a plan view as shown in fig. 3. For example, the groove GR may partially penetrate the anti-reflective structure AL, while the grooves 46, 60 may completely penetrate the anti-reflective structure AL.

Referring to fig. 3 and 4, on the contact region BR1, a back contact BCA may be provided on the rear surface 1b of the first substrate 1. On the via region BR2, a first backside via BVS (1) may be provided on the rear surface 1b of the first substrate 1. On the PAD region PR, a back conductive PAD and a second back via BVS (2) may be disposed on the back surface 1b of the first substrate 1. Several second backside vias BVS (2) may form a group, and a plurality of groups may be disposed around the corresponding backside conductive PAD. External signals may be input/output through the rear conductive PAD. The back side conductive PAD may become an interface for external signals.

As shown in fig. 3, the groove GR may surround the back contact BCA. The groove GR may not be interposed between the back contacts BCA. The groove GR may surround the first back surface path BVS (1). The groove GR may surround the back conductive PAD. The groove GR may simultaneously surround the second backside passages BVS (2), several of which constitute a group. Portions of the groove GR may be connected to each other.

The arrangement of the first backside via BVS (1) may be variously changed, not limited to the arrangement shown in fig. 3. For example, as shown in fig. 6, the first backside via BVS (1) may constitute a backside via array BVSA on the via area BR 2. The first backside vias BVS (1) may be arranged in several columns and several rows. The groove GR may surround the first back surface path BVS (1). As shown in fig. 6, the first spacing DS1 between one first back surface path BVS (1) and its adjacent second pixel separation part DTI2 may be greater than the second spacing DS2 between the second pixel separation part DTI2 and its adjacent groove GR. The adjacent second pixel separation portions DTI2 may be spaced apart from each other by a third interval DS 3. The third interval DS3 may be greater than the second interval DS2 and less than the first interval DS1. For example, the first spacing DS1 may range from about 1.5 μm to about 2.5 μm. The second spacing DS2 may range from about 0.1 μm to about 0.5 μm. The third spacing DS3 may range from about 0.5 μm to about 1.5 μm.

Referring to fig. 4 and 7A, the back contact BCA, the first back via BVS (1), the second back via BVS (2), and the back conductive PAD may penetrate the anti-reflection structure AL and at least a portion of the first substrate 1. The back contact BCA may be disposed in the first back groove 46. The back contact BCA may include a first conductive pattern 52a and a first metal pattern 54a. The first conductive pattern 52a may conformally cover the side surfaces and the bottom surface of the first back trench 46. The first conductive pattern 52a may have a single-layer or multi-layer structure including at least one selected from a titanium layer, a titanium nitride layer, and a tungsten layer. The first metal pattern 54a may include, for example, aluminum. The first metal pattern 54a may fill the first back trench 46.

The back contact BCA may be in contact with the separation conductive pattern 16 of the first pixel separation portion DTI 1. A negative bias may be applied to the separation conductive pattern 16 of the first pixel separation portion DTI1 through the back contact BCA. The separated conductive patterns 16 may be used as a common bias line. Accordingly, holes that may exist in the surface of the first substrate 1 in contact with the first pixel separation portion DTI1 may be trapped to reduce dark current.

The first backside via BVS (1) may be disposed in the corresponding first hole H1. The first back surface via BVS (1) may penetrate the anti-reflection structure AL, the first substrate 1, the first interlayer dielectric layer IL1 and a portion of the second interlayer dielectric layer IL2. The first back surface via BVS (1) may connect a first wiring in the first wiring 15 to a second wiring in the second wiring 217. The first back surface path BVS (1) may conformally cover the inner wall and the bottom surface of the first hole H1. The first back surface via BVS (1) may include the same material and thickness as those of the first conductive pattern 52 a. The first backside via BVS (1) may have a single-layer or multi-layer structure including at least one selected from a titanium layer, a titanium nitride layer, and a tungsten layer.

A first backside via BVS (1) may be electrically connected to one of the backside contacts BCA through one of the backside connection lines 52 b. The back connection line 52b may be disposed on the anti-reflection structure AL. The back connection line 52b may include the same material and thickness as those of the first conductive pattern 52 a. The back connection line 52b may have a single-layer or multi-layer structure including at least one selected from a titanium layer, a titanium nitride layer, and a tungsten layer.

The backside conductive pad may be disposed in the second backside trench 60. The rear conductive PAD may include a second conductive pattern 52c and a second metal pattern 54b. The second conductive pattern 52c may conformally cover the side surfaces and the bottom surface of the second back trench 60. The second conductive pattern 52c may include the same material and thickness as those of the first conductive pattern 52 a. The second conductive pattern 52c may have a single-layer or multi-layer structure including at least one selected from a titanium layer, a titanium nitride layer, and a tungsten layer. The second metal pattern 54b may include, for example, aluminum. The second metal pattern 54b may fill the second back trench 60.

The second backside via BVS (2) may be disposed in a corresponding second hole H2. The second backside via BVS (2) may penetrate the anti-reflection structure AL, the first substrate 1, the first interlayer dielectric layer IL1, and a portion of the second interlayer dielectric layer IL2. The second back surface via BVS (2) may be connected to a second wiring among the second wirings 217. Although not shown, the second backside via BVS (2) may be connected to a first wiring among the first wirings 15. The second backside via BVS (2) may conformally cover the inner wall and the bottom surface of the second hole H2. The second backside via BVS (2) may include the same material and thickness as those of the first conductive pattern 52 a. The second backside via BVS (2) may have a single-layer or multi-layer structure including at least one selected from a titanium layer, a titanium nitride layer, and a tungsten layer. One of the second back side vias BVS (2) may be electrically connected to one of the back side conductive PADs PAD through the other one of the back side connection lines 52 b.

The grooves GR may include first to fifth grooves GR (1) to GR (5). The first groove GR (1) may be interposed between the optical black area OB and the contact area BR 1. The second groove GR (2) may be interposed between the back contact BCA and the first back via BVS (1). The third groove GR (3) may be interposed between the first back surface via BVS (1) and the back surface conductive PAD. The fourth groove GR (4) may be interposed between the rear conductive PAD and the second rear via BVS (2). The fifth groove GR (5) may be spaced apart from the second back surface path BVS (2) and disposed at one side of the second back surface path BVS (2).

In the second groove GR (2), one of the back connection lines 52b may conformally cover the sidewalls and bottom surface of the third dielectric layer A4. In the fourth groove GR (4), the other one of the back connection lines 52b may conformally cover the sidewalls and bottom surface of the third dielectric layer A4.

The groove GR may cut the titanium oxide layer A2. The titanium oxide layer A2 may have a conductivity greater than that of the other dielectric layers. When there is no groove GR, the titanium oxide layer A2 may cause an undesired leakage current to occur between the back contact BCA, the back via BVS, and the back conductive PAD adjacent to each other. Therefore, an operation error of the image sensor or a degradation of image quality may be caused. In contrast, in the inventive concept, because the groove GR cuts the titanium oxide layer A2, it is possible to prevent or reduce the generation of an undesired leakage current between the back contact BCA, the back via BVS, and the back conductive PAD adjacent to each other. Therefore, an operation error or image quality degradation of the image sensor 500 can be prevented or reduced.

On the optical black region OB, the first optical black pattern 52p may be disposed on the anti-reflection structure AL. The first optical black pattern 52p may include the same material and thickness as those of the first conductive pattern 52 a. The first optical black pattern 52p may have a single-layer or multi-layer structure including at least one selected from a titanium layer, a titanium nitride layer, and a tungsten layer.

On the pixel array area APS, the louver pattern 48a may be disposed on the anti-reflection structure AL. The louver pattern 48a may be correspondingly provided with a low refractive louver pattern 50a thereon. The louver pattern 48a and the low refractive louver pattern 50a may overlap the first pixel separation portion DTI1 and may have a grid shape when viewed in a plan view. The louver pattern 48a may include, for example, at least one selected from titanium and titanium nitride. The low refractive grid patterns 50a may have the same thickness and the same organic material. The low refractive grid pattern 50a may have a refractive index smaller than that of the color filters CF1 and CF2 to be discussed below. For example, the low refractive grid pattern 50a may have a refractive index equal to or less than about 1.3. The louver patterns 48a and the low refractive louver patterns 50a may prevent or reduce crosstalk between adjacent unit pixels UP.

The groove GR may be provided with and filled with a low refractive residual pattern 50r. The first low refractive protection pattern 50b may be disposed in the first hole H1. The second low refractive protection pattern 50c may be disposed in the second hole H2. The low refractive residual pattern 50r, the first low refractive protection pattern 50b, and the second low refractive protection pattern 50c may include the same material as that of the low refractive grid pattern 50 a. The first and second low refractive protection patterns 50b and 50c may be concave on the top surfaces thereof.

On the pixel array area APS, color filters CF1 and CF2 may be disposed between the low refractive grid patterns 50 a. Each of the color filters CF1 and CF2 may have one of blue, green, and red. Alternatively, the color filters CF1 and CF2 may include different colors, such as cyan, magenta, or yellow. In the image sensor 500 according to some example embodiments, the color filters CF1 and CF2 may be arranged in a bayer pattern. Alternatively, the color filters CF1 and CF2 may be arranged in one of a 2×2 four pattern, a 3×3 nine pattern, and a 4×4 sixteen pattern.

A cover pattern CFR may be provided on each of the first and second low refractive protection patterns 50b and 50 c. The overlay pattern CFR may include, for example, a photoresist material. The overlay pattern CFR may prevent or reduce moisture absorption of the back-side via BVS and may solve the step difference between the back-side via BVS.

The second optical black pattern CFB may be disposed on the rear surface 1b of the first substrate 1. The second optical black pattern CFB may include, for example, the same material as that of the blue color filter.

On the pixel array area APS, microlenses ML may be disposed on the color filters CF1 and CF 2. The microlenses ML can have their edges in contact and connected to each other. The microlenses ML may constitute an array. The microlenses ML may be referred to as "microlens arrays"

On the edge region ER, a lens residual layer MLR may be disposed on the second optical black pattern CFB. The lens residual layer MLR may include the same material as that of the microlens ML. On the PAD region PR, the lens residual layer MLR may have an opening 35, the opening 35 being formed to expose the rear surface conductive PAD.

Referring to fig. 8A, a first sub-chip CH1 may be manufactured. An ion implantation process may be performed on the first substrate 1 including the pixel array region APS and the edge region ER, thereby forming the photoelectric conversion element PD and the black photoelectric conversion element PD'. The edge region ER may include a contact region BR1, a via region BR2, and a pad region PR. The device isolation portion STI may be formed on the front surface 1a of the first substrate 1, thereby defining an active region. The device isolation portion STI may be formed by a shallow trench isolation process. The device isolation portion STI and a portion of the first substrate 1 may be etched to form a deep trench 22. The deep trench 22 may limit unit pixels on the pixel array area APS and the optical black area OB.

A separation dielectric layer may be conformally formed on the front surface 1a of the first substrate 1, the deep trenches 22 may be filled with a conductive material, and then an etch-back process may be performed to form the separation conductive patterns 16 in the deep trenches 22 accordingly. Thereafter, the buried dielectric pattern 12 may be formed on the separation conductive pattern 16, and the separation dielectric layer on the front surface 1a may be removed to expose the front surface 1a. Accordingly, the first and second pixel separation portions DTI1 and DTI2 may be formed simultaneously.

Thereafter, a general process may be performed to form the gate dielectric layer Gox, the transfer gate electrode TG, the floating diffusion FD, the first interlayer dielectric layer IL1, the first contact plug 17, and the first wiring line 15 may be formed on the front surface 1a of the first substrate 1.

Still referring to fig. 8A, a second sub-chip CH2 may be prepared, which has the structure discussed with reference to fig. 4. The first sub-chip CH1 may be inverted to allow the rear surface 1b to face upward. The first sub-chip CH1 may be placed such that the first interlayer dielectric layer IL1 is in contact with the second interlayer dielectric layer IL2, and then a thermal compression process may be performed to bond the first sub-chip CH1 to the second sub-chip CH 2.

Referring to fig. 8B, a polishing process may be performed on the rear surface 1B of the first substrate 1 shown in fig. 8A, and thus the thickness of the first substrate 1 may be reduced to a desired thickness. In this step, the separation conductive patterns 16 of the first and pixel separation portions DTI1 and DTI2 may be exposed. The first dielectric layer A1, the titanium oxide layer A2, and the second dielectric layer A3 may be sequentially stacked on the rear surface 1b of the first substrate 1. The first dielectric layer A1, the titanium oxide layer A2, and the second dielectric layer A3 may be each formed by Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). As shown in fig. 7B, the first dielectric layer A1 may be formed of aluminum oxide to have a first thickness T1. As shown in fig. 7B, the second dielectric layer A3 may be formed of aluminum oxide to have a third thickness T3. As shown in fig. 7B, the titanium oxide layer A2 may be formed to have a second thickness T2.

Referring to fig. 8C, the second dielectric layer A3 and the titanium oxide layer A2 may be partially and sequentially etched to form a groove GR exposing the first dielectric layer A1. The position and planar shape of the groove GR may be the same as or similar to those discussed with reference to fig. 3 to 7B.

Referring to fig. 8D, in a state in which the groove GR is formed, a third dielectric layer A4 may be conformally formed on the second dielectric layer A3. The third dielectric layer A4 may be formed by Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). The third dielectric layer A4 may be formed of hafnium oxide. As shown in fig. 7B, the third dielectric layer A4 may be formed to have a fourth thickness T4. The third dielectric layer A4 may conformally cover sidewalls and bottom surfaces of the groove GR. Thus, the anti-reflection structure AL may be formed.

Referring to fig. 8E, on the edge region ER, the anti-reflection structure AL and the first substrate 1 may be partially etched to form a first back trench 46 and a second back trench 60. When the first back trench 46 is formed, the first pixel separation portion DTI1 may be partially etched to expose the separation conductive pattern 16 of the first pixel separation portion DTI 1. On the edge region ER, the anti-reflection structure AL, the first substrate 1, the first interlayer dielectric layer IL1, and the second interlayer dielectric layer IL2 may be partially etched to form a first hole H1 and a second hole H2. The first and second back grooves 46 and 60 and the first and second holes H1 and H2 may be formed between the grooves GR.

Referring to fig. 8F, a conductive layer may be conformally stacked on the rear surface 1b of the first substrate 1, and the conductive layer may be etched to form a first conductive pattern 54a, a second conductive pattern 52c, a rear connection line 52b, a first optical black pattern 52p, and first and second rear vias BVS (1) and BVS (2). The third dielectric layer A4 may serve as an etch stop layer when the conductive layer is etched. The first and second holes H1 and H2 may be filled with the sacrificial layer 70, a mask pattern (not shown) may be formed to cover a specific region, and then an electroplating or deposition process may be performed to form first and second metal patterns 54a and 54b filling the first and second back trenches 46 and 60, respectively. Accordingly, the back contact BCA and the back conductive PAD can be formed.

Referring to fig. 8G, a light shielding layer and a low refractive layer may be sequentially and conformally stacked on the rear surface 1b of the first substrate 1, and the light shielding layer and the low refractive layer may be etched to form a light shielding grid pattern 48a and a low refractive grid pattern 50a. The third dielectric layer A4 may serve as an etch stop layer when etching the light shielding layer and the low refractive layer.

Referring to fig. 8H, a protective layer 56 may be conformally formed on the rear surface 1b of the first substrate 1. A general process may be performed to form the color filters CF1 and CF2 and the second optical black pattern CFB. The second optical black pattern CFB may be formed simultaneously with the formation of the blue color filter. The microlenses ML and the lens remaining layer MLR may be formed on the color filters CF1 and CF2 and the second optical black pattern CFB. Subsequently, referring to fig. 4, on the PAD region PR, an opening 35 may be formed in the lens residual layer MLR exposing the rear surface conductive PAD.

Fig. 9 is a sectional view taken along line A-A' of fig. 3.

Referring to fig. 9, an image sensor 501 according to some example embodiments may not include the back connection line 52b of fig. 4. The back bonding wire 52b may not be disposed in the groove GR. The back contact BCA, the first back via BVS (1), the back conductive PAD, and the second back via BVS (2) may be electrically insulated from each other without being electrically connected to each other. The groove GR may be disposed between the back contact BCA, the first back via BVS (1), the back conductive PAD, and the second back via BVS (2). The groove GR may cut the titanium oxide layer A2, and thus may prevent or reduce leakage current or electrical short between the back contact BCA, the first back via BVS (1), the back conductive PAD, and the second back via BVS (2). Other configurations may be the same or similar to those discussed with reference to fig. 3-7B.

Fig. 10 illustrates a cross-sectional view showing an image sensor according to some example embodiments of the inventive concepts. Fig. 11A shows an enlarged view showing a portion P1 of fig. 10. Fig. 11B shows an enlarged view showing the P2 portion of fig. 10.

Referring to fig. 10, 11A and 11B, an image sensor 502 according to some example embodiments may have a structure in which a first sub-chip CH1 and a second sub-chip CH2 are bonded to each other. The first sub-chip CH1 may be disposed on the second sub-chip CH 2. The first sub-chip CH1 may include a first substrate 1.

Each of the first and second pixel separation portions DTI1 and DTI2 may be located in a deep trench 22 formed from the rear surface 1b of the first substrate 1 toward the front surface 1 a. Each of the first and second pixel separation portions DTI1 and DTI2 may be a back side deep trench isolation (BDTI). A portion of the anti-reflection structure AL may be inserted into the deep trench 22 to constitute the first and second pixel separation portions DTI1 and DTI2. For example, each of the first and second pixel separation portions DTI1 and DTI2 may include a first dielectric pattern A1P, a titanium oxide pattern A2P, and a second dielectric pattern A3P sequentially covering an inner wall of the deep trench 22. The second dielectric pattern A3P may fill the deep trench 22. The first dielectric pattern A1P may be formed of a portion of the first dielectric layer A1 of the anti-reflection structure A1. The titanium oxide pattern A2P may be formed of a portion of the titanium oxide layer A2 of the anti-reflection structure AL. The second dielectric pattern A3P may be formed of a portion of the second dielectric layer A3 of the anti-reflection structure AL.

The first, second and third dielectric patterns A1P, A3P and A4 may include materials different from each other. For example, the first dielectric layer A1 and the first dielectric pattern A1P may include aluminum, the second dielectric layer A3 and the second dielectric pattern A3P may include silicon oxide, and the third dielectric layer A4 may include hafnium oxide.

The first substrate 1 may have a first refractive index n1, the first dielectric pattern A1P may have a second refractive index n2, the titanium oxide layer A2 may have a third refractive index n3, and the second dielectric pattern A3P may have a fourth refractive index n4. The average value (n2+n3)/2 of the second refractive index n2 and the third refractive index n3 may be smaller than the first refractive index n1 and larger than the fourth refractive index n4. For example, the first refractive index n1 may range from about 4.0 to about 4.4. The second refractive index n2 may range from about 2.0 to about 3.0. The third refractive index n3 may range from about 2.2 to about 2.8. The fourth refractive index n4 may range from about 1.0 to about 1.9.

As shown in fig. 11B, the first dielectric layer A1 may have a first thickness T1, the titanium oxide layer A2 may have a second thickness T2, the second dielectric layer A3 may have a third thickness T3, and the third dielectric layer A4 may have a fourth thickness T4. In some example embodiments, the second thickness T2 may be less than the third thickness T3 and greater than each of the first thickness T1 and the fourth thickness T4.

For example, the first thickness T1 may range from aboutTo about->The second thickness T2 may range from aboutTo about->The third thickness T3 may range from about +.>To about->The fourth thickness T4 may range from about +. >To about->

As shown in fig. 11B, the relationship between the refractive index and/or the thickness may allow the light L1 incident on the microlens ML to be refracted and penetrate the multilayer structure of the antireflection structure AL, and then be appropriately incident on the photoelectric conversion element PD. Accordingly, the image sensor 502 can have increased light receiving efficiency and clear image quality.

In addition, in the image sensor 502 according to the inventive concept, the anti-reflection structure AL may include a titanium oxide layer A2. The titanium oxide layer A2 can completely reduce the reflectance of all colors, and in particular, can further reduce the reflectance of blue light. Accordingly, quantum Efficiency (QE) of the blue pixel can be increased.

The first dielectric pattern A1P and the first dielectric layer A1 may function as a negative fixed charge layer. Therefore, dark current and white spots can be reduced.

According to some example embodiments, the image sensor 502 may not include the back contact BCA. On the edge region ER, a back surface via BVS and a back surface conductive PAD may be provided on the back surface 1b of the first substrate 1. As shown in fig. 6, the second pixel separation portion DTI2 may surround each of the back surface passages BVS when viewed in a plan view. The backside via BVS may include a first backside via BVS (1) and a second backside via BVS (2). Other configurations may be the same or similar to those discussed with reference to fig. 3-7B.

Referring to fig. 12, an image sensor 503 according to some example embodiments may have a structure in which first to third sub-chips CH1 to CH3 are sequentially stacked. The first sub-chip CH1 may have, for example, an image sensing function.

The first sub-chip CH1 may include a transfer gate electrode TG on the front surface 1a of the first substrate 1 and a first interlayer dielectric layer IL1 covering the transfer gate electrode TG. A first device isolation portion STI1 defining an active portion may be provided in the first substrate 1. The first sub-chip CH1 may include neither the back contact BCA nor the back via BVS. The first sub-chip CH1 may further include internal connection contacts 17a. On the edge region ER, at least one internal connection contact 17a may penetrate the buried dielectric pattern 12 of the first pixel separation portion DTI1 to connect one of the first wirings 15 to the separation conductive pattern 16 of the first pixel separation portion DTI1, thereby applying a negative bias to the separation conductive pattern 16. At least another one of the internal connection contacts 17a may penetrate the buried dielectric pattern 12 of the second pixel separation portion DTI2 under the back surface conductive PAD to connect one of the first wirings 15 to the separation conductive pattern 16 of the second pixel separation portion DTI 2. The first conductive pad CP1 may be disposed in the lowermost first interlayer dielectric layer IL1. The first conductive pad CP1 may include copper.

The second sub-chip CH2 may include a second substrate SB2, a selection gate electrode SEL, a source follower gate electrode SF, and a reset gate electrode (not shown) disposed on the second substrate SB2, and a second interlayer dielectric layer IL2 covering the selection gate electrode SEL, the source follower gate electrode SF, and the reset gate electrode. The second substrate SB2 may be provided therein with a second device isolation portion STI2 defining an active portion. The second interlayer dielectric layer IL2 may be provided therein with the second contact 215 and the second wiring 217. The second conductive pad CP2 may be disposed in the uppermost second interlayer dielectric layer IL2. The second conductive pad CP2 may include copper. The second conductive pad CP2 may be in contact with the first conductive pad CP 1. The source follower gate electrode SF may be correspondingly connected to the floating diffusion FD of the first sub-chip CH 1.

The third sub-chip CH3 may include a third substrate SB3, a peripheral transistor PTR disposed on the third substrate SB3, and a third interlayer dielectric layer IL3 covering the peripheral transistor PTR. The third substrate SB3 may be provided therein with a third device isolation portion STI3 defining an active portion. The third interlayer dielectric layer IL3 may be provided therein with a third contact 317 and a third wiring 315. The uppermost third interlayer dielectric layer IL3 may be in contact with the second substrate SB 2. The through electrode TSV may penetrate the second interlayer dielectric layer IL2, the second device isolation portion STI2, the second substrate SB2, and the third interlayer dielectric layer IL3, thereby connecting one of the second wirings 217 to one of the third wirings 315. The sidewalls of the through electrode TSV may be surrounded by the via dielectric layer TVL. The third sub-chip CH3 may include a circuit for driving one or both of the first sub-chip CH1 and the second sub-chip CH2 or for storing an electrical signal generated from one or both of the first sub-chip CH1 and the second sub-chip CH 2.

In the image sensor of the present inventive concept, the anti-reflection structure may include a titanium oxide layer. The titanium oxide layer can completely reduce the reflectivity of all colors, and especially can further reduce the reflectivity of blue light. Accordingly, the Quantum Efficiency (QE) of color pixels, particularly blue pixels, can be increased.

In the image sensor of the inventive concept, a groove of the anti-reflection structure may be formed between the back contact, the back via and the back conductive pad on the edge region, and the groove may cut the titanium oxide layer. Accordingly, the generation of leakage current due to the titanium oxide layer between the back surface contact, the back surface via, and the back surface conductive pad adjacent to each other can be reduced or prevented. As a result, it is possible to prevent or reduce operation errors and realize a clear image of the image sensor.

When the term "about" or "substantially" is used in this specification with a numerical value, it is intended that the relevant numerical value includes manufacturing or operating tolerances (e.g., ±10%) around the stated numerical value. Furthermore, when the words "generally" and "substantially" are used in connection with a geometric shape, it is meant that the accuracy of the geometric shape is not required, but that the shape is within the scope of the present disclosure. Further, whether numerical values or shapes are modified to be "about" or "substantially," it is understood that such numerical values and shapes should be construed to include manufacturing or operating tolerances (e.g., ±10%) around the numerical values or shapes.

The image sensor (or other circuitry, e.g., row driver 1003, row decoder 1002, timing generator 1005, input/output buffer 1008, column decoder 1004, CDS 1006, ADC 1007) may include: hardware, including logic circuitry; a hardware/software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and the like.

Although the present inventive concept has been described with reference to some exemplary embodiments thereof shown in the drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential characteristics of the present inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the present inventive concept. The embodiments of fig. 3 to 12 may be combined with each other.

The U.S. non-provisional application claims priority from korean patent application No. 10-2022-0055033 filed on day 5, month 3 of 2022 and korean patent application No. 10-2022-0095589 filed on day 8, month 1 of 2022, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. An image sensor, comprising:

a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a pixel array region and an edge region;

an anti-reflective structure on the second surface;

a pixel separation portion in the first substrate, the pixel separation portion separating pixels from each other; and

a microlens array on the anti-reflective structure, the anti-reflective structure including a first dielectric layer, a titanium oxide layer, a second dielectric layer, and a third dielectric layer sequentially stacked, the first dielectric layer, the second dielectric layer, and the third dielectric layer including materials different from each other, and the third dielectric layer penetrating the second dielectric layer and the titanium oxide layer on the edge region to be in contact with the first dielectric layer.

2. The image sensor of claim 1, wherein

The first dielectric layer comprises aluminum oxide,

the second dielectric layer comprises silicon oxide, and

the third dielectric layer includes hafnium oxide.

3. The image sensor of claim 1, wherein

The first substrate has a first refractive index,

The first dielectric layer has a second refractive index,

the titanium oxide layer has a third refractive index,

the second dielectric layer has a fourth refractive index, and

an average of the second refractive index and the third refractive index is smaller than the first refractive index and larger than the fourth refractive index.

4. The image sensor of claim 1, further comprising first and second contacts on the second surface of the first substrate on the edge region, and

wherein the method comprises the steps of

The pixel separating part extends to the edge region,

the first contact penetrates a portion of the first substrate to be in contact with the pixel separation portion, and

between the first contact and the second contact, the third dielectric layer penetrates the second dielectric layer and the titanium oxide layer to be in contact with the first dielectric layer.

5. The image sensor of claim 4, wherein

The pixel separation portion includes a separation conductive pattern and a separation dielectric pattern between the separation conductive pattern and the first substrate, and

the first contact is in contact with the separated conductive pattern.

6. The image sensor of claim 4, further comprising:

A first interlayer dielectric layer on the first surface of the first substrate;

a first interconnect layer in the first interlayer dielectric layer;

a second interlayer dielectric layer under the first interlayer dielectric layer;

a second interconnect layer in the second interlayer dielectric layer; and

a second substrate under the second interlayer dielectric layer,

wherein the second contact penetrates the first substrate, the first interlayer dielectric layer, and a portion of the second interlayer dielectric layer to contact the second interconnect layer.

7. The image sensor of claim 4, wherein

On the edge region, recesses are in the titanium oxide layer and the second dielectric layer,

the first dielectric layer is exposed on a bottom surface of the recess,

the third dielectric layer conformally covers the side surfaces and the bottom surface of the recess, and

the image sensor further includes a conductive line connecting the first contact to the second contact, the conductive line covering the side surface and the bottom surface of the recess.

8. The image sensor of claim 4, wherein

The first dielectric layer is exposed on a bottom surface of the recess,

the groove surrounds the second contact when seen in plan view.

9. The image sensor of claim 8 further comprising a substrate isolation portion surrounding the second contact between the second contact and the recess and spaced apart from the second contact on the edge region,

wherein a first spacing between the second contact and the substrate isolation portion is greater than a second spacing between the substrate isolation portion and the recess.

10. The image sensor of claim 1, wherein

the first dielectric layer is exposed on a bottom surface of the recess,

the image sensor further includes

A low refractive grid pattern on the pixel array region of the first substrate and the anti-reflective structure; and

And filling the low-refraction residual pattern of the groove.

11. The image sensor of claim 1, further comprising:

a first interconnect layer in the first interlayer dielectric layer;

a second interconnect layer in the second interlayer dielectric layer;

a second substrate under the second interlayer dielectric layer;

conductive pads on the edge region and on the second surface of the first substrate; and

a via on the edge region, the via penetrating the first substrate, the first interlayer dielectric layer, and a portion of the second interlayer dielectric layer to contact the second interconnect layer,

wherein the third dielectric layer penetrates the second dielectric layer and the titanium oxide layer between the conductive pad and the via on the edge region to contact the first dielectric layer.

12. The image sensor of claim 1, wherein

The pixel separation portion is in a deep trench extending from the second surface toward the first surface, and

A portion of the anti-reflection structure is inserted into the deep trench to constitute the pixel separation portion.

13. The image sensor of claim 11, wherein

The first dielectric layer has a first thickness,

the titanium oxide layer has a second thickness,

the second dielectric layer has a third thickness,

the third dielectric layer has a fourth thickness, and

the second thickness is less than the third thickness and greater than each of the first thickness and the fourth thickness.

14. The image sensor of claim 1, wherein

the first dielectric layer is exposed on a bottom surface of the recess,

the groove surrounds the pixel array area when viewed in plan.

15. An image sensor, comprising:

an anti-reflective structure on the second surface;

A pixel separation portion on the first substrate, the pixel separation portion separating pixels from each other;

a color filter on the antireflective structure;

a microlens array on the color filter;

a first interconnect layer in the first interlayer dielectric layer;

a second interconnect layer in the second interlayer dielectric layer;

a second substrate under the second interlayer dielectric layer;

a first contact on the second surface of the first substrate on the edge region; and

a second contact on the edge region, the second contact penetrating the first substrate, the first interlayer dielectric layer, and a portion of the second interlayer dielectric layer to contact the second interconnect layer,

the anti-reflection structure includes a first dielectric layer, a titanium oxide layer, a second dielectric layer, and a third dielectric layer sequentially stacked, the first dielectric layer, the second dielectric layer, and the third dielectric layer including materials different from each other, and between the first contact and the second contact, the third dielectric layer penetrating the second dielectric layer and the titanium oxide layer to be in contact with the first dielectric layer.

16. The image sensor of claim 15, wherein

The first substrate has a first refractive index,

the first dielectric layer has a second refractive index,

the titanium oxide layer has a third refractive index,

the second dielectric layer has a fourth refractive index, and

17. The image sensor of claim 15, wherein

the first contact is in contact with the separated conductive pattern.

18. An image sensor, comprising:

an anti-reflective structure on the second surface;

a microlens array on the antireflective structure,

the antireflective structure includes a first dielectric layer, a titanium oxide layer, a second dielectric layer, and a third dielectric layer sequentially stacked, the first dielectric layer, the second dielectric layer, and the third dielectric layer including materials different from each other,

A recess in the titanium oxide layer and the second dielectric layer on the edge region, the first dielectric layer being exposed on a bottom surface of the recess, the third dielectric layer conformally covering side surfaces and the bottom surface of the recess, and the recess surrounding the pixel array region when viewed in plan.

19. The image sensor of claim 18, wherein

The first dielectric layer has a first thickness,

the titanium oxide layer has a second thickness,

the second dielectric layer has a third thickness,

the third dielectric layer has a fourth thickness, and

the second thickness is less than the third thickness and greater than the first thickness and the fourth thickness.

20. The image sensor of claim 18, further comprising:

a first interconnect layer in the first interlayer dielectric layer;

a second interconnect layer in the second interlayer dielectric layer;

a second substrate under the second interlayer dielectric layer;

wherein the pixel separation portion includes a separation conductive pattern and a separation dielectric pattern between the separation conductive pattern and the first substrate,

wherein the recess is between the first contact and the second contact, and

wherein the first contact is in contact with the separated conductive pattern.