CN117012722A

CN117012722A - Semiconductor structure and forming method thereof

Info

Publication number: CN117012722A
Application number: CN202310847578.XA
Authority: CN
Inventors: 沙哈吉·B·摩尔; 张正伟
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-07-14
Filing date: 2023-07-11
Publication date: 2023-11-07

Abstract

According to embodiments of the present application, a semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes receiving a workpiece including a channel region over a substrate, source/drain features adjacent to the channel region, a gate structure over the channel region, and a dielectric structure over the source/drain features. The method further includes forming a contact opening through the dielectric structure to expose the source/drain feature, forming a silicide layer in the contact opening and over the source/drain feature, forming a tungsten-containing layer in the contact opening and over the silicide layer, and forming a conductive layer in the contact opening and over the tungsten-containing layer, wherein the composition of the conductive layer is different than the composition of the tungsten-containing layer.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present application relate to semiconductor structures and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in several generations of ICs, each of which has smaller, more complex circuitry than the previous generation. During the development of ICs, it is common for the functional density (i.e., the number of interconnected devices per chip area) to increase, while the geometry (i.e., the smallest component (or wire) that can be created using the manufacturing process) is reduced. Such scaled down processes generally provide benefits by increasing production efficiency and reducing associated costs.

As Integrated Circuit (IC) technology advances toward smaller technology nodes, parasitic resistance of source/drain contacts disposed over source/drain features may severely impact the overall performance of the IC device. While existing source/drain contacts are generally adequate for their intended purpose, they are not satisfactory in all respects.

Disclosure of Invention

According to an embodiment of the present application, there is provided a method of forming a semiconductor structure, including: receiving a workpiece, the workpiece comprising: a channel region over the substrate; source/drain features adjacent the channel region; a gate structure over the channel region; and a dielectric structure over the source/drain features. The method of forming a semiconductor structure further includes forming a contact opening through the dielectric structure to expose the source/drain feature; forming a silicide layer in the contact opening and on the source/drain feature; forming a tungsten-containing layer in the contact opening and on the silicide layer; and forming a conductive layer in the contact opening and on the tungsten-containing layer, wherein the composition of the conductive layer is different from the composition of the tungsten-containing layer.

According to another embodiment of the present application, there is provided a method of forming a semiconductor structure, including: receiving a workpiece comprising a first region and a second region, the workpiece comprising: a first gate structure over channel regions of the first fin and the second fin over the first region; a p-type source/drain feature disposed over and spanning over the first fin and the second fin; a second gate structure over channel regions of the third fin and the fourth fin over the second region; an n-type source/drain feature disposed over and spanning over the third and fourth fins over the second region; and a dielectric structure over the p-type source/drain feature and the n-type source/drain feature. The method of forming a semiconductor structure further includes: forming a first contact opening extending through the dielectric structure to expose the p-type source/drain feature and a second contact opening extending through the dielectric structure to expose the n-type source/drain feature; performing a first deposition process to form a first conductive layer in the first contact opening and a second conductive layer in the second contact opening; and performing a second deposition process to form a third conductive layer over the first conductive layer and a fourth conductive layer over the second conductive layer, wherein the first deposition process is different from the second deposition process and the composition of the first conductive layer and the second conductive layer is different from the composition of the third conductive layer and the fourth conductive layer.

According to yet another embodiment of the present application, there is provided a semiconductor structure including: a gate structure over channel regions of the first fin and the second fin; source/drain features disposed over and spanning over the first fin and the second fin; a dielectric layer over the source/drain features; and a source/drain contact extending through the dielectric layer and electrically coupled to the source/drain feature, wherein the source/drain contact includes a first conductive layer over the source/drain feature and a second conductive layer over the first conductive layer, the composition of the first conductive layer being different than the composition of the second conductive layer, and wherein a bottom surface of the second conductive layer is over a top surface of the source/drain feature in a first cross-sectional view through the gate structure and the source/drain feature.

Embodiments of the present application relate to source/drain contacts and methods of forming the same.

Drawings

The disclosure is best understood from the following detailed description when read with the accompanying drawing figures. It is noted that the various components are not drawn to scale and are for illustrative purposes only, according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a flow chart of a method for forming a semiconductor structure in accordance with one or more aspects of the present disclosure.

Fig. 2 illustrates a partial top view of an exemplary workpiece that is to undergo various stages of operation in the method of fig. 1, in accordance with various aspects of the present disclosure.

Fig. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A (fig. 3A-15A) illustrate partial cross-sectional views of a workpiece taken along line A-A' shown in fig. 2 during various stages of manufacture of the method of fig. 1, according to one or more aspects of the present disclosure.

Fig. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B (fig. 3B-15B) illustrate partial cross-sectional views of a workpiece taken along line B-B' shown in fig. 2 during various stages of manufacture of the method of fig. 1, according to one or more aspects of the present disclosure.

Fig. 16A and 16B illustrate partial cross-sectional views of a first alternative workpiece taken along lines A-A 'and B-B', respectively, shown in fig. 2, in accordance with one or more aspects of the present disclosure.

Fig. 17A and 17B illustrate partial cross-sectional views of a second alternative workpiece taken along lines A-A 'and B-B', respectively, shown in fig. 2, in accordance with one or more aspects of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, of the different components used to implement the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In addition, when numerical values or numerical ranges are described as "about," "approximately," etc., the term is intended to encompass numerical values within a reasonable range, taking into account variations that inherently occur during manufacture as understood by one of ordinary skill in the art. For example, a value or range of values encompasses a reasonable range including the recited value, such as within +/-10% of the recited value, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value. For example, a material layer has a thickness of "about 5nm," which may encompass a size range from 4.25nm to 5.75nm, with a manufacturing tolerance of +/-15% known to one of ordinary skill in the art associated with depositing the material layer.

As Integrated Circuit (IC) technology evolves toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-to-channel coupling, reducing off-state current, and reducing Short Channel Effects (SCE). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed over multiple sides of a channel region. Fin field effect transistors (finfets) and multi-bridge channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. A FinFET has a raised channel wrapped by gates on multiple sides (e.g., the gate wraps the top and sidewalls of a "fin" of semiconductor material extending from a substrate). MBC transistors have a gate structure that may extend partially or entirely around the channel region to provide access to the channel region on two or more sides. MBC transistors may also be referred to as wrap gate transistors (SGT) or full ring Gate (GAA) transistors because their gate structure surrounds the channel region. The channel region of the MBC transistor may be formed from nanowires, nanoplates, other nanostructures, and/or other suitable structures. The shape of the channel region is also given the MBC transistor alternative names, such as a nanoplate transistor or nanowire transistor.

To form source/drain features for multi-gate devices, source/drain regions of fin-shaped active regions (for FinFET or MBC transistors) are recessed. As used herein, a source/drain region or "s/d region" may refer to the source or drain of a device. It may also refer to a region that provides a source and/or drain for multiple devices. After recessing, a plurality of epitaxial layers are sequentially formed over the source/drain regions. A silicide layer and source/drain contacts may then be formed over the epitaxial layers of the source/drain features to provide electrical connection. During the formation of the source/drain contacts, in some prior embodiments, the epitaxial layer of the source/drain features may be recessed, and thus the source/drain contacts may extend into the source/drain features, resulting in reduced source/drain contact landing area and increased resistance. In some existing embodiments, source/drain contacts formed by conventional fabrication processes may have one or more bubbles or voids trapped therein, which may increase the parasitic resistance of the source/drain contacts, thereby degrading the electrical performance of the IC device.

The present disclosure provides a method for forming a semiconductor structure having reduced resistance. In an exemplary method, contact openings are formed after source/drain features are formed. The formation of the contact openings slightly recesses the source/drain features. A silicide layer is then formed in the contact opening. In this embodiment, in a first cross-sectional view, the silicide layer has a substantially planar top surface, and in a second cross-sectional view, the silicide layer has a concave top surface. After forming the silicide layer, a tungsten layer formed by a Physical Vapor Deposition (PVD) process is formed in the contact opening and on the silicide layer. In a first cross-sectional view, the tungsten layer has a substantially planar top surface, while in a second cross-sectional view, the tungsten layer has a convex top surface. The top surface of the tungsten layer is over the top surfaces of the source/drain features. After forming the tungsten layer, a metal layer (e.g., cobalt, ruthenium, or molybdenum) formed by a Chemical Vapor Deposition (CVD) process is formed in the contact opening and on the tungsten layer. The metal layer is separated from the silicide layer by a tungsten layer. By forming a bi-layer source/drain contact over a silicide layer having a substantially planar top surface, the landing area of the source/drain contact and the contact area between the source/drain contact and the silicide layer may be increased, thereby reducing the resistance of the IC device and improving the performance of the IC device.

Various aspects of the disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, fig. 1 is a flow chart illustrating a method 100 of forming a semiconductor structure, in accordance with an embodiment of the present disclosure. The method 100 is described below in conjunction with fig. 2, 3A-17A, and 3B-17B, with fig. 2, 3A-17A, and 3B-17B being partial top/cross-sectional views of a workpiece 200 at different stages of manufacture according to an embodiment of the method 100. The method 100 is merely one example and is not intended to limit the present disclosure to what is explicitly described therein. Additional steps may be provided before the method 100, during the method 100, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around to obtain other embodiments of the method. For simplicity, not all steps are described in detail herein. Since the workpiece 200 will be manufactured into a semiconductor structure at the end of the manufacturing process, the workpiece 200 may be referred to as the semiconductor structure 200 when the context requires. For the avoidance of doubt, X, Y and Z directions in fig. 2, 3A-17A, 3B-17B are perpendicular to each other and are used consistently throughout this disclosure. Throughout this disclosure, like reference numerals refer to like parts unless otherwise specified.

Referring to fig. 1, 2 and 3, the method 100 includes a block 102 in which a workpiece 200 including a first region 10 and a second region 20 is received. Fig. 2 depicts a partial top view of a workpiece 200 that is to undergo various stages of operation in the method of fig. 1, in accordance with various aspects of the present disclosure. Fig. 3A shows a partial cross-sectional view of the workpiece 200 taken along the line A-A 'shown in fig. 2, and fig. 3B shows a partial cross-sectional view of the workpiece 200 taken along the line B-B' shown in fig. 2. Since the partial cross-sectional view of the workpiece 200 taken along line C-C ' is similar to the partial cross-sectional view of the workpiece 200 taken along line A-A ', the partial cross-sectional view of the workpiece 200 taken along line C-C ' is omitted for simplicity.

As shown in fig. 3A-3B, the workpiece 200 includes a substrate 202. The substrate 202 may be an elemental (single element) semiconductor, such as silicon (Si) or germanium (Ge) of crystalline structure; compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); alloy semiconductors such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP); non-semiconductor materials such as soda lime glass, fused silica, and/or calcium fluoride (CaF) ₂ ) The method comprises the steps of carrying out a first treatment on the surface of the And/or combinations thereof. In one embodiment, the substrate 202 is a silicon (Si) substrate. The substrate 202 may be of uniform composition or may include multiple layers, some of which may be selectively etched to form fin-shaped active regions (e.g., fin-shaped active regions 204A-204D). These layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thereby tailor device performance. Examples of layered substrates include a silicon-on-insulator (SOI) substrate 202. In some such examples, the layers of the substrate 202 may include insulators such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, and/or other suitable insulationAnd (3) edge materials. Doped regions, such as wells, may be formed on the substrate 202. In the embodiment shown in fig. 2, a portion of the substrate 202 in the first region 10 is doped with n-type dopants and a portion of the substrate 202 in the second region 20 is doped with p-type dopants. The n-type dopant may include phosphorus (P) or arsenic (As). The p-type dopant may include boron (B), boron difluoride (BF ₂ ) Or indium (In). The n-type well and the p-type well may be formed using ion implantation or thermal diffusion and may be considered as part of the substrate 202. As will be described further below, the first region 10 is a p-type field effect transistor (PFET) region for forming a p-type field effect transistor (PFET) and the second region 20 is an n-type field effect transistor (NFET) region for forming an n-type field effect transistor (NFET).

Still referring to fig. 2 and 3A-3B, the workpiece 200 includes a plurality of fin-shaped active regions (e.g., 204A, 204B, 204C, 204D) over the substrate 202. In the present embodiment, the first region 10 includes a fin active region 204A and a fin active region 204B extending perpendicularly from the substrate 202, and the second region 20 includes a fin active region 204C and a fin active region 204D extending perpendicularly from the substrate 202. The number of fin-shaped active regions depicted in fig. 2 and 3A-3B is merely an example, and the workpiece 200 may include any suitable number of active regions. Each of the fin active regions 204A-204D may be formed from a respective semiconductor layer over the substrate 202 and a top portion 202t (shown in fig. 3B) of the substrate 202 using a combination of photolithography and etching steps. For example, in the present embodiment, to form the fin-shaped active regions 204A-204B in the first region 10 (e.g., PFET region) and the fin-shaped active regions 204C-204D in the second region 20 (e.g., NFET region), a first semiconductor layer formed of silicon germanium (SiGe) is formed over a portion of the substrate 202 in the first region 10 and a second semiconductor layer formed of silicon (Si) is formed over a portion of the substrate 202 in the second region 20. The first semiconductor layer, the second semiconductor layer, and the top portion 202t of the substrate 202 are patterned to form fin active regions 204A-204B in the first region 10 and fin active regions 204C-204D in the second region. Exemplary lithographic processes include spin coating a photoresist layer, soft baking of the photoresist layer, mask alignment, exposure, post exposure baking, developing the photoresist layer, rinsing, and drying (e.g., hard baking). In some cases, the patterning of the fin active regions 204A-204D may be performed using a double patterning or multiple patterning process to create a pattern having a smaller pitch than that obtainable using a single direct photolithography process. The etching process may include dry etching, wet etching, and/or other suitable processes. In this embodiment, finfets will be formed in the first region 10 and the second region 20. In some other embodiments, GAA transistors may be formed in the first region 10 and the second region 20. In an embodiment where GAA transistors are to be formed, instead of forming respective semiconductor layers on the substrate 202, a vertical stack of alternating semiconductor layers comprising a plurality of channel layers interleaved by a plurality of sacrificial layers may be formed over the substrate 202. Each of the channel layers may be formed of silicon (Si), and each of the sacrificial layers may be formed of silicon germanium (SiGe).

As shown in fig. 2 and 3B, each of the fin-shaped active regions 204A-204D extends longitudinally along the X-direction and is spaced apart from one another along the Y-direction by portions (shown in fig. 3B) of the spacer member 206. The isolation feature 206 may also be referred to as a Shallow Trench Isolation (STI) feature 206. In an example process, a dielectric material for isolation feature 206 is first deposited over workpiece 200, filling the trenches between fin active regions 204A-204D with the dielectric material. In some embodiments, the dielectric material may include silicon oxide, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectrics, combinations thereof, and/or other suitable materials. In various examples, the dielectric material may be deposited by a CVD process, a Flowable CVD (FCVD) process, spin coating, and/or other suitable processes. The deposited dielectric material is then thinned and planarized, such as by a Chemical Mechanical Polishing (CMP) process, until the top surfaces of the fin active regions 204A-204D are exposed. The planarized dielectric material is further recessed or etched back by a dry etch process, a wet etch process, and/or combinations thereof to form isolation features 206. In some embodiments shown in fig. 3B, upper portions 204A-204D of fin active regions 204A-204D rise above isolation feature 206, while lower portions of fin active regions 204A-204D (formed by top portion 202t of substrate 202) remain covered or buried in isolation feature 206. In an embodiment, the height T1 of each of the upper portions 204a-204d may be between about 30nm and about 80 nm. In an embodiment, the top surfaces of the upper portions 204a-204d are coplanar. The top surface of the upper portion 204A/204B/204C/204D (i.e., the top surface of the fin-shaped active region 204A/204B/204C/204D) is referred to as the top surface 204t. In this embodiment, the upper portions 204a-204b are formed of silicon germanium, while the upper portions 204c-204d are formed of silicon. In this embodiment, fin active region 204A and fin active region 204B will serve as dual fin active regions for the dual fin devices in first region 10. The fin active region 204C and the fin active region 204D will serve as dual fin active regions for the dual fin devices in the second region 20. The present disclosure also applies to single-fin devices or other multi-fin devices.

Workpiece 200 also includes hybrid fins 210 that extend into isolation feature 206. In the embodiment shown in fig. 3B, hybrid fin 210 is formed to isolate subsequently formed source/drain features (e.g., source/drain features 222P and 222N). Hybrid fin 210 may be formed with spacer component 206 and may include an outer layer 210a and an inner layer 210b. In an example process, a dielectric material for the isolation feature 206 is first conformally deposited over the workpiece 200. Thereafter, an outer layer 210a and an inner layer 210b are sequentially deposited over the workpiece 200. After the planarization process, only the dielectric layer for the isolation feature 206 is selectively etched back to form the isolation feature 206. Due to the selective nature, the etch back also leaves hybrid fin 210. Hybrid fin 210 is not formed between the fins in the dual-fin active region because the dielectric material for isolation feature 206 substantially fills the space between fin active region 204A and fin active region 202B and between fin active region 204C and fin active region 204D. Hybrid fins 210 may also be referred to as dielectric fins 210 because they are formed of a dielectric material. In an embodiment, the outer layer 210a may include silicon oxynitride (SiOCN), and the inner layer 210b may also include silicon oxynitride (SiOCN), the carbon concentration of the outer layer 210a being greater than the carbon concentration of the inner layer 210b. As shown in fig. 3B, each of hybrid fins 210 extends into isolation feature 206 and is spaced apart from fin active regions 204A-204D or a lower portion of substrate 202 by isolation feature 206.

The fin-shaped active region 204 extends longitudinally along the X-direction and is divided into a channel region overlapping the dummy gate stack 212 (described below) and a source/drain region not overlapping the dummy gate stack 212 may refer to a source region or a drain region, either alone or in combination depending on the context. Each of the channel regions is disposed between two source/drain regions along the X direction. Three dummy gate stacks 212 are shown in fig. 2 and 3A, but the workpiece 200 may include any suitable number of dummy gate stacks 212. In this embodiment, a gate replacement process (or a back-gate process) is employed, wherein the dummy gate stack 212 serves as a placeholder for a functional gate structure (e.g., gate structure 230 shown in fig. 9A). Other processes and configurations are possible. The dummy gate stack 212 includes a dummy gate dielectric layer 212a, a dummy gate electrode layer 212b over the dummy gate dielectric layer 212a, a first gate top hard mask layer 212c over the dummy gate electrode layer 212b, and a second gate top hard mask layer 212d over the first gate top hard mask layer 212 c. The dummy gate dielectric layer 212a may include silicon oxide. The dummy gate electrode layer 212b may include polysilicon. The first gate top hard mask layer 212c and the second gate top hard mask layer 212d may include a silicon oxide layer, silicon nitride, and/or other suitable materials. Suitable deposition processes, photolithography and etching processes may be employed to form the dummy gate stack 212.

Referring to fig. 1 and 4A-4B, the method 100 includes a block 104 in which a first spacer layer 214 is conformally deposited over the workpiece 200 and a second spacer layer 216 is conformally deposited over the first spacer layer 214. First spacer layer 214 is conformally deposited over workpiece 200 including fin active regions 204A-204D and hybrid fin 210 by ALD, CVD, or any other suitable deposition process. For ease of description, the term "conformally" may be used herein to describe a layer having a substantially uniform thickness over various regions of the workpiece 200. The first spacer layer 214 may comprise silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitrides, or other suitable dielectric materials. In an embodiment, the first spacer layer 214 comprises silicon carbonitride (SiCN). After forming the first spacer layer 214, a second spacer layer 216 is conformally deposited over the first spacer layer 214 by ALD, CVD, or any other suitable deposition process. The second spacer layer 216 may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitrides, or other suitable dielectric materials. The composition of the first spacer layer 214 is different from the composition of the second spacer layer 216 to introduce etch selectivity. In an embodiment, the second spacer layer 216 comprises silicon nitride (SiN).

Referring to fig. 1 and 5A-5B, the method 100 includes a block 106 in which the first spacer layer 214 and the second spacer layer 216 are etched back to form gate spacers 218a and fin sidewall spacers 218B. After forming the first spacer layer 214 and the second spacer layer 216, an etching process is performed to remove portions of the first spacer layer 214 and the second spacer layer 216 above the top-facing surface of the workpiece 200 to form gate spacers 218a extending along sidewalls of the dummy gate stack 212 and fin sidewall spacers 218b extending along lower portions of sidewalls of the fin active regions 204A-204D and the dielectric fin 210. In some other embodiments, each of the gate spacers 218a and fin sidewall spacers 218b may be a single layer structure formed from one spacer layer.

Referring to fig. 1 and 6A-6B, the method 100 includes a block 108 in which source/drain regions of the fin active regions 204A-204D are recessed to form source/drain openings 220. In some embodiments, the source/drain regions of the fin active regions 204A-204D are anisotropically etched by plasma etching with a suitable etchant, such as a fluorine-containing etchant, an oxygen-containing etchant, a hydrogen-containing etchant, a fluorine-containing etchant (e.g., CF ₄ 、SF ₆ 、CH ₂ F ₂ 、CHF ₃ And/or C ₂ F ₆ ) Chlorine-containing etchants (e.g. Cl ₂ 、CHCl ₃ 、CCl ₄ And/or BCl ₃ ) Bromine-containing etchants (e.g., HBr and/or CHBr ₃ ) Iodine-containing etchants, other suitable etchants, and/or combinations thereof. In this embodiment, the upper portions 2 of raised fin-shaped active regions 204A-204D are recessed above spacer 20604a-204d to form source/drain openings 220. In an embodiment, the top surfaces of the recessed upper portions 204a-204d are below the top surfaces of the fin sidewall spacers 218 b.

Referring to fig. 1 and 7A-7B, the method 100 includes a block 110 in which source/drain features are formed in source/drain openings 220. Source/drain features may refer to source features or drain features, individually or collectively depending on the context. The source/drain features may be n-type source/drain features or p-type source/drain features depending on the conductivity type of the transistor to be formed. In the present embodiment, N-type source/drain features 222N are formed in the source/drain openings 220 in the second regions 20 and over the recessed upper portions 204C-204D of the fin-shaped active regions 204C-204D, and P-type source/drain features 222P are formed in the source/drain openings 220 in the first regions 10 and over the recessed upper portions 204A-204B of the fin-shaped active regions 204A-204B. It can be seen that hybrid fin 210 functions to keep adjacent source/drain features separated from each other.

The P-type source/drain feature 222P in the first region 10 and the N-type source/drain feature 222N in the second region 20 have different compositions and are formed separately. The P-type source/drain feature 222P may comprise silicon germanium (SiGe) or other semiconductor composition with good hole mobility and is doped with at least one P-type dopant such as boron (B), boron difluoride (BF 2), or indium (In). The N-type source/drain feature 222N may comprise silicon (Si) or other semiconductor composition with good electron mobility and is doped with at least one N-type dopant, such As phosphorus (P) or arsenic (As). In one example process, a first mask layer is first deposited to cover the second region 20 and an epitaxial deposition process is performed to form P-type source/drain features 222P in the first region 10. The first mask layer is then removed. A second mask layer is deposited to cover the first region 10 and an epitaxial deposition process is performed to form N-type source/drain features 222N in the second region 20.

The P-type source/drain feature 222P may include multiple epitaxial layers. The multiple epitaxial layers of the P-type source/drain features 222P may be deposited using suitable techniques, such as Vapor Phase Epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), reduced pressure CVD, cyclic Deposition and Etching (CDE) processes, molecular Beam Epitaxy (MBE), and/or other suitable processes. The process temperature may be between about 600 ℃ and about 700 ℃. To form P-type source/drain features 222P comprising silicon germanium (SiGe), epitaxial deposition may include the use of Silane (SiH) ₄ ) Dichlorosilane (Si) ₂ H ₂ Cl ₂ ) Germane (GeH) ₄ ) And hydrogen (H) ₂ ). One or more of the plurality of epitaxial layers may use diborane (B) ₂ H ₆ ) Is doped in situ. In an embodiment, the P-type source/drain feature 222P includes a first epitaxial layer and a second epitaxial layer over the first epitaxial layer, the first epitaxial layer and the second epitaxial layer each include SiGe, and each of the germanium content of the first epitaxial layer and the germanium content of the second epitaxial layer is between 25% and about 60%, and each of the boron (B) concentration of the first epitaxial layer and the boron concentration of the second epitaxial layer is about 1 x 10 ²⁰ atoms/cm ³ And about 3 x 10 ²¹ atoms/cm ³ Between them. In an embodiment, the boron concentration of the first epitaxial layer is less than the boron concentration of the second epitaxial layer.

The N-type source/drain feature 222N may include multiple epitaxial layers. The multiple epitaxial layers of N-type source/drain features 222N may be deposited using suitable techniques such as Vapor Phase Epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), reduced pressure CVD, cyclical Deposition and Etching (CDE) processes, molecular Beam Epitaxy (MBE), and/or other suitable processes. The process temperature may be between about 600 ℃ and about 700 ℃. To form N-type source/drain features 222N comprising silicon (Si), epitaxial deposition may include the use of silane (SiH ₄ ) Dichlorosilane (Si) ₂ H ₂ Cl ₂ ) Germane (GeH) ₄ ) And hydrogen (H) ₂ ). One or more of the plurality of epitaxial layers may be formed using, for example, phosphine (PH ₃ ) Or arsine (AsH) ₃ ) N-type dopants of (c) are doped in situ. In an embodiment, the N-type source/drain feature 222N includes a first epitaxial layer and a second epitaxial layer over the first epitaxial layer, the first epitaxial layer and the second epitaxial layer each include Si, and each of a phosphorus (P) concentration of the first epitaxial layer and a phosphorus concentration of the second epitaxial layer is about 1×10 ²⁰ atoms/cm ³ And about 4×10 ²¹ atoms/cm ³ Between them. In an embodiment, the phosphorus concentration of the first epitaxial layer is less than the phosphorus concentration of the second epitaxial layer. In the cross-sectional view of the workpiece 200 shown in fig. 7A, the P-type source/drain feature 222P spans the width D1 along the X-direction. In an embodiment, the width D1 may be between about 20nm and about 30 nm. In a cross-sectional view taken along line C-C', N-type source/drain feature 222N may span a width equal to width D1.

Refer to fig. 7B. During formation of the P-type source/drain feature 222P, the epitaxial layers of the P-type source/drain feature 222P merge and form the P-type source/drain feature 222P having a substantially planar top surface 222 Pt. The highest point of the substantially planar top surface 222Pt is above the top surface 204t of the fin active region 204A/204B. The distance between the highest point of the substantially planar top surface 222Pt and the top surface 204T of the fin active region 204A/204B may be referred to as the elevation height T2. In an embodiment, the raised height T2 of the P-type source/drain feature 222P may be between about 1nm and about 10 nm. The raised height of N-type source/drain feature 222N may also be between about 1nm and about 10 nm. In an embodiment, the raised height T2 of the P-type source/drain feature 222P is greater than the raised height of the N-type source/drain feature 222N. During formation of the N-type source/drain feature 222N, the epitaxial layers of the N-type source/drain feature 222N merge and form the N-type source/drain feature 222N having a wavy and concave top surface 222 Nt. The highest point of the undulating and concave top surface 222Nt is above the top surface of the fin active region 204A/204B. N-type source/drain feature 222N spans width D1N along the Y-direction. In an embodiment, the width D1N may be between about 60nm and about 70 nm. The P-type source/drain feature 222P spans the width D1P along the Y-direction. The width D1P may be smaller than the width D1N. In an embodiment, the width D1P is greater than D1 and may be between about 55nm and about 65 nm.

Referring to fig. 1 and 8A-8B, the method 100 includes a block 112 in which a Contact Etch Stop Layer (CESL) 226 and a first interlayer dielectric (ILD) layer 228 are deposited over the workpiece 200. CESL 226 may comprise silicon nitride, silicon oxynitride, and/or other suitable materials and may be formed by ALD, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and/or other suitable deposition or oxidation processes. After depositing CESL 226, a first ILD layer 228 is deposited over workpiece 200 by a PECVD process or other suitable deposition technique. The first ILD layer 228 may comprise doped silicon oxide, such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. A planarization process, such as a Chemical Mechanical Polishing (CMP) process, may be performed on the workpiece 200 to remove excess material and expose the top surface of the dummy gate electrode layer 212b in the dummy gate stack 212.

Referring to fig. 1 and 9A-9B, the method 100 includes a block 114 in which the dummy gate stack 212 is replaced with a gate structure 230. With the dummy gate electrode layer 212b exposed, the dummy gate stack 212 is selectively removed. The removal of the dummy gate stack 212 may include one or more etching processes selective to the material in the dummy gate stack 212. For example, the removal of dummy gate stack 212 may be performed using a selective wet etch, a selective dry etch, or a combination thereof. In the embodiment shown in fig. 9A, after removing the dummy gate stack layer 212, a gate structure 230 is formed. Each of the gate structures 230 may include a gate dielectric layer and a gate electrode layer 230c over the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interfacial layer 230a disposed over the substrate 202 and a high-k dielectric layer 230b over the interfacial layer 230 a. In some embodiments, interface layer 230a comprises silicon oxide. High-k dielectric layer 230b is then deposited over the interfacial layer using ALD, CVD, and/or other suitable methods. Here, the high-k dielectric layer 230b refers to a dielectric material having a dielectric constant greater than that of silicon dioxide, which has a dielectric constant of about 3.9. High-k dielectric layer 230b may include hafnium oxide. Alternatively, the high-k dielectric layer 230b may include other high-k dielectrics such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, srTiO ₃ 、BaTiO ₃ BaZrO, lanthanum hafnium oxide, lanthanum silicon oxide, aluminum silicon oxide, tantalum hafnium oxide, titanium hafnium oxide, (Ba, sr) TiO ₃ (BST)、Silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials. A gate electrode layer 230c is then deposited over the gate dielectric layer using Atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), electron beam evaporation, or other suitable method. The gate electrode layer 230c may comprise a single layer or alternatively a multi-layer structure such as various combinations of metal layers (work function metal layers), liner layers, wetting layers, adhesion layers, metal alloys, or metal silicides having a work function selected to enhance device performance. For example, the gate electrode layer 230c may include titanium nitride, titanium aluminum nitride, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, tantalum silicon nitride, copper, other refractory metals, or other suitable metallic materials, or combinations thereof. In some embodiments, different gate electrode layers 230c may be formed for the n-type transistor and the p-type transistor, respectively, which may include different work function metal layers (e.g., to provide different n-type and p-type work function metal layers).

Referring to fig. 1 and 10A-10B, the method 100 includes a block 116 in which a second ILD layer 232 is deposited over the workpiece 200. The second ILD layer 232 may be similar in composition and formation process to the first ILD layer 228. The second ILD layer 232 may be deposited using CVD, FCVD, spin-on, or a suitable deposition method. The second ILD layer 232 may comprise doped silicon oxide such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.

Referring to fig. 1 and 11A-11B, the method 100 includes a block 118 in which a first contact opening 234a is formed to expose the P-type source/drain feature 222P and a second contact opening 234B is formed to expose the N-type source/drain feature 222N. The contact openings 234a and 234b penetrate the second ILD layer 232, the first ILD layer 228, and the CESL 226 using a combination of photolithography and etching processes. In an example process, a hard mask layer and photoresist are deposited over the workpiece 200. The photoresist layer is then exposed to light transmitted through or reflected from the photomaskThe patterned radiation is baked in a post-exposure bake process, developed in a developer solution, and then rinsed to form a patterned photoresist layer. The patterned photoresist layer is then used as an etch mask to etch the hard mask layer to form a patterned hard mask layer. The patterned hard mask layer is then used as an etch mask to etch the second ILD layer 232, the first ILD layer 228, and the CESL 226. The etching process for etching the second ILD layer 232, the first ILD layer 228, and the CESL 226 may be a dry etching process including using argon (Ar), a fluorine-containing etchant (e.g., SF ₆ 、NF ₃ 、CH ₂ F ₂ 、CHF ₃ And/or C ₂ F ₆ ) An oxygen-containing etchant, a chlorine-containing etchant (e.g., cl) ₂ 、CHCl ₃ 、CCl ₄ And/or BCl ₃ ) Bromine-containing etchants (e.g., HBr and/or CHBr ₃ ) An iodine-containing etchant, or a combination thereof.

The etching process further recesses the P-type source/drain feature 222P and the N-type source/drain feature 222N. Since the etching characteristics and shapes of the P-type source/drain feature 222P and the N-type source/drain feature 222N are different, the first contact opening 234a and the second contact opening 234b have different shapes after the etching process is performed. More specifically, since the P-type source/drain feature 222P has a substantially planar top surface 222Pt and the N-type source/drain feature 222N has a concave and undulating top surface 222Nt, the first contact opening 234a has a first depth that is less than the second depth of the second contact opening 234 b. In an embodiment, the depth difference H1 between the first depth and the second depth is greater than 1nm. Since the P-type source/drain feature 222P has a substantially planar top surface 222Pt and the N-type source/drain feature 222N has a concave and undulating top surface 222Nt, as shown in fig. 11B, after the etching process, the recessed P-type source/drain feature 222P has a substantially planar top surface 222Pt 'and the recessed N-type source/drain feature 222N has a concave and undulating top surface 222Nt'. In the embodiment shown in fig. 11A, a distance T3 between the lowest point of recessed top surface 222Pt' and top surface 204T of fin active region 204A/204B is between about 10nm and about 15 nm. In the embodiment shown in fig. 11A, the first contact opening 234a exposes a portion 226b of the bottom surface of the CESL 226 and a portion of the sidewall surface of the CESL 226, and further exposes a portion of the sidewall surface of the first ILD layer 228. That is, CESL 226 overhangs recessed P-type source/drain feature 222P.

Referring to fig. 1 and 12A-12B, the method 100 includes a block 120 in which a silicide layer 236a and a silicide layer 236B are formed in the first contact opening 234a and the second contact opening 234B, respectively. To reduce contact resistance, a silicide layer 236a is formed on recessed P-type source/drain feature 222P and a silicide layer 236b is formed on recessed N-type source/drain feature 222N. To form silicide layer 236a and silicide layer 236b, a metal precursor such as titanium (Ti) is deposited over the exposed surfaces of recessed N-type source/drain features 222N and over the exposed surfaces of recessed P-type source/drain features 222P. An annealing process is then performed to cause silicidation (and germanation in the first region 10) between the metal precursor and the exposed semiconductor surface. In the depicted embodiment, titanium may react with silicon germanium in P-type source/drain feature 222P to form silicide layer 236a and may react with silicon in N-type source/drain feature 222N to form silicide layer 236b. In some embodiments, unreacted metal precursor is selectively removed after the silicide layer 236a and the silicide layer 236b are formed. The silicide layers 236a/236b may be partially oxidized during the removal of unreacted metal precursor. In this embodiment, the silicide layer 236a is formed simultaneously with the silicide layer 236b. In some other embodiments, the silicide layer 236a and the silicide layer 236b may be formed in any suitable order.

In the present embodiment, in the cross-sectional view shown in fig. 12B, since the recessed P-type source/drain feature 222P has a substantially flat top surface 222Pt', the silicide layer 236a formed on the recessed P-type source/drain feature 222P has a substantially uniform thickness, and the top surface of the silicide layer 236a is substantially flat. Since the recessed N-type source/drain feature 222N has a concave and wavy top surface 222Nt', the silicide layer 236b formed on the recessed N-type source/drain feature 222N has a substantially planar top surface and a non-uniform thickness. More specifically, silicide layer 236b is thicker in the middle and thinner near its edges. In the cross-sectional view shown in fig. 12A, the thickness T4 of the silicide layer 236a is between about 5nm and about 10 nm. In the cross-sectional view shown in fig. 12A, the top surface of the silicide layer 236a has a concave surface.

Referring to fig. 1 and 13A-13B, the method 100 includes a block 122 in which the silicide layer 236a and the silicide layer 236B are recessed. In the present embodiment, after the silicide layer 236a and the silicide layer 236b are formed, the silicide layer 236a and the silicide layer 236b are recessed to remove oxidized portions of the silicide layer. In an embodiment, after recessing, the thickness T5 of the silicide layer 236a is between about 3nm and about 5nm in a cross-sectional view of the workpiece 200 taken along line A-A'. As shown in fig. 13A, recessed silicide layer 236a spans width D2 along the X-direction. The width D2 may be between about 15nm and about 20 nm. In the embodiment shown in fig. 13B, silicide layer 236B spans width D2N along the Y-direction. The width D2N is greater than the width D2. In an embodiment, the width D2N may be between about 40nm and about 50 nm. Silicide layer 236a spans width D2P along the Y-direction. The width D2P is greater than the width D2. In an embodiment, the width D2P may be between about 35nm and about 45 nm.

As shown in fig. 13B, recessed silicide layer 236a has a thickness T5P. Thickness T5P is greater than thickness T5 and may be between about 5nm and about 10 nm. In an embodiment, the thickness difference between thickness T5P and thickness T5 is between about 2nm and about 5 nm. The recessed silicide layer 236b is thicker in the middle and thinner near its edges and has a thickness T5N in the middle. Thickness T5N is greater than thickness T5 and may be between about 5nm and about 10 nm. In an embodiment, the thickness difference between thickness T5N and thickness T5 is between about 2nm and about 5 nm. The recessed silicide layer 236a and the recessed silicide layer 236b each have a substantially planar top surface. Forming a planar top surface will reduce the step coverage of the metal formed thereon and reduce contact resistance.

Referring to fig. 1 and 14A-14B, the method 100 includes a block 124 in which a first conductive layer 238a is formed in a first contact opening 234A and a second conductive layer 238B is formed in a second contact opening 234B. In an embodiment, the first conductive layer 238a and the second conductive layer 238b are formed by the same Physical Vapor Deposition (PVD) process. That is, the composition and thickness of the first conductive layer 238a are the same as those of the second conductive layer 238b. In an embodiment, the first conductive layer 238a and the second conductive layer 238b include tungsten (W). Performing the PVD process may advantageously reduce gaps or voids in the first conductive layer 238a and the second conductive layer 238b.

Referring now to FIG. 14A, a cross-sectional view of the workpiece 200 is depicted taken along line A-A'. In the cross-sectional view shown in fig. 14A, the top surface of the first conductive layer 238a includes a convex top surface, and the bottom surface of the first conductive layer 238a follows the shape of the top surface of the silicide layer 236 a. Since the first contact opening 234a exposes a portion 226b of the bottom surface of the CESL 226 and the CESL 226 overhangs the recessed P-type source/drain feature 222P, after the first and second conductive layers 238a and 238b are formed, a portion of the first conductive layer 238a is formed directly under and in direct contact with the portion 226b of the bottom surface of the CESL 226 previously exposed by the second contact opening 234 a. As shown in fig. 14A, the first conductive layer 238a spans the width D3 along the X direction. The width D3 is smaller than the width D2 (as shown in fig. 13A). In an embodiment, the width D3 may be between about 10nm and about 15 nm. In a cross-sectional view of the workpiece taken along line A-A', the thickness T6 of the first conductive layer 238a (i.e., the distance between the highest point of the first conductive layer 238a and the lowest point of the first conductive layer 238 a) may be between about 15nm and about 20 nm. After forming the first conductive layer 238a and the second conductive layer 238b, at least a portion of a top surface of the first conductive layer 238a is over a top surface of the P-type source/drain feature 222P. That is, the first conductive layer 238a has a lower portion extending into the P-type source/drain feature 222P and an upper portion protruding from the P-type source/drain feature 222P. The depth T7 of the portion of the first conductive layer 238a extending from the top surface of the fin active region 204A into the P-type source/drain feature 222P (i.e., the distance between the bottommost point of the first conductive layer 238a and the top surface 204T of the fin active region 204A) is between about 5nm and about 10 nm. The thickness T8 of the portion of the first conductive layer 238a protruding from the P-type source/drain feature 222P (i.e., the distance between the highest point of the first conductive layer 238a and the bottom surface of the CESL 226) is between about 1nm and about 5 nm.

Referring now to FIG. 14B, a cross-sectional view of the workpiece 200 is depicted taken along line B-B'. As shown in fig. 14B, the top surface of the first conductive layer 238a includes a substantially flat top surface, and the top surface of the second conductive layer 238B includes a substantially flat top surface. Forming a planar top surface will reduce the step coverage of the third/fourth conductive layer to be formed over it and reduce the extent to which the third/fourth conductive layer to be formed protrudes into the source/drain features, thereby reducing contact resistance. In the embodiment shown in fig. 14B, each of the first conductive layer 238a and the second conductive layer 238B has a thickness T6N. Since the first conductive layer 238a and the second conductive layer 238B have a flatter top surface in the sectional view shown in fig. 14B than in the sectional view shown in fig. 14A, the thickness T6N is smaller than the thickness T6. In an embodiment, the thickness T6N is between about 10nm and about 15 nm. As shown in fig. 14B, the first conductive layer 238a spans the width D3P along the Y direction. In an embodiment, the width D3P may be between about 40nm and about 45 nm. The second conductive layer 238b spans the width D3N along the Y direction. In an embodiment, the width D3N may be between about 40nm and about 45 nm. In some embodiments, width D3N may be greater than width D2N, and width D3P may be greater than width D2P.

Referring to fig. 1 and 15A-15B, the method 100 includes a block 126 in which a third conductive layer 240a is formed over the first conductive layer 238a and a fourth conductive layer 240B is formed over the second conductive layer 238B to fill the first and second contact openings 234a and 234B, respectively. In the embodiment shown in fig. 15A and 15B, the third conductive layer 240a is on the first conductive layer 238a and is in direct contact with the first conductive layer 238a and is spaced apart from the silicide layer 236a by the first conductive layer 238 a. The fourth conductive layer 240b is on the second conductive layer 238b and is in direct contact with the second conductive layer 238b and is spaced apart from the silicide layer 236b by the second conductive layer 238 b. In an example process, a layer of conductive material is deposited over the workpiece 200 to substantially fill the first contact opening 234a and the second contact opening 234b by any suitable process. The conductive material layer may include cobalt (Co), ruthenium (Ru), or molybdenum (Mo). In one embodiment, the layer of conductive material comprises ruthenium (Ru) formed by a CVD process. A planarization process, such as a Chemical Mechanical Polishing (CMP) process, may then be performed to remove the excess portion of the conductive material layer to form the third conductive layer 240a directly on the first conductive layer 238a and the fourth conductive layer 240b directly on the second conductive layer 238 b. After performing the planarization process, the top surfaces of the third conductive layer 240a and the fourth conductive layer 240b are coplanar. Since the depth of the first contact opening 234a is smaller than the depth of the second contact opening 234B, as shown in fig. 15B, the thickness T10N of the fourth conductive layer 240B is greater than the thickness T10P of the third conductive layer 240 a. That is, the bottom surface of the third conductive layer 240a is above the bottom surface of the fourth conductive layer 240b. In an embodiment, the thickness T10N may be between about 20nm and about 25nm, and the thickness T10P is between about 15nm and about 20 nm. In an embodiment, the thickness difference between the thickness T10N and the thickness T10P is between about 1nm and about 5 nm.

In an embodiment, as shown in fig. 15A, portions of the first ILD layer 228 and CESL 226 are interposed between the third conductive layer 240a and the gate spacer 218 a. The bottom surfaces of the third and fourth conductive layers 240a and 240b follow the shape of the top surfaces of the first and second conductive layers 238a and 238b, respectively. That is, the bottom surfaces of the third conductive layer 240a and the fourth conductive layer 240b are bent upward. As shown in fig. 15A, the bottom surface of the third conductive layer 240a spans the width D4 along the X direction. The width D4 is smaller than the width D3. In some embodiments, the ratio of width D4 to width D1 may be between about 0.4 and 0.7. In an embodiment, the width D4 may be between about 8nm and about 12 nm. The top surface of the third conductive layer 240a spans the width D5 along the X direction. In an embodiment, the width W5 may be between about 20nm and about 25 nm. In some embodiments, the width W5 may be equal to the width W1 of the P-type source/drain feature 222P.

In an embodiment, as shown in fig. 15B, an interface between the fourth conductive layer 240B and the second conductive layer 238B is disposed in the first ILD layer 228. As shown in fig. 15B, the top surface of the third conductive layer 240a spans the width D5P along the Y direction. The width D5P is smaller than the width D1P. In an embodiment, the width D5P is between about 45nm and about 50 nm. The top surface of the fourth conductive layer 240b spans the width D5N along the Y direction. The width D5N is smaller than the width D1N. In an embodiment, the width D5N is between about 45nm and about 50 nm.

Referring to fig. 1, the method 100 includes a block 128 in which further processing is performed to complete the manufacture of the workpiece 200. Such further processing may include forming a multi-layer interconnect (MLI) structure (not shown) over the workpiece 200. In some embodiments, the MLI structure may include a plurality of inter-metal dielectric (IMD) layers and a plurality of metal lines or contact vias in each of the IMD layers. In some cases, IMD layer and first ILD layer 228 may share similar compositions. The metal lines and contact vias in each IMD layer may be formed of a metal such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined with a barrier layer to insulate the metal lines and contact vias from the IMD layer.

In the above-described methods and structures, the first conductive layer 238a is over and in direct contact with the silicide layer 236a, and the third conductive layer 240a is over and in direct contact with the first conductive layer 238 a. Similarly, the second conductive layer 238b is over and in direct contact with the silicide layer 236b, and the fourth conductive layer 240b is over and in direct contact with the second conductive layer 238 b. In some alternative embodiments, the workpiece 200 may also include a barrier layer. For example, in the embodiment shown in fig. 16A-16B, the workpiece 200 includes a barrier layer 242a formed in the first contact opening 234a and a barrier layer 242B formed in the second contact opening 234B. In an example process, after forming the first conductive layer 238a and the second conductive layer 238b, a layer of barrier material may be conformally deposited over the workpiece 200 by ALD, CVD, or other suitable process. The conductive material layer for forming the third conductive layer 240a and the fourth conductive layer 240b may be deposited after the barrier material layer is deposited. A planarization process may then be performed to remove the excess portions of the barrier material layer and the excess portions of the conductive material layer to define the final structure of the source/drain contacts (i.e., including the first/second conductive layers 238a/238b, the barrier layers 242a/242b, and the third/fourth conductive layers 240a/240 b) are formed in the first and second contact openings 234a-234 b. In some embodiments, the barrier material layer may include titanium nitride (TiN), tantalum nitride (TaN), cobalt nitride (CoN), nickel nitride (NiN), manganese nitride (MnN), tungsten nitride (WN), or other transition metal nitrides. In one embodiment, the barrier material layer comprises titanium nitride (TiN). Since barrier layer 242a and barrier layer 242b are portions of conformally deposited barrier material layers, the composition and thickness of barrier layer 242a is the same as the composition and thickness of barrier layer 242b. In the embodiment shown in fig. 16B, the barrier layer 242a includes a flat portion sandwiched between the first conductive layer 238a and the third conductive layer 240a and a vertical portion extending along a sidewall surface of the third conductive layer 240 a. The barrier layer 242b includes a flat portion sandwiched between the second conductive layer 238b and the fourth conductive layer 240b and a vertical portion extending along a sidewall surface of the fourth conductive layer 240 b.

Fig. 17A-17B illustrate cross-sectional views of a workpiece 200 according to another alternative embodiment of the present disclosure. In the embodiment shown in fig. 17A-17B, the workpiece 200 includes a barrier layer 244a and a barrier layer 244B. More specifically, the workpiece 200 includes a barrier layer 244a formed in the first contact opening 234a and a barrier layer 244b formed in the second contact opening 234 b. In an example process, after the silicide layer 236a and the silicide layer 236b are formed, a layer of barrier material may be conformally deposited over the workpiece 200 by ALD, CVD, or other suitable process. The process for forming the first conductive layer 238a, the second conductive layer 238b, the third conductive layer 240a, and the fourth conductive layer 240b is performed after depositing the barrier material layer. Before or after forming the first, second, third, and fourth conductive layers 238a, 238b, 240a, and 240b, a planarization process for removing excess portions of the barrier material layer may be performed to define the final shape of the barrier layers 244a-244b and/or source/drain contacts formed in the contact openings 234a-234 b. The composition of barrier layers 244a/244b may be the same as the composition of barrier layers 242a/242 b. In the embodiment shown in fig. 17B, the barrier layer 244a includes a flat portion sandwiched between the first conductive layer 238a and the silicide layer 236a and a vertical portion extending along the sidewall surfaces of the first conductive layer 238a and the third conductive layer 240a, and the barrier layer 244B includes a flat portion sandwiched between the second conductive layer 238B and the silicide layer 236B and a vertical portion extending along the sidewall surfaces of the third conductive layer 240a and the fourth conductive layer 240B.

Although not intended to be limiting, one or more embodiments of the present disclosure provide a number of benefits to semiconductor structures and their formation. For example, one advantage is that during formation of the source/drain contact openings, the source/drain features are slightly recessed and the subsequently formed silicide layer has a planar top surface. The flat top surface will reduce the step coverage of the metal formed thereon and reduce contact resistance. Another advantage is that the source/drain contacts can be formed substantially without voids or gaps. In an embodiment, to form the source/drain contacts, the first deposition process may be a PVD process configured to partially fill the source/drain contact openings without trapping voids in the deposited tungsten layer. Eliminating (or at least significantly reducing) voids or gaps in the resulting source/drain contacts may reduce the parasitic resistance of the source/drain contacts, as any trapped air bubbles in the source/drain contacts may greatly increase their parasitic resistance.

The present disclosure provides many different embodiments. Semiconductor structures and methods of making the same are disclosed herein. In one exemplary aspect, the present disclosure is directed to a method. The method includes receiving a workpiece including a channel region over a substrate, source/drain features adjacent the channel region, a gate structure over the channel region, and a dielectric structure over the source/drain features. The method further includes forming a contact opening through the dielectric structure to expose the source/drain feature, forming a silicide layer in the contact opening and over the source/drain feature, forming a tungsten-containing layer in the contact opening and over the silicide layer, and forming a conductive layer in the contact opening and over the tungsten-containing layer, wherein the composition of the conductive layer is different than the composition of the tungsten-containing layer.

In some embodiments, the method may further include, prior to forming the tungsten-containing layer, performing a cleaning process on the silicide layer to remove oxidized portions of the silicide layer. In some embodiments, forming the tungsten-containing layer may include performing a Physical Vapor Deposition (PVD) process, and forming the conductive layer may include performing a Chemical Vapor Deposition (CVD) process. In some embodiments, the tungsten-containing layer may include tungsten (W), and the conductive layer may include ruthenium (Ru), molybdenum (Mo), or cobalt (Co). In some embodiments, the silicide layer may include a concave top surface in a first cross-sectional view through the gate structure and the source/drain feature, and may include a substantially planar top surface in a second cross-sectional view through the source/drain feature without passing through the gate structure. In some embodiments, in the first cross-sectional view, the tungsten-containing layer may include a convex top surface, and a highest point of the convex top surface of the tungsten-containing layer may be above a highest point of the top surface of the source/drain feature. In some embodiments, in the second cross-sectional view, the silicide layer is not uniform in thickness. In some embodiments, in the first cross-sectional view, a lower portion of the tungsten-containing layer may extend into the source/drain feature, and an upper portion of the tungsten-containing layer may overlie the source/drain feature, and the entire conductive layer may overlie the source/drain feature. In some embodiments, portions of the tungsten-containing layer may be in direct contact with portions of the bottom surface of the dielectric structure.

In another exemplary aspect, the present disclosure is directed to a method. The method includes receiving a workpiece comprising a first region and a second region, the workpiece comprising a first gate structure over channel regions of a first fin and a second fin over the first region; a p-type source/drain feature disposed over and spanning over the first fin and the second fin; a second gate structure over channel regions of the third fin and the fourth fin over the second region; and an n-type source/drain feature disposed over and spanning over the third and fourth fins over the second region; and a dielectric structure over the p-type source/drain feature and the n-type source/drain feature. The method further includes forming a first contact opening extending through the dielectric structure to expose the p-type source/drain feature and a second contact opening extending through the dielectric structure to expose the n-type source/drain feature, performing a first deposition process to form a first conductive layer in the first contact opening and a second conductive layer in the second contact opening, and performing a second deposition process to form a third conductive layer over the first conductive layer and a fourth conductive layer over the second conductive layer, the first deposition process being different from the second deposition process, and the compositions of the first conductive layer and the second conductive layer being different from the compositions of the third conductive layer and the fourth conductive layer.

In some embodiments, the first deposition process may include a Physical Vapor Deposition (PVD) process, and the second deposition process may include a Chemical Vapor Deposition (CVD) process. In some embodiments, the first and second conductive layers may include tungsten (W), and the third and fourth conductive layers may include ruthenium (Ru), molybdenum (Mo), or cobalt (Co). In some embodiments, the depth of the first contact opening may be less than the depth of the second contact opening. In some embodiments, the thickness of the third conductive layer may be less than the thickness of the fourth conductive layer. In some embodiments, the method may further include, prior to performing the first deposition process, forming a first silicide layer in the first contact opening and forming a second silicide layer in the second contact opening, and in a cross-sectional view, a top surface of the first silicide layer and a top surface of the second silicide layer may be substantially planar. In some embodiments, the method may further include forming a barrier layer in and over the first and second contact openings after performing the first deposition process and before performing the second deposition process.

In yet another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a gate structure over channel regions of the first fin and the second fin; a source/drain feature disposed over and spanning over the first fin and the second fin; a dielectric layer over the source/drain features; and a source/drain contact extending through the dielectric layer to electrically couple to the source/drain feature, wherein the source/drain contact includes a first conductive layer over the source/drain feature and a second conductive layer over the first conductive layer, the composition of the first conductive layer being different from the composition of the second conductive layer, and wherein a bottom surface of the second conductive layer is above a top surface of the source/drain feature in a first cross-sectional view through the gate structure and the source/drain feature.

In some embodiments, portions of the first conductive layer may extend into the source/drain features, and the first conductive layer may include a convex top surface. In some embodiments, the semiconductor structure may further include a gate spacer extending along a sidewall surface of the first gate structure, and a portion of the dielectric layer may be interposed between the source/drain contact and the gate spacer. In some embodiments, the semiconductor structure may further include a silicide layer on the source/drain features, wherein the silicide layer may include a concave top surface in a first cross-sectional view and a substantially planar top surface in a second cross-sectional view different from the first cross-sectional view.

According to an embodiment of the present application, there is provided a method of forming a semiconductor structure, including: receiving a workpiece, the workpiece comprising: a channel region over the substrate; source/drain features adjacent the channel region; a gate structure over the channel region; and a dielectric structure over the source/drain features. The method of forming a semiconductor structure further includes forming a contact opening through the dielectric structure to expose the source/drain feature; forming a silicide layer in the contact opening and on the source/drain feature; forming a tungsten-containing layer in the contact opening and on the silicide layer; and forming a conductive layer in the contact opening and on the tungsten-containing layer, wherein the composition of the conductive layer is different from the composition of the tungsten-containing layer. In some embodiments, the method of forming a semiconductor structure further comprises: a cleaning process is performed on the silicide layer to remove oxidized portions of the silicide layer prior to forming the tungsten-containing layer. In some embodiments, wherein forming the tungsten-containing layer comprises performing a Physical Vapor Deposition (PVD) process, and forming the conductive layer comprises performing a Chemical Vapor Deposition (CVD) process. In some embodiments, wherein the tungsten-containing layer comprises tungsten (W), and the conductive layer comprises ruthenium (Ru), molybdenum (Mo), or cobalt (Co). In some embodiments, the silicide layer includes a concave top surface in a first cross-sectional view through the gate structure and the source/drain feature and a substantially planar top surface in a second cross-sectional view through the source/drain feature but not through the gate structure. In some embodiments, wherein in the first cross-sectional view, the tungsten-containing layer includes a convex top surface, and a highest point of the convex top surface of the tungsten-containing layer is above a highest point of the top surface of the source/drain feature. In some embodiments, wherein in the second cross-sectional view, the silicide layer is not uniform in thickness. In some embodiments, wherein in the first cross-sectional view, a lower portion of the tungsten-containing layer extends into the source/drain feature and an upper portion of the tungsten-containing layer is over the source/drain feature and the entire conductive layer is over the source/drain feature. In some embodiments, a portion of the tungsten-containing layer is in direct contact with a portion of the bottom surface of the dielectric structure.

According to another embodiment of the present application, there is provided a method of forming a semiconductor structure, including: receiving a workpiece comprising a first region and a second region, the workpiece comprising: a first gate structure over channel regions of the first fin and the second fin over the first region; a p-type source/drain feature disposed over and spanning over the first fin and the second fin; a second gate structure over channel regions of the third fin and the fourth fin over the second region; an n-type source/drain feature disposed over and spanning over the third and fourth fins over the second region; and a dielectric structure over the p-type source/drain feature and the n-type source/drain feature. The method of forming a semiconductor structure further includes: forming a first contact opening extending through the dielectric structure to expose the p-type source/drain feature and a second contact opening extending through the dielectric structure to expose the n-type source/drain feature; performing a first deposition process to form a first conductive layer in the first contact opening and a second conductive layer in the second contact opening; and performing a second deposition process to form a third conductive layer over the first conductive layer and a fourth conductive layer over the second conductive layer, wherein the first deposition process is different from the second deposition process and the composition of the first conductive layer and the second conductive layer is different from the composition of the third conductive layer and the fourth conductive layer. In some embodiments, wherein the first deposition process comprises a Physical Vapor Deposition (PVD) process and the second deposition process comprises a Chemical Vapor Deposition (CVD) process. In some embodiments, wherein the first and second conductive layers comprise tungsten (W), and the third and fourth conductive layers comprise ruthenium (Ru), molybdenum (Mo), or cobalt (Co). In some embodiments, wherein the depth of the first contact opening is less than the depth of the second contact opening. In some embodiments, wherein the thickness of the third conductive layer is less than the thickness of the fourth conductive layer. In some embodiments, the method of forming a semiconductor structure further comprises: a first silicide layer is formed in the first contact opening and a second silicide layer is formed in the second contact opening prior to performing the first deposition process, wherein, in a cross-sectional view, a top surface of the first silicide layer and a top surface of the second silicide layer are substantially planar. In some embodiments, the method of forming a semiconductor structure further comprises: after performing the first deposition process and before performing the second deposition process, a barrier layer is formed in the first contact opening and the second contact opening and over the first conductive layer and the second conductive layer.

The foregoing disclosure outlines components of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor structure, comprising:

receiving a workpiece, the workpiece comprising:

a channel region, over the substrate,

a source/drain feature adjacent to the channel region,

a gate structure over the channel region, and

a dielectric structure over the source/drain features;

forming a contact opening through the dielectric structure to expose the source/drain feature;

forming a silicide layer in the contact opening and on the source/drain feature;

forming a tungsten-containing layer in the contact opening and on the silicide layer; and

A conductive layer is formed in the contact opening and on the tungsten-containing layer, wherein a composition of the conductive layer is different from a composition of the tungsten-containing layer.

2. The method of claim 1, further comprising:

a cleaning process is performed on the silicide layer to remove oxidized portions of the silicide layer prior to the forming the tungsten-containing layer.

3. The method of claim 1, wherein the forming the tungsten-containing layer comprises performing a Physical Vapor Deposition (PVD) process, and the forming the conductive layer comprises performing a Chemical Vapor Deposition (CVD) process.

4. The method of claim 1, wherein the tungsten-containing layer comprises tungsten (W) and the conductive layer comprises ruthenium (Ru), molybdenum (Mo), or cobalt (Co).

5. The method of claim 1, wherein the silicide layer comprises a concave top surface in a first cross-sectional view through the gate structure and the source/drain feature and a substantially planar top surface in a second cross-sectional view through the source/drain feature but not through the gate structure.

6. The method of claim 5, wherein in the first cross-sectional view the tungsten-containing layer comprises a convex top surface and a highest point of the convex top surface of the tungsten-containing layer is above a highest point of a top surface of the source/drain feature.

7. The method of claim 5, wherein in the second cross-sectional view, the silicide layer is non-uniform in thickness.

8. The method of claim 5, wherein in the first cross-sectional view, a lower portion of the tungsten-containing layer extends into the source/drain feature and an upper portion of the tungsten-containing layer is over the source/drain feature and the entire conductive layer is over the source/drain feature.

9. A method of forming a semiconductor structure, comprising:

receiving a workpiece comprising a first region and a second region, the workpiece comprising:

a first gate structure over channel regions of the first fin and the second fin over the first region,

a p-type source/drain feature disposed over and spanning over the first fin and the second fin,

a second gate structure over channel regions of the third fin and the fourth fin over the second region,

an n-type source/drain feature disposed over and spanning over the third fin and the fourth fin over the second region, and

A dielectric structure over the p-type source/drain feature and the n-type source/drain feature;

forming a first contact opening extending through the dielectric structure to expose the p-type source/drain feature and a second contact opening extending through the dielectric structure to expose the n-type source/drain feature;

performing a first deposition process to form a first conductive layer in the first contact opening and a second conductive layer in the second contact opening; and

a second deposition process is performed to form a third conductive layer over the first conductive layer and a fourth conductive layer over the second conductive layer,

wherein the first deposition process is different from the second deposition process and the composition of the first and second conductive layers is different from the composition of the third and fourth conductive layers.

10. A semiconductor structure, comprising:

a gate structure over channel regions of the first fin and the second fin;

source/drain features disposed over and spanning over the first fin and the second fin;

a dielectric layer over the source/drain features; and

Source/drain contacts extending through the dielectric layer and electrically coupled to the source/drain features,

wherein the source/drain contact comprises a first conductive layer over the source/drain feature and a second conductive layer over the first conductive layer, the first conductive layer having a composition different from the composition of the second conductive layer, and

wherein in a first cross-sectional view through the gate structure and the source/drain feature, a bottom surface of the second conductive layer is above a top surface of the source/drain feature.