CN117012265A

CN117012265A - Memory testing method and device, electronic equipment and storage medium

Info

Publication number: CN117012265A
Application number: CN202310699351.5A
Authority: CN
Inventors: 代宇; 钱治丞; 宋博
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-06-12
Filing date: 2023-06-12
Publication date: 2023-11-07

Abstract

The disclosure provides a memory testing method, and belongs to the technical field of semiconductors. The memory testing method comprises the following steps: acquiring a preset test pattern; according to a preset test pattern, performing data writing operation on a memory array to be tested on a memory; reducing the voltage difference between the grid electrode and the source electrode of the transistor in the memory array to be tested; performing data reading operation on the storage array to be tested after the pressure difference is reduced to obtain read data; based on the preset test pattern and the read data, determining a failure test result of the memory. The method and the device have the advantages that the poor testing condition aiming at PC-PG short circuit failure is manufactured by reducing the voltage difference between the grid electrode and the source electrode of the transistor in the memory array to be tested, so that the failure which is not easy to be exposed is captured in the early testing period, and the reliability of a memory product is improved.

Description

Memory testing method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a memory testing method, apparatus, electronic device, and computer readable storage medium.

Background

Memories such as dynamic random access memory (Dynamic Random Access Memory, DRAM) are semiconductor memory devices commonly used in computers. With the increasing reduction of process sizes, devices and circuits are more prone to Fail Bit (FB), which needs to be grasped out using memory test methods.

As the process size decreases to make the size of the peripheral contacts (periphery contact, PC) less controllable, the PC size is often made larger than the target value, resulting in a closer distance between the PC and the gate (PG) on the periphery, which is prone to failure (fail) of the memory cell. Such failures often do not directly expose themselves in the early stages of testing, but rather occur due to sample aging after customer use or during early life failure rate (Early Life Failure Rate, ELFR) testing, reducing product reliability. To improve reliability, these failures need to be captured out at an early stage.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The disclosure aims to provide a memory testing method, a device, an electronic device and a storage medium, which can grasp failure which is not easy to be exposed in the early stage of testing, and improve the reliability of a memory product.

According to one aspect of the present disclosure, there is provided a memory testing method, the method comprising: acquiring a preset test pattern; according to the preset test pattern, performing data writing operation on the memory array to be tested on the memory; reducing the voltage difference between the grid electrode and the source electrode of the transistor in the memory array to be tested; performing data reading operation on the storage array to be tested after the pressure difference is reduced to obtain read data; and determining a failure test result of the memory based on the preset test pattern and the read data.

In some exemplary embodiments of the present disclosure, adjusting down the voltage difference between the gate and the source of the transistor in the memory array to be tested includes: regulating the grid voltage of the transistor in the memory array to be tested from a first voltage value to a second voltage value; and/or, the source voltage of the transistor in the memory array to be tested is regulated to be higher than the fourth voltage value from the third voltage value.

In some exemplary embodiments of the present disclosure, the memory array to be tested includes a plurality of bit lines and a plurality of memory cells distributed in an array, and the transistors in the memory array to be tested are transistors in the memory cells, and each bit line is coupled to a column of memory cells; the preset test pattern is used for writing a first numerical value on the memory cells coupled with the odd bit lines and writing a second numerical value on the memory cells coupled with the even bit lines; or, the predetermined test pattern is a test pattern for writing the second value on the memory cells coupled to the odd bit lines and writing the first value on the memory cells coupled to the even bit lines.

In some exemplary embodiments of the present disclosure, the memory array to be tested includes a plurality of word lines and a plurality of memory cells distributed in an array, and the transistors in the memory array to be tested are transistors in the memory cells, and each word line is coupled with a row of memory cells; after the voltage difference between the gate and the source of the transistor in the memory array to be tested is reduced, and before the data reading operation is performed on the memory array to be tested after the voltage difference is reduced, the method further includes: sequentially performing a precharge operation on the plurality of word lines, a row address precharge time of the plurality of word lines being greater than or equal to a charge threshold; and executing refreshing operation on the precharged word lines.

In some exemplary embodiments of the present disclosure, the charge threshold has a value in the range of 8ns to 20ns.

In some exemplary embodiments of the present disclosure, the second voltage value ranges from 2.0V to 3.0V; the value range of the fourth voltage value is-0.2V-0.1V.

In some exemplary embodiments of the present disclosure, the second voltage value is greater than a threshold voltage of the transistor.

According to another aspect of the present disclosure, there is provided a memory test apparatus, the apparatus comprising: the acquisition module is used for acquiring a preset test pattern; the writing module is used for executing data writing operation on the storage array to be tested on the storage according to the preset test pattern; the voltage regulating module is used for regulating the voltage difference between the grid electrode and the source electrode of the transistor in the storage array to be tested; the reading module is used for executing data reading operation on the storage array to be tested after the pressure difference is reduced, so as to obtain read data; and the determining module is used for determining a failure test result of the memory based on the preset test pattern and the read data.

According to still another aspect of the present disclosure, there is provided an electronic apparatus including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described memory testing method via execution of the executable instructions.

According to yet another aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the above-described memory test method.

According to yet another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the memory testing method described above.

According to the memory testing method, the device, the electronic equipment and the storage medium, a preset test pattern is obtained, data writing operation is performed on a memory array to be tested on the memory according to the preset test pattern, voltage regulation is performed on the memory, the voltage difference between the grid electrode and the source electrode of a transistor in the memory array to be tested is regulated down, then data reading operation is performed on the memory array to be tested after the voltage difference is reduced, read data are obtained, and failure testing results of the memory are determined based on the preset test pattern and the read data. The method and the device have the advantages that the poor testing condition (word condition) aiming at PC-PG short circuit failure (short fail) is manufactured by reducing the voltage difference between the grid electrode and the source electrode of the transistor in the memory array to be tested, the test is carried out under the testing condition, normal memory cells cannot fail, the memory cells which are not obviously caused to fail (short fail) due to the PC-PG short circuit are exposed under the testing condition, so that the failure which is not easy to be exposed is captured in the early stage of the test, and the reliability of a memory product is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

FIG. 1 shows a schematic diagram of a memory array of a DRAM product of the present disclosure.

Fig. 2 shows a schematic diagram of the structure of a memory cell on the memory array of fig. 1.

Fig. 3 shows a schematic diagram of a PC-PG short circuit failure of the present disclosure.

FIG. 4 illustrates an architecture diagram of a memory test system provided in an exemplary embodiment of the present disclosure.

FIG. 5 illustrates a flow chart of a memory testing method in an exemplary embodiment of the present disclosure.

FIG. 6 illustrates a schematic diagram of a memory array to be tested in an exemplary embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a memory array to be tested after a pressure differential is reduced in an exemplary embodiment of the present disclosure.

FIG. 8 illustrates a memory test process schematic diagram according to an exemplary embodiment of the present disclosure.

FIG. 9 illustrates a schematic diagram of a memory test device in an embodiment of the disclosure.

Fig. 10 shows a block diagram of an electronic device according to an embodiment of the disclosure.

Fig. 11 shows a schematic diagram of a computer-readable storage medium in an embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.

It should be noted that the terms "first," "second," and the like in this disclosure are merely used to distinguish between different devices, modules, or units and are not used to define an order or interdependence of functions performed by the devices, modules, or units.

It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to mean "one or more" unless the context clearly indicates otherwise, where "a plurality" means two or more.

In order to facilitate understanding, technical terms related to the embodiments of the present disclosure are described before describing the technical solutions provided by the embodiments of the present disclosure.

(1) Early life failure rate (Early Life Failure Rate, ELFR) used to simulate the burn-in test means used by customers. Illustratively, the burn-in test means employed may be an alternating current (Alternating Current, AC) stress test.

(2) The AC stress test is a state in which the position to be stressed is always in a state of alternating high and low voltages, and the AC stress test is a plurality of times of reading and writing under a high voltage. Because the AC stress test can only read and write one word line WL, the time for completing the whole memory test is long, and the test cost is too high.

(3) Memories, such as dynamic random access memory (Dynamic Random Access Memory, DRAM) are semiconductor memory devices commonly used in computers, and their memory arrays are composed of many repeated memory cells. As shown in fig. 1, 10 is used to indicate a memory array, 11 is used to indicate Bit Lines (BL), 12 is used to indicate Word Lines (WL), and 13 is used to indicate memory cells. As shown in fig. 2, each memory cell 13 may include a transistor 131 and a storage capacitor 132, the word line 12 is connected to the gate of the transistor 131, and the voltage signal on the word line 12 can control the transistor 131 to be turned on or off; the bit line 11 is connected to the source of the transistor 131, and is controlled by a voltage signal on the word line 12, the bit line 11 is used for reading data information stored in the storage capacitor 132, the bit line 11 can also write the data information into the storage capacitor 132 for storage, the bit line 14 is used for indicating the bit line capacitance, and the bit line capacitance 14 is used for assisting the bit line 11 to read the data information or write the data information.

(4) A transistor (transistor) is a solid state semiconductor device (which may include a transistor, a field effect transistor, a thyristor). For example, the transistor in the embodiment of the present disclosure may be a MOS transistor (metal oxide semiconductor (metal oxide semiconductor), a field effect transistor), to which the present disclosure is not limited.

Having described the foregoing, a description of a memory test scheme is continued.

In the production of DRAM products, as the process size is increasingly reduced, the size of the peripheral contact PC is made more difficult to control, the peripheral contact PC is often made larger than a target value, resulting in a closer distance between the peripheral contact PC and the gate PG on the periphery, and the memory cell is likely to fail, as shown in fig. 3, a target box 31 is used to indicate the target value size of the peripheral contact PC, a box 32 is used to indicate the size of the peripheral contact PC that causes failure, and a box 33 is used to indicate the size of the gate PG on the periphery. When the peripheral contact PC is made too large during the process, for example, when the peripheral contact PC is larger than the target size, it is caused to be too close to the gate PG on the periphery to cause a short circuit.

The inventors found that whether the short circuit phenomenon is significantly likely to vary depending on the distance between the peripheral contact PC and the gate PG on the periphery or the size of the peripheral contact PC. Illustratively, when the size of the peripheral contact PC is greater than the target value and less than the threshold size (e.g., 6 x 10 ^-6 Leather rice ² (pm ² ) There is no particular limitation thereto), a short circuit between the peripheral contact PC and the gate PG on the periphery is not obvious. And, when the size of the peripheral contact PC is less than or equal to the target value, no short circuit is generated; when the size of the peripheral contact PC is greater than or equal to the threshold size, a short circuit between the peripheral contact PC and the gate PG on the periphery is significant.

The inventors have studied and found that the following problems exist with respect to the above-mentioned obvious PG short circuit phenomenon and the unobvious short circuit phenomenon: when normal read-write operation is performed, failure caused by obvious PC-PG short circuit phenomenon can be grasped, however, when the PC-PG short circuit phenomenon is not obvious, the failure problem cannot be detected in the early stage of testing, and the failure problem often occurs after the use of a customer or during ELFR testing due to sample aging, so that the reliability of a product is affected.

Based on this, the embodiment of the disclosure provides a memory test method, which can be applied to a semiconductor manufacturing scene, and can be applied to a specific scene of DRAM manufacturing by way of example. For example, the method is applied to a specific scene of manufacturing the 4F2 DRAM or the 6F2 DRAM, and can also be used in manufacturing scenes of other memories, and the method is not particularly limited. In the embodiment of the disclosure, a preset test pattern is acquired, a data writing operation is performed on a memory array to be tested on a memory according to the preset test pattern, then voltage regulation is performed on the memory, the voltage difference between the gate and the source of a transistor in the memory array to be tested is reduced, then a data reading operation is performed on the memory array to be tested with the reduced voltage difference, read data are obtained, and a failure test result of the memory is determined based on the preset test pattern and the read data. The method and the device have the advantages that the poor testing condition aiming at PC-PG short circuit failure is manufactured by reducing the voltage difference between the grid electrode and the source electrode of the transistor in the memory array to be tested, the test is carried out under the testing condition, the normal memory unit cannot fail, the memory unit which fails due to the fact that the PC-PG short circuit is not obvious fails under the testing condition, and therefore the failure which is not easy to be exposed is captured in the early stage of the test, and the reliability of a memory product is improved.

The present exemplary embodiment will be described in detail below with reference to the accompanying drawings and examples.

In order to facilitate overall understanding of the technical solutions provided by the embodiments of the present disclosure, a description is first given of a memory test system provided by the embodiments of the present disclosure.

FIG. 4 illustrates an architecture diagram of a memory test system provided in an exemplary embodiment of the present disclosure. As shown in fig. 4, the memory test system 40 may include a control device 41 and a failure test device 42.

The control device 41 may be a host computer having a control function, and may control the memory test operation of one or more failure test devices 42. Specifically, the control device 41 may send various instructions, such as a failure test command, a data reading instruction, and the like, to the failure test device 42. In some embodiments, the control device 41 may also receive a selection operation of an operator for the storage array to be tested, so as to flexibly select, according to a requirement, an object of a required storage detection in the storage 43 connected to the failure testing device 42, thereby improving flexibility of storage detection.

For failure testing device 42, it may be coupled to one or more memories 43, where memory 43 may be a single memory granule (die) or a plurality of memory granules. The failure test device 42 may be configured to obtain a preset test pattern, perform a data writing operation on a storage array to be tested on the memory according to the preset test pattern, reduce a voltage difference between a gate and a source of a transistor in the storage array to be tested, perform a data reading operation on the storage array to be tested after the voltage difference is reduced, obtain read data, and determine a failure test result of the memory based on the preset test pattern and the read data. The failure testing apparatus 42 may be an automated testing device (Automatic Test Equipment, ATE), to which the present disclosure is not limited, as long as the above-described functions can be implemented.

Specifically, the failure testing device 42 is connected to locate a storage array to be tested in the connected memory 43 in response to a failure test command sent by the control device 41, and then test it. It should be noted that the memory 43 may include at least one physical storage 431, where the physical storage 431 includes a plurality of memory granules 432, and the memory granules 432 may include a plurality of memory blocks (banks), and the memory blocks may include a plurality of arrays to be tested (arrays).

In terms of connection, in some exemplary embodiments, the control device 41 and the failure testing device 42 may be in wired communication. Illustratively, to save communication costs, serial communication may be provided between the control device 41 and the failure testing device 42. Note that, the communication modes such as parallel communication or wireless communication may be selected between the control device 41 and the failure testing device 42 according to the actual application scenario and the specific application requirement, which is not limited in particular.

Embodiments of the present disclosure provide a memory testing method that may be performed by any electronic device having computing processing capabilities. The method may be performed by, for example, a semiconductor manufacturing device such as an automated test equipment (Automatic Test Equipment, ATE), or other processing device to which the semiconductor manufacturing device is communicatively coupled, without limitation.

Fig. 5 illustrates a flowchart of a memory test method in an exemplary embodiment of the present disclosure, and as illustrated in fig. 5, the memory test method provided in the embodiment of the present disclosure may include the following S501 to S505.

S501, acquiring a preset test pattern.

The predetermined test pattern may be a data pattern formed by a data topology to be written into the memory array to be tested. For example, a column stripe test pattern, i.e., a topology (topo) for writing 1 on the memory cells coupled to the odd bit lines and writing 0 on the memory cells coupled to the even bit lines. The specific patterns related to the preset test patterns may be set to other test patterns consisting of "1" and "0" according to the actual test scenario and specific test requirements, for example, checkerboard test patterns, all "1" or all "0" test patterns, etc., which are not limited in the present disclosure.

The data written into the memory array to be tested in the preset test pattern is shown in table 1 below.

TABLE 1

	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	0	0	0	0	0	0	0	0
BL1	1	1	1	1	1	1	1	1
									BL2	0	0	0	0	0	0	0	0
BL3	1	1	1	1	1	1	1	1
									BL4	0	0	0	0	0	0	0	0
BL5	1	1	1	1	1	1	1	1
									BL6	0	0	0	0	0	0	0	0
BL7	1	1	1	1	1	1	1	1

As shown in table 1, 1 is written on the memory cells coupled to the odd bit lines (BL 1, BL3, BL5, BL 7) in the memory array to be tested, and 0 is written on the memory cells coupled to the even bit lines (BL 0, BL2, BL4, BL 6) in the memory array to be tested.

For another example, a predetermined test pattern is used to indicate that a 0 is written on a memory cell coupled to an odd bit line and a 1 is written on a memory cell coupled to an even bit line. The data written into the memory array to be tested in the preset test pattern is shown in table 2 below.

TABLE 2

	WL0	WL1	WL2	WL3	WL4	WL5	WL6	WL7
									BL0	1	1	1	1	1	1	1	1
BL1	0	0	0	0	0	0	0	0
									BL2	1	1	1	1	1	1	1	1
BL3	0	0	0	0	0	0	0	0
									BL4	1	1	1	1	1	1	1	1
BL5	0	0	0	0	0	0	0	0
									BL6	1	1	1	1	1	1	1	1
BL7	0	0	0	0	0	0	0	0

As shown in table 2, 0 is written on the memory cells coupled to the odd bit lines (BL 1, BL3, BL5, BL 7) in the memory array to be tested, and 1 is written on the memory cells coupled to the even bit lines (BL 0, BL2, BL4, BL 6) in the memory array to be tested.

S502, according to a preset test pattern, performing data writing operation on the memory array to be tested on the memory.

The storage array to be tested is a storage array (array) to be tested on the memory. It should be noted that, in the embodiment of the present disclosure, the memory array to be tested may include one memory array, or may include a plurality of memory arrays, which is not limited thereto.

The embodiments of the present disclosure are not limited in terms of how data write operations are performed on a memory array to be tested. For example, a data write operation is performed on the memory array to be tested by a logic control unit on the memory working in conjunction with a mode register. For another example, the data writing operation may be performed by connecting the memory with the terminal device. The terminal equipment can be a computer, a test machine, a mobile phone and other equipment.

It should be noted that the present disclosure is not limited to what writing order is used to write the data in the predetermined test pattern into the memory array to be tested. For example, a Y-direction Write operation (Y-Page Write) is adopted, a word line is turned on before each Write operation is performed, and after all the memory cells corresponding to the word line are sequentially written, the word line is turned off. Then the next word line is started to sequentially write all the memory cells. For example, as shown in table 1, the word line WL0 is turned on, the memory cells corresponding to the bit lines BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7 on the word line WL0 are sequentially written, the word line WL0 is turned off, the word line WL1 is turned on, the memory cells corresponding to the bit lines BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7 on the word line WL1 are sequentially written, and so on, and all the memory cells are sequentially written. The data writing is performed by adopting a Y-Page Write mode, so that the accuracy of the data writing can be improved, and the accuracy of failure test is ensured.

In the embodiment of the disclosure, since the memory cell has leakage, the stored data needs to be refreshed at regular time. For example, after the memory array to be tested performs a data writing operation, the memory array to be tested is refreshed, so that the written data is ensured not to generate electric leakage, and the integrity of initial data is ensured.

S503, regulating down the voltage difference between the grid electrode and the source electrode of the transistor in the memory array to be tested.

In the disclosed embodiments, the voltage difference between the gate and source of the transistors in the memory array to be tested is reduced by a Test Mode (TM) on an automated test equipment. Illustratively, the source voltage of the MOS transistor controlling the voltage on the word line is pulled up from a negative value using the test module, and the gate voltage of the MOS transistor controlling the voltage on the word line is pulled down from a positive value using the test module. Thereby enabling a voltage differential between the gate and source of the transistor to be reduced.

It should be noted that when the PC-PG is shorted, the source and the gate of the MOS transistor controlling the voltage on the word line will be shorted, and the voltages of the two are at the same value of an intermediate potential, that is, the voltage on the PC is the source voltage of the MOS transistor, and the voltage on the PG is the gate voltage of the MOS transistor. However, this is the case for failures that are evident from PC-PG shorts, which can be grasped by reading and writing to the storage array under test. If the failure caused by the short circuit of PC-PG is not obvious, the potential of the source electrode and the grid electrode of the MOS tube still keeps the target value at the grabbing edge (margin), that is, when the short circuit of PC-PG is not obvious, the reading of the memory array to be tested is normal, and the failure caused by the short circuit of PC-PG cannot be grabbed. By the embodiment of the invention, the voltage difference between the grid electrode and the source electrode of the MOS tube is reduced, and the obvious PC-PG short circuit condition can be simulated. In this case, the time of the word line closing is lengthened far beyond the time of the word line closing during normal reading and writing, and failure caused by the fact that PC-PG short circuit is not obvious can be caught during reading and writing.

S504, executing data reading operation on the memory array to be tested after the pressure difference is reduced, and obtaining read data.

The embodiments of the present disclosure are not limited in terms of how to perform a data read operation on the reduced differential pressure memory array to be tested. For example, a data read operation is performed on the memory array to be tested by a logic control unit on the memory operating in conjunction with a mode register. For another example, the data reading operation may be performed by connecting the memory to the terminal device. The terminal equipment can be a computer, a test machine, a mobile phone and other equipment.

The present disclosure is not limited to what read-out order is used to read out data on the reduced differential pressure memory array to be tested. For example, a Y-direction Read operation (Y-Fast Read) is used to turn on a word line before each Read operation is performed, and turn off the word line after a burst length (burst) unit on the word line is sequentially Read. This word line is then turned on again to read out a burst length cell sequentially. The word line is repeatedly turned on and off until all the corresponding memory cells on the word line are completely read. And then starting the next word line to execute the same operation until all the memory cells on the memory array to be tested are read. The data is Read by adopting a Y-Fast Read mode, so that the accuracy of data reading can be improved, and the accuracy of failure test is ensured.

S505, determining a failure test result of the memory based on the preset test pattern and the read data.

In the embodiment of the disclosure, whether the memory cell fails or not can be judged by whether the preset test pattern is consistent with the read data or not. That is, whether the memory cell fails is determined by determining the consistency of the data written into the memory array to be tested (preset test pattern) and the data read out from the memory array to be tested after the voltage difference is reduced (read data). If the written data is the same as the read data, it is indicated that the memory cell is normal. If the written data is not equal to the read data, the failure caused by the fact that the PC-PG short circuit is not obvious exists in the storage unit is indicated. For example, as shown in fig. 6, the data written into the memory array to be tested is 11111111 00000000, as shown in fig. 7, the data read out from the memory array to be tested after the voltage difference is reduced is 11111011 0001000, and since the written data is inconsistent with the read out data, 2 memory cells fail, and the 2 failed memory cells are the memory cells (WL 0, BL 5) and the memory cells (WL 1, BL 3), respectively. Before the test of the present disclosure, the memory array to be tested is a memory array with normal reading and writing (no exposure to failure caused by the inconspicuous short circuit of PC-PG), that is, the written data of the memory array to be tested is consistent with the data read from the memory array to be tested.

According to the embodiment of the disclosure, the poor testing condition for PC-PG short circuit failure is manufactured by reducing the voltage difference between the grid electrode and the source electrode of the transistor in the memory array to be tested, the test is performed under the testing condition, the normal memory cell cannot fail, and the memory cell which is not obviously caused to fail due to the PC-PG short circuit is exposed under the testing condition, so that the failure which is not easy to be exposed is captured in the early stage of the test, and the reliability of a memory product is improved.

The following describes how to reduce the voltage difference between the gate and source of the transistors in the memory array to be tested.

In an exemplary embodiment, reducing the voltage difference between the gate and the source of the transistor in the memory array to be tested may include: and regulating the grid voltage of the transistor in the memory array to be tested from the first voltage value to the second voltage value.

The second voltage value is not particularly limited as long as the voltage that does not significantly cause failure due to the PC-PG short circuit can be grasped. For example, the second voltage value is smaller than the first voltage value, and both the first voltage value and the second voltage value may be positive values. For example, the first voltage value ranges from 3.1V to 3.6V, and the second voltage value ranges from 2.0V to 3.0V. For another example, the first voltage value is 3.4V and the second voltage value is 2.4V. For another example, the first voltage value is 3.4V and the second voltage value is 2.8V. Illustratively, the second voltage value is greater than the threshold voltage of the transistor, and the second voltage value is greater than the threshold voltage, which may ensure the on state of the transistor. For example, the second voltage value ranges from 2.0V to 3.0V.

It should be noted that the gate voltage of the transistor is greater than the source voltage, and the voltage difference between the gate and the source of the transistor in the memory array to be tested can be reduced by reducing the gate voltage.

According to the embodiment of the disclosure, the voltage difference between the grid electrode and the source electrode of the transistor is reduced by reducing the grid voltage, so that a poor test condition for PC-PG short circuit failure is manufactured, and a storage unit which is not obviously caused to fail due to the PC-PG short circuit is exposed in advance, so that the reliability of a storage product is improved.

In another exemplary embodiment, reducing the voltage difference between the gate and the source of the transistor in the memory array to be tested may include: and (3) regulating the source voltage of the transistor in the memory array to be tested from the third voltage value to the fourth voltage value.

As to the specific fourth voltage value, the embodiment of the present disclosure is not limited as long as it is a voltage that can achieve the grabbing out, which does not significantly cause the failure due to the PC-PG short circuit. The fourth voltage value is greater than the second voltage value, and the third voltage value may be a negative value, or the fourth voltage value may be a positive value. For example, the fourth voltage value ranges from-0.2V to 0.1V, and the third voltage value ranges from-0.5V to 0.1V. For another example, the third voltage value is-0.4V and the fourth voltage value is 0V. For another example, the third voltage value is-0.4V and the fourth voltage value is-0.1V.

It should be noted that the gate voltage of the transistor is greater than the source voltage, and the voltage difference between the gate and the source of the transistor in the memory array to be tested can be reduced by raising the source voltage.

According to the embodiment of the disclosure, the voltage difference between the grid electrode and the source electrode of the transistor is reduced by increasing the source electrode voltage, so that a poor test condition for PC-PG short circuit failure is manufactured, and a storage unit which is not obviously caused to fail due to the PC-PG short circuit is exposed in advance, so that the reliability of a storage product is improved.

In an exemplary embodiment, reducing the voltage difference between the gate and the source of the transistor in the memory array to be tested may include: regulating the grid voltage of a transistor in the memory array to be tested from a first voltage value to a second voltage value; and (3) regulating the source voltage of the transistor in the memory array to be tested from the third voltage value to the fourth voltage value.

The first voltage value, the second voltage value, the third voltage value and the fourth voltage value have been described in the above two exemplary embodiments, and are not described herein.

It should be noted that the gate voltage of the transistor is greater than the source voltage, and the voltage difference between the gate and the source of the transistor in the memory array to be tested can be reduced by raising the source voltage and lowering the gate voltage.

According to the embodiment of the disclosure, the voltage difference between the grid electrode and the source electrode of the transistor is reduced by increasing the source electrode voltage and reducing the grid electrode voltage, so that a poor test condition aiming at PC-PG short circuit failure is manufactured, and a storage unit which is not obviously caused to fail due to the PC-PG short circuit is exposed in advance, so that the reliability of a storage product is improved.

The preset test pattern is described below.

In an exemplary embodiment, the memory array to be tested may include a plurality of bit lines and a plurality of memory cells distributed in an array, and the transistors in the memory array to be tested are transistors in the memory cells, and each bit line is coupled to a column of memory cells; the preset test pattern is used for writing a first numerical value on the memory cells coupled with the odd bit lines and writing a second numerical value on the memory cells coupled with the even bit lines; or, the predetermined test pattern is a test pattern for writing the second value on the memory cells coupled to the odd bit lines and writing the first value on the memory cells coupled to the even bit lines.

In the embodiment of the disclosure, the first value and the second value are different values, and by writing different values on the odd bit lines and the even bit lines, stress between the adjacent bit lines is increased. By interleaving the writing of different values on the bit lines, more stress times may be created between the bit lines, and embodiments of the present disclosure are not limited thereto. It should be noted that the existence of a primary voltage difference on adjacent bit lines is called primary stress. The greater the number of stresses, the more likely the potentially failing cell will be exposed.

For example, as shown in table 1, the first value is 0, the second value is 1, 0 is written on the memory cells coupled to the odd bit lines, and 1 is written on the memory cells coupled to the even bit lines. For another example, as shown in Table 2, the first value is 1, the second value is 0, 1 is written on the memory cells coupled to the odd bit lines, and 0 is written on the memory cells coupled to the even bit lines.

According to the embodiment of the disclosure, the voltage difference between two adjacent bit lines is increased, so that the failed memory cell is easier to expose, that is, the memory cell which is not obviously caused by PC-PG short circuit is easier to expose in advance, and the reliability of a memory product is improved.

How to refresh the memory array to be tested is described below.

In an exemplary embodiment, the memory array to be tested may include a plurality of word lines and a plurality of memory cells distributed in the array, and the transistors in the memory array to be tested may be transistors in the memory cells, and each word line is coupled to a row of memory cells. After the voltage difference between the gate and the source of the transistor in the memory array to be tested is reduced and before the data reading operation is performed on the memory array to be tested after the voltage difference is reduced, the memory test method may further include: after reducing the voltage difference between the gate and the source of the transistor in the memory array to be tested and before performing a data reading operation on the memory array to be tested after the voltage difference is reduced to obtain the read data, the method further includes:

Sequentially performing precharge operation on the plurality of word lines, wherein the row address precharge time of the plurality of word lines is greater than or equal to a charge threshold; and performing a refresh operation on the precharged plurality of word lines.

A Row address precharge Time (TRP) that is used to set the charge time required for the current Row before another Row address can be activated.

With respect to the charging threshold in particular, embodiments of the present disclosure are not limited. Illustratively, the charge threshold value ranges from 8 nanoseconds (ns) to 20ns. For example, the charge threshold may be 8ns, 9ns, 10ns, 11ns, 12ns, 13ns, 14ns, 15ns, 16ns, 17ns, 18ns, 19ns, 20ns. As another example, the charge threshold may be a minimum time specified by the electronic component industry association (Joint Electron Device Engineering Council, JEDEC). If JEDEC specifies a minimum time of 14 nanoseconds (ns), the row address precharge time to precharge the word line is 14ns.

In the disclosed embodiments, the word line to be precharged is in an activated state before a precharge operation is performed. Illustratively, the word line to be precharged may be activated by means of an active Address (ACT). Activating addressing can be understood simply as opening a word line, and the opening of the transistor of the corresponding word line can be achieved by applying a voltage.

It should be noted that, since the memory such as DRAM has exclusivity in addressing, if the addressing is to be performed on another row of the same bank (8 banks are included in one granule, and a row in each bank has shared active addressing (active) and precharge (precharge) circuits), the original row is to be closed, the row/column address is to be resent, the existing row is closed, the operation of opening the new row is to be precharge, and the precharge may be controlled by a command or by an auxiliary setting to allow the memory to be automatically precharged after each read/write operation.

The precharge operation is used for precharging the activated row to end the active state, and returns to the idle state after the precharge is ended, and can be activated again, and at the moment, operation commands such as low power consumption, automatic refresh, self-refresh, mode setting and the like can be input.

In the embodiment of the disclosure, by setting the row address precharge time to the minimum time specified by JEDEC, normal read-write can be ensured, test time can be saved, and the influence of storage capacitor leakage on test results can be prevented.

The test procedure of the present disclosure is illustrated by two examples below.

As shown in fig. 8, after a wafer (wafer) is bound on a test machine, the wafer is in a form before the memory is divided, so to speak, after the memory is bound on the test machine, the test machine is controlled by software to power up the wafer/memory, the source voltage of the MOS transistor controlling the voltage on the word line is set to-0.4V, and the gate voltage of the MOS transistor controlling the voltage on the word line is set to 3.4V. The following operations are performed:

in one embodiment, as shown in fig. 8 (1), a network topology (topo) topo of a dual row stripe (double row stripe) is written to a memory array to be tested on a memory according to a predetermined test pattern, wherein 0 is written to a memory cell connected to an odd bit line, 1 is written to a memory cell connected to an even bit line, and a global refresh is performed after writing. As shown in fig. 8 (2), a Test Mode (TM) command adjusts the source voltage of the MOS transistor from-0.4V to 0V and adjusts the gate voltage of the MOS transistor from 3.4V to 2.4V. As shown in fig. 8 (3), the plurality of word lines are refreshed in sequence, and the TRP time is set to the minimum time specified by JEDEC. As shown in (4) of fig. 8, a data reading operation is performed on the memory array to be tested to obtain read data, and a failure test result of the memory is determined based on a preset test pattern and the read data.

The embodiment of the disclosure can grasp out failures caused by the fact that PC-PG short circuits are not obvious. The embodiment of the disclosure can write different network topologies for testing, and is closer to the actual application scene. The test is convenient, and the test time is long, so that the test cost is saved.

In another embodiment, as shown in fig. 8 (1), a network topology (topo) of a dual row stripe (dual row stripe) is written to a memory array to be tested on a memory according to a predetermined test pattern, wherein all 1's are written to memory cells connected to odd bit lines, all 0's are written to memory cells connected to even bit lines, and a global refresh is performed after the writing is completed. As shown in fig. 8 (2), a Test Mode (TM) command is issued to adjust the source voltage of the MOS transistor from-0.4V to-0.1V and the gate voltage of the MOS transistor from 3.4V to 2.8V. As shown in fig. 8 (3), the plurality of word lines are refreshed sequentially, and the TRP time is set to the minimum time specified by JEDEC, and the minimum time specified by JEDEC is set to 14ns. As shown in (4) of fig. 8, a data reading operation is performed on the memory array to be tested to obtain read data, and a failure test result of the memory is determined based on a preset test pattern and the read data.

Based on the same inventive concept, a memory test device is also provided in the embodiments of the present disclosure, as follows. Since the principle of solving the problem of the embodiment of the device is similar to that of the embodiment of the method, the implementation of the embodiment of the device can be referred to the implementation of the embodiment of the method, and the repetition is omitted.

Fig. 9 shows a schematic diagram of a memory testing device in an embodiment of the disclosure, as shown in fig. 9, the device may include an acquisition module 91, a writing module 92, a voltage adjustment module 93, a reading module 94, and a determination module 95, where: the acquiring module 91 may be configured to acquire a preset test pattern; the writing module 92 may be configured to perform a data writing operation on the memory array to be tested on the memory according to a preset test pattern; the voltage regulation module 93 may be used to regulate down the voltage difference between the gate and source of the transistors in the memory array to be tested; the reading module 94 may be configured to perform a data reading operation on the storage array to be tested after the differential pressure is reduced, to obtain read data; the determining module 95 may be configured to determine a failure test result of the memory based on the preset test pattern and the read data.

In an embodiment, the voltage adjustment module 93 may be further configured to adjust the gate voltage of the transistor in the memory array to be tested from a first voltage value to a second voltage value; and/or, the source voltage of the transistor in the memory array to be tested is regulated to be higher than the fourth voltage value from the third voltage value.

In one embodiment, the memory array to be tested may include a plurality of bit lines and a plurality of memory cells distributed in an array, where the transistors in the memory array to be tested are transistors in the memory cells, and each bit line is coupled to a column of memory cells; the preset test pattern is used for writing a first numerical value on the memory cells coupled with the odd bit lines and writing a second numerical value on the memory cells coupled with the even bit lines; or, the predetermined test pattern is a test pattern for writing the second value on the memory cells coupled to the odd bit lines and writing the first value on the memory cells coupled to the even bit lines.

In one embodiment, the memory array to be tested may include a plurality of word lines and a plurality of memory cells distributed in an array, where the transistors in the memory array to be tested are transistors in the memory cells, and each word line is coupled to a row of memory cells; after reducing the voltage difference between the gate and the source of the transistor in the memory array to be tested and before performing a data reading operation on the memory array to be tested after the voltage difference is reduced to obtain the read data, the voltage adjusting module 93 may be further configured to sequentially perform a precharge operation on a plurality of word lines, where a row address precharge time of the plurality of word lines is greater than or equal to a charge threshold; and performing a refresh operation on the precharged plurality of word lines.

In one embodiment, the charge threshold is in the range of 8ns-20ns.

In one embodiment, the second voltage value ranges from 2.0V to 3.0V; the value range of the fourth voltage value is-0.2V-0.1V.

In one embodiment, the second voltage value is greater than a threshold voltage of the transistor.

The memory test device in the embodiment of the disclosure makes a worse test condition (condition) for PC-PG short-circuit failure by regulating down the voltage difference between the grid electrode and the source electrode of the transistor in the memory array to be tested, and tests under the test condition, normal memory cells cannot fail, and the memory cells which fail due to the fact that the PC-PG short circuit is not obvious are exposed under the test condition, so that the failure which is not easy to be exposed is captured in the early stage of testing, and the reliability of a memory product is improved.

Those skilled in the art will appreciate that the various aspects of the present disclosure may be implemented as a system, method, or program product. Accordingly, various aspects of the disclosure may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.

An electronic device 1000 according to such an embodiment of the present disclosure is described below with reference to fig. 10. The electronic device 1000 shown in fig. 10 is merely an example and should not be construed as limiting the functionality and scope of use of the disclosed embodiments.

As shown in fig. 10, the electronic device 1000 is embodied in the form of a general purpose computing device. Components of electronic device 1000 may include, but are not limited to: the at least one processing unit 1010, the at least one memory unit 1020, and a bus 1030 that connects the various system components, including the memory unit 1020 and the processing unit 1010.

Wherein the storage unit stores program code that is executable by the processing unit 1010 such that the processing unit 1010 performs steps according to various exemplary embodiments of the present disclosure described in the above section of the present specification.

The memory unit 1020 may include readable media in the form of volatile memory units such as Random Access Memory (RAM) 10201 and/or cache memory unit 10202, and may further include Read Only Memory (ROM) 10203.

The storage unit 1020 may also include a program/utility 10204 having a set (at least one) of program modules 10205, such program modules 10205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.

Bus 1030 may be representing one or more of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 1000 can also communicate with one or more external devices 1040 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device 1000, and/or with any device (e.g., router, modem, etc.) that enables the electronic device 1000 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 1050.

Also, electronic device 1000 can communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet, through network adapter 1060.

As shown in fig. 10, the network adapter 1060 communicates with other modules of the electronic device 1000 over the bus 1030.

It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with the electronic device 1000, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a terminal device, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.

In an exemplary embodiment of the present disclosure, a computer-readable storage medium, which may be a readable signal medium or a readable storage medium, is also provided. Fig. 11 illustrates a schematic diagram of a computer-readable storage medium in an embodiment of the present disclosure, as shown in fig. 11, on which a program product capable of implementing the method of the present disclosure is stored 1100.

In some possible implementations, various aspects of the disclosure may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps according to the various exemplary embodiments of the disclosure as described in the "exemplary methods" section of this specification, when the program product is run on the terminal device.

More specific examples of the computer readable storage medium in the present disclosure may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

In this disclosure, a computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing.

A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

In some examples, program code embodied on a computer readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

In particular implementations, the program code for carrying out operations of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

Embodiments of the present disclosure provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions to cause the computer device to perform the memory testing methods provided in the various alternatives in any of the embodiments of the disclosure.

It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

Furthermore, although the steps of the methods in the present disclosure are depicted in a particular order in the drawings, this does not require or imply that the steps must be performed in that particular order or that all illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.

From the description of the above embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware.

Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a mobile terminal, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein.

This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A method of testing a memory, the method comprising:

acquiring a preset test pattern;

according to the preset test pattern, performing data writing operation on the memory array to be tested on the memory;

Reducing the voltage difference between the grid electrode and the source electrode of the transistor in the memory array to be tested;

performing data reading operation on the storage array to be tested after the pressure difference is reduced to obtain read data;

and determining a failure test result of the memory based on the preset test pattern and the read data.

2. The method of claim 1, wherein reducing the voltage difference between the gate and source of the transistors in the memory array to be tested comprises:

regulating the grid voltage of the transistor in the memory array to be tested from a first voltage value to a second voltage value; and/or the number of the groups of groups,

and the source voltage of the transistor in the memory array to be tested is regulated to be higher than a fourth voltage value from the third voltage value.

3. The method of claim 1, wherein the memory array to be tested comprises a plurality of bit lines and a plurality of memory cells distributed in an array, the transistors in the memory array to be tested being transistors in the memory cells, each bit line being coupled to a column of memory cells;

the preset test pattern is used for writing a first numerical value on the memory cells coupled with the odd bit lines and writing a second numerical value on the memory cells coupled with the even bit lines; or alternatively, the first and second heat exchangers may be,

The predetermined test pattern is a test pattern for writing the second value on the memory cells coupled to the odd bit lines and writing the first value on the memory cells coupled to the even bit lines.

4. The method of claim 1, wherein the memory array to be tested comprises a plurality of word lines and a plurality of memory cells distributed in an array, the transistors in the memory array to be tested being transistors in the memory cells, each of the word lines being coupled to a row of memory cells;

after the voltage difference between the gate and the source of the transistor in the memory array to be tested is reduced, and before the data reading operation is performed on the memory array to be tested after the voltage difference is reduced, the method further includes:

sequentially performing a precharge operation on the plurality of word lines, a row address precharge time of the plurality of word lines being greater than or equal to a charge threshold;

and executing refreshing operation on the precharged word lines.

5. The method of claim 4, wherein the charge threshold has a value in the range of 8ns to 20ns.

6. The method of claim 2, wherein the second voltage value ranges from 2.0V to 3.0V; the value range of the fourth voltage value is-0.2V-0.1V.

7. The method of claim 2, wherein the second voltage value is greater than a threshold voltage of the transistor.

8. A memory test apparatus, the apparatus comprising:

the acquisition module is used for acquiring a preset test pattern;

the writing module is used for executing data writing operation on the storage array to be tested on the storage according to the preset test pattern;

the voltage regulating module is used for regulating the voltage difference between the grid electrode and the source electrode of the transistor in the storage array to be tested;

the reading module is used for executing data reading operation on the storage array to be tested after the pressure difference is reduced, so as to obtain read data;

and the determining module is used for determining a failure test result of the memory based on the preset test pattern and the read data.

9. An electronic device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the memory testing method of any of claims 1-7 via execution of the executable instructions.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the memory testing method of any of claims 1-7.