CN117012253A - Reading circuit for memory and memory - Google Patents

Reading circuit for memory and memory Download PDF

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Publication number
CN117012253A
CN117012253A CN202310917497.2A CN202310917497A CN117012253A CN 117012253 A CN117012253 A CN 117012253A CN 202310917497 A CN202310917497 A CN 202310917497A CN 117012253 A CN117012253 A CN 117012253A
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China
Prior art keywords
voltage
current
transistor
unit
bit line
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CN202310917497.2A
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Chinese (zh)
Inventor
许延华
陈艳
白俊峰
孟颖
李欢
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Beijing CEC Huada Electronic Design Co Ltd
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Beijing CEC Huada Electronic Design Co Ltd
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Priority to CN202310917497.2A priority Critical patent/CN117012253A/en
Publication of CN117012253A publication Critical patent/CN117012253A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

Disclosed are a read circuit for a memory and a memory, the read circuit including: a first comparator having a first input coupled to the bit line of the memory cell to receive the bit line current and a second input receiving the reference current; and the compensation module is used for compensating the reference current and/or compensating the word line voltage of the memory cell so as to increase the difference value between the bit line current and the reference current along with the rise of temperature. According to the reading circuit and the memory provided by the application, the compensation module is added in the reading circuit to compensate the bit line current and/or the reference current along with the increase of the temperature, so that the correlation between the difference value of the bit line current and the reference current and the temperature is reduced, the window of reading operation at the high temperature is increased, and the reading reliability of the memory at the high temperature is further improved.

Description

Reading circuit for memory and memory
Technical Field
The present application relates to the field of integrated circuits, and more particularly, to a reading circuit for a memory and a memory.
Background
Memory is an important component of digital integrated circuits, which is an integral part of the construction of microprocessor-based application systems. In recent years, various memories are embedded in a processor to improve the integration and the working efficiency of the processor, so that the performance of the memory array and its peripheral circuits largely determine the working condition of the whole system.
The read circuit is an important component of the peripheral circuit of the memory, and since the read circuit is generally used to sample, convert and amplify a minute signal on a Bit Line (bit_line) of a memory cell when performing a read operation on the memory cell of the memory, thereby determining the stored information in the memory cell, the operation performance of the read circuit has a decisive influence on the application effect of the memory.
The read circuit operates by comparing the current/voltage on the Bit line of a memory Cell (Bit Cell) of the memory with a reference current/voltage to read the data in the memory Cell. Specifically, one read action process of the read circuit is: comparing the current Icell on the Bit line of the memory Cell (Bit Cell) with the reference current Iref, and if the current Icell on the Bit line of the memory Cell (Bit Cell) is greater than the reference current Iref, determining that the read is 1; on the contrary, the read-out determination is 0.
However, the current Icell on the Bit line of the memory Cell (Bit Cell) generally decreases with increasing temperature, exhibiting negative temperature characteristics. If the temperature characteristic of the reference current Iref is not matched with the characteristic of the bit line current Icell, the window of reading operation at high temperature is reduced, the reading performance of the memory is affected, and the reading reliability of the memory at high temperature is further reduced.
Disclosure of Invention
In view of the foregoing, an object of the present application is to provide a memory reading circuit and a memory, in which a compensation module is added in the reading circuit to compensate a bit line current and/or a reference current according to an increase of temperature, and a correlation between a current difference between the bit line current and the reference current and the temperature is reduced according to the increase of temperature, so as to increase a window of a reading operation at a high temperature, and further improve a reading reliability of the memory at the high temperature.
According to an aspect of the present application, there is provided a read circuit for a memory, including: a first comparator having a first input coupled to the bit line of the memory cell to receive the bit line current and a second input receiving the reference current; and the compensation module is used for compensating the reference current and/or compensating the word line voltage of the memory cell so as to increase the difference value between the bit line current and the reference current along with the rise of temperature.
Optionally, the compensation module includes: a voltage compensation unit for generating an intermediate voltage of positive temperature coefficient according to the reference voltage; the voltage-to-current unit is connected with the voltage compensation unit and is used for generating reference current with a negative temperature coefficient according to the intermediate voltage, wherein the reference current generated by the voltage-to-current unit is the reference current after compensation.
Optionally, the compensation module includes: a voltage compensation unit for generating an intermediate voltage of positive temperature coefficient according to the reference voltage; and the voltage conversion unit is connected with the voltage compensation unit and is used for generating word line voltage with positive temperature coefficient according to the intermediate voltage, wherein the control end of the storage unit receives the word line voltage to generate compensated bit line current.
Optionally, the compensation module includes: a voltage compensation unit for generating an intermediate voltage of positive temperature coefficient according to the reference voltage; the voltage-to-current unit is connected with the voltage compensation unit and is used for generating a reference current with a negative temperature coefficient according to the intermediate voltage; the voltage conversion unit is connected with the voltage compensation unit and is used for generating word line voltage with positive temperature coefficient according to the intermediate voltage, wherein the reference current generated by the voltage-to-current conversion unit is the compensated reference current, and the control end of the storage unit receives the word line voltage to generate the compensated bit line current.
Optionally, the voltage compensation unit includes: the first channel end of the first current source is connected with the power supply voltage; the first channel end of the first transistor is connected with the second channel end of the first current source, and the control end receives a reference voltage; the first channel end of the second transistor is connected with the second channel end of the first current source, and the control end of the second transistor is connected with the second channel end; a third transistor, a first pass terminal of which is connected to the second pass terminal of the first transistor, and a control terminal of which is connected to the first pass terminal; and the first pass end of the fourth transistor is connected with the second pass end of the second transistor, the control end of the fourth transistor is connected with the control end of the third transistor, the second pass end of the fourth transistor is connected with the second pass end of the third transistor, the second pass ends of the third transistor and the fourth transistor are grounded, and the control end of the second transistor is the output end of the voltage compensation unit.
Optionally, the voltage-to-current unit includes: the first channel end of the fifth transistor is connected with the power supply voltage, and the control end of the fifth transistor is connected with the output end of the voltage compensation unit; the first path end of the second current source is connected with the power supply voltage, and the second path end of the second current source is connected with the second path end of the fifth transistor; a first resistor, wherein a first path end of the first resistor is connected with a second path end of the fifth transistor, and the second path end is grounded; and the first input end of the voltage clamp is connected with the fixed voltage, the second input end of the voltage clamp is connected with the output end, and the output end of the voltage clamp is connected with the first path end of the first resistor, wherein the second current source provides the compensated reference current.
Optionally, the current flowing through the first resistor is a fixed value.
Optionally, the voltage conversion unit includes: the first end of the resistor string is grounded, and the second end of the resistor string is connected with the word line end of the memory cell; the first input end of the second comparator is connected with the output end of the voltage compensation unit, and the second input end of the second comparator is connected with the resistor string; the first input end of the logic unit is connected with the clock signal, and the second input end of the logic unit is connected with the output end of the second comparator; and the input end of the charge pump is connected with the output end of the logic unit, and the output end of the charge pump is connected with the second end of the resistor string.
Optionally, the method further comprises: and the reference module is connected with the compensation module and used for providing the reference voltage.
According to another aspect of the present application, there is provided a memory including a driving circuit, a memory circuit, and the above-described reading circuit.
According to the memory reading circuit and the memory, the compensation module is added in the reading circuit to compensate the bit line current and/or the reference current along with the temperature rise, the correlation between the current difference between the bit line current and the reference current and the temperature is reduced, so that the window of reading operation at high temperature is increased, and the reading reliability of the memory at high temperature is further improved.
In one embodiment, the reading circuit of the memory and the memory provided by the application generate an intermediate voltage with a positive temperature coefficient through the voltage compensation unit, and then generate a reference current with a negative temperature coefficient according to the intermediate voltage with the positive temperature coefficient, wherein the reference current decreases along with the increase of temperature and is consistent with the temperature characteristic of the bit line current. Compared with the reference current without temperature coefficient, the reference current with negative temperature coefficient in the application increases with the temperature and the difference between the bit line current, or the reduction of the difference between the reference current with negative temperature coefficient and the bit line current in the application decreases, thereby improving the reading reliability at high temperature.
In another embodiment, the read circuit of the memory and the memory provided by the application generate an intermediate voltage with a positive temperature coefficient through the voltage compensation unit, and then obtain a word line voltage with a positive temperature coefficient according to the intermediate voltage with a positive temperature coefficient and the feedback control distance, and control the bit line current flowing through the memory cell through the word line voltage. Compared with a bit line current with a negative temperature coefficient, the word line voltage with the positive temperature coefficient reduces the reduction amplitude of the difference between the control bit line current and the reference current along with the rise of temperature, so that the reading reliability at high temperature is improved.
In another embodiment, the reference current and the bit line current are compensated at the same time, so that the temperature dependence of the difference between the bit line current and the reference current is further reduced, and the reading reliability at high temperature is further improved.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings, in which:
FIG. 1 shows a schematic diagram of a read circuit for a memory;
FIG. 2 is a graph showing the temperature_magnitude relationship between the bit line current and the reference current when reading data according to an embodiment of the present application;
FIG. 3a shows a schematic diagram of a read circuit according to a first embodiment of the application;
FIG. 3b shows a schematic diagram of the structure of the compensation module in the read circuit according to the first embodiment of the present application;
fig. 3c shows a temperature-magnitude relation of the intermediate voltage according to the first embodiment of the present application;
FIG. 4a shows a schematic diagram of a read circuit according to a second embodiment of the application;
FIG. 4b shows a schematic diagram of the structure of a compensation module in a read circuit according to a second embodiment of the application;
FIG. 5a shows a schematic diagram of a read circuit according to a third embodiment of the application;
fig. 5b shows a schematic diagram of the structure of the compensation module in the read circuit according to the third embodiment of the application.
Detailed Description
Various embodiments of the present application will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
The following describes in further detail the embodiments of the present application with reference to the drawings and examples.
Fig. 1 shows a schematic diagram of a read circuit for a memory.
Specifically, the structure of the reading circuit 100 will be described briefly taking the reading memory cell M1 as an example. The control terminal of the memory cell M1 is connected to the word line WL, the source terminal of the memory cell M1 is connected to the source line SL, and the drain terminal of the memory cell M1 is connected to the bit line BL. One end of the first current source I1 is connected to the power supply VDD, and the other end of the first current source I1 is connected to the drain of the memory cell M1.
Referring to fig. 1, a read circuit 100 includes a reference block 101 and a first comparator 102. The reference module 101 is used to generate a reference voltage Vref and/or a reference current Iref, which may be chosen in particular according to a particular embodiment. The first input terminal of the first comparator 102 is connected to the drain of the memory cell M1, the second input terminal is configured to receive the reference current Iref, and the output terminal of the first comparator 102 is configured to output the data Dout stored in the memory cell M1. In this embodiment, the current source Iref is obtained, for example, after the reference block 101 passes through the mirror circuit.
When the memory cell M1 is read, a read voltage is applied to the control terminal of the memory cell M1 through the word line WL. At this time, the first comparator 102 obtains the bit line current Icell of the memory cell M1 through the first input terminal, obtains the reference current Iref through the second input terminal, and then the first comparator 102 compares the bit line current Icell with the reference current Iref, and if the bit line current Icell is greater than the reference current Iref, the readout decision is 1; on the contrary, the read-out determination is 0.
However, the bit line current Icell obtained by the first comparator 102 through the first input terminal is affected by temperature, that is, the bit line current Icell decreases with an increase in temperature without changing the word line voltage, as shown by the solid line in fig. 2.
In the embodiment shown in fig. 1, the magnitude of the bit line current Icell decreases with the increase of the temperature, but the magnitude of the reference current Iref does not change with the change of the temperature, and the larger the difference between the bit line current Icell and the reference current Iref is, the larger the window of the read operation is, and the higher the reliability is.
Referring to FIG. 2, at a temperature of-40 ℃, the difference between the bit line current Icell and the reference current Iref is △ I1, the difference between the bit line current Icell and the reference current Iref is when the temperature rises to 125 DEG C △ I2 due to △ I2 is less than △ I1, whereby the read operation reliability of the read circuit at high temperature is reduced.
The present application has been made keeping in mind the above problems occurring in the prior art, and an object of the present application is to provide a new reading circuit, which includes a compensation module for compensating a bit line current Icell and/or a reference current Iref to increase a difference between the two at a high temperature. Wherein, referring to the dashed line in FIG. 2, the compensation module can be used to compensate the reference current Iref such that the difference between the bit line current Icell and the reference current Iref at high temperature is △ I2+ △ I4; the bit line current Icell can also be compensated to make the difference between the bit line current Icell and the reference current Iref at high temperature as △ I2+ △ I3; the bit line current Icell and the reference current Iref can be compensated at the same time, so that the difference between the bit line current Icell and the reference current Iref at high temperature is △ I2+ △ I3+ △ I4. Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Referring to fig. 3a, the read circuit 200 according to the first embodiment of the present application has a compensation module 210 based on the existing structure, the compensation module 210 is configured to generate a compensated reference current iref_comp according to the reference voltage Vref, the reference current iref_comp is a negative temperature coefficient current, and decreases with increasing temperature, so that the compensated reference current iref_comp can increase a difference value with the bit line current Icell with increasing temperature compared to the reference current Iref, so as to increase a read operation window at high temperature.
Further, referring to fig. 3b, the compensation module 210 includes a voltage compensation unit 211 and a voltage to current unit 212. The voltage compensation unit 211 is used for generating an intermediate voltage Vref_comp with a positive temperature coefficient according to the reference voltage Vref; the voltage-to-current unit 212 is used for generating a negative temperature coefficient reference current Iref_comp according to the intermediate voltage Vref_comp.
Specifically, the voltage compensation unit 211 includes a first current source I1, a first transistor PM1, a second transistor PM2, a third transistor NM1, and a fourth transistor NM2. The first current source I1 has a first path terminal connected to the power supply voltage VDD, and a second path terminal connected to the first path terminals of the first and second transistors PM1 and PM 2. The control terminal of the first transistor PM1 is connected to the reference voltage Vref, and the control terminal of the second transistor PM2 is connected to the second path terminal. The first pass terminal of the third transistor NM1 is connected to the second pass terminal of the first transistor PM1, and the control terminal is connected to the first pass terminal of the third transistor NM 1. The first pass terminal of the fourth transistor NM2 is connected to the second pass terminal of the second transistor PM2, the control terminal is connected to the control terminal of the third transistor NM1, the second pass terminal is connected to the second pass terminal of the third transistor NM1, and the second pass terminals of the third transistor NM1 and the fourth transistor NM2 are grounded. In this embodiment, the control terminal of the second transistor PM2 outputs the intermediate voltage vref_comp.
The voltage-to-current unit 212 includes a fifth transistor NM3, a second current source I2, a first resistor R1 and a voltage clamp U1. The first pass terminal of the fifth transistor NM3 is connected to the power voltage VDD, and the control terminal is connected to the output terminal of the voltage compensation unit 211. The first path terminal of the second current source I2 is connected to the power supply voltage VDD, and the second path terminal is connected to the second path terminal of the fifth transistor NM3. The first path terminal of the first resistor R1 is connected to the second path terminal of the fifth transistor NM3, and the second path terminal is grounded. The first input end of the voltage clamp U1 is connected with the fixed voltage Vset, the second path end is connected with the third path end, and the third path end is connected with the first path end of the first resistor R1.
In this embodiment, the reference voltage Vref in the voltage compensation unit 211 is the reference voltage Vref output by the reference module 101, and the reference module 101 is, for example, a bandgap reference circuit, so that the temperature coefficient of the reference voltage Vref is small, the intermediate voltage vref_comp generated by the voltage compensation unit 211 is a positive temperature coefficient, and the magnitude of the temperature coefficient can be adjusted by adjusting the dimensions of the first current source I1, the first transistor PM1, the second transistor PM2, the third transistor NM1 and the fourth transistor NM2. The resulting waveform of the temperature_magnitude of the intermediate voltage vref_comp is shown in fig. 3 c.
Further, the control terminal of the fifth transistor NM3 in the voltage-to-current unit 212 is connected to the output terminal of the voltage compensation unit 211, i.e. the intermediate voltage vref_comp controls the on and off of the fifth transistor NM3. Since the intermediate voltage vref_comp is a positive temperature coefficient voltage, the fifth transistor NM3 controlled by the intermediate voltage vref_comp generates a positive temperature coefficient current Inm3. In addition, the current Ir flowing through the first resistor R1 in the voltage-to-current unit 212 is an accurate current value, and the magnitude of the current Ir is related to the fixed voltage Vset at the first input terminal of the voltage clamp U1 and the magnitude of the first resistor R1, and the calculated formula is ir=vset++r1.
Further, according to the circuit structure of the voltage-to-current unit 212, the current relationship between the current Inm flowing through the fifth transistor NM3 and the current iref_comp flowing through the second current source I2 is the current Ir flowing through the first resistor R1, so as to obtain the current iref_comp=ir_ Inm3 of the second current source I2. In this embodiment, since the current Inm3 flowing through the fifth transistor NM3 is a positive temperature coefficient current, the current iref_comp flowing through the second current source I2 is a negative temperature coefficient current.
In this embodiment, using the negative temperature coefficient current Iref_comp as the reference current Iref_comp for comparison in the read circuit, referring to FIG. 2, the read operation window at high temperature can be increased, such that the read operation window is increased △ I4, thereby increasing read reliability at high temperatures.
In the embodiment shown in fig. 3a, the current of the current source located between the memory cell M1 and the supply voltage is, for example, the reference current iref_comp mirrored by the mirror circuit.
Further, fig. 4a shows a schematic diagram of a structure of a reading circuit according to a second embodiment of the present application. In comparison with the first embodiment, the read circuit of the second embodiment compensates the word line voltage Vwl of the memory cell M1, and compensates the bit line current by compensating the word line voltage Vwl.
Fig. 4b shows a schematic structural diagram of the compensation module of the second embodiment. Referring to fig. 4b, the compensation module 210 includes a voltage compensation unit 211 and a voltage conversion unit 213. The voltage compensation unit 211 is used for generating an intermediate voltage Vref_comp with a temperature coefficient according to the reference voltage Vref; the voltage conversion unit 213 is used for generating a word line voltage VWL with a positive temperature coefficient according to the intermediate voltage vref_comp. In this embodiment, the structure of the voltage compensation unit 211 is the same as that of the first embodiment, and will not be described here again.
The voltage conversion unit 213 includes a resistor string, a second comparator U2, a logic unit U3, and a charge pump CP. The resistor string includes a plurality of resistors connected in series, for example, a second resistor R2 to an nth resistor Rn, and one end of the resistor string is grounded, and the other end is connected to the control end of the memory cell M1. The first input of the second comparator U2 is connected to the output of the voltage compensation unit 211 and the second input is connected to the resistor string, and in the embodiment shown in fig. 4b the second input of the second comparator U2 is connected to a node between a fourth resistor R4 and a fifth resistor R5 in the resistor string, for example.
In one embodiment, the worker skilled in the art can make corresponding adjustments according to the technical scheme to connect the second input of the second comparator U2 to the node between any two resistors in the resistor string.
Further, the first input terminal of the logic unit U3 is connected to the clock signal, and the second input terminal is connected to the output terminal of the second comparator U2. In this embodiment, the logic unit U3 is, for example, a nand gate.
Further, the input terminal of the charge pump CP is connected to the output terminal of the logic unit U3, and the output terminal is connected to the word line of the memory unit M1.
In this embodiment, the intermediate voltage Vref_comp of positive temperature coefficient generated by the voltage compensation unit 211 is applied to the input terminal of the second comparator U2 controlling the voltage generated by the charge pump CP by feedbackThe control principle results in the voltage output by the charge pump CP being vwl=m×vref_comp, where M is the resistance scaling factor. In this embodiment, since the intermediate voltage vref_comp is a positive temperature coefficient, the voltage VWL generated by the charge pump CP is also a positive temperature coefficient. Applying the voltage VWL with positive temperature coefficient to the control terminal of the memory cell M1 compensates the current of the memory cell M1 at high temperature, thereby compensating the word line current Icell_comp of the memory cell M1 at high temperature, so that the read operation window at high temperature is increased △ And I3, the reliability of the reading operation is improved.
Further, fig. 5a shows a schematic diagram of a structure of a reading circuit according to a third embodiment of the present application, and fig. 5b shows a schematic diagram of a compensation module according to a third embodiment of the present application. The third embodiment is a combination of the first embodiment and the second embodiment, compared with the first embodiment and the second embodiment.
Referring to fig. 5b, the compensation module 210 of the third embodiment includes a voltage compensation unit 211, a voltage-to-current unit 212, and a voltage conversion unit 213. That is, in the third embodiment, the reference current Iref and the bit line current Icell are compensated at the same time, thereby increasing the read operation window at high temperature.
The structures of the voltage compensation unit 211, the voltage-to-current unit 212 and the voltage conversion unit 213 in the compensation module 210 of the third embodiment are the same as those of the first embodiment and the second embodiment, and will not be described in detail herein.
According to the memory reading circuit and the memory, the compensation module is added in the reading circuit to compensate the bit line current and/or the reference current along with the temperature rise, so that the correlation between the current difference between the bit line current and the reference current and the temperature is reduced, the window of reading operation at high temperature is increased, and the reading reliability of the memory at high temperature is further improved.
In one embodiment, the reading circuit of the memory and the memory provided by the application generate an intermediate voltage with a positive temperature coefficient through the voltage compensation unit, and then generate a reference current with a negative temperature coefficient according to the intermediate voltage with the positive temperature coefficient, wherein the reference current decreases along with the increase of temperature and is consistent with the temperature characteristic of the bit line current. Compared with the reference current without temperature coefficient, the application has the advantages that the correlation between the difference value between the reference current with negative temperature coefficient and the bit line current and the temperature is improved, thereby improving the reading reliability at high temperature.
In another embodiment, the read circuit of the memory and the memory provided by the application generate an intermediate voltage with a positive temperature coefficient through the voltage compensation unit, and then obtain a word line voltage with a positive temperature coefficient according to the intermediate voltage with a positive temperature coefficient and the feedback control distance, and control the bit line current flowing through the memory cell through the word line voltage. Compared with a bit line current with a negative temperature coefficient, the word line voltage with the positive temperature coefficient in the application controls the correlation between the difference value between the bit line current and the reference current and the temperature to be reduced along with the rise of the temperature, thereby improving the reading reliability at high temperature.
In another embodiment, the reference current and the bit line current are compensated at the same time, so that the correlation between the difference value between the bit line current and the reference current and the temperature is further reduced, and the reading reliability at high temperature is further improved.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.

Claims (10)

1. A read circuit for a memory, wherein the read circuit comprises:
a first comparator having a first input coupled to the bit line of the memory cell to receive the bit line current and a second input receiving the reference current;
and the compensation module is used for compensating the reference current and/or compensating the word line voltage of the memory cell, so that the correlation between the difference value of the bit line current and the reference current and the temperature is reduced.
2. The read circuit of claim 1, wherein the compensation module comprises:
a voltage compensation unit for generating an intermediate voltage of positive temperature coefficient according to the reference voltage;
a voltage-to-current unit connected with the voltage compensation unit for generating a reference current with a negative temperature coefficient according to the intermediate voltage,
the reference current generated by the voltage-to-current unit is the compensated reference current.
3. The read circuit of claim 1, wherein the compensation module comprises:
a voltage compensation unit for generating an intermediate voltage of positive temperature coefficient according to the reference voltage;
a voltage conversion unit connected with the voltage compensation unit for generating word line voltage with positive temperature coefficient according to the intermediate voltage,
the control end of the memory cell receives the word line voltage to generate a compensated bit line current.
4. The read circuit of claim 1, wherein the compensation module comprises:
a voltage compensation unit for generating an intermediate voltage of positive temperature coefficient according to the reference voltage;
the voltage-to-current unit is connected with the voltage compensation unit and is used for generating a reference current with a negative temperature coefficient according to the intermediate voltage;
a voltage conversion unit connected with the voltage compensation unit for generating word line voltage with positive temperature coefficient according to the intermediate voltage,
wherein the reference current generated by the voltage-to-current unit is the compensated reference current,
the control terminal of the memory cell receives the word line voltage to generate a compensated bit line current.
5. The read circuit of any of claims 2-4, wherein the voltage compensation unit comprises:
the first channel end of the first current source is connected with the power supply voltage;
the first channel end of the first transistor is connected with the second channel end of the first current source, and the control end receives a reference voltage;
the first channel end of the second transistor is connected with the second channel end of the first current source, and the control end of the second transistor is connected with the second channel end;
a third transistor, a first pass terminal of which is connected to the second pass terminal of the first transistor, and a control terminal of which is connected to the first pass terminal;
a fourth transistor, a first pass terminal of the fourth transistor being coupled to a second pass terminal of the second transistor, a control terminal being coupled to a control terminal of the third transistor, the second pass terminal being coupled to a second pass terminal of the third transistor,
and the second paths of the third transistor and the fourth transistor are grounded, and the control end of the second transistor is the output end of the voltage compensation unit.
6. The reading circuit according to claim 2 or 4, wherein the voltage-to-current unit includes:
the first channel end of the fifth transistor is connected with the power supply voltage, and the control end of the fifth transistor is connected with the output end of the voltage compensation unit;
the first path end of the second current source is connected with the power supply voltage, and the second path end of the second current source is connected with the second path end of the fifth transistor;
a first resistor, wherein a first path end of the first resistor is connected with a second path end of the fifth transistor, and the second path end is grounded;
the first input end of the voltage clamp is connected with the fixed voltage, the second input end of the voltage clamp is connected with the output end, the output end of the voltage clamp is connected with the first path end of the first resistor,
wherein the second current source provides a compensated reference current.
7. The read circuit of claim 6, wherein the current flowing through the first resistor is a fixed value.
8. The reading circuit according to claim 3 or 4, wherein the voltage converting unit includes:
the first end of the resistor string is grounded, and the second end of the resistor string is connected with the word line end of the memory cell;
the first input end of the second comparator is connected with the output end of the voltage compensation unit, and the second input end of the second comparator is connected with the resistor string;
the first input end of the logic unit is connected with the clock signal, and the second input end of the logic unit is connected with the output end of the second comparator;
and the input end of the charge pump is connected with the output end of the logic unit, and the output end of the charge pump is connected with the second end of the resistor string.
9. The read circuit of any of claims 2-4, further comprising:
and the reference module is connected with the compensation module and used for providing the reference voltage.
10. A memory comprising a drive circuit, a memory circuit and a read circuit as claimed in any one of claims 1 to 9.
CN202310917497.2A 2023-07-25 2023-07-25 Reading circuit for memory and memory Pending CN117012253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310917497.2A CN117012253A (en) 2023-07-25 2023-07-25 Reading circuit for memory and memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310917497.2A CN117012253A (en) 2023-07-25 2023-07-25 Reading circuit for memory and memory

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