CN117010306A - Method for optimizing memory in RTL logic synthesis - Google Patents

Abstract

The invention discloses a method for optimizing a memory in RTL logic synthesis, which comprises the following steps: step 1, defining a memory to be optimized based on a port signal of the memory; step 2, traversing the memory instance in the circuit design, and searching the memory instance consistent with the port signal of the defined memory; and 3, analyzing the state of initial data and/or a write enable signal of each storage unit of each found storage instance, deleting the invalid port corresponding to the storage instance or setting the corresponding data bit as X according to the analysis result. The invention can optimize the structural redundancy of the specific memory and can improve the logic synthesis speed.

Description

Method for optimizing memory in RTL logic synthesis

Technical Field

The invention relates to the technical field of logic synthesis of RTL (real time digital) level circuits, in particular to a method for optimizing structural redundancy of a storage unit in a circuit in a logic synthesis stage.

Background

In integrated circuit design, the hierarchy of the design can be divided from top to bottom into a design idea (idea), a Behavior level description (behavir level), a register-transfer level, a gate level netlist, and a physical layout. (RTL) is an abstraction level used to describe the operation of synchronous digital circuits.

At the RTL level, an IC chip is made up of a set of registers and logical operations between registers. The difference between the RTL level and gate level netlists is: the RTL level is the function which is ideally achieved by using a hardware description language (Verilog or VHDL), the gate level netlist is the function which is achieved by using specific logic units (depending on libraries of manufacturers), the RTL level and the gate level netlist are different stages in design and implementation, and the gate level netlist can be obtained after logic synthesis of the circuit design of the RTL level.

While memory is an important component of the circuit, it takes on the role of data information storage. There are various types of memories, and the difference in their structures reflects the complexity thereof. When RTL logic is integrated, if optimization is not considered on a memory, the obtained gate-level netlist has redundancy on a memory structure, and is not beneficial to circuit design.

How to provide a method for optimizing a memory in RTL logic synthesis is a technical problem to be solved.

Disclosure of Invention

In order to solve the technical problem that the optimization of the memory is not considered in the prior art, the invention provides a memory optimization method in RTL logic synthesis.

The invention provides a method for optimizing a memory in RTL logic synthesis, which comprises the following steps:

step 1, defining a memory to be optimized based on a port signal of the memory;

step 2, traversing the memory instance in the circuit design, and searching the memory instance consistent with the port signal of the defined memory;

and 3, analyzing the state of initial data and/or a write enable signal of each storage unit of each found storage instance, deleting the invalid port corresponding to the storage instance or setting the corresponding data bit as X according to the analysis result.

Further, the step 1 includes: the memory to be optimized is defined as a dual port memory without a reset signal based on a read clock signal, a read enable signal, a read address signal, a read data signal, a write clock signal, a write enable signal, a write address signal, and a write data signal of the memory.

Further, the step 1 includes: the memory to be optimized is defined as a dual port memory with a reset signal based on a read clock signal, a read enable signal, a read address signal, a read data signal, a write clock signal, a write enable signal, a write address signal, a write data signal, a read asynchronous reset signal, a read synchronous reset signal of the memory.

Further, the step 3 includes: and deleting the ports corresponding to the write clock signal, the write enable signal, the write address signal and the write data signal of the current storage unit if the current storage unit meets that all write enable bits of the current storage unit are write-forbidden when the state of the write enable signal of each storage unit of each found storage example is the state of the write enable signal.

Further, the step 3 includes: and aiming at the state of the write enable signal of each storage unit of each found storage example, if the current storage unit meets the condition that part of write enable bits of the current storage unit are forbidden to be written, the data position corresponding to the write enable bits is X.

Further, the step 3 includes: and deleting the constant data channel for each storage unit of each found memory instance if the current initial data is constant.

Further, if all data bits of the current memory location or memory instance are constant, then the memory location or memory instance is deleted.

Further, if all data bits of the current memory cell or memory instance are not all constant, then after the corresponding constant data channel is deleted, the remaining data bits are bit-width reorganized.

The invention optimizes the actual use condition of the memory in the circuit design according to different redundancy conditions, so that the redundant structure (such as that all write port information is not effective caused by Wr_en all 0, new data cannot be written due to constant initial data) existing in the memory is deleted, the structure of the memory is simplified to the maximum extent, and the speed of the comprehensive stage is accelerated.

Drawings

The invention is described in detail below with reference to examples and figures, wherein:

FIG. 1 is a flow chart of an embodiment of the present invention;

FIG. 2 is a schematic diagram of a memory cell structure of the present invention;

FIG. 3 is a schematic diagram of a first memory cell of the present invention;

FIG. 4 is a schematic diagram of a read-write structure of a first memory cell according to the present invention;

FIG. 5 is a schematic diagram of an optimized structure when the write enable of the first memory cell of the present invention is all zero;

FIG. 6 is a schematic diagram of an optimized structure with write enable not all zeros for the first memory cell of the present invention.

FIG. 7 is an optimized view of the first memory cell of the present invention with constant initial data;

FIG. 8 is a schematic diagram of the optimization of the initial data of the first memory cell of the present invention, which is not always constant.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Thus, reference throughout this specification to one feature will be used in order to describe one embodiment of the invention, not to imply that each embodiment of the invention must be in the proper motion. Furthermore, it should be noted that the present specification describes a number of features. Although certain features may be combined together to illustrate a possible system design, such features may be used in other combinations not explicitly described. Thus, unless otherwise indicated, the illustrated combinations are not intended to be limiting.

The invention relates to a method for optimizing a memory in RTL logic synthesis, which mainly comprises the following steps.

Step 1, defining a memory to be optimized based on a port signal of the memory.

And step 2, traversing the memories in the circuit design, and searching the memories consistent with the port signals of the defined memories.

And 3, analyzing the state of initial data and/or a write enable signal of each storage unit of each found storage, deleting an invalid storage instance or deleting an invalid port corresponding to the storage instance or setting a corresponding data bit as X according to the analysis result.

In the practical use process of the memory, the invention deletes the signal port which does not work, the invalid memory instance, the data channel corresponding to the data bit which cannot be written with new data, and the like, thereby simplifying the structure of the memory to the maximum extent and accelerating the speed of the comprehensive stage.

In one embodiment, defining the memory to be optimized based on the port signal of the memory in the above technical solution includes: the memory to be optimized is defined as a dual port memory without a reset signal based on a read clock signal, a read enable signal, a read address signal, a read data signal, a write clock signal, a write enable signal, a write address signal, and a write data signal of the memory.

In another embodiment, defining the memory to be optimized based on the port signal of the memory in the above technical solution includes: the memory to be optimized is defined as a dual port memory with a reset signal based on a read clock signal, a read enable signal, a read address signal, a read data signal, a write clock signal, a write enable signal, a write address signal, a write data signal, a read asynchronous reset signal, a read synchronous reset signal of the memory.

In a further embodiment, the memories of the two embodiments may be optimized at the same time, and the optimization manner may be universal, but when traversing the two types of memories (memories), since there may be a plurality of memories (memories) in the circuit design, in order to distinguish the memories, the present invention sets the port information of the two types of memories first, then traverses according to the set type in the circuit design, and the memories conforming to the set are collected.

In one embodiment, the above step 3 specifically includes the following.

When the state of the write enable signal of each memory cell of each found memory is the state, if the current memory cell satisfies that all write enable bits of the current memory cell are write-forbidden, the write clock signal, the write enable signal, the write address signal and the write data signal of the current memory cell are deleted. This is because when all write enable bits of a memory cell are write disabled, the ports to which they are written are essentially all inactive ports, and thus all of these ports can be deleted.

In another embodiment, the above step 3 specifically includes the following.

For the state of the write enable signal of each memory cell of each found memory, if the current memory cell satisfies that part of the write enable bits are write-prohibited, the data position corresponding to the write enable bits are X.

When a Write Enable bit is a disable Write, the corresponding Write data is typically set to an indeterminate state (e.g., X). This is to ensure that any existing data is not accidentally written to the memory location in the event that the write enable is write-disabled.

In another embodiment, the above step 3 specifically includes the following.

And deleting the constant data channel if the current initialization data bit is constant for each memory cell of each found memory.

In a further embodiment, a current memory location or memory instance is deleted if all data bits of the memory location or memory instance are constant. If all data bits of the current memory cell or memory instance are not all constant, then after the corresponding constant data channel is deleted, the remaining data bits are bit-width reorganized.

A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 1, the memory type to be optimized is defined first. In this embodiment, two memories are optimized, one dual-port memory without reset signal and one dual-port memory with reset signal.

For example, the dual port memory mem1 without a reset signal may be defined as follows:

module mem1(Rd_clk,Rd_en,Rd_addr,Rd_data,Wr_clk,Wr_en,Wr_addr,Wr_data)；

……；

Endmodule；

rd_clk and Wr_clk are respectively a read clock signal and a write clock signal; rd_en and Wr_en are read enable signals and write enable signals respectively; rd_addr and Wr_addr are respectively a read address signal and a write address signal; rd_data and Wr_data are respectively read data signals and write data signals.

For example, the dual-port memory men2 with reset signal can be defined as follows:

module mem2(Rd_clk,Rd_en,Rd_addr,Rd_data,Rd_arst,Rd_srst,Wr_clk,Wr_en,Wr_addr,Wr_data)；

……；

Endmodule；

the definition of the remaining port signals is identical to that of the dual port memory without the reset signal except for rd_arst (read asynchronous reset signal asynchronous reset) and rd_srst (read synchronous reset signal synchronous reset).

The same memory type as defined in the circuit design is then looked up.

The memory (memory) in each module is traversed by reading in the circuit design (design).

All memory is collected.

All memories of the same type as defined present in the circuit design are collected. The sources of memory are mainly created memory units, and memory instantiated in the top layer or sub-module, i.e. created memory units and memory instances.

The memory type that needs to be optimized is selected and if the specified memory type exists, the following operations are performed.

Here, for convenience of explanation, we designate the type of memory mem to be optimized as a memory without a reset signal, i.e., the first type, and the given port signal information is as follows:

module mem(Rd_clk,Rd_en,Rd_addr,Rd_data,Wr_clk,Wr_en,Wr_addr,Wr_data)；

input Rd_clk,Wr_clk；

input [1:0] Rd_en (read enable signal is 2 bit input signal);

input [3:0] Rd_addr (read address signal is 4-bit input signal);

output [7:0] Rd_data (reading data signal is 8 as output signal);

input [7:0] Wr_en (write enable signal is 8-bit input signal);

input [3:0] Wr_addr (write address signal is 4-bit input signal);

input [7:0] Wr_data (write data signal is 8 as input signal);

reg [7:0] mem [15:0] (8 bits wide and 16 bits deep of memory);

……；

Endmodule；

the general structure of the memory mem with the width of 8 bits and the depth of 16 bits is shown in fig. 2, wherein the memory array is divided into memory cells according to addresses, that is, each memory cell is one memory cell, and each memory cell can store one byte, that is, 8 bits of data.

FIG. 3 shows the structure of the first memory cell (mem [0] [7:0 ]), and the read/write structure is shown in FIG. 4. The following operations are all described with reference to fig. 4.

There are four cases in the lookup memory that need to be optimized, and there are four cases in total in this embodiment.

First case: the write enable bit is all zeros.

Traversing the write port related information, if the write enable wr_en bits are all zero, i.e., wr_en=8' b0000_0000, this means that there is no valid data write, each write enable bit controls a corresponding write data bit, so the related information (wr_en, wr_clk, wr_addr, wr_data) of the write port (wr_port) is all deleted. Meaning that when the write enable is inactive then the other write related signals are also inactive.

The deleted structure is substantially as shown in fig. 5, and only the read port (rd_port) related information is left.

Second case: the write enable bit is not all zero.

When the write enable Wr_en bit is not all 0's, the enable bit that is not 0's and the corresponding write data bit are traversed, for convenience of explanation, described as whether Wr_en [0] is 0.

When Wr_en [0] +|! When=0, if the corresponding write data bit (wr_data [0] |=1 'bx) & (wr_data [0] |=1' b0), the address unit data bit mem [0] [0] is not 0, i.e. is 1; if the corresponding write data bit (wr_data [0] |=1 'bx) & (wr_data [0] |=1' b1), then the address cell data bit mem [0] [0] is not 1, i.e., 0.

When wr_en [0] =0, no valid data is written at this time, so that there is no state of the data bit (i.e., no state of 0,1 or X), and the corresponding data position is X, i.e., an unstable state, wr_data [0] =1' bx. The suspension end of the data selector in fig. 4 is provided with an X indefinite state signal, so that the read-write structure is changed to the form as in fig. 6 in consideration of the case that the write enable bit is 0.

An indefinite signal to the suspension, rather than having its write data directly floating, i.e., not connected to a certain logic level (e.g., logic high or logic low), may cause the following problems:

(1) Write data interference: unconnected signal lines may be subject to electromagnetic interference or other signals, resulting in unstable jitter of signal values between high and low levels. Such an unstable state may cause errors in writing data, making the data in the memory unreliable.

(2) Memory bit flip: unconnected signal lines may flip when there is a disturbance, resulting in erroneous data writing. This can cause the data in memory to become unpredictable, potentially affecting the correctness and stability of the system.

Therefore, the invention can solve the two problems by giving an unstable state signal to the suspension end.

Third case: there is a constant for the initialization data bits.

At the time of initialization, it corresponds to the case where wr_en=0, that is, as shown in fig. 5.

When the initial value of a certain bit of the address unit data bit is constant, namely constant is 0,1 or X state, the constant data channel can be deleted. For example: if mem [0] [0] =1 ' b1, mem [0] [1] =1 ' b0, mem [0] [2] =1 ' bx, then the constant data channel is deleted, as shown in fig. 7. At this time, mem [0] [0] and the corresponding read data bits Rd_data [0] are constant at 1' b1, mem [0] [1] and Rd_data [1] are constant at 1' b0, and mem [0] [2] and Rd_data [2] are constant at 1' bX.

Fourth case: the initialization data bits are all or not all constant.

When the initialization data is all constant, meaning that new data cannot be written but only once, the storage function of the memory is not realized. At this point, the entire memory is deleted from the module (module). Note that the invalid memory instantiated in the module is deleted, not the created memory unit.

When the initialization data is not all constant, the data bits which are constant are processed according to the third condition, the bits which are not constant are reserved, and the bit width of the bits which are not constant are recombined.

For example, in the specific example of FIG. 7, the non-constant bits are left as [7:3], which are reorganized as [4:0]. At this time, the relevant port signal bit widths are redefined as well, such as wr_data, wr_en, rd_data, etc. The structure after recombination is shown in FIG. 8.

In the preferred embodiment, the invention optimizes various redundant structures of the memory, simplifies the structure of the memory to the maximum extent and accelerates the speed of the comprehensive stage.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (8)

1. A method for optimizing memory in RTL logic synthesis, comprising:

step 1, defining a memory to be optimized based on a port signal of the memory;

step 2, traversing the memory instance in the circuit design, and searching the memory instance consistent with the port signal of the defined memory;

and 3, analyzing the state of initial data and/or a write enable signal of each storage unit of each found storage instance, deleting the invalid port corresponding to the storage instance or setting the corresponding data bit as X according to the analysis result.

2. The method for optimizing memory in RTL logic synthesis according to claim 1, wherein step 1 comprises: the memory to be optimized is defined as a dual port memory without a reset signal based on a read clock signal, a read enable signal, a read address signal, a read data signal, a write clock signal, a write enable signal, a write address signal, and a write data signal of the memory.

3. The method for optimizing memory in RTL logic synthesis according to claim 1, wherein step 1 comprises: the memory to be optimized is defined as a dual port memory with a reset signal based on a read clock signal, a read enable signal, a read address signal, a read data signal, a write clock signal, a write enable signal, a write address signal, a write data signal, a read asynchronous reset signal, a read synchronous reset signal of the memory.

4. The method for optimizing memory in RTL logic synthesis according to claim 1, wherein the step 3 includes: and deleting the ports corresponding to the write clock signal, the write enable signal, the write address signal and the write data signal of the current storage unit if the current storage unit meets that all write enable bits of the current storage unit are write-forbidden when the state of the write enable signal of each storage unit of each found storage example is the state of the write enable signal.

5. The method for optimizing memory in RTL logic synthesis according to claim 1, wherein the step 3 includes: and aiming at the state of the write enable signal of each storage unit of each found storage example, if the current storage unit meets the condition that part of write enable bits of the current storage unit are forbidden to be written, the data position corresponding to the write enable bits is X.

6. The method for optimizing memory in RTL logic synthesis according to claim 1, wherein the step 3 includes: and deleting the constant data channel for each storage unit of each found memory instance if the current initial data is constant.

7. The method of claim 6, wherein a current memory location or instance is deleted if all data bits of the memory location or instance are constant.

8. The method of claim 6, wherein if all data bits of the current memory location or memory instance are not all constant, then performing bit width reorganization on the remaining data bits after the corresponding constant data channel is deleted.