CN117008873A - Probability bit unit circuit, probability bit circuit system and control method thereof - Google Patents
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Abstract
The application provides a probability bit unit circuit, a probability bit circuit system and a control method thereof, which are used for realizing mutual cascading of probability bit unit circuits, thereby improving the calculation parallelism and reducing the iteration time delay and the power consumption. The application provides a probability bit unit circuit, which specifically comprises at least two first transistors, a probability bit device and an output device; the gates of the at least two first transistors are input ends of the probability bit unit circuit, and analog signals are input to the input ends; one ends of the source drains of the at least two first transistors are connected with the bottom end of the probability bit device and the input end of the output device, the other ends of the source drains of the at least two first transistors are grounded, and the output end of the output device outputs a digital signal.
Description
Technical Field
The present application relates to the field of probability computation, and in particular, to a probability bit unit circuit, a probability bit circuit system, and a control method thereof.
Background
The combination optimization problem is increasingly converted into the I Xin Moxing, and the I Xin Moxing is subjected to annealing operation to obtain the minimum energy state or the approximate minimum energy state of the Ictan, so that the optimal solution or the approximate optimal solution of the combination optimization problem is obtained. Such as the noise averaging field i Xin Tuihuo algorithm. The t Xin Moxing and combinatorial optimization class problem can now be solved with a special probability computer, which can be implemented by probability bit circuitry. Wherein, probability bit refers to a bit that continuously jumps between 0 and 1 states over time, wherein the probability of 0 and 1 occurrence can be regulated by the input signal. The main implementation basis of the probability bit circuit is probability bit devices, such as random magnetic tunnel junctions, resistive random access memory devices, superconducting devices and the like. The random magnetic tunnel junction is a magnetic tunnel junction with a low energy barrier, and the state of the random magnetic tunnel junction continuously jumps between a low resistance state and a high resistance state with time under the excitation of thermal disturbance or current and voltage, so that the random magnetic tunnel junction can be used for constructing a probability bit device. Random magnetic tunnel junction based probability bit devices can regulate the probability of occurrence of low and high resistance states by varying the magnitude of the current, voltage, and the like applied to the magnetic tunnel junction.
The structure of the current probability bit cell circuit may be as shown in fig. 1a, which includes 1 transistor, 1 random magnetic tunnel junction, 1 comparator, 1 resistor. The connection of the probability bit circuitry based on this probability bit cell circuit is shown in fig. 1b, i.e. each probability bit cell circuit is connected to a digital-to-analog converter (Digital to Analog Converter, DAC) and a microcontroller (micro controller). In the probability bit circuit system, the output of each probability bit unit circuit is sent to a microcontroller to carry out multiply-accumulate operation on weights corresponding to the problem to be solved, and then the result is fed back to the input end of the probability bit unit circuit to carry out iterative refreshing.
In the scheme, a plurality of probability bit unit circuits are respectively connected with the DAC and the microcontroller, so that each calculation result is calculated independently when calculation is performed, and the calculation parallelism is poor, the iteration is prolonged, and the power consumption is high.
Disclosure of Invention
The application provides a probability bit unit circuit, a probability bit circuit system and a control method thereof, which are used for realizing mutual cascading of probability bit unit circuits, thereby improving the calculation parallelism and reducing the iteration time delay and the power consumption.
In a first aspect, the present application provides a probability bit cell circuit, which specifically includes at least two first transistors, a probability bit device, and an output device; the gates of the at least two first transistors are input ends of the probability bit unit circuit, and analog signals are input to the input ends; one ends of the source drains of the at least two first transistors are connected with the bottom end of the probability bit device and the input end of the output device, the other ends of the source drains of the at least two first transistors are grounded, and the output end of the output device outputs a digital signal.
It can be understood that the other ends of the source and drain electrodes of the at least two first transistors may be grounded after being connected to the resistor, that is, only the other ends of the source and drain electrodes of the at least two first transistors are grounded, and the specific connection method is not described herein.
In the technical scheme provided by the application, the plurality of first transistors in the probability bit unit circuit are used as the input ends of the probability bit unit circuit, so that the probability bit unit circuit comprises a plurality of input ends, and the probability bit unit circuits are mutually cascaded, so that the calculation parallelism is improved, and the iteration time delay and the power consumption are reduced.
Optionally, the probability bit unit circuit further comprises a control module, wherein the control module is connected with the bottom end of the probability bit device and is used for changing the bias current or the bias voltage applied to the probability bit device. This allows for a higher scalability of the probability bit cell circuit.
Optionally, the control module is a second transistor, one end of a source drain electrode of the second transistor is connected with the bottom end of the probability bit device, and the other end of the source drain electrode of the second transistor is grounded;
or, the control module comprises two third transistors, one ends of source and drain electrodes of the two third transistors are connected, the other ends of the source and drain electrodes of the two third transistors are respectively connected with the bottom of the probability bit device and grounded, and the gate electrodes of the two third transistors are used as input ends of the control module;
or, the control module is a current source, one end of the current source is connected with the bottom end of the probability bit device, and the other end of the current source is grounded. Thus, the implementation mode of the control module in the probability bit unit circuit is diversified, and the implementation cost of the control module is reduced.
Optionally, the probability bit unit circuit further includes a hysteresis module, where the hysteresis module is connected to the bottom end of the probability bit device, or is located between one of the source and drain electrodes of the at least two first transistors and the bottom end of the probability bit device, and is used to slow down a change of a current or a voltage acting on the probability bit device. Therefore, the system formed by the probability bit unit circuit operates more stably, and the steady state or the minimum state of the isooctyl energy of the target problem of the circuit system is more easily achieved.
Optionally, the hysteresis module includes a capacitor and a fourth transistor, where one end of the capacitor and a gate of the fourth transistor are connected to one ends of source and drain electrodes of the at least two first transistors, another end of the capacitor is connected to a power supply voltage, one end of the source and drain electrode of the fourth transistor is connected to a bottom end of the probability bit device, and another end of the source and drain electrode of the fourth transistor is grounded;
or,
the hysteresis module comprises a capacitor and a fifth transistor, wherein one end of the capacitor and a grid electrode of the fifth transistor are connected with one ends of source and drain electrodes of the at least two first transistors, the other end of the capacitor is connected with the bottom end of the probability bit device, one end of a source and drain electrode of the fourth transistor is connected with the bottom end of the probability bit device, and the other end of the source and drain electrode of the fourth transistor is grounded;
Or,
the hysteresis module comprises a capacitor, one end of the capacitor is connected with one ends of the source and drain electrodes of the at least two first transistors, and the other end of the capacitor is connected with a power supply voltage.
Optionally, the probability bit device is a random magnetic tunnel junction, a resistive memory device, or a superconducting device.
Optionally, the output device is an inverter, a comparator or an operational amplifier.
In a second aspect, the present application provides a probability bit circuitry comprising N probability bit cell circuits as described in the first aspect above, N being an integer greater than 1; the N probability bit unit circuits are connected in cascade through M connecting circuits to generate a probability bit circuit system, wherein M is an integer greater than or equal to N; the connection circuit is used for realizing the transformation from the output signal of the former probability bit unit circuit to the input signal of the latter probability bit unit circuit.
Optionally, the connection circuit has a control terminal for implementing a transformation of the output signal of the previous probability bit unit circuit to the input signal of the subsequent probability bit unit circuit.
In the technical scheme provided by the application, the plurality of first transistors in the probability bit unit circuit are used as the input ends of the probability bit unit circuit, so that the probability bit unit circuit comprises a plurality of input ends, and the mutual cascade between the probability bit unit circuits is realized, so that the calculation parallelism is improved, and the iteration time delay and the power consumption are reduced.
Optionally, the cascade generation of the probability bit unit circuits by the M connection circuits includes: the probability bit units in the N probability bit unit circuits are connected in pairs through the M connection circuits, M is equal to N (N-1), and each probability bit unit circuit in the N probability bit unit circuits comprises N-1 first transistors. The probability bit unit circuits are mutually connected in pairs during cascading, so that full connection is realized, and the universality of solving the problem and the speed of calculating the problem are increased.
Optionally, the probability bit circuitry is configured to periodically expand in a set of vertical or horizontal directions with the N probability bit cell circuits. That is, the probability bit circuitry may include a structure of a set of probability bit cell circuits for periodic expansion, thereby expanding the scale of the probability bit circuitry, which increases the scale and breadth of solving the problem.
Optionally, in the present application, the probability bit circuitry may be extended as follows: the probability bit circuit system comprises X probability bit circuit modules comprising N probability bit unit circuits, the N probability bit unit circuits in the probability bit circuit modules are connected in pairs, the X probability bit circuit modules are connected through the probability bit unit circuits, and X is a positive integer greater than 1. Assuming, for example, that the probability bit circuitry comprises 2 probability bit circuit blocks (a first probability bit circuit block and a second probability bit circuit block), each probability bit circuit block comprising 8 probability bit cell circuits, the connection between the respective probability bit circuit blocks may be as follows:
In one possible implementation manner, four probability bit unit circuits in the first probability bit circuit module are connected with four probability bit unit circuits in the second probability bit circuit module one by one, and meanwhile, the remaining four probability bit unit circuits of the first probability bit circuit module are connected with the remaining four probability bit unit circuits in the second probability bit circuit module one by one.
In another possible implementation, one probability bit cell circuit in the first probability bit circuit module is connected to 8 probability bit cell circuits in the second probability bit circuit module.
In another possible implementation, one probability bit unit circuit in the first probability bit circuit module is connected to 4 probability bit unit circuits in the second probability bit circuit module, and another probability bit unit circuit in the first probability bit circuit module is connected to the remaining 4 probability bit unit circuits in the second probability bit circuit module.
It is understood that the connection manner between the first probability bit circuit module and the second probability bit circuit module is not limited as long as the connection between the first probability bit circuit module and the second probability bit circuit module can be realized. Optionally, the connection circuit includes at least two sixth transistors, gates of the at least two sixth transistors are connected in parallel and then connected to an output end of one probability bit unit circuit of the N probability bit unit circuits, one ends of source and drain electrodes of the at least two sixth transistors are connected to an input end of another probability bit unit circuit of the N probability bit unit circuits, and another ends of source and drain electrodes of the at least two sixth transistors are used as control ends of the connection circuit.
Optionally, the at least two sixth transistors include an N-type transistor and a P-type transistor. This allows an efficient design of the connection circuit function.
In a third aspect, the present application provides a control method of a probability bit circuit system, which is mainly applied to the probability bit circuit system described in the second aspect, and specifically includes: the control device controls the control signal in the probability bit circuit system to be gradually adjusted from a first set of preset values to a second set of preset values, so that the probability bit circuit system is subjected to annealing operation to obtain an output signal; it will be appreciated that the control signal may be a continuous change or a step change; and outputting an output signal corresponding to the second set of preset values when the control signal reaches the second set of preset values. For example, the probability bit circuitry has 2 control voltages, a first set of preset values (1 v,1 v) and a second set of preset values (0.5 v,1.5 v). The control voltage may be continuously variable, such as from 1V to 1.5V, or may be step-variable, such as 1V, 1.1V, …, 1.5V.
In this embodiment, based on the architecture of the probability bit circuit system, annealing operation is performed on the probability bit circuit system, so that the isooctyl energy steady state of the target problem corresponding to the probability bit circuit system can be reached more quickly, and the problem of the combination optimization class can be solved.
Optionally, when the connection circuit of the probability bit circuit system is a transistor, the controlling the control signal in the probability bit circuit system to perform an annealing operation on the probability bit circuit system to obtain an output signal includes: the output signal is obtained by controlling the voltages of the two control terminals of the connection circuit from the first set of preset values (e.g., (1V, 1V)) to the second set of preset values (e.g., (0.5V, 1.5V)), and performing an annealing operation on the probability bit circuit system.
In a fourth aspect, the present application provides a control device for probabilistic bit circuitry, the device having a function to implement the behavior of the control device in the third aspect. The functions can be realized by hardware, and can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the functions described above.
In a possible implementation manner, the apparatus includes a unit or a module for performing the steps of the above third aspect. For example, the apparatus includes: the control module is used for controlling the control signals in the probability bit circuit system from a first set of preset values to a second set of preset values so as to enable the probability bit circuit system to be subjected to annealing operation to obtain output signals; and the output module is used for outputting an output signal corresponding to the second set of preset values when the control signal reaches the second set of preset values.
Optionally, the device further comprises a storage module for storing necessary program instructions and data of the control device.
In one possible implementation, the apparatus includes: a processor and a transceiver, the processor being configured to support the control device to perform the corresponding functions of the method provided in the third aspect. Optionally, the apparatus may further comprise a memory for coupling with the processor, which holds the program instructions and data necessary for controlling the apparatus.
In one possible implementation, when the device is a chip within a control device, the chip includes: the processing module and the transceiver module may be, for example, a processor, where the processor is configured to control a control signal of the probability bit circuitry for signals applied to each probability bit device to be from a first set of preset values to a second set of preset values, so that annealing operation is performed on the probability bit circuitry to obtain multiple sets of output signals, and the processing module may execute computer execution instructions stored in the storage unit, so as to support the control device to execute the method provided in the third aspect. The transceiver module may be, for example, an input/output interface, a pin, or a circuit on the chip, and when the control signal range reaches the second set of preset values, output signals corresponding to the second set of preset values are output and transmitted to other chips or modules coupled to the chip. Alternatively, the storage unit may be a storage unit within the chip, such as a register, a cache, or the like, and the storage unit may also be a storage unit located outside the chip, such as a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a random access memory (random access memory, RAM), or the like.
In one possible implementation, the apparatus includes a communication interface and logic circuitry for controlling a control signal in the probability bit circuitry from a first set of preset values to a second set of preset values such that annealing the probability bit circuitry results in an output signal; the communication interface is further configured to output an output signal corresponding to the second set of preset values when the control signal reaches the second set of preset values.
The processor mentioned in any of the above may be a general purpose central processing unit (Central Processing Unit, CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the data transmission method of the above aspects.
In a fifth aspect, embodiments of the present application provide a computer-readable storage medium storing computer instructions for performing the method of the fourth aspect.
In a sixth aspect, embodiments of the present application provide a computer program product comprising instructions which, when run on a computer, cause the computer instructions to perform the method of the fourth aspect described above.
In a seventh aspect, the present application provides a chip system comprising a processor for supporting a control device to implement the functions involved in the above aspects, such as generating or processing data and/or information involved in the above methods. In one possible design, the system-on-chip further includes a memory for storing program instructions and data necessary for the control device to implement the functions of any of the above aspects. The chip system may be formed of a chip or may include a chip and other discrete devices.
Drawings
FIG. 1a is a schematic diagram of a probability bit cell circuit;
FIG. 1b is a schematic diagram of a probability bit circuit system based on the probability bit cell circuit shown in FIG. 1 a;
FIG. 2 is a schematic diagram of one embodiment of a probability bit cell circuit in accordance with an embodiment of the present application;
FIG. 2a is a schematic diagram of another embodiment of a probability bit cell circuit according to an embodiment of the present application;
FIG. 2b is a schematic diagram illustrating a signal control of a probability bit cell circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another embodiment of a probability bit cell circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of another embodiment of a probability bit cell circuit according to an embodiment of the present application;
FIG. 5 is a schematic diagram of another embodiment of a probability bit cell circuit according to an embodiment of the present application;
FIG. 6 is a schematic diagram of another embodiment of a probability bit cell circuit according to an embodiment of the present application;
FIG. 7 is a schematic diagram of another embodiment of a probability bit cell circuit according to an embodiment of the present application;
FIG. 8 is a schematic diagram of another embodiment of a probability bit cell circuit in accordance with an embodiment of the present application;
FIG. 9 is a schematic diagram of another embodiment of a probability bit cell circuit according to an embodiment of the present application;
FIG. 10 is a schematic diagram of another embodiment of a probability bit cell circuit according to an embodiment of the present application;
FIG. 11 is a schematic diagram of another embodiment of a probability bit cell circuit according to an embodiment of the present application;
FIG. 12 is a schematic diagram of another embodiment of a probability bit cell circuit in accordance with an embodiment of the present application;
FIG. 13 is a diagram of one embodiment of probability bit circuitry in an embodiment of the present application;
FIG. 14 is a schematic diagram of one embodiment of a connection circuit according to an embodiment of the present application;
FIG. 15 is a schematic diagram of another embodiment of probability bit circuitry in accordance with an embodiment of the application;
FIG. 16a is a schematic diagram of one embodiment of a probabilistic bit topology network in accordance with an embodiment of the present application;
FIG. 16b is a schematic diagram of another embodiment of a probabilistic bit topology network in an embodiment of the present application;
FIG. 17 is a diagram of one embodiment of a method for controlling probability bit circuitry in accordance with an embodiment of the present application;
FIG. 18 is a diagram of one embodiment of the control results of the probability bit circuitry in an embodiment of the present application;
FIG. 19 is a schematic diagram of an embodiment of a control device for probability bit circuitry in accordance with an embodiment of the application;
fig. 20 is a schematic diagram of another embodiment of a control device for probability bit circuitry in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. As a person skilled in the art can know, with the appearance of a new application scenario, the technical scheme provided by the embodiment of the application is also applicable to similar technical problems.
The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules that are expressly listed or inherent to such process, method, article, or apparatus. The naming or numbering of the steps in the present application does not mean that the steps in the method flow must be executed according to the time/logic sequence indicated by the naming or numbering, and the execution sequence of the steps in the flow that are named or numbered may be changed according to the technical purpose to be achieved, so long as the same or similar technical effects can be achieved. The division of the units in the present application is a logical division, and may be implemented in another manner in practical application, for example, a plurality of units may be combined or integrated in another system, or some features may be omitted or not implemented, and in addition, coupling or direct coupling or communication connection between the units shown or discussed may be through some interfaces, and indirect coupling or communication connection between the units may be electrical or other similar manners, which are not limited in the present application. The units or sub-units described as separate components may be physically separated or not, may be physical units or not, or may be distributed in a plurality of circuit units, and some or all of the units may be selected according to actual needs to achieve the purpose of the present application.
The combination optimization problem is increasingly converted into the I Xin Moxing, and the I Xin Moxing is subjected to annealing operation to obtain the minimum energy state or the approximate minimum energy state of the Ictan, so that the optimal solution or the approximate optimal solution of the combination optimization problem is obtained. Such as the noise averaging field i Xin Tuihuo algorithm. The divide and combine optimization class problem can now be solved with a special probability computer, which can be implemented by probability bit circuitry. Wherein, probability bit refers to a bit that continuously jumps between 0 and 1 states over time, wherein the probability of 0 and 1 occurrence can be regulated by the input signal. The main implementation basis of the probability bit circuit is probability bit devices, such as random magnetic tunnel junctions, resistive random access memory devices, superconducting devices and the like. The random magnetic tunnel junction is a magnetic tunnel junction with a low energy barrier, and the state of the random magnetic tunnel junction continuously jumps between a low resistance state and a high resistance state with time under the excitation of thermal disturbance or current and voltage, so that the random magnetic tunnel junction can be used for constructing a probability bit device. Random magnetic tunnel junction based probability bit devices can regulate the probability of occurrence of low and high resistance states by varying the magnitude of the current, voltage, and the like applied to the magnetic tunnel junction. The structure of the current probability bit cell circuit may be as shown in fig. 1a, which includes 1 transistor, 1 random magnetic tunnel junction, 1 comparator, 1 resistor. The connection of the probability bit circuitry based on this probability bit cell circuit is shown in fig. 1b, i.e. each probability bit cell circuit is connected to a digital-to-analog converter (Digital to Analog Converter, DAC) and a microcontroller (micro controller). In the probability bit circuit system, the output of each probability bit unit circuit is sent to a microcontroller to carry out multiply-accumulate operation on weights corresponding to the problem to be solved, and then the result is fed back to the input end of the probability bit unit circuit to carry out iterative refreshing. In the scheme, a plurality of probability bit unit circuits are respectively connected with the DAC and the microcontroller, so that each calculation result is calculated independently when calculation is performed, and the calculation parallelism is poor, the iteration is prolonged, and the power consumption is high.
In order to solve the above-described problems, the present application provides a probability bit cell circuit, which is specifically shown in fig. 2, the probability bit cell circuit 200 includes at least two first transistors 201, a probability bit device 202, and an output device 203; wherein the gates of the at least two first transistors 201 are to be input terminals of the probability bit cell circuit 200, i.e. the probability bit cell circuit comprises at least two input terminals, which input analog signals; one ends of the source and drain electrodes of the at least two first transistors 201 are connected to the bottom end of the probability bit device 202 and the input end of the output device 203, the other ends of the source and drain electrodes of the at least two first transistors 201 are grounded, and the output end of the output device 203 outputs a digital signal. In this scheme, by adjusting the magnitude of the input signal obtained by the first transistor 201, the probability of the output signal of the output device 203 being the digital signal 0 and the data signal 1 can be regulated.
In an exemplary scenario, a probability bit cell circuit as shown in fig. 2a, which comprises 2 first transistors, where the probability bit cell circuit comprises two inputs, where the probability of the output signal being digital signal 0 and digital signal 1 can be regulated by modifying the size of the input signal. Such as shown in FIG. 2b, when the input voltage V in1 ＝1V、V in2 When the output voltage is=1v, the probability of occurrence of the output voltage is similar to that of the output voltage of 0V and 5V; when the input voltage V in1 ＝1V、V in2 When=0.8v, the probability of the output voltage being 0V is greater than the probability of the output voltage being 5V; when the input voltage V in1 ＝1V、V in2 When=1.2v, the probability of the output voltage being 5V is greater than the probability of the output voltage being 0V.
In this embodiment, the probability bit device 202 may have various implementations, and in particular, the probability bit device 202 may be a random magnetic tunnel junction, a resistive random access memory device, or a superconducting device. The output device 203 may be implemented in various ways, and specifically, the output device 203 may be an inverter, a comparator, or an operational amplifier. On this basis, one possible implementation of the probability bit cell circuit 200 may be as shown in fig. 3, the probability bit cell circuit 200 comprising at least two first transistors 201, a random magnetic tunnel junction 202, an inverter 203.
In this embodiment, in order to change the bias current of the probability bit device or the bias voltage of the probability bit device, the control module 204 may be accessed at the bottom of the probability bit device, as shown in fig. 4 in particular. In this embodiment, the control module 204 may have various implementation manners, which are specifically as follows:
In a possible implementation manner, the control module 204 is a second transistor, one end of the source-drain electrode of the second transistor is connected to the bottom of the probability bit device 202, the other end of the source-drain electrode of the second transistor is grounded, and the gate of the second transistor is used as the input terminal of the control module 204, where the probability bit unit circuit 200 can be as shown in fig. 5. In this scheme, the bias current of the random magnetic tunnel junction can be regulated by changing the gate voltage of the second transistor. For example, when the gate voltage of the second transistor is 1 volt, the current flowing into the random magnetic tunnel junction increases by 10 microamps.
In another possible implementation manner, the control module 204 is two third transistors, one ends of source and drain electrodes of the two third transistors are connected, and the other ends of the source and drain electrodes of the two third transistors are respectively connected to the bottom of the probability bit device 202 and grounded, and gate stages of the two second transistors are used as input terminals of the control module 204, where the probability bit unit circuit 200 may be as shown in fig. 6. In this scheme, the bias current of the random magnetic tunnel junction can be regulated by changing the gate voltage of the two third transistors.
In another possible implementation, the control module 204 is a current source, where one end of the current source is connected to the bottom of the probability bit device 202 and the other end of the current source is grounded, where the probability bit cell circuit 200 may be as shown in fig. 7. In the scheme, the bias current of the random magnetic tunnel junction can be regulated by changing the current of the current source.
In this embodiment, in order to slow down the change of the magnitude of the current or voltage signal acting on the probability bit device, a hysteresis module 205 may be connected between the bottom of the probability bit device or the bottom of the probability bit device and one end of the source/drain of the first transistor, as shown in fig. 8. In this embodiment, the hysteresis module 205 may have various implementation manners, which are specifically as follows:
in a possible implementation manner, the hysteresis module 205 includes a capacitor and a fourth transistor, where one end of the capacitor and the gate of the fourth transistor are connected to one ends of the source and drain of the at least two first transistors, the other end of the capacitor is connected to a power supply voltage, one end of the source and drain of the fourth transistor is connected to the bottom end of the probability bit device, and the other end of the source and drain of the fourth transistor is grounded, where the probability bit cell circuit 200 may be as shown in fig. 9. In this scenario, when the voltage at the input of the probability bit cell circuit changes, the current change at the random magnetic tunnel junction can be hysteretic changed by the capacitance of the hysteretic module 205 and the fourth transistor, resulting in a hysteretic change in current. For example, when the input voltage is changed from (1 volt ) to (1 volt, 0 volt), without the hysteresis module 205, the current flowing into the random magnetic tunnel junction will change from 20 microamperes to 10 microamperes; if there is a hysteresis module, the current flowing into the random magnetic tunnel junction is slowly changed from 20 microamps to 10 microamps.
In another possible implementation manner, the hysteresis module 205 includes a capacitor and a fifth transistor, where one end of the capacitor and the gate of the fifth transistor are connected to one ends of the source and drain of the at least two first transistors, the other end of the capacitor is connected to the bottom end of the probability bit device, one end of the source and drain of the fifth transistor is connected to the bottom end of the probability bit device, and the other end of the source and drain of the fifth transistor is grounded, where the probability bit cell circuit 200 may be as shown in fig. 10. In this scheme, when the voltage at the input of the probability bit cell circuit changes, the current change at the random magnetic tunnel junction can be hysteretic changed by the capacitance of the hysteretic module 205 and the third transistor, resulting in a hysteretic change in current. For example, when the input voltage is changed from (1 volt ) to (1 volt, 0 volt), without the hysteresis module 205, the current flowing into the random magnetic tunnel junction will change from 20 microamperes to 10 microamperes; if there is a hysteresis module, the current flowing into the random magnetic tunnel junction is slowly changed from 20 microamps to 10 microamps.
In another possible implementation, the hysteresis module 205 includes a capacitor, where one end of the capacitor is connected to one end of the source and drain of the at least two first transistors, and the other end of the capacitor is connected to the power supply voltage, where the probability bit unit circuit 200 may be as shown in fig. 11. In this scenario, when the voltage at the input of the probability bit cell circuit changes, the current change at the random magnetic tunnel junction can be hysteretic changed by the capacitance of the hysteretic module 205, resulting in a hysteretic change in current. For example, when the input voltage is changed from (1 volt ) to (1 volt, 0 volt), without the hysteresis module 205, the current flowing into the random magnetic tunnel junction will change from 20 microamperes to 10 microamperes; if there is a hysteresis module, the current flowing into the random magnetic tunnel junction is slowly changed from 20 microamps to 10 microamps.
It is understood that the control module 204 and the hysteresis module 205 can be included in the probability bit cell circuit at the same time, and one possible implementation of the probability bit cell circuit 200 can be as shown in fig. 12. The different implementations of the control module 204 and the hysteresis module 205 may be implemented in cooperation with each other, which will not be described herein.
Based on the probability bit unit circuit 200 described in fig. 2 to 12, the probability bit circuitry 300 may be as shown in fig. 13, where the probability bit circuitry 300 includes N probability bit units 200, and the N probability bit units 200 are cascaded through M connection circuits 400 to generate the probability bit circuitry, where M and N are positive integers, and M is greater than N; the connection circuit 400 is configured to perform a transformation of an output signal of a previous probability bit cell circuit to an input signal of a subsequent probability bit cell circuit.
Optionally, the connection circuit 400 has a control terminal for implementing a signal conversion function by converting an output signal of a previous probability bit unit circuit to an input signal of a subsequent probability bit unit circuit.
In this embodiment, the connection circuit 400 may be a transistor or a resistor. In a possible implementation manner, as shown in fig. 14, the connection circuit 400 includes at least two sixth transistors 401, where gates of the at least two sixth transistors 401 are connected in parallel and then connected to an output terminal of one of the N probability bit cell circuits 200, one ends of source and drain electrodes of the at least two sixth transistors 401 are connected to an input terminal of another probability bit cell circuit of the N probability bit cell circuits 200, and another ends of source and drain electrodes of the at least two sixth transistors 401 are used as control terminals of the connection circuit 400. In this aspect, the at least two sixth transistors include an N-type transistor and a P-type transistor.
Based on the connection circuit 400, in one possible implementation manner, as shown in fig. 15, the probability bit circuit system 300 in the embodiment of the present application includes 4 probability bit unit circuits and 8 connection circuits, where an output end of each probability bit unit circuit is connected to input ends of 2 adjacent probability bit unit circuits through the connection circuits, so as to form a topology network with the probability bit unit circuits as nodes and the connection circuits as edges. The connecting circuit consists of 1 NMOS tube and 1 PMOS tube; the grid electrodes of the NMOS tube and the PMOS tube are connected with the output ends of the 1 probability bit unit circuits; the source electrode of the NMOS tube and the drain electrode of the PMOS tube are connected with the input end of another probability bit unit circuit; the drain electrode of the NMOS tube is connected with the control signal Va, and the source electrode of the PMOS tube is connected with the control signal Vb.
It will be appreciated that the probability bit circuitry may implement a two-by-two connection (i.e., a full connection) of respective probability bit cell circuits, where M is equal to N x (N-1), each of the N probability bit cell circuits including N-1 first transistors. For example, in the probability bit circuit system shown in fig. 15, full connection between the respective probability bit unit circuits is not achieved, and if full connection between the respective probability bit unit circuits in the probability bit circuit system shown in fig. 15 is to be achieved, three connection circuits are required to be connected to the output terminals of the respective probability bit unit circuits, that is, in the probability bit circuit system shown in fig. 15, the number of connection circuits is 4*3 =12, and each probability bit unit circuit in the probability bit circuit system includes 3 first transistors.
In this embodiment, the probability bit circuit system is configured to periodically expand in a longitudinal direction or a transverse direction with a probability bit circuit module including a plurality of probability bit unit circuits, so as to implement a probability bit topology network. In a possible implementation manner, the structure of the probability bit topology network may be as shown in fig. 16a, and in the scheme shown in fig. 16a, the probability bit topology network includes four probability bit unit circuit modules, where each probability bit unit circuit module includes 8 probability bit unit circuits (i.e., each circle in fig. 16a indicates one probability bit unit circuit), where 8 probability bit circuits in each probability bit unit circuit module are connected in pairs, and each probability bit unit circuit module is connected through a probability bit unit circuit, as in the scheme shown in fig. 16a, there are four probability bit unit circuits in the upper left probability bit unit circuit module and four probability bit unit circuits in the lower left probability bit unit circuit module. It will be appreciated that the number of first transistors included in the probability bit cell circuit is related to the number of probability bit cell circuits to which the connected connection circuit is connected. Such as the probability bit cell circuit shown in fig. 16a, which has 8 probability bit cell circuits connected thereto, it comprises at least 8 of the first transistors, to which at least 8 connection circuits are connected.
In another possible implementation, the structure of the probability bit topology network may be as shown in fig. 16b, in the scheme shown in fig. 16b, the probability bit topology network includes four probability bit cell circuit modules, wherein each probability bit cell circuit module includes 8 probability bit cell circuits (i.e., each circle in fig. 16b indicates one probability bit cell circuit), wherein the 8 probability bit circuits within each probability bit cell circuit module are connected in pairs, and the connection between each probability bit cell circuit module is as shown in fig. 16b, and the probability bit cell circuit 1 of the upper left probability bit cell circuit module is connected with the probability bit cell circuits 1 to 4 of the lower left probability bit cell circuit module; the probability bit unit circuit 5 of the upper left probability bit unit circuit block is connected to the probability bit unit circuits 1 to 4 of the upper right probability bit unit circuit block; the probability bit unit circuit 5 of the upper right probability bit unit circuit block is connected with the probability bit unit circuits 5 to 7 of the lower right probability bit unit circuit block; the probability bit unit circuits 8 of the lower left probability bit unit circuit block are connected to the probability bit unit circuits 1 to 4 of the lower right probability bit unit circuit block. It will be appreciated that the number of first transistors included in the probability bit cell circuit is related to the number of probability bit cell circuits to which the connected connection circuit is connected. Such as the probability bit cell circuit 1 shown in fig. 16b, which has 11 probability bit cell circuits connected thereto, it comprises at least 11 of the first transistors, to which at least 11 connection circuits are connected.
It will be appreciated that the number of probability bit cell circuits included in each set of probability bit circuit blocks in the probability bit topology network may be any set integer, such as 8, 16, 32, 64, etc.
The probability bit unit circuit and the probability bit circuit system in the embodiment of the present application are described above, and the control method of the probability bit circuit system in the embodiment of the present application is described below, referring to fig. 17 specifically, the control method of the probability bit circuit system includes:
1701. the control device controls the control signal in the probability bit circuit system to be gradually adjusted from a first set of preset values to a second set of preset values, so that the probability bit circuit system is subjected to annealing operation to obtain an output signal.
The control device controls the control voltage on the control end of the probability bit circuit system to change from a first set of preset values to a second set of preset values, so that an output signal is obtained.
It will be appreciated that the control signal may be a continuous change or a step change. The voltage range indicated by the first set of preset values may be greater than the voltage range indicated by the second set of preset values; alternatively, the voltage range indicated by the first set of preset values may be smaller than the voltage range indicated by the second set of preset values. The specific case is not limited here, as long as it can be expressed that the control voltage is changed. For example, the probability bit circuitry has 2 control voltages, a first set of preset values (1 v,1 v) and a second set of preset values (0.5 v,1.5 v). The control voltage may be continuously variable, such as from 1V to 1.5V, or may be step-variable, such as 1V, 1.1V, …, 1.5V.
It can be understood that if the connection circuit adopted by the probability bit circuit system is a transistor, the control voltages at two ends of the connection circuit can be directly controlled to make the voltage difference between the two ends of the connection circuit become larger, so as to implement annealing operation on the probability bit circuit system.
1702. And outputting an output signal corresponding to the second set of preset values when the control signal range reaches the second set of preset values.
And when the control device enables the control signal loaded on the control end of the probability bit circuit system to reach the second preset value, outputting the output signal corresponding to each probability bit unit circuit at the moment.
In an exemplary scenario, based on the adjustment scenario shown in fig. 17, in the probability bit circuit system shown in fig. 15, the evolution result of the output signals of the respective probability bit unit circuits with time may be as shown in fig. 18, and the final outputs of the 4 probability bit unit circuits are respectively stabilized at 5V, 0V and 5V.
Referring specifically to fig. 19, in an embodiment of the present application, the control apparatus 1900 includes: the device comprises a processing module 1901 and an output module 1902, wherein the processing module 1901 and the output module 1902 are connected through a bus. The control device 1900 may be a control device in the above method embodiment, or may be configured as one or more chips in the control device.
For example, the processing module 1901 is configured to obtain an input signal of the probability bit circuitry; the processing module 1901 may be configured to perform step 1701 of the above method embodiment, for example, the processing module 1901 controls a control signal in the probability bit circuitry to be from a first set of preset values to a second set of preset values, so that an annealing operation is performed on the probability bit circuitry to obtain an output signal; the output module 1902 may be configured to perform step 1702 of the method embodiment described above. For example, the output module 1903 outputs an output signal corresponding to the second set of preset values when the control signal range reaches the second set of preset values.
Optionally, the control device 1900 further includes a storage module coupled to the processing module, such that the processing module can execute the computer-executable instructions stored in the storage module to implement the functions of the control device in the above-described method embodiment. In one example, the memory module optionally included in control apparatus 1900 may be an on-chip memory unit, such as a register, a cache, etc., or may be an off-chip memory unit, such as a ROM or other type of static storage device, RAM, etc., that may store static information and instructions.
It should be understood that the flow executed between the modules of the control device 1900 in the corresponding embodiment of fig. 19 is similar to the flow executed by the control device in the corresponding method embodiment of fig. 17, and detailed descriptions thereof are omitted herein.
Fig. 20 shows a possible schematic configuration of a control device 2000 in the above embodiment, and the control device 2000 may be configured as the aforementioned control device. The control device 2000 may include: a processor 2002, computer-readable storage media/memory 2003, a transceiver 2004, input devices 2005 and output devices 2006, and a bus 2001. Wherein the processor, transceiver, computer readable storage medium, etc. are connected by a bus. Embodiments of the present application are not limited to the specific connection medium between the components described above.
In one example of this, the first and second embodiments,
the processor 2002 control means controls the control signals in the probability bit circuitry to be gradually adjusted from a first set of preset values to a second set of preset values so that the probability bit circuitry is annealed to obtain output signals;
the output device 2006 outputs an output signal corresponding to the second set of preset values when the control signal reaches the second set of preset values.
It is understood that fig. 20 shows only a simplified design of a control device, and that in practical applications, the control device may comprise any number of transceivers, processors, memories, etc., and all control devices that may implement the present application are within the scope of the present application.
The processor 2002 of the above-described device 2000 may be a general-purpose processor, such as a CPU, network processor (network processor, NP), microprocessor, etc., or may be an ASIC, or one or more integrated circuits for controlling the execution of the program of the present application. But also digital signal processors (digital signal processor, DSP), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The controller/processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, etc. Processors typically perform logical and arithmetic operations based on program instructions stored in memory.
The bus 2001 may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus, an extended industry standard architecture (extended industry standard architecture, EISA) bus, or the like. The bus may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in fig. 20, but not only one bus or one type of bus.
The computer-readable storage media/memory 2003 referred to above may also hold an operating system and other application programs. In particular, the program may include program code including computer-operating instructions. More specifically, the memory may be ROM, other types of static storage devices that can store static information and instructions, RAM, other types of dynamic storage devices that can store information and instructions, disk storage, and the like. The memory 2003 may be a combination of the above memory types. And the computer readable storage medium/memory described above may be in the processor, or may be external to the processor, or distributed across multiple entities including the processor or processing circuitry. The above-described computer-readable storage medium/memory may be embodied in a computer program product. For example, the computer program product may include a computer readable medium in a packaging material.
Alternatively, embodiments of the present application also provide a general processing system, for example, commonly referred to as a chip, including: one or more microprocessors that provide processor functions; and an external memory providing at least a portion of the storage medium, all of which are coupled to the other support circuits via an external bus architecture. The instructions stored by the memory, when executed by the processor, cause the processor to perform some or all of the steps of the control means in the control method of the probability bit circuitry in this embodiment of fig. 17, and/or other processes for the techniques described herein.
The steps of a method or algorithm described in connection with the present disclosure may be embodied in hardware, or may be embodied in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. In addition, the ASIC may be located in the control device. It is also possible that the processor and the storage medium are present in the control device as discrete components.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Claims (16)
1. A probability bit cell circuit, comprising:
at least two first transistors, a probability bit device, and an output device;
the gates of the at least two first transistors are input ends of the probability bit unit circuit, and analog signals are input to the input ends;
One ends of the source drains of the at least two first transistors are connected with the bottom end of the probability bit device and the input end of the output device, the other ends of the source drains of the at least two first transistors are grounded, and the output end of the output device outputs a digital signal.
2. The probability bit cell circuit of claim 1, further comprising a control module coupled to a bottom end of the probability bit device;
the control module is used for adjusting the bias current acting on the probability bit device.
3. The probability bit cell circuit of claim 2, wherein the control module is a second transistor, one end of a source-drain electrode of the second transistor is connected to a bottom end of the probability bit device, and the other end of the source-drain electrode of the second transistor is grounded;
or alternatively, the first and second heat exchangers may be,
the control module is a current source, one end of the current source is connected with the bottom end of the probability bit device, and the other end of the current source is grounded;
or alternatively, the first and second heat exchangers may be,
the control module is provided with two third transistors, one ends of source and drain electrodes of the two third transistors are connected, the other ends of the source and drain electrodes of the two third transistors are respectively connected with the bottom of the probability bit device and grounded, and the gate electrodes of the two third transistors are used as input ends of the control module.
4. A probability bit cell circuit according to any one of claims 1 to 3, further comprising a hysteresis module connected to the bottom end of the probability bit device or located between one of the source and drain electrodes of the at least two first transistors and the bottom end of the probability bit device;
the hysteresis module is used for slowing down the change of current or voltage acting on the probability bit.
5. The probability bit cell circuit of claim 4, wherein the hysteresis module comprises a capacitor and a fourth transistor, wherein one end of the capacitor and a gate of the fourth transistor are connected to one ends of the source and drain of the at least two first transistors, the other end of the capacitor is connected to a power supply voltage, one end of the source and drain of the fourth transistor is connected to a bottom end of the probability bit device, and the other end of the source and drain of the fourth transistor is grounded;
or alternatively, the first and second heat exchangers may be,
the hysteresis module comprises a capacitor and a fifth transistor, wherein one end of the capacitor and a grid electrode of the fifth transistor are connected with one ends of source and drain electrodes of the at least two first transistors, the other end of the capacitor is connected with the bottom end of the probability bit device, one end of a source and drain electrode of the fourth transistor is connected with the bottom end of the probability bit device, and the other end of the source and drain electrode of the fourth transistor is grounded;
Or alternatively, the first and second heat exchangers may be,
the hysteresis module comprises a capacitor, one end of the capacitor is connected with one ends of the source and drain electrodes of the at least two first transistors, and the other end of the capacitor is connected with a power supply voltage.
6. The probability bit cell circuit of any one of claims 1 to 5, wherein the probability bit device is a random magnetic tunnel junction, a resistive-switching memory device, or a superconducting device.
7. A probability bit cell circuit according to any one of claims 1 to 5, wherein the output device is an inverter, a comparator or an operational amplifier.
8. A probabilistic bit circuitry comprising:
n probability bit cell circuits as described in any one of the preceding claims 1 to 7, said N being an integer greater than 1;
the N probability bit unit circuits are connected in cascade through M connecting circuits to generate a probability bit circuit system, M is an integer larger than or equal to N, and the connecting circuits are used for realizing the transformation from an output signal of a previous probability bit unit circuit to an input signal of a subsequent probability bit unit circuit.
9. The probabilistic bit circuitry of claim 8, wherein the N probabilistic bit cell circuits cascade through M connection circuits to generate the probabilistic bit circuitry comprises:
The probability bit units in the N probability bit unit circuits are connected in pairs through the M connection circuits, M is equal to N (N-1), and each probability bit unit circuit in the N probability bit unit circuits comprises N-1 first transistors.
10. The probability bit circuitry of claim 9, wherein the probability bit circuitry is periodically spread out in a set of the N probability bit cell circuits, either vertically or horizontally.
11. The probabilistic bit circuitry of claim 10, wherein the probabilistic bit circuitry comprises X probabilistic bit circuitry modules comprising the N probabilistic bit cell circuits, the N probabilistic bit cell circuits in the probabilistic bit circuitry modules are connected two by two, and the X probabilistic bit circuitry modules are connected by a probabilistic bit cell circuit, the X being an integer greater than 1.
12. The probability bit circuitry of any one of claims 8 to 11, wherein the connection circuit has a control terminal for effecting a transformation of an output signal of a preceding probability bit cell circuit to an input signal of a following probability bit cell circuit.
13. The probabilistic bit circuitry of claim 12, wherein,
the connecting circuit comprises at least two sixth transistors, wherein the gates of the at least two sixth transistors are connected in parallel and then connected with the output end of one probability bit unit circuit of the N probability bit unit circuits, one ends of the source and drain electrodes of the at least two sixth transistors are connected and then connected with the input end of the other probability bit unit circuit of the N probability bit unit circuits, and the other ends of the source and drain electrodes of the at least two sixth transistors are used as the control end of the connecting circuit.
14. The probabilistic bit circuitry of claim 13, wherein the at least two sixth transistors comprise an N-type transistor and a P-type transistor.
15. A method of controlling a probability bit circuitry, applied to any one of claims 8 to 14, comprising:
the control signal in the probability bit circuit system is controlled to be gradually adjusted from a first set of preset values to a second set of preset values, so that annealing operation is carried out on the probability bit circuit system to obtain an output signal;
And outputting an output signal corresponding to the second set of preset values when the control signal reaches the second set of preset values.
16. The method of claim 15, wherein when the connection circuit of the probability bit circuitry is a transistor, the controlling the control signal in the probability bit circuitry to anneal the probability bit circuitry to obtain the output signal comprises:
and controlling the voltage of the control ends at two ends of the connecting circuit so as to enable annealing operation to be carried out on the probability bit circuit system to obtain the output signal.
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| CN202210467078.9A CN117008873A (en) | 2022-04-29 | 2022-04-29 | Probability bit unit circuit, probability bit circuit system and control method thereof |
| PCT/CN2023/073771 WO2023207236A1 (en) | 2022-04-29 | 2023-01-30 | Probability bit unit circuit, probability bit circuit system and control method therefor |
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| JPS5849956B2 (en) * | 1979-07-10 | 1983-11-08 | 日本電信電話株式会社 | Matrix memory circuit using MIS field effect transistors |
| US7221582B2 (en) * | 2003-08-27 | 2007-05-22 | Hewlett-Packard Development Company, L.P. | Method and system for controlling write current in magnetic memory |
| WO2010147029A1 (en) * | 2009-06-15 | 2010-12-23 | ソニー株式会社 | Semiconductor device |
| CN105913118B (en) * | 2015-12-09 | 2019-06-04 | 上海大学 | A kind of Hardware for Artificial Neural Networks realization device based on probability calculation |
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