CN117008869A - Floating point number processing method, device, computer equipment and storage medium - Google Patents
Floating point number processing method, device, computer equipment and storage medium Download PDFInfo
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- 238000007667 floating Methods 0.000 title claims abstract description 770
- 238000003672 processing method Methods 0.000 title claims abstract description 43
- 238000012545 processing Methods 0.000 claims abstract description 121
- 238000000034 method Methods 0.000 claims abstract description 87
- 238000006073 displacement reaction Methods 0.000 claims abstract description 40
- 238000013473 artificial intelligence Methods 0.000 claims abstract description 34
- 238000004590 computer program Methods 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims description 48
- 238000010801 machine learning Methods 0.000 claims description 28
- 238000006243 chemical reaction Methods 0.000 claims description 16
- 238000012549 training Methods 0.000 claims description 10
- 238000010276 construction Methods 0.000 claims description 7
- 238000012216 screening Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 19
- 238000005516 engineering process Methods 0.000 description 17
- 239000011159 matrix material Substances 0.000 description 6
- 230000006870 function Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000010606 normalization Methods 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- ZLIBICFPKPWGIZ-UHFFFAOYSA-N pyrimethanil Chemical compound CC1=CC(C)=NC(NC=2C=CC=CC=2)=N1 ZLIBICFPKPWGIZ-UHFFFAOYSA-N 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 238000013145 classification model Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013135 deep learning Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000007477 logistic regression Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003058 natural language processing Methods 0.000 description 1
- 238000003062 neural network model Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000012706 support-vector machine Methods 0.000 description 1
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Abstract
The present application relates to the field of artificial intelligence, and in particular, to a floating point number processing method, apparatus, computer device, storage medium, and computer program product. The method comprises the following steps: acquiring a first exponent of a first floating point number, a first mantissa and a first leading zero number of the first mantissa, and acquiring a second exponent and a second mantissa of a second floating point number overlapped with the first floating point number; in parallel, performing order matching processing on the first floating point number and the second floating point number to obtain a first shift mantissa and a second shift mantissa, and determining a superposed exponent according to the first exponent, the first leading zero number and the second exponent; in parallel, superposing the first displacement mantissa and the second displacement mantissa to obtain a superposed mantissa, and predicting a second leading zero number of the superposed mantissa; and determining a floating point number superposition result after the first floating point number and the second floating point number are superposed according to the superposed mantissa, the superposed exponent and the second leading zero number. By adopting the method, the superposition efficiency of floating point numbers can be improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a floating point number processing method, apparatus, computer device, and storage medium.
Background
In the field of artificial intelligence, there are a large number of scenarios where data is superimposed, for example, a matrix needs to be superimposed in a certain dimension. The superposition operation is divided into superposition of fixed-point numbers and superposition of floating-point numbers, the fixed-point superposition is simpler, and a general processor can finish the superposition operation in one clock period. However, the superposition of the floating-point numbers is complex, and the addition operation of the floating-point numbers involves operations of order, shift, addition, normalization, rounding and the like, and all the operations occupy a large number of time sequence paths, so that the processor completes the superposition operation in one clock cycle, and the superposition performance of the processor is greatly affected.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a floating point number processing method, apparatus, computer device, computer readable storage medium, and computer program product that can improve the efficiency of superposition.
In a first aspect, the present application provides a floating point number processing method, the method including:
acquiring a first exponent of a first floating point number, a first mantissa and a first leading zero number of the first mantissa, and acquiring a second exponent and a second mantissa of a second floating point number overlapped with the first floating point number;
In parallel, performing a first order-matching process on the first floating point number and the second floating point number to obtain a first shift mantissa of the first mantissa and a second shift mantissa of the second mantissa, and determining a post-superposition exponent according to the first exponent, the first leading zero number and the second exponent;
in parallel, superposing the first displacement mantissa and the second displacement mantissa to obtain a superposed mantissa, and predicting a second leading zero number of the superposed mantissa based on the first displacement mantissa and the second displacement mantissa;
and determining a floating point number superposition result after superposition of the first floating point number and the second floating point number according to the superposition mantissa, the superposition exponent and the second leading zero number.
In a second aspect, the present application also provides a floating point number processing apparatus, the apparatus comprising:
the data acquisition module is used for acquiring a first exponent of a first floating point number, a first mantissa and a first leading zero number of the first mantissa, and acquiring a second exponent and a second mantissa of a second floating point number overlapped with the first floating point number; for the other floating point number processing rounds except the first floating point number processing round, the second floating point number is a currently traversed floating point number in a floating point number sequence, and the first floating point number is a floating point superposition number obtained by superposing the floating point number positioned before the second floating point number in the floating point number sequence;
The parallel processing module is used for performing order-matching processing on the first floating point number and the second floating point number to obtain a first shift mantissa of the first mantissa and a second shift mantissa of the second mantissa in parallel, and determining a superposed exponent according to the first exponent, the first leading zero number and the second exponent; in parallel, superposing the first displacement mantissa and the second displacement mantissa to obtain a superposed mantissa, and predicting a second leading zero number of the superposed mantissa based on the first displacement mantissa and the second displacement mantissa;
the data generation module is used for determining a floating point number superposition result obtained by superposing the first floating point number and the second floating point number according to the superposed mantissa, the superposed exponent and the second leading zero number;
and the return module is used for taking the floating point superposition number in the floating point superposition result as a new first floating point number, determining the floating point number traversed to next in the floating point sequence, taking the floating point number traversed to next as a new second floating point number, entering the next floating point number processing round, and returning to execute the steps of acquiring the first exponent, the first mantissa and the first leading zero number of the first mantissa until the last floating point number in the floating point sequence is traversed to obtain a target floating point superposition result after superposition of the floating points in the floating point sequence.
In one embodiment, for a first floating point processing round, the first floating point is a first floating point in the sequence of floating points, and the second floating point is a next floating point in the sequence of floating points immediately adjacent to the first floating point.
In one embodiment, the parallel processing module is further configured to determine a first difference between the first exponent and the first leading zero number, and take the first difference as the true exponent of the first floating point number; determining first shift information of the first mantissa and second shift information of the second mantissa according to the real exponent and the second exponent; and carrying out shift processing on the first mantissa and the second mantissa in parallel according to the first shift information and the second shift information to obtain a first shift mantissa and a second shift mantissa.
In one embodiment, the first shift information includes a first shift direction and a first shift amount; the second shift information includes a second shift direction and a second shift amount; the parallel processing module is further configured to determine a first shift amount according to the first leading zero number, and determine a second shift amount according to the real index and the second index, when the real index is greater than the second index, with a preset first direction as a first shift direction and a preset second direction as a second shift direction; when the real index is smaller than the second index, determining that the second shift amount is zero, and determining a first shift direction and a first shift amount according to at least one of the real index, the first index and the second index.
In one embodiment, the parallel processing module is further configured to take the first leading zero number as a first shift amount and take a first difference between the real exponent and the second exponent as a second shift amount when the real exponent is greater than the second exponent.
In one embodiment, the parallel processing module is further configured to subtract the real exponent from the second exponent to obtain a second difference when the real exponent is less than the second exponent; when the first leading zero number is larger than the second difference value, taking a preset first direction as a first shift direction, and taking a third difference value obtained by subtracting the second index from the first index as a first shift value; when the first leading zero number is smaller than the second difference value, taking a preset second direction as a first shift direction, and taking a fourth difference value obtained by subtracting the first index from the second index as a first shift value.
In one embodiment, the parallel processing module is further configured to obtain a second shift mantissa by performing shift processing on the second mantissa according to the second shift information through a preset first shifter; the first mantissa is shifted according to the first shifting information through a preset second shifter, and a first candidate shifting mantissa is obtained; the first mantissa is shifted according to the first shifting information through a preset third shifter, and a second shifting mantissa is obtained; screening a first shift mantissa from the first candidate shift mantissa and the second candidate shift mantissa through a preset selector according to the first bit information; the first shifter, the second shifter and the third shifter are used for carrying out shift processing on corresponding mantissas in parallel.
In one embodiment, the second shifter is a first direction shifter; the first direction shifter is used for shifting the mantissa towards a first direction; the third shifter is a second direction shifter; the second direction shifter is used for shifting the mantissa towards a second direction; the parallel processing module is further used for taking the first candidate shift mantissa generated by the second shifter as a first shift mantissa when the selector determines that the first shift direction in the first shift information is a preset second direction; when the selector determines that the first shift direction in the first shift information is a preset first direction, the selector takes the second candidate shift mantissa generated by the third shifter as a first shift mantissa.
In one embodiment, the target floating point number superposition result includes a target floating point superposition number and a third leading zero number of a third mantissa of the target floating point superposition number; the floating point number processing device further comprises a format conversion module, wherein the format conversion module is used for normalizing the target floating point number according to the third leading zero number of the third mantissa of the target floating point number to obtain a normalized floating point number; and rounding the normalized floating point addend to obtain a standard floating point addend.
In one embodiment, the format conversion module is further configured to add 1 to the third preamble zero number to obtain a third shift amount; shifting the third mantissa to the left by a third shift amount to obtain a fourth mantissa, and subtracting the third shift amount from the third exponent to obtain a fourth exponent; and determining a normalized floating point addend according to the fourth exponent and the fourth mantissa.
In one embodiment, the floating point number processing device is further configured to obtain a first floating point number and a second floating point number; the second floating point number is a floating point number derived from the artificial intelligence field; the first floating point number is determined based on the superposition result of a plurality of floating point numbers from the artificial intelligence field; the floating point number from the artificial intelligence field at least comprises one of training data extracted from a training sample through a machine learning model, data to be detected extracted from an object to be detected through the machine learning model and construction data constructed through the machine learning model; the floating point number processing method is executed by the artificial intelligent processor, and the floating point number superposition result obtained by superposition of the first floating point number and the second floating point number is generated in a unit clock period of the artificial intelligent processor.
In a third aspect, the present application further provides a computer device, where the computer device includes a memory and a processor, where the memory stores a computer program, and where the processor implements steps in any one of the floating point number processing methods provided by the embodiments of the present application when the computer program is executed by the processor.
In a fourth aspect, the present application also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of any of the floating point number processing methods provided by the embodiments of the present application.
In a fifth aspect, the present application also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the floating point number processing methods provided by the embodiments of the present application.
The floating point number processing method, apparatus, computer device, storage medium and computer program product may perform a dyadic processing operation with the first mantissa and the second mantissa by obtaining the first exponent, the first mantissa, the first leading zero number, the second mantissa and the second mantissa to obtain a first shifted mantissa and a second shifted mantissa, and determine a post-stack exponent based on the first exponent, the first leading zero number and the second mantissa. By deriving the first shift mantissa and the second shift mantissa, the first shift mantissa and the second shift mantissa may be superimposed to derive a post-superimposed position, and the second leading zero number of the post-superimposed mantissa may be predicted based on the first shift mantissa and the second shift mantissa. And obtaining the floating point number superposition result obtained after the superposition of the first floating point number and the second floating point number by obtaining the superposition mantissa, the superposition exponent and the second leading zero number. Because the opposite-order processing and the determination process of the index after superposition are executed in parallel, the superposition efficiency of floating point number superposition can be improved; and because the mantissa superposition process and the leading zero number prediction process are also executed in parallel, the superposition efficiency of floating point number superposition can be further improved.
Drawings
FIG. 1 is a diagram of an application environment for a floating point number processing method in one embodiment;
FIG. 2 is a flow diagram of a floating point number processing method in one embodiment;
FIG. 3 is a schematic diagram of a memory space in one embodiment;
FIG. 4 is a schematic diagram of a shifter in one embodiment;
FIG. 5 is a schematic diagram of a sequential superposition of floating point numbers in one embodiment;
FIG. 6 is a schematic diagram of floating point number superposition in one embodiment;
FIG. 7 is a schematic diagram of an overall framework of floating point number superposition in one embodiment;
FIG. 8 is a schematic diagram of a storage structure of floating point numbers in one embodiment;
FIG. 9 is a schematic diagram of a storage structure of floating point numbers in another embodiment;
FIG. 10 is a flow chart of a floating point number processing method in one embodiment;
FIG. 11 is a block diagram of a floating point number processing device in one embodiment;
fig. 12 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The floating point number processing method provided by the embodiment of the application can be applied to an application environment shown in FIG. 1. Wherein the terminal 102 communicates with the server 104 via a network. The data storage system may store data that the server 104 needs to process. The data storage system may be integrated on the server 104 or may be located on the cloud or other servers. Both the terminal 102 and the server 104 may be used separately to perform the floating point number processing method provided in the embodiments of the present application. The terminal 102 and the server 104 may also cooperate to perform the floating point number processing method provided in embodiments of the present application. Taking the example that the terminal 102 and the server 104 can cooperate to execute the floating point number processing method provided in the embodiment of the present application as an example, a user may initiate a data processing request through the terminal 102, so that the terminal 102 may send the data processing request to the server 104, so that the server 104 obtains corresponding first floating point data and second floating point data based on the received data processing request, and superimposes the first floating point data and the second floating point data to obtain floating point superimposed data. The terminal 102 may be, but not limited to, various desktop computers, notebook computers, smart phones, tablet computers, internet of things devices, and portable wearable devices, where the internet of things devices may be smart speakers, smart televisions, smart air conditioners, smart vehicle devices, and the like. The portable wearable device may be a smart watch, smart bracelet, headset, or the like. The server 104 may be implemented as a stand-alone server or as a server cluster of multiple servers.
It should be noted that, the floating point number processing method according to the embodiment of the present application may be executed by a computer device, where the computer device may be the terminal 102 or the server 104. The computer device may be deployed with machine learning models having different functions, through which different kinds of services may be provided. For example, the computer device may provide a face detection service, a face registration service, an identification service, or the like through a machine learning model having a face detection function. The computer device may also provide an image classification service, a target object recognition service, or an object analysis service, etc., through a machine learning model (such as a semantic segmentation model or an image classification model, etc.) having an image processing function. The different machine learning models can involve superposition operation of floating point numbers when providing services, at this time, the computer equipment can superpose the floating point numbers through the AI processor (also called artificial intelligence processor) and through the floating point number processing method of the embodiment of the application to obtain a floating point superposition result, so that the machine learning model can perform the next processing through obtaining the obtained floating point superposition result to provide corresponding services. Of course, the floating point number in the embodiment of the present application may be other data that needs to be overlapped, and may be related to a specific application scenario, which is not limited in the embodiment of the present application.
It should be further noted that, the floating point number processing method mentioned in the embodiments of the present application is mainly aimed at a scenario that two or more floating point numbers need to be superimposed when a machine learning model implemented by an artificial intelligence technology performs operation, where the artificial intelligence (Artificial Intelligence, AI) is a theory, a method, a technique, and an application system that uses a digital computer or a machine controlled by the digital computer to simulate, extend, and expand the intelligence of a person, sense an environment, acquire knowledge, and use knowledge to obtain an optimal result. In other words, artificial intelligence is an integrated technology of computer science that attempts to understand the essence of intelligence and to produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence, i.e. research on design principles and implementation methods of various intelligent machines, enables the machines to have functions of sensing, reasoning and decision.
The artificial intelligence technology is a comprehensive subject, and relates to the technology with wide fields, namely the technology with a hardware level and the technology with a software level. Artificial intelligence infrastructure technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technologies, operation/interaction systems, mechatronics, and the like. The artificial intelligence software technology mainly comprises a computer vision technology, a voice processing technology, a natural language processing technology, machine learning/deep learning and other directions.
With research and progress of artificial intelligence technology, research and application of artificial intelligence technology are developed in various fields, such as common smart home, smart wearable devices, virtual assistants, smart speakers, smart marketing, unmanned, automatic driving, unmanned aerial vehicles, robots, smart medical treatment, smart customer service, etc., and it is believed that with development of technology, artificial intelligence technology will be applied in more fields, exerting more and more important values.
It should be noted that the terms "first," "second," and the like as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The singular forms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one, unless the context clearly dictates otherwise. The numbers of "plural" or "multiple" etc. mentioned in the embodiments of the present application each refer to the number of "at least two", for example, "plural" means "at least two", and "multiple" means "at least two".
In one embodiment, as shown in fig. 2, a floating point number processing method is provided, and the method is applied to a computer device, which is a terminal or a server in fig. 1, for example. The floating point number processing method comprises the following steps:
Step 202, obtaining a first exponent of a first floating point number, a first mantissa and a first leading zero number of the first mantissa, and obtaining a second exponent and a second mantissa of a second floating point number superimposed with the first floating point number.
Wherein floating point numbers are digital representations of numbers belonging to a particular subset of rational numbers, used in computers to approximateWhich is likely to represent any real number. Floating point numbers are derived from an integer or fixed point number multiplied by the integer power of a base. For example, any one binary floating point number N can be written as n=sx2 j Where j is an exponent (also referred to as a step code) and S is a pure fraction (also referred to as a mantissa). That is, the floating point number includes an exponent and a mantissa. Exemplary, binary number 110.11 can be written as 0.11011 ×2 11 Wherein the exponent (also called the step code) is 11 and the mantissa is 0.11011. Leading zeros is a format that adds zeros in front of numbers, e.g., for data 1, when the agreed data bit is 3 bits, zeros may be added in front of 1, forming 001, to enable alignment of the format. The leading zero number of mantissas refers to the number of zeros preceding the first significant digit position from the most significant digit in the fraction portion following the fraction point in the mantissa (i.e., in the numeric portion of the mantissa). The significant digit position refers to the position of the first non-zero digit. For example, for floating point numbers 0.0011011 ×2 11 The mantissa is 0.0011011, the fraction in the mantissa (i.e., the numerical fraction in the mantissa) is 0011011, the pair of binary numbers, the first significant digit position from the most significant digit, refers to the first digit "1" from the most significant digit, and thus the significant digit position is the third digit, and thus there are two zeros before the third digit, and thus the floating point number 0.0011011 ×2 11 The leading zero number of mantissas of (2).
In particular, when it is desired to superimpose floating point numbers, the computer device may obtain a first exponent of the first floating point number, a first mantissa, and a first leading zero number of the first mantissa, and obtain a second exponent and a second mantissa of a second floating point number superimposed with the first floating point number. The first floating point number may be a superposition result obtained after the plurality of floating point numbers are superposed, and the second floating point number may be data that needs to be superposed to the first floating point number. For example, for a floating point sequence that includes a plurality of floating point numbers, a first floating point number may be a result of stacking the first N floating point numbers in the floating point sequence, and a second floating point number may be the n+1th number in the floating point sequence. Wherein N is a positive integer, and N+1 is less than the number of floating point numbers included in the floating point number sequence. As will be readily understood, when it is required to continuously superimpose floating points in a floating point sequence, the floating point superimposed number obtained by superimposing the first floating point and the second floating point may be used as a new first floating point, and the n+2th floating point in the floating point sequence may be used as a new second floating point, and then, the floating point processing method according to the embodiment of the present application may be continued to superimpose floating points.
In one embodiment, when a first floating point number is obtained, the computer device may identify components of the first floating point number, thereby obtaining a first exponent, a first mantissa, and a first leading zero number of the first mantissa. Similarly, the computer device may identify components of the second floating point number to obtain a second exponent and a second mantissa.
In one embodiment, a machine learning model may be deployed in a computer device, where processing a large amount of data may involve overlaying floating point numbers when the machine learning model provides a service to a user, such that when the floating point numbers are required to be overlaid, the machine learning model may obtain a first exponent of a first floating point number, a first mantissa, and a first leading zero number of the first mantissa to be overlaid, and obtain a second exponent of a second floating point number to be overlaid, and a second mantissa. The machine learning model refers to a model with corresponding capability through sample learning. The machine learning model may employ a neural network model, a dual path network model (DPN, dualPathNetwork), a support vector machine, or a logistic regression model, among others.
Step 204, in parallel, performing a first order matching process on the first floating point number and the second floating point number to obtain a first shift mantissa of the first mantissa and a second shift mantissa of the second mantissa, and determining a post-stack exponent according to the first exponent, the first leading zero number and the second exponent.
Specifically, for the superposition of floating point numbers, since the exponent bits of the superposition operation may be different, it is first necessary to perform a first order-matching process on the first floating point number and the second floating point number, so that the exponent of the first floating point number is the same as the exponent of the second floating point number, which is convenient for the subsequent addition operation. To ensure that the value remains unchanged before and after the remainder processing by the same floating point number, the mantissas also need to be shifted synchronously when the exponent is adjusted. Where shifting refers to shifting the mantissa left or right. Thus, in performing the order-checking process, the computer device may cause the first floating point number to be the same as the exponent of the second floating point number by shifting the first mantissa and the second mantissa. For example, the computer device may shift the first mantissa of the first floating point number to obtain a first shifted mantissa of the first mantissa. Similarly, the second mantissa may be shifted to obtain a second shifted mantissa of the second mantissa. Where shifting mantissas refers to mantissas generated after left or right shifting the mantissas.
The computer device may also perform the step of determining the post-stack index simultaneously with performing the step of performing the step-wise processing. The step of determining the post-stack index includes: and determining the index of the floating point superposition number obtained by superposition of the first floating point number and the second floating point number, namely determining the index after superposition according to the first index, the second index and the first leading zero number.
In one embodiment, during the step-by-step processing, the computer device may determine a reference exponent based on the first exponent and the second exponent, where the reference exponent refers to an exponent to which the first exponent and the second exponent are to be adjusted, for example, the reference exponent may be an intermediate value between the first exponent and the second exponent, so that the computer device adjusts the first exponent to the reference exponent by performing a shift processing on the first mantissa; and the computer device adjusts the second exponent to the reference exponent by performing a shift process on the second mantissa. Exemplary, at first floating point number 0.0011011 ×2 3 The second floating point number is 0.0011111 multiplied by 2 5 When the reference exponent is determined to be 4, the computer device may obtain the first floating point number after the opposite-order processing by shifting the decimal point of the first mantissa of the first floating point number by one bit in the left direction, that is, by shifting the numerical portion of the first mantissa by one bit in the right direction, so that the first exponent of the first floating point number becomes 4 4 Wherein, in the first floating point number after the opposite-order processingThe mantissa is the first shift mantissa. Similarly, the computer device may obtain the second floating point number 0.011111 ×2 after the opposite-order processing by shifting the fractional point of the mantissa of the second floating point number by one bit in the right direction, that is, by shifting the numerical portion of the second mantissa by one bit in the left direction, so that the second exponent of the second floating point number becomes 4 4 The mantissa of the second floating point number after the opposite-order processing is the second shift mantissa. Therefore, the first floating point number after the opposite-order processing and the second floating point number after the opposite-order processing have the same index.
In one embodiment, the computer device may determine the post-stack exponent from the first exponent and the second exponent, e.g., by taking an intermediate value of the first exponent and the second exponent as the post-stack exponent.
In one embodiment, during the step-by-step processing, the computer device may subtract the first leading zero number from the first exponent to obtain the real exponent, use a median value of the real exponent and the second exponent as the reference exponent, or use a larger value of the real exponent and the second exponent as the reference exponent, and use a smaller value of the real exponent and the second exponent as the reference exponent, so that the computer device changes the first exponent to the reference exponent and changes the second exponent to the reference exponent by shifting the first mantissa and the second mantissa. The computer device may perform the step of determining the post-stack index while performing the contrast processing. When the intermediate value of the real index and the second index is taken as the reference index, in the process of determining the superimposed index, the computer equipment can subtract the first leading zero number from the first index to obtain the real index, and average the real index and the second index to obtain the superimposed index. When the larger value in the real index and the second index is taken as the reference index in a convention, in the process of executing the determination of the superimposed index, the computer equipment can subtract the first leading zero number from the first index to obtain the real index, subtract the second index from the real index, and take the second index as the superimposed index when the value obtained by subtracting the second index from the real index is negative; and when the value obtained by subtracting the second index from the real index is a positive number, taking the real index as the superimposed index. Similarly, when the convention takes the smaller value of the real index and the second index as the reference index, in performing the determination of the post-stack index, the computer device may determine the smaller value of the real index and the second index and take the index having the smaller value as the post-stack index.
In one embodiment, the computer device may perform the process of the scala processing and the process of determining the post-stack index in parallel by the AI processor, e.g., the AI processor may open up two threads, and perform the process of the scala processing and the process of determining the post-stack index separately by different threads.
In parallel, the first and second shifted mantissas are superimposed to obtain a superimposed mantissa, and a second leading zero number of the superimposed mantissa is predicted based on the first and second shifted mantissas, step 206.
Specifically, when performing the level-shifting process on the first floating-point number and the second floating-point number so that the exponents of the first floating-point number and the second floating-point number after the level-shifting process are the same, the computer device may superimpose the mantissa of the first floating-point number after the level-shifting process with the mantissa of the second floating-point number after the level-shifting process, that is, superimpose the first shift mantissa and the second shift mantissa, to obtain a superimposed mantissa. For example, the first floating point number after the antipodal processing is 0.00011011×2 4 And the second floating point number after the opposite-order processing is 0.011111 multiplied by 2 4 When the computer equipment is used, 0.00011011 and 0.011111 can be overlapped to obtain the overlapped mantissa.
While superimposing the first shift mantissa and the second shift mantissa, the computer device may also predict a second leading zero number of the superimposed mantissa based on the first shift mantissa and the second shift mantissa. For example, a leading zero number prediction model is deployed in the computer device, and the computer device may input the first shift mantissa and the second shift mantissa into the leading zero number prediction model to obtain the second leading zero number.
In one embodiment, the computer device may execute the mantissa addition process and the leading zero number prediction process in parallel by the AI processor, e.g., the AI processor may open up two threads to execute the mantissa addition process and the leading zero number prediction process separately by different threads.
In one embodiment, the leading zero number prediction is performed only with one positive number plus one negative number, and when one of the first shift mantissa and the second shift mantissa is positive and one is negative, the leading zero number prediction may be performed on the superposition result of the first shift mantissa and the second shift mantissa by the leading zero prediction model. When the leading zero number needs to be predicted, the leading zero number prediction model can subtract the second shift mantissa from the first shift mantissa to obtain a target difference portion, and determine the position of the first non-zero value in the target difference portion according to the target difference portion, so as to obtain the second leading zero number according to the position of the first non-zero value in the target difference portion. For example, since the mantissa of the floating point number is a pure fraction, the integer portion may be ignored, with the value portion of the first shifted mantissa being a=a 0 a 1 …a n-1 The method comprises the steps of carrying out a first treatment on the surface of the The numerical part of the second shift mantissa is b=b 0 b 1 …b n-1 When the target difference portion is determined to be r=a-b=r 0 r 1 …r n-1 . When the first mantissa portion and the second mantissa portion are both binary, r i The value of (2) may be 1,0, -1. Thus, the target difference portion R may be written in a sequence, such as 0 k 11 (x), or 0 k 10 (x) or may be 0 k 1 (-1) 0 (x), etc. Wherein 0 is k K0 s are represented, and x is an arbitrary number of sub-strings. Further, the computer device stores the correspondence between the various sequence forms and the calculation rule of the first non-zero number position. The computer device may determine a target sequence form to which the target difference portion R matches, and determine a first non-zero position in the target difference portion according to a target calculation rule corresponding to the target sequence form in the correspondence, thereby determining a number of zeros preceding the first non-zero position based on the first non-zero position to obtain a second leading zero number. Wherein the first nonzero position refers to the occurrence from the high positionFor example, when the target difference portion R is 0011 and the position of the agreed highest bit is the first, the first non-zero position (i.e., the first 1) is the third position in 0011.
In one embodiment, the computer device may further have a leading zero prediction circuit built therein, and the computer device may obtain the second leading zero number through the built leading zero prediction circuit.
Step 208, determining a floating point number superposition result after superposition of the first floating point number and the second floating point number according to the post-superposition mantissa, the post-superposition exponent and the second leading zero number.
The floating point number superposition result refers to a result obtained by superposing the first floating point number and the second floating point number. The floating point number superposition result includes a floating point superposition number and a second leading zero number. The floating point superposition number is a floating point number, the mantissa in the floating point superposition number is the superposed mantissa, and the exponent in the floating point superposition number is the superposed exponent. For example, in the case where the first floating point number and the second floating point number are both binary numbers, the result of floating point number superposition is "0.0011×2" when the post-superposition mantissa is 0.0011, the post-superposition exponent is 3, and the second leading zero number is 2 3 Lz=2 ", the floating point addend is" 0.0011×2 3 ". Where the symbol lz represents the second leading zero number.
Specifically, the computer device may obtain a floating point number superposition result according to the post-superposition mantissa, the post-superposition exponent, and the second leading zero number. After the floating point number superposition result is obtained, the computer equipment can further acquire the next floating point number, and superimpose the next floating point number and the floating point number superposition result according to the floating point number processing method, so that the superposition result after the plurality of floating point numbers are superimposed can be obtained through circulation. When the next floating point number is overlapped with the floating point number overlapping result, the computer equipment can directly read the corresponding leading zero number from the floating point number overlapping result, and the numerical value at each position in the mantissa is not required to be read any more so as to determine the leading zero number, so that the overlapping efficiency of the floating point number overlapping can be improved.
In one embodiment, when there is no longer a need to superimpose the floating point number overlay result with the next floating point number, the computer device may convert the floating point number overlay result to a standard floating point format and output the floating point number overlay result having the standard floating point format.
In the floating point number processing method, by acquiring the first exponent, the first mantissa, the first leading zero number, the second mantissa and the second mantissa, a step-by-step processing operation can be performed through the first mantissa and the second mantissa to obtain the first shift mantissa and the second shift mantissa, and the exponent after superposition is determined according to the first exponent, the first leading zero number and the second mantissa. By deriving the first shift mantissa and the second shift mantissa, the first shift mantissa and the second shift mantissa may be superimposed to derive a post-superimposed position, and the second leading zero number of the post-superimposed mantissa may be predicted based on the first shift mantissa and the second shift mantissa. And obtaining a superposition result of the first floating point number and the second floating point number by obtaining the superposition mantissa, the superposition exponent and the second leading zero number. Because the opposite-order processing and the determination process of the index after superposition are executed in parallel, the superposition efficiency of floating point number superposition can be improved; and because the mantissa superposition process and the leading zero number prediction process are also executed in parallel, the superposition efficiency of floating point number superposition can be further improved.
In one embodiment, performing a first order processing on the first floating point number and the second floating point number to obtain a first shifted mantissa of the first mantissa and a second shifted mantissa of the second mantissa includes: determining a first difference value between the first exponent and the first leading zero number, and taking the first difference value as a real exponent of the first floating point number; determining first shift information of the first mantissa and second shift information of the second mantissa according to the real exponent and the second exponent; and carrying out shift processing on the first mantissa and the second mantissa in parallel according to the first shift information and the second shift information to obtain the first shift mantissa and the second shift mantissa.
In particular, when it is desired to perform a relative order process on the first floating point number and the second floating point number, the computer device may first determine a true exponent of the first floating point number. The true index refers to removalAfter the leading zero in the first mantissa of the first floating point number, the first floating point number corresponds to the exponent. For example, at the first floating point number 0.011111 ×2 4 When the leading zero in the first mantissa of the first floating point number is removed, the exponent in the first floating point number should be changed so that the first floating point number becomes 0.11111 ×2 in order to ensure that the value of the first floating point number is unchanged 3 And the true index is 3.
Because the first leading zero number characterizes the leading zero number in the first mantissa, when it is desired to determine the true exponent in the first floating point number, the computer device may subtract the first leading zero number from the first exponent to obtain a first difference value, and use the first difference value as the true exponent of the first floating point number. For example, at the first floating point number 0.011111 ×2 4 When the first leading zero number is 1, the computer device may determine that the real exponent is 4-1=3. Further, the computer device determines first shift information in the first mantissa and second shift information in the second mantissa based on the real exponent and the second exponent. The shift information comprises a shift direction and a shift amount, and the computer equipment can carry out shift processing on the mantissa according to the shift direction and the shift amount so as to obtain a shift mantissa. For example, the computer device may perform a shift process on the first mantissa according to the first shift direction and the first shift amount in the first shift information to obtain a first shift mantissa; and performing shift processing on the second mantissa according to a second shift direction and a second shift amount in the second shift information to obtain a second shift mantissa. In order to improve the processing efficiency of the order processing, the computer equipment can shift the first mantissa and the second mantissa in parallel, so that a critical path in the stacking process is greatly shortened, and the stacking efficiency is improved.
In one embodiment, when obtaining the real exponent and the second exponent, the computer device may use a larger value of the real exponent and the second exponent as a reference exponent, or use a smaller value of the real exponent and the second exponent as a reference exponent, or use an intermediate value of the real exponent and the second exponent as a reference exponent, and obtain the first shift information and the second shift information according to the determined reference value, so as to perform shift processing on the first mantissa and the second mantissa based on the first shift information and the second shift information, and obtain the first shift mantissa and the second shift mantissa.
In the above embodiment, since the real index reflects the real index of the first floating point number, the first shift information and the second shift information determined by the second index and the real index reflecting the real condition of the index can be more accurate, thereby improving the accuracy of floating point number superposition.
In one embodiment, the first shift information includes a first shift direction and a first shift amount; the second shift information includes a second shift direction and a second shift amount; determining the first shift information of the first mantissa and the second shift information of the second mantissa based on the real exponent and the second exponent, comprising: when the real index is larger than the second index, taking a preset first direction as a first displacement direction and a preset second direction as a second displacement direction, determining a first displacement according to the real index and the second index, and determining a second displacement according to the first leading zero number; when the real index is smaller than the second index, the first shift amount is determined to be zero, and the second shift direction and the second shift amount are determined according to at least one of the real index, the first index, and the second index.
The shift direction refers to the direction of mantissa shift, and the shift amount refers to the amount of mantissa shift, for example, for "mantissa shift one bit to the left", the shift direction is "left", and the shift amount is "1 bit".
Specifically, in the embodiment of the application, in the process of the opposite-order processing, the small-order code is agreed to be aligned to the large-order code, so that the computer equipment can judge the index size between the real index and the second index, determine the larger value of the real index and the second index according to the index size, take the index with the larger value as the reference index, determine the first shift amount and the first shift direction based on the difference between the first index and the reference index, and determine the second shift amount and the second shift direction based on the difference between the second index and the reference index.
For example, in trueWhen the real index is larger than the second index, the real index may be used as a reference index, so that, in order to make the indexes of the first floating point number and the second floating point number after the opposite-order processing be both reference indexes, the computer device may use a preset first direction as a first shift direction, use a preset second direction as a second shift direction, determine a first shift amount according to the first leading zero number, and determine a second shift amount according to the real index and the second index. The preset first direction may be a "left" direction, and the preset second direction may be a "right" direction. Exemplary, when the first floating point number is 0.011111 ×2 5 And the first leading zero number is 1, the second floating point number is 0.11111 multiplied by 2 2 When the real index is 4, which is greater than the second index 2, the computer device may determine the real index 4 as the reference index. To reduce the first exponent of the first floating point number from 5 to 4, the computer device may move the first mantissa of the first floating point number 1 bit in a left direction (the mantissa is moved to the left so that the magnitude of the floating point number before and after the shift remains unchanged), and thus may determine the first shift direction as a first direction that characterizes the "left" direction and the first shift amount as a first leading zero number. To increase the second exponent of the second floating point number from 2 to 4, the computer device may move the second mantissa of the second floating point number in a right direction (the exponent increases, the mantissa moves to the right, so the magnitude of the floating point number before and after the shift may remain unchanged), and thus the second shift direction may be determined to be a second direction that characterizes the "right" direction, and the second shift amount may be determined from the true exponent and the second exponent.
For another example, when the real index is smaller than the second index, the second index may be used as the reference index. Since the second exponent is greater than the true exponent, the computer device may determine that the second mantissa of the second floating point number is not to be shifted if the contracted small-order code moves to the large-order code, and thus may determine that the second shift direction is absent and that the second shift amount is zero. Further, in order to make the indexes of the first floating point number and the second floating point number after the opposite-order processing be the reference indexes, the computer device may determine according to the first index and the second index The first shift direction and the first shift amount are determined. Exemplary, when the first floating point number is 0.011111 ×2 2 And the first leading zero number is 1, the second floating point number is 0.11111 multiplied by 2 5 When the true index is 1, which is smaller than the second index 5, the computer device may use the second index 5 as the reference index. The computer device may determine that the second shift amount corresponding to the second mantissa is zero and to adjust the first exponent of the first floating point number from 2 to 5, determine a particular first shift direction and first shift amount from the first exponent and the second exponent. For example, the computer device may subtract the second exponent from the first exponent to obtain an exponent difference, and determine the first shift direction and the first shift amount based on the sign of the exponent difference and the magnitude of the difference of the exponent difference. Illustratively, in the above example, 2 may be subtracted by 5 to obtain an exponent difference of-3, and since-3 is a negative number, it may be determined that the first exponent needs to be increased, while the exponent needs to be shifted to the right by the exponent increase, and thus the first shift direction is a second direction that characterizes the "right" direction, and the first shift amount is determined to be 3.
It is easy to understand that the large-order code can be aligned to the small-order code, and the manner of aligning the large-order code to the small-order code can be referred to the manner of aligning the small-order code to the large-order code, which is not described herein.
In one embodiment, when the real exponent is greater than the second exponent, determining the first shift amount from the first leading number of zeros and determining the second shift amount from the real exponent and the second exponent includes: when the real exponent is greater than the second exponent, the first leading zero number is taken as a first shift amount, and a first difference between the real exponent and the second exponent is taken as a second shift amount.
Specifically, when the real exponent is greater than the second exponent, the computer device may take the first leading zero number as a first shift amount and determine a first difference between the real exponent and the second exponent, take the first difference as a second shift amount, so that the first mantissa may be shifted based on the first shift amount and the second mantissa may be shifted based on the second shift amount. For example, when a first floating point number0.011111 ×2 5 And the first leading zero number is 1, the second floating point number is 0.11111 multiplied by 2 2 When the first shift amount is determined to be 1, and the second shift amount is determined to be (5-1) -2=2.
In this embodiment, by using the first leading zero number as the first shift amount, in the subsequent process of shifting the first mantissa based on the first leading zero number, not only the purpose of order matching can be achieved, but also the leading zero in the first mantissa can be removed, so that the first shift mantissa does not include the leading zero, and further the subsequent superposition of the first shift mantissa and the second shift mantissa is facilitated. In addition, under the condition that the number of digits of the mantissa is unchanged, the precision of the mantissa can be improved by removing the leading zero, and further the precision of floating point number superposition is improved. For example, referring to FIG. 3, for a 1B storage space and floating point number 0.01001X 2 1 For the numerical part "01001" of mantissa, the stored number is "0100" and the last digit in "01001" is discarded before the leading zero is not removed; after the leading zero is removed, the floating point number is changed to 0.1001 multiplied by 2 0 For the numerical portion "1001" in mantissa, the stored number is "1001", and any one digit is not discarded, so that the floating point number 0.1001 ×2 0 Can be stored in its entirety, compared to the floating point number 0.0100 x 2 stored prior to the division of the leading zero 1 And the accuracy of the data is improved. FIG. 3 illustrates a schematic diagram of a storage space in one embodiment.
In one embodiment, when the real index is smaller than the second index, determining the second shift direction and the second shift amount according to the first index and the second index includes: subtracting the real index from the second index to obtain a second difference; when the first leading zero number is larger than the second difference value, taking a preset first direction as a first shift direction, and taking a third difference value obtained by subtracting the second index from the first index as a first shift value; when the first leading zero number is smaller than the second difference value, taking the preset second direction as a first shift direction, and taking a fourth difference value obtained by subtracting the first index from the second index as a first shift value.
In particular, when the true index is less than the second index, the computer device may compare the second indexThe number minus the true exponent yields a second difference. The computer device determines whether the first leading zero number is greater than the second difference value, and if the first leading zero number is greater than the second difference value, characterizes the first index as being greater than the second index. Since the real index is to be aligned with the second index when the real index is smaller than the second index, when the first index is larger than the second index, the first direction representing the "left" direction needs to be used as the first shift direction, so that the first index can be reduced, and further the first index can be aligned with the second index, and at this time, the first shift amount is a third difference value obtained by subtracting the second index from the first index. Exemplary, when the first floating point number is 0.000111 ×2 6 And the first leading zero number is 3, the second floating point number is 0.11111 multiplied by 2 4 When the true exponent is 3 and less than the second exponent 4, the second difference is 1, and the first leading zeros number 3 is greater than the second difference 1. At this time, the first exponent 6 is smaller than the second exponent 4, and in order to look at the second exponent, the first mantissa needs to be shifted to the left by 2 bits so that the first exponent decreases from 6 to 4, so that the computer device determines the first shift direction as the first direction representing the "left" direction, and the first shift amount is the third difference 2 obtained by subtracting the second exponent from the first exponent.
And if the first leading zero number is smaller than the second difference value, the first index is represented to be smaller than the second index. Since the real index is to be aligned with the second index when the real index is smaller than the second index, when the first index is smaller than the second index, the second direction representing the right direction needs to be used as the first shift direction, so that the first index can be increased, and further the first index can be aligned with the second index, and at this time, the first shift amount is a fourth difference value obtained by subtracting the first index from the second index. Exemplary, when the first floating point number is 0.011111 ×2 2 And the first leading zero number is 1, the second floating point number is 0.11111 multiplied by 2 5 When the true exponent is 1, less than the second exponent 5, the second difference is 4, and the first leading zeros number 1 is less than the second difference 4. At this time, the first exponent 2 is smaller than the second exponent 5, and in order to look at the second exponent, the first mantissa needs to be shifted by 3 bits in the right direction, so that the first exponent increases from 2 to 5,the computer device thus determines the first shift direction as the second direction characterizing the "right" direction and the first shift amount as the fourth difference 3 of the second index minus the first index.
In one embodiment, the scalars are performed before the shift mantissas are superimposed, and the following is a complete example of performing the scalars. Assuming that the second exponent exp_a of the second floating point number a, the first exponent of the first floating point number partial sum is exp_partial, and the first leading zero number of the first mantissa is lz, according to three inputs of exp_a, exp_partial and lz, second shift information of the second mantissa mant_a and first shift information of the first mantissa_partial can be obtained.
The real index of the first floating point number is exp_partial_real=exp_partial-lz, and the computer equipment compares the sizes of exp_partial_real and exp_a to obtain the first shift information and the second shift information. If exp_partial_real is greater than exp_a, then it needs to be looked at to exp_partial_real, and if exp_partial_real is less than exp_a, then it needs to be looked at to exp_a. The specific shift direction and shift amount are calculated as follows:
let shift_amt_a be the second shift amount corresponding to the second mantissa.
(1) If exp_partial_real is greater than exp_a, then a right shift operation is required for the second mantissa mant_a, and the second shift amount shift_amt_a=exp_partial_real-exp_a;
(2) If exp_partial_real is smaller than exp_a, the shift operation on the second mantissa mant_a is not required, and the second shift amount shift_amt_a=0.
Let shift_amt_partial be the first shift amount corresponding to the first mantissa.
(1) If exp_partial_real is greater than exp_a, then a left shift operation is required for the first mantissa mant_partial, and the first shift amount shift_amt_partial=lz;
(2) If exp_partial_real is smaller than exp_a and lz is larger than exp_a-exp_partial_real, then a left shift operation is required for the first mantissa mant_partial, and the first shift amount shift_amt_partial=lz- (exp_a-exp_partial_real) =lz-exp_a+exp_partial-lz=exp_partial-exp_a;
(3) If exp_partial_real is smaller than exp_a and lz is smaller than exp_a-exp_partial_real, then a right shift operation on the first mantissa mant_partial is required and the first shift amount shift_amt_partial= (exp_a-exp_partial_real) -lz=exp_a-exp_partial+lz-lz=exp_a-exp_partial.
After determining the first shift information and the second shift information, the computer device may shift the first mantissa and the second mantissa based on the first shift information and the second shift information. For example, when the first floating point number is 0.011111 ×2 for the case where the real exponent exp_partial_real is greater than exp_a of the second exponent 5 The second floating point number is 0.11111 multiplied by 2 2 When the first shift amount is 1, the second shift amount is 2, the first moving direction is a first direction representing a left direction, and the second moving direction is a second direction representing a right direction, at this time, the computer device moves 1 bit left in the first mantissa, thereby obtaining a first moving mantissa 0.11111; the computer device shifts the second mantissa to the right by 2 bits resulting in a second shifted mantissa 0.0011111.
In the above embodiment, when the real exponent is taken as the reference exponent and the first mantissa is moved to the left in the process of looking up the real exponent, not only all or part of the leading zeros in the first mantissa are removed, but also the aim of matching the order can be achieved. That is, in the embodiment of the present application, the two purposes of leading zero removal and order matching can be achieved by performing a shift on the first mantissa once, and compared with the traditional method of leading zero removal and order matching in the floating point number stacking process, the method of the present application can simultaneously perform leading zero removal and order matching, thereby improving the stacking efficiency of floating point number stacking. And as described above, the leading zero removal can also improve the precision of the floating point number stored by the computer, so that the embodiment of the application can also improve the precision of the stored first floating point number by removing the leading zero, thereby improving the precision of the floating point superposition number generated by the first floating point number based on precision improvement.
In one embodiment, in performing the order-matching process, the computer device may further determine the post-stack index in parallel, and the computer device may determine the post-stack index by the formula exp_next=max (exp_a, exp_partial-lz), exp_next. Wherein exp_next is the post-stack exponent, exp_a is the second exponent, and (exp_partial-lz) is the real exponent. That is, since the contracted small-order code is aligned to the large-order code, the computer device may take the larger value of the second exponent and the real exponent as the superimposed exponent and register the superimposed exponent through the register.
In one embodiment, shifting the first mantissa and the second mantissa in parallel according to the first shift information and the second shift information to obtain the first shift mantissa and the second shift mantissa includes: the method comprises the steps of obtaining a first shift mantissa through a preset first shifter and carrying out shift processing on the first mantissa according to first shift information; the first candidate shift mantissa is obtained through a preset second shifter and shift processing is carried out on the second mantissa according to second shift information; the second candidate shift mantissa is obtained through a preset third shifter and shift processing is carried out on the second mantissa according to the second shift information; screening a second shift mantissa from the first candidate shift mantissa and the second candidate shift mantissa through a preset selector according to the second shift information; the first shifter, the second shifter and the third shifter are used for carrying out shift processing on corresponding mantissas in parallel.
In particular, a shifter may be provided in the computer device, by which the respective mantissas are shifted. For example, as analyzed above, since the second mantissa will only shift in the second direction that characterizes the "right" direction, and the first mantissa may shift in the second direction that characterizes the "right" direction, or in the first direction that characterizes the "left" direction, to shift the first mantissa and the second mantissa in parallel, the efficiency of mantissa shift may be improved, and three shifters as shown with reference to fig. 4 may be provided in the computer device. Wherein the first shifter is a second direction shifter for shifting the mantissa in a second direction characterizing the "right" direction; the second shifter is a first direction shifter for shifting the mantissa in a first direction that characterizes the "left" direction; the third shifter is also a second direction shifter for shifting the mantissa in a second direction representing the "right" direction.
Further, since the second mantissa will only be shifted in the second direction representing the "right" direction, the computer device may input the second mantissa and the second shift information into the first shifter for shifting the mantissa in the second direction, so that the first shifter shifts the second mantissa according to the second shift information to obtain the second shifted mantissa. Since the first mantissa may be shifted in a first direction characterizing a "left" direction and possibly also in a second direction characterizing a "right" direction, the computer device may input the first shift information and the first mantissa to a second shifter for shifting the mantissa in the first direction and the first shift information and the first mantissa to a third shifter for shifting the mantissa in the second direction, output a first candidate shift mantissa by the second shifter based on the input first shift information and the first mantissa, and output a second candidate mantissa by the third shifter based on the input first shift information and the first mantissa. Further, since the second shifter and the third shifter each output a shift result, a selector is further required to be provided, and the first shift mantissa is selected from the first candidate shift mantissa and the second candidate shift mantissa by the provided selector. Fig. 4 shows a schematic diagram of a shifter in one embodiment.
It is noted that the first shifter, the second shifter and the third shifter work in parallel, and the shift efficiency of mantissas is improved by parallel work, so that the superposition efficiency of floating point numbers is improved.
In one embodiment, when the second direction representing the "left" direction is taken as the first shift direction, since the second shifter is a shifter for shifting the mantissa toward the first direction, the second shifter cannot shift the first mantissa normally based on the first shift information, and at this time, the second shifter may output a random number generated randomly. Since the third shifter is a shifter for shifting the mantissa in the second direction, the third shifter can normally shift the first mantissa based on the first shift information, at which time the third shifter outputs a normal shift result. When the first direction representing the "right" direction is taken as the first shift direction, the second shifter outputs a normal shift result, and the third shifter outputs a random value, similarly to the above.
In one embodiment, the first shifter, the second shifter and the third shifter may be all shifters written by a program, or may be shifters composed of circuits.
In the embodiment, by arranging the three shifters and performing shift processing on the corresponding mantissas in parallel through the three shifters, the mantissa shift efficiency is greatly improved, and the floating point number superposition efficiency is further improved.
In one embodiment, the selecting, by a preset selector and according to the first bit information, the first shift mantissa from the first candidate shift mantissa and the second candidate shift mantissa includes: when the selector determines that the first shifting direction in the first shifting information is a preset second direction, the selector takes the first candidate shifting mantissa generated by the second shifter as a first shifting mantissa; when the selector determines that the first shift direction in the first shift information is the preset first direction, the selector takes the second candidate shift mantissa generated by the third shifter as the first shift mantissa.
Specifically, when the first direction representing the "left" direction is taken as the first shift direction, since the second shifter is a shifter for shifting the mantissa toward the first direction, the selector takes the first candidate shift mantissa generated by the second shifter as the first shift mantissa. When the second direction representing the "right" direction is taken as the first shift direction, the selector takes the second candidate shift mantissa generated by the third shifter as the first shift mantissa, since the third shifter is a shifter for shifting the mantissa toward the second direction.
In one embodiment, for the remaining floating point number processing rounds other than the first floating point number processing round, the first floating point number is a superposition result obtained by superposing part of the floating point numbers in the floating point number sequence; the partial floating point number is the floating point number positioned before the currently traversed floating point number in the floating point number sequence; the second floating point number is the currently traversed floating point number in the floating point number sequence; the floating point number superposition result comprises a floating point superposition number and a second leading zero number; after determining the floating point addend of the first floating point number and the second floating point number, the method further comprises: entering a next round of floating point number superposition process, taking a floating point superposition number in a floating point number superposition result as a new first floating point number, determining a next traversed floating point number in a floating point number sequence, taking the next traversed floating point number as a new second floating point number, returning to the step of obtaining a first exponent of the first floating point number, a first mantissa and a first leading zero number of the first mantissa, and continuing to execute until the last floating point number in the floating point number sequence is traversed, so as to obtain a target floating point superposition number after superposition of each floating point number in the floating point number sequence; and converting the target floating point superposition number into a standard floating point number format to obtain the standard floating point superposition number.
Specifically, in the field of artificial intelligence, there is a situation that a series of floating point numbers are continuously overlapped, so the computer equipment can also adopt the floating point number processing method to sequentially overlap a series of floating point numbers. More specifically, when floating points in the floating point sequence need to be stacked in turn, the computer device may traverse the floating points in the floating point sequence, the second floating point may be a floating point traversed currently, the first floating point may be a result of stacking floating points located before the floating point traversed currently in the floating point sequence, that is, the first floating point may be a stacked result obtained by stacking floating points located before the second floating point in the floating point sequence. For example, when the floating point number traversed currently is the fourth number in the floating point number sequence, the second floating point number is the fourth number in the floating point number sequence, and the first floating point number is a superposition result obtained by superposing the first number, the second number and the third number in the floating point number sequence. Wherein the computer device may superimpose floating point numbers preceding the second floating point number according to the floating point number processing method mentioned in the present application. For example, in the above example, the computer device may first superimpose the first bit number and the second bit number in the floating-point number sequence to obtain a corresponding floating-point number superimposed result, and superimpose the corresponding floating-point number superimposed result and the third bit number in the floating-point number sequence to obtain the first floating-point number.
Further, the computer device may superimpose the first floating point number and the second floating point number according to the method described in steps 202 to 208, so as to obtain a floating point number superimposing result after the first floating point number and the second floating point number are superimposed. When the floating point number superposition result obtained after the first floating point number and the second floating point number are superposed is obtained, the computer equipment can enter the next round of superposition process, the floating point number superposition result generated in the previous round of superposition process is used as a new first floating point number, the next traversed floating point number in the floating point number sequence is determined, the next traversed floating point number is used as a new second floating point number, and the step 202 is returned to continue to be executed until the last floating point number in the floating point number sequence is traversed, and the target floating point number superposition result obtained after the floating point numbers in the floating point number sequence are superposed is obtained. Similar to the floating point number overlay result, the target floating point number overlay result includes not only the target floating point overlay number, but also a third leading zero number of a third mantissa of the target floating point overlay number.
Further, when the target floating point overlay result is obtained, the computer device may format convert the target floating point overlay number in the target floating point overlay result to obtain a standard overlay number having a standard floating point number format.
In one embodiment, referring to FIG. 5, assume that there are 4 numbers (floating point A, floating point B, floating point C, and floating point D) in the sequence of floating point numbers. In the first round of floating point number superposition process, the computer device may use a first floating point number in the floating point number sequence as a first floating point number, use a second floating point number in the floating point number sequence as a second floating point number, and identify a leading zero number of a first mantissa in the first floating point number to obtain the parameter lz. Further, the computer device superimposes the floating point number a and the floating point number B according to the method described in steps 204 to 208, to obtain a floating point number superimposed result a. Further, the computer device enters the floating point number processing process of the next round, the computer device takes the floating point number in the floating point number superposition result a as a new first floating point number, takes the floating point number C in the floating point number sequence as a new second floating point number, and since the floating point number superposition result a already includes the leading zero number of the mantissa, that is, the first leading zero number of the new first floating point number, the computer device can directly return to the step 202 for continuous execution without identifying the first leading zero number, that is, the computer device directly acquires the corresponding mantissa, the corresponding exponent and the corresponding leading zero number of the floating point superposition number in the floating point number superposition result a, and does not need to identify the leading zero number of the floating point superposition number in the floating point number superposition result a any more, and continuously execute based on the acquired corresponding mantissa, corresponding exponent and corresponding leading zero number to acquire the floating point superposition result b. The floating point number superposition result comprises floating point superposition numbers and leading zero numbers, wherein the floating point superposition numbers are floating point numbers obtained by combining the superposed exponents and the superposed mantissas, and the leading zero numbers are numbers obtained by predicting the superposed mantissas. Similarly, the computer device may superimpose the floating point superimposed number b with the floating point number D in the floating point number sequence to obtain a floating point superimposed result c. Since floating point number D is the last floating point number in the sequence of floating point numbers, the computer device takes floating point overlay result c as the target floating point overlay result. FIG. 5 illustrates a schematic diagram of the sequential stacking of floating point numbers in one embodiment.
In one embodiment, for a first floating point processing round, a first floating point is the first floating point in the sequence of floating points and a second floating point is the next floating point in the sequence of floating points immediately adjacent to the first floating point. For the other rounds except the first floating point number processing round, the second floating point number is the currently traversed floating point number in the floating point number sequence, and the first floating point number is a floating point superposition number obtained by superposing the floating point numbers before the second floating point number in the floating point number sequence.
In one embodiment, the application can determine the exponent after superposition according to the first exponent, the first leading zero number and the second exponent while performing the order-matching processing on the first floating point number and the second floating point number, and predict the second leading zero number of the superposed mantissa based on the first displacement mantissa and the second displacement mantissa while superposing the first displacement mantissa and the second displacement mantissa, and shift the first mantissa and the second mantissa in parallel in the order-matching processing on the first floating point number and the second floating point number. For example, referring to fig. 6, the computer device may input a floating point number to be stacked in each clock cycle, so that in each clock cycle, the computer device may stack the floating point number stacking result with the input floating point number to be stacked to obtain a new floating point number stacking result. The clock period may specifically be a clock period of the AI processor. FIG. 6 illustrates a schematic diagram of floating point number superposition in one embodiment.
In one embodiment, referring to fig. 7, the computer device may perform the process of "performing a first order process on the first floating point number and the second floating point number, determining an post-stack exponent based on the first exponent, the first leading zero number, and the second exponent, stacking the first displacement mantissa and the second displacement mantissa to obtain a post-stack mantissa, predicting the second leading zero number of the post-stack mantissa based on the first displacement mantissa and the second displacement mantissa, determining a floating point stacking result after stacking the first floating point number and the second floating point number based on the post-stack mantissa, the post-stack exponent, and the second leading zero number" in process 1, and perform the process of "performing a format conversion on the target floating point stacking result to obtain a standard floating point stacking result having a standard floating point number format". In the process 1, the operations such as format conversion are not needed, and the operations such as format conversion are only needed after all floating point numbers are overlapped, so that a critical path is greatly shortened, and power consumption is saved. In addition, the application shortens the critical path without adding extra computing resources, so the application consumes resources equivalent to a common floating point adder, consumes less chip area resources, reduces the area consumption and improves the surface effect ratio. FIG. 7 illustrates an overall framework diagram of floating point number overlay in one embodiment.
In one embodiment, the target floating point number overlay result includes a target floating point overlay number and a third leading zero number of a third mantissa of the target floating point overlay number; performing format conversion on the target floating point number superposition result to obtain a standard floating point superposition number with a standard floating point number format, wherein the format conversion comprises the following steps: normalizing the target floating point superposition number according to the third leading zero number of the third mantissa of the target floating point superposition number to obtain a normalized floating point superposition number; and rounding the normalized floating point addend to obtain the standard floating point addend.
The standard floating point number format may be specifically a floating point number format conforming to the IEEE754 standard. The IEEE754 standard logically represents a floating point number V by a triplet { S, E, M }, i.e., V= (-1) s ×(1+M)×2 (E+127) (single precision); v= (-1) S ×(1+M)×2 (E+1023) (double precision); since the computer device stores binary numbers, reflecting the binary numbers in the storage space, referring to fig. 8, ieee754 shows floating point numbers as three parts including S, E, M, S is a sign bit, and E is an exponent bit (including E 1 …E w-1 ) M is mantissa bits (including M 1 …M p-1 ). FIG. 8 illustrates a schematic diagram of a storage structure of floating point numbers in one embodiment.
Specifically, the target floating point number superposition result may include a third leading zero number including the target floating point superposition number and a third mantissa of the target floating point superposition number, for example, the target floating point superposition result may be "0.0011×2 3 Lz=2 ", wherein the symbol lz represents the third leading zero number. As will be readily appreciated, since the computer device stores data into the storage space, and the number stored in the storage space is 0 or 1, for the target floating point number, the computer device stores the form 0 or 1 corresponding to the target floating point number, for example, referring to fig. 9, for the floating point number in the custom format, the computer device can pass through the storage space as shown in fig. 9Floating point numbers are stored. For example, "0.0011×2" for floating point numbers 3 The computer device converts 0.0011 to the corresponding 0, 1 form (e.g., 0011, conceals the most significant 0), converts exponent 3 to the corresponding 0, 1 form (e.g., 011), and stores the data in the 0, 1 form in the memory space as shown in fig. 9. FIG. 9 illustrates a schematic diagram of a storage structure of floating point numbers in one embodiment.
Further, for the floating point number in IEEE754 format, the most significant bit in the mantissa of the floating point number is 1, and the exponent needs to be converted to binary for storage after being added with 127 or 1023. Therefore, in order to convert the floating point number in the custom format into the floating point number in IEEE754 format, that is, in order to convert the target floating point addend into the standard floating point addend in the standard floating point format, the computer device performs normalization processing on the target floating point addend according to the third leading zero number of the third mantissa of the target floating point addend, so as to change the highest order of the third mantissa of the target floating point addend into 1, to obtain the normalized floating point addend; because the normalizing process is performed on the target floating-point addend to obtain the normalized floating-point number, in order to make the value size of the normalized floating-point number as close as possible to the value size of the target floating-point addend, rounding operation is further performed on the normalized floating-point addend to obtain the standard floating-point addend.
In one embodiment, normalizing the target floating point addend according to a third leading zero number of a third mantissa of the target floating point addend to obtain a normalized floating point addend includes: adding 1 to the third leading zero quantity to obtain a third shift quantity; shifting the third mantissa to the left by a third shift amount to obtain a fourth mantissa, and subtracting the third shift amount from the third exponent to obtain a fourth exponent; the normalized floating point addend is determined from the fourth exponent and the fourth mantissa.
Specifically, the computer device adds 1 to the third leading zero number to obtain a third shift amount, and then shifts the third digit by the third shift amount to the left to obtain a fourth mantissa, so that the highest bit 1 of the fourth mantissa can be obtained. Further, since the third mantissa is shifted, the computer apparatus also needs to adjust the size of the third exponent of the target floating point addend to keep the value size unchanged. The computer device subtracts the third shift amount from the third exponent to obtain a fourth exponent, and obtains a normalized floating point addend based on the fourth exponent and the fourth mantissa. For example, when the fourth exponent is a binary number stored in the exponent bits shown in fig. 9, the computer device adds the binary number corresponding to 127 or the binary number corresponding to 1023 to the fourth exponent to obtain a modified exponent that can be stored in the exponent bits shown in fig. 8 in accordance with the IEEE754 format, and then the computer device stores the fourth mantissa in the mantissa bits in fig. 8 and stores the modified indication in the exponent bits in fig. 8 to obtain the normalized floating point superposition.
In one embodiment, since the third mantissa of the target floating point superposition is obtained by superposition of the first shifted mantissa and the second shifted mantissa, the probability of overflow may occur when the first shifted mantissa is superimposed with the second shifted mantissa. When the sum of the first shift mantissa and the second shift mantissa overflows, the computer device may right normalize a third mantissa of the target floating point addend, i.e., move the third mantissa to the right, to obtain a normalized floating point addend.
In one embodiment, since the mantissa is left or right shifted, a rounding operation is also required to keep the value size as unchanged as possible. The computer apparatus may perform a rounding operation on the shifted third mantissa (i.e., the fourth mantissa) according to a preset rounding rule to obtain a fifth mantissa, e.g., the rounding operation may be performed according to a 0-house-1 method, or a constant-1 method, such that a difference in value between the standard floating point addend and the normalized floating point addend obtained after performing the rounding operation is less than or equal to a difference threshold.
In the above embodiments, the target floating point addend may be converted into a standard floating point addend conforming to the standard floating point format by performing normalization and rounding operations, and thus, subsequent processing by the Ai processor based on the standard floating point addend conforming to the standard floating point format may be facilitated.
In one embodiment, the second floating point number is a floating point number derived from an artificial intelligence domain; the first floating point number is determined based on the superposition result of a plurality of floating point numbers from the artificial intelligence field; the floating point number from the artificial intelligence field at least comprises one of training data extracted from a training sample through a machine learning model, data to be detected extracted from an object to be detected through the machine learning model and construction data constructed through the machine learning model; the floating point number processing method is executed by the artificial intelligent processor, and a floating point number superposition result obtained by superposition of the first floating point number and the second floating point number is generated in a unit clock period of the artificial intelligent processor.
Specifically, the second floating point number may be a floating point number from the artificial intelligence field, and the first floating point number may be a superposition result obtained by superposing the plurality of floating point numbers. The floating point number derived from the artificial intelligence field includes at least one of training data extracted from a training sample by a machine learning model, data to be detected extracted from an object to be detected by the machine learning model, and construction data constructed by the machine learning model. For example, floating point numbers derived from the artificial intelligence field may be image features extracted from image samples, speech features extracted from speech to be detected, or may be construction data constructed by a machine learning model, etc. It will be readily appreciated that floating point numbers derived from the field of artificial intelligence may also be data obtained from further processing of the image features, speech features or construction data described above. The floating point number processing method related to the embodiment of the application can be executed by the artificial intelligent processor, and can realize the superposition of the first floating point number and the second floating point number in one clock period of the artificial intelligent processor so as to obtain a floating point number superposition result, thereby greatly improving the processing efficiency of the floating point number.
In the application, the floating point number from the artificial intelligence field is obtained, and the floating point number from the artificial intelligence field can be overlapped by the floating point number processing method in the embodiment of the application, so that the data processing efficiency of the artificial intelligence field can be improved.
In one embodiment, referring to FIG. 10, FIG. 10 illustrates a floating point number processing method in one embodiment, comprising the steps of:
s1002, a computer device obtains a first exponent of a first floating point number, a first mantissa, and a first leading zero number of the first mantissa, and the computer device obtains a second exponent and a second mantissa of a second floating point number superimposed with the first floating point number.
At S1004, the computer device determines a first difference between the first exponent and the first leading zero number, and uses the first difference as a true exponent of the first floating point number.
S1006, when the real index is larger than the second index, the computer device uses the preset first direction as a first shift direction, uses the preset second direction as a second shift direction, determines a first shift amount according to the first leading zero number, and determines a second shift amount according to the real index and the second index.
S1008, when the real exponent is greater than the second exponent, the computer device takes the first leading zero amount as a first shift amount and takes a first difference between the real exponent and the second exponent as a second shift amount.
S1010, when the true index is smaller than the second index, subtracting the true index from the second index by the computer equipment to obtain a second difference value; when the first leading zero number is larger than the second difference value, taking a preset first direction as a first shift direction, and taking a third difference value obtained by subtracting the second index from the first index as a first shift value; when the first leading zero number is smaller than the second difference value, taking the preset second direction as a first shift direction, and taking a fourth difference value obtained by subtracting the first index from the second index as a first shift value.
S1012, through a preset first shifter, shifting the second mantissa according to the second shifting information to obtain a second shifting mantissa.
S1014, through a preset second shifter, shifting the first mantissa according to the first shifting information to obtain a first candidate shifting mantissa.
S1016, through a preset third shifter, shifting the first mantissa according to the first shifting information to obtain a second shifting mantissa.
S1018, screening the first shift mantissa from the first candidate shift mantissa and the second candidate shift mantissa through a preset selector according to the first bit information; the first shifter, the second shifter and the third shifter are used for carrying out shift processing on corresponding mantissas in parallel.
S1020, in the process of shifting the corresponding mantissas through the first shifter, the second shifter and the third shifter in parallel, the computer equipment determines the exponent after superposition according to the first exponent, the first leading zero number and the second exponent.
S1022, in parallel, the computer device superimposes the first displacement mantissa and the second displacement mantissa to obtain a superimposed mantissa, and predicts a second leading zero number of the superimposed mantissa based on the first displacement mantissa and the second displacement mantissa.
S1024, the computer equipment determines a floating point number superposition result after the first floating point number and the second floating point number are superposed according to the superposed mantissa, the superposed exponent and the second leading zero number.
S1026, entering a next round of floating point number superposition process, wherein the computer equipment takes a floating point superposition number in a floating point number superposition result as a new first floating point number, determines a floating point number to be traversed next in a floating point number sequence, takes the floating point number to be traversed next as a new second floating point number, and returns the steps of obtaining the first exponent of the first floating point number, the first mantissa and the first leading zero number of the first mantissa to continue to be executed until the last floating point number in the floating point number sequence is traversed, so that a target floating point number superposition result after superposition of each floating point number in the floating point number sequence is obtained.
S1028, the computer equipment performs format conversion on the target floating point number superposition result to obtain a standard floating point superposition number with a standard floating point number format.
In this embodiment, since the order processing and the determination of the post-superposition index are performed in parallel, the superposition efficiency of floating point number superposition can be improved; and because the mantissa superposition and the leading zero number prediction are also executed in parallel, the superposition efficiency of floating point number superposition can be further improved.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
The application also provides an application scene, which applies the floating point number processing method. Specifically, the floating point number processing method is applied to the application scene as follows:
the computer equipment is operated with a face recognition model, when the face recognition model obtains a face image to be recognized, the computer equipment can extract a face feature matrix from the face image to be recognized, and perform superposition operation on floating points in the face feature matrix according to the floating point processing method to obtain target face features, so that the face in the face image to be recognized is recognized based on target face recognition.
The application further provides an application scene, and the application scene applies the floating point number processing method. Specifically, the floating point number processing method is applied to the application scene as follows:
the computer equipment is provided with a voice recognition model in operation, when the voice recognition model obtains voice to be recognized, the computer equipment can extract voice characteristics from the voice to be recognized and perform characteristic processing on the voice characteristics to obtain a data matrix, wherein floating points are stored in the data matrix, so that the voice recognition model can superimpose the floating points in the data matrix according to the floating point processing method to obtain a floating point superposition result, and the floating point superposition result is processed to obtain a voice recognition result.
The above application scenario is only illustrative, and it is to be understood that the application of the schedule synchronization method provided by the embodiments of the present application is not limited to the above scenario.
Based on the same inventive concept, the embodiment of the application also provides a floating point number processing device for realizing the floating point number processing method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in the embodiments of the floating point number processing device or devices provided below may refer to the limitation of the floating point number processing method hereinabove, and will not be repeated herein.
In one embodiment, as shown in FIG. 11, there is provided a floating point number processing apparatus 1100, a data acquisition module 1102, a parallel processing module 1104, a data generation module 1106, and a return module 1108, wherein:
a data obtaining module 102, configured to obtain a first exponent of the first floating point number, a first mantissa, and a first leading zero number of the first mantissa, and obtain a second exponent of the second floating point number and a second mantissa superimposed with the first floating point number; for the rest floating point number processing rounds except the first floating point number processing round, the second floating point number is the currently traversed floating point number in the floating point number sequence, and the first floating point number is a floating point superposition number obtained by superposing the floating point numbers before the second floating point number in the floating point number sequence.
A parallel processing module 1104, configured to perform a first-order processing on the first floating point number and the second floating point number in parallel to obtain a first shift mantissa of the first mantissa and a second shift mantissa of the second mantissa, and determine a post-stack exponent according to the first exponent, the first leading zero number, and the second exponent; in parallel, the first and second displacement mantissas are superimposed to obtain a superimposed mantissa, and a second leading zero number of the superimposed mantissa is predicted based on the first and second displacement mantissas.
The data generating module 1106 is configured to determine a floating point number superposition result obtained by superposing the first floating point number and the second floating point number according to the post-superposition mantissa, the post-superposition exponent and the second leading zero number.
The return module 1108 is configured to take the floating point superposition number in the floating point superposition result as a new first floating point number, determine a floating point number to be traversed next in the floating point sequence, take the floating point number to be traversed next as a new second floating point number, enter a next floating point number processing round, and return the steps of obtaining the first exponent of the first floating point number, the first mantissa and the first leading zero number of the first mantissa to continue to be executed until the last floating point number in the floating point sequence is traversed, so as to obtain a target floating point superposition result after superposition of the floating points in the floating point sequence.
In one embodiment, for a first floating point processing round, the first floating point is a first floating point in the sequence of floating points, and the second floating point is a next floating point in the sequence of floating points immediately adjacent to the first floating point.
In one embodiment, the parallel processing module 1104 is further configured to determine a first difference between the first exponent and the first leading zero number, and use the first difference as the true exponent of the first floating point number; determining first shift information of the first mantissa and second shift information of the second mantissa according to the real exponent and the second exponent; and carrying out shift processing on the first mantissa and the second mantissa in parallel according to the first shift information and the second shift information to obtain the first shift mantissa and the second shift mantissa.
In one embodiment, the first shift information includes a first shift direction and a first shift amount; the second shift information includes a second shift direction and a second shift amount; the parallel processing module 1104 is further configured to determine a first shift amount according to the first leading zero number, and determine a second shift amount according to the real index and the second index, when the real index is greater than the second index, with the preset first direction being the first shift direction and the preset second direction being the second shift direction; when the real index is smaller than the second index, the second shift amount is determined to be zero, and the first shift direction and the first shift amount are determined according to at least one of the real index, the first index and the second index.
In one embodiment, the parallel processing module 1104 is further configured to use the first leading zero number as the first shift amount and the first difference between the real exponent and the second exponent as the second shift amount when the real exponent is greater than the second exponent.
In one embodiment, the parallel processing module 1104 is further configured to subtract the real exponent from the second exponent to obtain a second difference when the real exponent is less than the second exponent; when the first leading zero number is larger than the second difference value, taking a preset first direction as a first shift direction, and taking a third difference value obtained by subtracting the second index from the first index as a first shift value; when the first leading zero number is smaller than the second difference value, taking the preset second direction as a first shift direction, and taking a fourth difference value obtained by subtracting the first index from the second index as a first shift value.
In one embodiment, the parallel processing module 1104 is further configured to obtain a second shift mantissa by performing shift processing on the second mantissa by using a preset first shifter and according to the second shift information; the first candidate shift mantissa is obtained through a preset second shifter and shift processing is carried out on the first mantissa according to the first shift information; the first mantissa is shifted according to the first shifting information through a preset third shifter, and a second shifting mantissa is obtained; screening a first shift mantissa from the first candidate shift mantissa and the second candidate shift mantissa through a preset selector according to the first bit information; the first shifter, the second shifter and the third shifter are used for carrying out shift processing on corresponding mantissas in parallel.
In one embodiment, the second shifter is a first direction shifter; the first direction shifter is used for shifting the mantissa towards a first direction; the third shifter is a second direction shifter; the second direction shifter is used for shifting the mantissa towards a second direction; the parallel processing module 1104 is further configured to, when the selector determines that the first shift direction in the first shift information is a preset second direction, make the selector use the first candidate shift mantissa generated by the second shifter as the first shift mantissa; when the selector determines that the first shift direction in the first shift information is the preset first direction, the selector takes the second candidate shift mantissa generated by the third shifter as the first shift mantissa.
In one embodiment, the target floating point number overlay result includes a target floating point overlay number and a third leading zero number of a third mantissa of the target floating point overlay number; the floating point number processing device 1100 further includes a format conversion module 1110 for converting, based on a third leading number of zeros of a third mantissa of the target floating point addend, normalizing the target floating point superposition number to obtain a normalized floating point superposition number; and rounding the normalized floating point addend to obtain the standard floating point addend.
In one embodiment, the format conversion module 1110 is further configured to add 1 to the third preamble zero number to obtain a third shift amount; shifting the third mantissa to the left by a third shift amount to obtain a fourth mantissa, and subtracting the third shift amount from the third exponent to obtain a fourth exponent; the normalized floating point addend is determined from the fourth exponent and the fourth mantissa.
In one embodiment, the floating point number processing device 1100 is further configured to obtain a first floating point number and a second floating point number; the second floating point number is a floating point number derived from the artificial intelligence field; the first floating point number is a superposition result of a plurality of floating point numbers from the artificial intelligence field; the floating point number from the artificial intelligence field at least comprises one of training data extracted from a training sample through a machine learning model, data to be detected extracted from an object to be detected through the machine learning model and construction data constructed through the machine learning model; the floating point number processing method is executed by the artificial intelligent processor, and a floating point number superposition result obtained by superposition of the first floating point number and the second floating point number is generated in a unit clock period of the artificial intelligent processor.
The modules in the floating point number processing device may be implemented in whole or in part by software, hardware, or a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a computer device is provided, which may be a server, and the internal structure of which may be as shown in fig. 12. The computer device includes a processor, a memory, an Input/Output interface (I/O) and a communication interface. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface is connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is for storing floating point number processing data. The input/output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used for communicating with an external terminal through a network connection. The computer program when executed by a processor implements a floating point number processing method.
It will be appreciated by those skilled in the art that the structure shown in FIG. 12 is merely a block diagram of some of the structures associated with the present inventive arrangements and is not limiting of the computer device to which the present inventive arrangements may be applied, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In an embodiment, there is also provided a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the method embodiments described above when the computer program is executed.
In one embodiment, a computer-readable storage medium is provided, storing a computer program which, when executed by a processor, implements the steps of the method embodiments described above.
In one embodiment, a computer program product or computer program is provided that includes computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in the above-described method embodiments.
It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (19)
1. A method of floating point number processing, the method comprising:
acquiring a first exponent of a first floating point number, a first mantissa and a first leading zero number of the first mantissa, and acquiring a second exponent and a second mantissa of a second floating point number overlapped with the first floating point number;
in parallel, performing a first order-matching process on the first floating point number and the second floating point number to obtain a first shift mantissa of the first mantissa and a second shift mantissa of the second mantissa, and determining a post-superposition exponent according to the first exponent, the first leading zero number and the second exponent;
In parallel, superposing the first displacement mantissa and the second displacement mantissa to obtain a superposed mantissa, and predicting a second leading zero number of the superposed mantissa based on the first displacement mantissa and the second displacement mantissa;
and determining a floating point number superposition result after superposition of the first floating point number and the second floating point number according to the superposition mantissa, the superposition exponent and the second leading zero number.
2. The method of claim 1, wherein performing a scaling process on the first floating point number and the second floating point number to obtain a first shifted mantissa of the first mantissa and a second shifted mantissa of the second mantissa comprises:
determining a first difference between the first exponent and the first leading zero number, and taking the first difference as a true exponent of the first floating point number;
determining first shift information of the first mantissa and second shift information of the second mantissa according to the real exponent and the second exponent;
and carrying out shift processing on the first mantissa and the second mantissa in parallel according to the first shift information and the second shift information to obtain a first shift mantissa and a second shift mantissa.
3. The method of claim 2, wherein the first shift information includes a first shift direction and a first shift amount; the second shift information includes a second shift direction and a second shift amount; the determining the first shift information of the first mantissa and the second shift information of the second mantissa according to the real exponent and the second exponent includes:
when the real index is larger than the second index, taking a preset first direction as a first displacement direction, taking a preset second direction as a second displacement direction, determining a first displacement according to the first leading zero quantity, and determining a second displacement according to the real index and the second index;
when the real index is smaller than the second index, determining that the second shift amount is zero, and determining a first shift direction and a first shift amount according to at least one of the real index, the first index and the second index.
4. A method according to claim 3, wherein said determining a first shift amount from said first leading zero number and a second shift amount from said real exponent and said second exponent when said real exponent is greater than said second exponent comprises:
When the real exponent is greater than the second exponent, the first leading zero amount is taken as a first shift amount, and a first difference between the real exponent and the second exponent is taken as a second shift amount.
5. The method of claim 3, wherein the determining a first shift direction and a first shift amount from at least one of the real index, the first index, and the second index when the real index is less than the second index comprises:
when the real index is smaller than the second index, subtracting the real index from the second index to obtain a second difference value;
when the first leading zero number is larger than the second difference value, taking a preset first direction as a first shift direction, and taking a third difference value obtained by subtracting the second index from the first index as a first shift value;
when the first leading zero number is smaller than the second difference value, taking a preset second direction as a first shift direction, and taking a fourth difference value obtained by subtracting the first index from the second index as a first shift value.
6. The method according to claim 2, wherein the performing shift processing on the first mantissa and the second mantissa in parallel according to the first shift information and the second shift information to obtain a first shift mantissa and a second shift mantissa includes:
The second mantissa is shifted according to the second shifting information through a preset first shifter, and a second shifting mantissa is obtained;
the first mantissa is shifted according to the first shifting information through a preset second shifter, and a first candidate shifting mantissa is obtained;
the first mantissa is shifted according to the first shifting information through a preset third shifter, and a second shifting mantissa is obtained;
screening a first shift mantissa from the first candidate shift mantissa and the second candidate shift mantissa through a preset selector according to the first bit information;
the first shifter, the second shifter and the third shifter are used for carrying out shift processing on corresponding mantissas in parallel.
7. The method of claim 6, wherein the second shifter is a first direction shifter; the first direction shifter is used for shifting the mantissa towards a first direction; the third shifter is a second direction shifter; the second direction shifter is used for shifting the mantissa towards a second direction;
the step of screening the first shift mantissa from the first candidate shift mantissa and the second candidate shift mantissa through a preset selector according to the first bit information includes:
When the selector determines that a first shifting direction in the first shifting information is a preset second direction, the selector takes a first candidate shifting mantissa generated by a second shifter as a first shifting mantissa;
when the selector determines that the first shift direction in the first shift information is a preset first direction, the selector takes the second candidate shift mantissa generated by the third shifter as a first shift mantissa.
8. The method of claim 1, wherein for the remaining floating point number processing rounds other than the first floating point number processing round, the first floating point number is a superposition result obtained by superposing a portion of the floating point numbers in the floating point number sequence; the part of floating point numbers are floating point numbers positioned before the currently traversed floating point number in the floating point number sequence; the second floating point number is the currently traversed floating point number in the floating point number sequence; the floating point number superposition result comprises a floating point superposition number and a second leading zero number;
after the determining the floating point number superposition result after the first floating point number is superposed with the second floating point number, the method further includes:
taking the floating point superposition number in the floating point superposition result as a new first floating point number, determining the next traversed floating point number in the floating point sequence, taking the next traversed floating point number as a new second floating point number, entering the next round of floating point processing process, and returning to the step of obtaining the first exponent of the first floating point number, the first mantissa and the first leading zero number of the first mantissa to continue to execute until the last floating point number in the floating point sequence is traversed, so as to obtain a target floating point superposition result after superposition of all the floating points in the floating point sequence;
And carrying out format conversion on the target floating point number superposition result to obtain a standard floating point superposition number with a standard floating point number format.
9. The method of claim 8, wherein the target floating point number superposition result includes a target floating point superposition number and a third leading zero number of a third mantissa of the target floating point superposition number;
the format conversion is performed on the target floating point number superposition result to obtain a standard floating point superposition number with a standard floating point number format, which comprises the following steps:
normalizing the target floating point superposition number according to the third leading zero number of the third mantissa of the target floating point superposition number to obtain a normalized floating point superposition number;
and rounding the normalized floating point addend to obtain a standard floating point addend.
10. The method of claim 9, wherein normalizing the target floating point addend based on a third leading zero number of a third mantissa of the target floating point addend to obtain a normalized floating point addend, comprising:
adding 1 to the third leading zero quantity to obtain a third shift quantity;
shifting the third mantissa to the left by a third shift amount to obtain a fourth mantissa, and subtracting the third shift amount from the third exponent to obtain a fourth exponent;
And determining a normalized floating point addend according to the fourth exponent and the fourth mantissa.
11. The method of claim 1, wherein the second floating point number is a floating point number derived from an artificial intelligence domain; the first floating point number is determined based on the superposition result of a plurality of floating point numbers from the artificial intelligence field; the floating point number from the artificial intelligence field at least comprises one of training data extracted from a training sample through a machine learning model, data to be detected extracted from an object to be detected through the machine learning model and construction data constructed through the machine learning model; the floating point number processing method is executed by the artificial intelligent processor, and the floating point number superposition result obtained by superposition of the first floating point number and the second floating point number is generated in a unit clock period of the artificial intelligent processor.
12. A floating point number processing apparatus, the apparatus comprising:
the data acquisition module is used for acquiring a first exponent of a first floating point number, a first mantissa and a first leading zero number of the first mantissa, and acquiring a second exponent and a second mantissa of a second floating point number overlapped with the first floating point number; for the other floating point number processing rounds except the first floating point number processing round, the second floating point number is a currently traversed floating point number in a floating point number sequence, and the first floating point number is a floating point superposition number obtained by superposing the floating point number before the second floating point number in the floating point number sequence;
The parallel processing module is used for performing order-matching processing on the first floating point number and the second floating point number to obtain a first shift mantissa of the first mantissa and a second shift mantissa of the second mantissa in parallel, and determining a superposed exponent according to the first exponent, the first leading zero number and the second exponent; in parallel, superposing the first displacement mantissa and the second displacement mantissa to obtain a superposed mantissa, and predicting a second leading zero number of the superposed mantissa based on the first displacement mantissa and the second displacement mantissa;
the data generation module is used for determining a floating point number superposition result obtained by superposing the first floating point number and the second floating point number according to the superposed mantissa, the superposed exponent and the second leading zero number;
and the return module is used for taking the floating point superposition number in the floating point superposition result as a new first floating point number, determining the floating point number traversed to next in the floating point sequence, taking the floating point number traversed to next as a new second floating point number, entering the next floating point number processing round, and returning to execute the steps of acquiring the first exponent, the first mantissa and the first leading zero number of the first mantissa until the last floating point number in the floating point sequence is traversed to obtain a target floating point superposition result after superposition of the floating points in the floating point sequence.
13. The apparatus of claim 12, wherein for a first floating point number processing round, the first floating point number is a first floating point number in the sequence of floating point numbers, and the second floating point number is a next floating point number in the sequence of floating point numbers immediately adjacent to the first floating point number.
14. The apparatus of claim 12, wherein the parallel processing module is further configured to determine a first difference between the first exponent and the first leading number of zeros, and to treat the first difference as a true exponent of the first floating point number; determining first shift information of the first mantissa and second shift information of the second mantissa according to the real exponent and the second exponent; and carrying out shift processing on the first mantissa and the second mantissa in parallel according to the first shift information and the second shift information to obtain a first shift mantissa and a second shift mantissa.
15. The apparatus of claim 12, wherein the target floating point number superposition result comprises a target floating point superposition number and a third leading zero number of a third mantissa of the target floating point superposition number; the floating point number processing device also comprises a format conversion module which is used for carrying out format conversion on the target floating point number superposition result to obtain a standard floating point superposition number with a standard floating point number format.
16. The apparatus of claim 15, wherein the format conversion module is further configured to normalize the target floating point addend to obtain a normalized floating point addend based on a third leading zero number of a third mantissa of the target floating point addend; and rounding the normalized floating point addend to obtain a standard floating point addend.
17. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 11 when the computer program is executed.
18. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 11.
19. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any one of claims 1 to 11.
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