CN117008432A

CN117008432A - Method of manufacturing semiconductor device and semiconductor device manufacturing tool

Info

Publication number: CN117008432A
Application number: CN202310557072.5A
Authority: CN
Inventors: 李蕙君; 冯东鸿; 李邦鼎
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-06-28
Filing date: 2023-05-17
Publication date: 2023-11-07

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device and a semiconductor device manufacturing tool. A method of manufacturing a semiconductor device, comprising: a photoresist layer comprising a photoresist composition is formed over a substrate. The photoresist layer is selectively exposed to actinic radiation. After selectively exposing the photoresist layer to actinic radiation, the photoresist layer is heated. During heating of the photoresist layer, a gas is flowed through the photoresist layer. The flow of gas is changed during heating of the photoresist layer and the photoresist layer is developed after heating of the photoresist layer to form a pattern in the photoresist layer.

Description

Method of manufacturing semiconductor device and semiconductor device manufacturing tool

Technical Field

The present disclosure relates to a method of manufacturing a semiconductor device and a semiconductor device manufacturing tool.

Background

As consumer devices become smaller in response to consumer demand, the dimensions of the various components of these devices also necessarily shrink. Semiconductor devices, which are an integral part of devices such as mobile phones, tablet computers, etc., have been subject to pressure and become smaller, wherein individual devices (e.g., transistors, resistors, capacitors, etc.) within the semiconductor devices are also subject to corresponding pressure and reduced in size.

One implementation technique used in the fabrication process of semiconductor devices is the use of photolithographic materials. Such a material is applied to the surface of the layer to be patterned and then exposed to energy that itself has been patterned. Such exposure changes the chemical and physical properties of the exposed areas of the photosensitive material. Such changes, as well as the lack of changes to the unexposed areas of the photosensitive material, may be used to remove one area without removing another.

However, as the size of individual devices is reduced, the process window for photolithographic processing becomes more and more stringent. Accordingly, advances in the field of photolithographic processing are necessary to maintain the ability to shrink devices, and further improvements are needed to meet the intended design criteria so that smaller and smaller components can be maintained.

As the semiconductor industry moves into nanotechnology process nodes for higher device density, higher performance, and lower cost, challenges continue to exist in reducing semiconductor feature size. Extreme ultraviolet lithography (Extreme ultraviolet lithography, EUVL) has been developed to form smaller semiconductor device feature sizes and to increase device density on semiconductor wafers. In order to increase the efficiency of the EUVL process, it is desirable to reduce EUV exposure dose and improve photoresist performance.

Disclosure of Invention

According to one aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming a photoresist layer comprising a photoresist composition over a substrate; selectively exposing the photoresist layer to actinic radiation; heating the photoresist layer after selectively exposing the photoresist layer to actinic radiation, flowing a gas through the photoresist layer during heating the photoresist layer, wherein the flow of the gas is altered during heating the photoresist layer; and developing the photoresist layer after heating the photoresist layer to form a pattern in the photoresist layer.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming a photoresist layer comprising a photoresist composition over a substrate; patternwise exposing the photoresist layer to actinic radiation; after patternwise exposing the photoresist layer to actinic radiation, baking the photoresist layer, during baking the photoresist layer, flowing a gas through the photoresist layer, wherein during flowing a gas through the photoresist layer, the gas is supplied to a space above the photoresist layer from a gas shower head located above a major surface of the photoresist layer at a first flow rate, and the gas is exhausted from the space above the photoresist layer through one or more gas exhausts located near a periphery of the shower head, wherein the gas is exhausted from the space above the photoresist layer at a second flow rate for a first period of time, and then the gas is exhausted from the space above the photoresist layer at a third flow rate for a second period of time, wherein the third flow rate is greater than the second flow rate; and developing the photoresist layer after baking the photoresist layer to form a pattern in the photoresist layer.

According to yet another aspect of the present disclosure, there is provided a semiconductor device manufacturing tool comprising: a processing chamber; a wafer support disposed inside the processing chamber; a heating element disposed inside the wafer support; a gas manifold disposed over the wafer support, wherein the gas manifold comprises: a plurality of first openings in a surface of the gas manifold facing the wafer support, the plurality of first openings configured to direct a flow of gas through the first openings to the wafer support, and one or more second openings configured to exhaust the gas from the wafer support, wherein the one or more second openings are located in a peripheral portion of the gas manifold or in a central portion of the gas manifold; and a controller configured to control: a flow rate of the gas through the first opening; a flow rate of the gas through the one or more second openings; and the temperature of the heating element.

Drawings

The disclosure may be best understood from the following detailed description when read in connection with the accompanying drawing. It should be noted that the various features are not drawn to scale and are for illustrative purposes only, according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a process flow of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 2 illustrates process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 3A and 3B illustrate process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 4A, 4B, and 4C illustrate process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 5A and 5B illustrate process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 6A, 6B, and 6C illustrate embodiments of a gas shower in accordance with embodiments of the present disclosure.

Fig. 7 illustrates a semiconductor device manufacturing tool according to an embodiment of the present disclosure.

Fig. 8A and 8B illustrate an embodiment of a controller according to an embodiment of the present disclosure.

Fig. 9A and 9B illustrate process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 10A and 10B illustrate process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 11 illustrates process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 12 illustrates process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 13 illustrates process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 14A shows an organometallic precursor according to an embodiment of the present disclosure. Fig. 14B shows the reaction of an organometallic precursor that occurs upon exposure to actinic radiation. Fig. 14C shows an example of an organometallic precursor according to an embodiment of the disclosure.

Fig. 15 illustrates a reaction of photoresist composition components as a result of exposure to actinic radiation and heating in accordance with an embodiment of the present disclosure.

Fig. 16 illustrates a deposition apparatus according to an embodiment of the present disclosure.

Fig. 17 illustrates process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 18A and 18B illustrate process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 19 illustrates process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 20 illustrates process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 21 illustrates process stages of sequential operation according to an embodiment of the present disclosure.

Fig. 22 is a flow chart of a method according to an embodiment of the present disclosure.

Fig. 23 is a flow chart of a method according to an embodiment of the present disclosure.

Fig. 24 is a flow chart of a method according to an embodiment of the present disclosure.

Detailed Description

It should be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or desired characteristics of the device. Furthermore, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features such that the first and second features may not be in direct contact. The various features may be arbitrarily drawn for simplicity and clarity.

Moreover, spatially relative terms such as "below," "beneath," "below," "over," "above," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other directions) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, the term "made of …" may mean "including" or "consisting of …". Furthermore, in the following manufacturing process, there may be one or more additional operations in/between the operations described, and the order of the operations may be changed. Materials, configurations, dimensions, processes and/or operations explained with respect to one embodiment may be used in other embodiments and a detailed description thereof may be omitted. Source/drain region(s) may refer to source or drain, either individually or collectively depending on the context.

Metal-containing photoresists are considered to be highly sensitive and etch-selective photoresists. The metal particles in the metal-containing photoresist absorb high energy photons, such as extreme ultraviolet EUV photons. The metal-containing photoresist includes metal particles and ligands for complexing (complexation) the metal particles. In some embodiments, the metal particles are nanoparticles, and in some embodiments, the metal particles are metal oxide particles. In some embodiments, the metallized core comprising one or more metal nanoparticles is complexed by a plurality of ligand units forming a ligand-complexed metallized core.

The use of a metallized resist (e.g., a tin oxide resist) may reduce the number of resist layers and the number of operations, from three lithography and three etching operations to one lithography and etching operation. However, EUV exposure and metallization of the resist may not be cost effective because EUV exposure requires high doses. In some embodiments of the present disclosure, chamber exhaust is optimized to enhance photoresist cross-linking reactions during post exposure bake (post exposure bake, PEB) processes. As a result, EUV dose and operating costs (cost of operation, coO) of the method according to embodiments of the present disclosure are significantly reduced.

Fig. 1 illustrates a process flow 100 for fabricating a semiconductor device according to an embodiment of the present disclosure. In operation S110, a resist composition is prepared. In some embodiments, the resist is a photoresist.

In some embodiments, in operation S110, a photoresist composition is coated on a surface of a layer or substrate 10 to be patterned to form a resist layer 15, as shown in fig. 2. In some embodiments, the resist layer 15 is a photoresist layer. Then, in some embodiments, the resist layer 15 is subjected to a first baking operation (or pre-exposure baking) S120 to evaporate the solvent in the resist composition. The resist layer 15 is baked (prebaked) at a temperature and for a time sufficient to cure and dry the resist layer 15. In some embodiments, the resist layer is heated to a temperature of about 40 ℃ to about 120 ℃ for a duration of about 10 seconds to about 10 minutes.

After the first (or pre) bake operation S120, the photoresist layer 15 is selectively exposed to actinic radiation 45/97 (see fig. 3A and 3B) in operation S130. In some embodiments, the photoresist layer 15 is selectively exposed to ultraviolet radiation. In some embodiments, the ultraviolet radiation is Deep Ultraviolet (DUV) radiation. In some embodiments, the ultraviolet radiation is Extreme Ultraviolet (EUV) radiation. In some embodiments, the actinic radiation is an electron beam.

In some embodiments, as shown in FIG. 3A, exposure radiation 45 passes through photomask 30 before illuminating photoresist layer 15. In some embodiments, the photomask has a pattern to be replicated in the photoresist layer 15. In some embodiments, the pattern is formed by opaque pattern 35 on photomask substrate 40. The opaque pattern 35 may be formed of a material opaque to ultraviolet radiation, such as chromium, while the photomask substrate 40 is formed of a material transparent to ultraviolet radiation, such as fused silica.

In some embodiments, selective exposure of photoresist layer 15 is performed using extreme ultraviolet lithography to form exposed regions 50 and unexposed regions 52. In an extreme ultraviolet lithography operation, a reflective photomask 65 is used to form patterned exposure light, as shown in FIG. 3B. The reflective photomask 65 includes a low thermal expansion glass substrate 70, and a reflective multilayer 75 of Si and Mo is formed on the low thermal expansion glass substrate 70. A cap layer 80 and an absorber layer 85 are formed over the reflective multilayer 75. A rear conductive layer 90 is formed on the back surface of the low thermal expansion glass substrate 70. In euv lithography, euv radiation 95 is directed toward a reflective photomask 65 at an angle of incidence of about 6 °. The portion 97 of the euv radiation is reflected by the Si/Mo multilayer 75 toward the photoresist coated substrate 10, while the portion of the euv radiation incident on the absorber layer 85 is absorbed by the photomask. In some embodiments, additional optics (including mirrors) are located between reflective photomask 65 and the photoresist-coated substrate.

The radiation-exposed regions 50 of the photoresist layer chemically react, thereby altering the solubility (solubility) of the regions 50 in a subsequently applied developer relative to the non-radiation-exposed regions 52 of the photoresist layer. In some embodiments, the radiation-exposed portions 50 of the photoresist layer undergo a crosslinking reaction.

Next, in operation S140, the photoresist layer 15 is subjected to a second baking operation (or post-exposure baking). In some embodiments, the photoresist layer 15 is heated to a temperature of about 70 ℃ to about 220 ℃ for a duration of about 20 seconds to about 200 seconds. Post-exposure baking may be used to assist in the generation, dispersion, and reaction of acid/base/radicals generated by impingement of radiation 45/97 on photoresist layer 15 during exposure, or to enhance crosslinking of radiation exposed areas 50 of the photoresist layer. This assist helps to create or enhance a chemical reaction that creates a chemical differential between the exposed regions 50 and the unexposed regions 52 within the photoresist layer. These chemical differences further create a difference in solubility between the exposed areas 50 and the unexposed areas 52.

Fig. 4A, 4B, and 4C illustrate a post-exposure bake operation according to an embodiment of the present disclosure. Fig. 4A, 4B, and 4C illustrate a photoresist coated substrate 250 undergoing a post-exposure bake (or heating) operation. A photoresist coated substrate 250 is placed over the heating element 200 (e.g., an electric heater). In some embodiments, heating element 200 is a hot plate (hot plate). In some embodiments, the photoresist coated substrate 250 is supported above the heating element 200 by support pins 210 (see fig. 7). A manifold 220 with a flow of purge gas 230 is located over a photoresist coated substrate 250. The purge gas is then exhausted 275 from the manifold at the center portion of the manifold or at the edge portion of the manifold, as shown in fig. 4A. During post-exposure bake, the purge gas purges out a gas (outgas) from the photoresist layer. In some embodiments, the purge gas is Clean Dry Air (CDA); carbon dioxide; inert gases including nitrogen, helium, neon, and argon; or a combination thereof.

In some embodiments, the manifold 220 is lowered relative to the photoresist coated substrate 250 such that the purge gas 230 flows through the photoresist coated substrate 250, as shown in fig. 4A. In some embodiments, the photoresist coated substrate 250 is lifted toward the manifold by the support pins 210.

In some embodiments, during post-exposure bake (heating), the photoresist layer 15 is heated at a temperature in the range of about 70 ℃ to about 220 ℃ by controlling the temperature of the heating element 200. In some embodiments, during post-exposure bake (heating), the photoresist layer 15 is heated at a temperature in the range of about 100 ℃ to about 200 ℃. In some embodiments, during the post-exposure bake, the photoresist layer 15 is heated at a temperature in the range of about 150 ℃ to about 190 ℃. Heating at temperatures below the recited ranges may result in insufficient crosslinking of the exposed portions of the photoresist layer and insufficient removal of reaction byproducts. Heating the photoresist layer at temperatures above the recited ranges may damage the photoresist layer or other layers of the semiconductor device or unnecessarily increase the cost of the semiconductor device fabrication process.

In some embodiments, the photoresist layer 15 is heated for about 40 seconds to about 200 seconds during the post-exposure bake. In some embodiments, the photoresist layer 15 is heated for about 65 seconds to about 175 seconds. Heating the photoresist layer for a period of time less than the recited range may result in insufficient crosslinking of the exposed portions of the photoresist layer and insufficient removal of reaction byproducts. Heating the photoresist layer for a period of time greater than the recited range may damage the photoresist layer or other layers of the semiconductor device or reduce the yield of the semiconductor device.

In some embodiments, the exhaust flow rate of the purge gas is controlled to increase cross-linking of the photoresist layer and increase removal of photoresist outgassing. As shown in fig. 4B, at higher exhaust flow rates, greater amounts of outgassing, reaction byproducts, and contaminants are removed from the photoresist layer and the processing chamber. However, during the post exposure bake operation, the cross-linking reactant may also be removed using an exhaust gas, resulting in a thinner photoresist layer with reduced amounts of cross-linking, as shown in FIG. 4B. On the other hand, at lower exhaust flow rates, more crosslinking reactant remains in the photoresist layer and a greater amount of crosslinking occurs in the radiation exposed areas of the photoresist layer, as shown in fig. 4C. However, at lower exhaust flow rates, the outgassing of reaction byproducts is less vented, which may result in contamination of the process chamber and semiconductor devices. It is therefore desirable to control the exhaust flow rate so that crosslinking and contaminant removal are optimized. In embodiments of the present disclosure, the exhaust flow rate and post-exposure bake parameters are controlled to optimize photoresist layer crosslinking and contaminant reduction.

In some embodiments, the flow of purge gas 230 through the photoresist layer 15 is varied during the post-exposure bake operation. In some embodiments, as shown in fig. 5A, during a first period of flowing the gas 230 through the photoresist layer 15, the purge gas is discharged from only the gas exhaust 290a located at the edge portion of the manifold 220, and then, as shown in fig. 5B, during a second period of flowing the gas 230 through the photoresist layer 15, the gases 275A, 275B are discharged from the gas exhaust 290a located at the edge portion of the manifold 220 and the gas exhaust 290B located at the center portion of the manifold 220. In some embodiments, the first period of time is longer than the second period of time. In some embodiments, the first period of time is in a range from 40 seconds to 200 seconds and the second period of time is in a range from 2 seconds to 85 seconds. In other embodiments, the first period of time is in a range from about 60 seconds to about 115 seconds, and the second period of time is in a range from about 5 seconds to about 60 seconds.

In some embodiments, the flow rate of the gas 230 supplied to the space above the photoresist layer 15 is in the range from about 1L/min to about 20L/min; during the first and second periods, the exhaust flow rate of the gas 275A through the gas exhaust 290a located at the edge portion of the manifold 220 ranges from about 1L/min to about 20L/min, as shown in fig. 5A and 5B; while no gas is discharged through the gas exhaust 290b located at the central portion of the manifold 220 (flow rate=0), as shown in fig. 5A. Then, in fig. 5B, during the second period, the exhaust flow rate of the gas 275B through the gas exhaust 290B located at the center portion of the manifold 220 is in the range from about 10L/min to about 80L/min, while the flow rate of the inlet gas 230 and the flow rate of the exhaust gas 275a through the gas exhaust 290a located at the edge portion of the manifold 220 are maintained at about 1L/min to about 20L/min. In some embodiments, the flow rate of the inlet gas 230 supplied to the space above the photoresist layer 15 is in the range from about 2L/min to about 10L/min; during the first and second periods, a flow rate of the gas 275a through the gas exhaust 290a at the edge portion of the manifold 220 ranges from about 2L/min to about 10L/min; and during the second period, the flow rate of the gas 275b through the gas exhaust 290b located in the central portion of the manifold 220 is in the range from about 20L/min to about 60L/min. In some embodiments, during the second period, the flow rate of the gas 275b through the gas exhaust 290b located at the central portion of the manifold 220 is greater than the flow rate of the gas 275a through the gas exhaust located at the edge portion of the manifold 220. In some embodiments, during the second period, the flow rate of the gas 275b through the gas exhaust 290b located in the central portion of the manifold 220 is greater than the flow rate of the inlet purge gas 230 supplied through the manifold 220.

In some embodiments, the ratio of the flow rate F2C of the exhaust gas 275b through the gas exhaust 290b located in the center portion of the manifold 220 to the flow rate F2E of the exhaust gas 275a through the gas exhaust 290a located in the edge portion of the manifold during the second time period is in the range from about 1 to about 80, and in other embodiments, the ratio F2C/F2E is in the range from about 2 to about 30. In some embodiments, the ratio of the flow rate F2C of the exhaust gas 275b through the gas exhaust 290b located in the central portion of the manifold 220 to the flow rate F1 of the inlet gas 230 ranges from about 1 to about 80, and in other embodiments, the ratio F2C/F1 ranges from about 2 to about 30. In some embodiments, the ratio of the flow rate F1 of the inlet gas to the flow rate FE of the exhaust gas 275a flowing through the gas exhaust 290a at the edge portion of the manifold during the first period or the second period is in the range from about 0.2 to about 5. In some embodiments, the ratio F1/FE is about 1.

In some embodiments, the ratio of the second period P2 to the first period P1 is in a range from about 0.01 to about 1. In other embodiments, the ratio of the second period of time to the first period of time is in a range from about 0.04 to about 0.5.

The flow rates of the inlet gas 230 and the flow rates of the outlet gases 275a, 275b outside the disclosed ranges or ratios may result in insufficient crosslinking of the exposed portions of the photoresist layer and insufficient removal of reaction byproducts. Similarly, lengths of the first and second time periods outside of the disclosed ranges or ratios may also result in insufficient crosslinking of the exposed portions of the photoresist layer and insufficient removal of reaction byproducts.

In some embodiments, the gas shower 270 is used as a manifold, as shown in plan view in fig. 6A-6C. In some embodiments, the use of the gas shower 270 minimizes turbulence into the purge gas flow 230 and provides improved temperature control of the photoresist coated substrate 250.

In an embodiment, the surface of the showerhead 270 facing the photoresist layer 15 on the photoresist coated substrate 250 is spaced from the major surface of the photoresist layer by a distance in the range of from about 1mm to about 25 mm. In some embodiments, the surface of the showerhead 270 facing the photoresist layer 15 is spaced from the major surface of the photoresist layer 15 by a distance in the range of from about 3mm to about 15 mm.

In some embodiments, the showerhead 270 includes a plurality of openings 280 through which gas flows, as shown in fig. 6A-6C. As shown in fig. 6A, in some embodiments, the plurality of openings are arranged in a row and column arrangement. In some embodiments, each of the plurality of openings 280 has a diameter D1 in a range from about 0.1mm to about 10 mm. In some embodiments, each of the plurality of openings 280 has a diameter D1 in a range from about 1mm to about 5 mm. In some embodiments, the diameter D1 of the plurality of openings 280 is about 2mm. In some embodiments, the plurality of openings 180 have a spacing W1, W2 in the X-direction and the Y-direction in a range from about 0.5mm to about 24 mm. In some embodiments, the plurality of openings 280 have a pitch ranging from about 3mm to about 10 mm. In some embodiments, the plurality of openings 280 have a pitch of about 6 mm. In some embodiments, the X-direction pitch and the Y-direction pitch are substantially the same, and in other embodiments, the X-direction pitch and the Y-direction pitch are different. Openings having pitches outside of the ranges disclosed herein may result in photoresist patterns having reduced critical dimension uniformity and increased line width roughness.

In some embodiments, gas jets 270 are included having other patterns of openings 280. As shown in fig. 6B, in some embodiments, the plurality of openings 280 are arranged in rows, wherein the openings 280 in alternating rows are staggered relative to immediately adjacent rows. In another embodiment, the openings 280 are arranged in concentric circles around the central opening, as shown in FIG. 6C. In some embodiments, the diameter D1 of the opening 280 near the center of the gas shower 270 is greater than the diameter D1 of the opening 280 near the periphery of the gas shower 270. The pattern of openings 280 is not limited to the embodiments shown herein. In other embodiments, other patterns (e.g., spiral patterns, random patterns, etc.) are within the scope of the present disclosure.

A semiconductor device manufacturing tool 300 according to some embodiments of the present disclosure is shown in fig. 7. In some embodiments, the semiconductor device manufacturing tool 300 includes a processing chamber 310, such as a post-exposure bake chamber. The heating element 200 is disposed inside the chamber. In some embodiments, a plurality of support pins 210 are disposed inside the chamber 310. The plurality of support pins 210 are configured to support the photoresist coated semiconductor substrate 250 above the heating element 200. The plurality of support pins 210 are configured to raise and lower the semiconductor substrate 250. In some embodiments, the gas shower 270 is disposed above the heating element. In some embodiments, manifold raising/lowering mechanism 355 raises and lowers manifold 220. In other embodiments, other types of gas manifolds are used, such as gas manifold 220 shown in fig. 4A, 5B, and 9A-10B.

In some embodiments, the semiconductor device manufacturing tool 300 includes a purge gas source 320. The gas source 320 is connected to the manifold 220 by a gas distribution line 325. The gas source 320 supplies purge gas 230 to the manifold. In some embodiments, the first vacuum pump 340a is connected to the gas exhaust 290a located at the peripheral (edge) portion of the manifold 220 through a first vacuum line 345a, and the second vacuum pump 340b is connected to the gas exhaust 290b located at the center portion of the manifold 220 through a second vacuum line 345 b. The vacuum pumps 340a, 340b are used to evacuate the purge gas, photoresist outgassing, and contaminants after the purge gas flows through the photoresist coated substrate 250.

In some embodiments, the controller 400 is configured to control any or all of the following: the flow rate of the purge gas 230 supplied through the gas manifold 220, the flow rate of the exhaust gas 275a flowing through the gas exhaust 290a located at the peripheral (edge) portion of the gas manifold 220, the flow rate of the exhaust gas 275b flowing through the gas exhaust 290b located at the center portion of the gas manifold 220, the temperature of the heating element 200, the movement of the plurality of support pins 210 in the vertical direction, and the movement of the gas manifold 220 in the vertical direction are shown in fig. 7. In some embodiments, the controller 400 controls the mechanism 355 for raising and lowering the gas manifold 220. In some embodiments, adjustable valves 335, 370a, and 370b are in the gas distribution line 325 and vacuum lines 345a, 345b, respectively, which are controlled by the controller 400. Thus, in some embodiments, the controller may shut off the vacuum to either the first vacuum line 345a or the second vacuum line 345b, thereby shutting off the exhaust gas flow through either the gas exhaust 290a located at the edge portion of the manifold 220 or the gas exhaust 290b located at the center portion of the manifold 220 during the post-exposure bake operation S140. In some embodiments, the controller 400 communicates with the temperature sensor 200a and decides whether to increase or decrease the temperature of the heating element 200.

All or part of the methods or operations of the embodiments described above may be implemented using computer hardware and special purpose computer programs that are executed thereon. In fig. 8A, an embodiment of a controller 400 is shown. The controller 400 is a computer system 400, the computer system 400 having a computer 401, a keyboard 402, a mouse 403, and a display 404, the computer 401 including a compact disk read only memory (e.g., CD-ROM or DVD-ROM) drive 405 and a disk drive 406.

Fig. 8B is a diagram that illustrates the internal configuration of computer system 400 in some embodiments. In fig. 8B, in addition to an optical disk drive 405 and a magnetic disk drive 406, the computer 401 has: one or more processors 411, such as a microprocessor unit (MPU); a ROM 412 in which a program such as a start-up program is stored; a Random Access Memory (RAM) 413 connected to the processor 411, and in the Random Access Memory (RAM) 413, commands of an application program are temporarily stored, and a temporary electronic storage area is provided; a hard disk 414 in which application programs, operating system programs, and data are stored; and a data communication bus 415 connecting the processor 411, the ROM 412, and the like. Note that computer 401 may include a network card (not shown) for providing a connection to a computer network, such as a Local Area Network (LAN), a Wide Area Network (WAN), or any other useful computer network for transmitting data for use by computing system 400.

A program for causing the computer system 400 to perform a process of controlling the apparatus of fig. 7, and/or a process of performing a method of manufacturing a semiconductor device according to an embodiment disclosed herein is stored in the optical disk 421 or the magnetic disk 422 (the optical disk 421 or the magnetic disk 422 is inserted into the optical disk drive 405 or the magnetic disk drive 406), and is transferred to the hard disk 414. Alternatively, the program may be sent to the computer system 400 through a network (not shown) and stored in the hard disk 414. At execution time, the program is loaded into the RAM 413. The program may be loaded from the optical disk 421 or the magnetic disk 422, or directly from the network. The stored program does not necessarily include, for example, an Operating System (OS) or a third party program to cause the computer 401 to perform the methods disclosed herein. In some embodiments, the program includes a command portion for calling an appropriate function (module) in the control mode and obtaining a desired result.

Another embodiment of the post-exposure bake operation S140 is shown in fig. 9A and 9B. In this embodiment, during the first period of time, the flow rate of the gas 230 supplied to the space above the photoresist layer 15 is in the range from about 1L/min to about 20L/min; and during the first period, an exhaust flow rate of the gas 275a through the gas exhaust 290a located at the edge portion of the manifold 220 is in a range from about 1L/min to about 20L/min; while no gas is discharged through the gas exhaust 290b located at the central portion of the manifold 220 (flow rate=0), as shown in fig. 9A. Then, in fig. 9B, during the second period, the exhaust flow rate of the gas 275a through the gas exhaust 290a located at the edge portion of the manifold 220 is in the range from about 10L/min to about 80L/min while the flow rate of the inlet gas 230 is maintained at about 1L/min to about 20L/min, and no exhaust gas flows out through the gas exhaust 290B located at the center portion of the manifold 220. In some embodiments, the flow rate of the inlet gas 230 supplied to the space above the photoresist layer 15 is in the range from about 2L/min to about 10L/min; during the first period, a flow rate of the gas 275a through the gas exhaust 290a located at the edge portion of the manifold 220 is in a range from 2L/min to 10L/min; and during the second period, the flow rate of the gas 275a through the gas exhaust 290a located at the edge portion of the manifold 220 is in a range from 20L/min to 60L/min. In some embodiments, the flow rate of the gas 275a through the gas exhaust 290a located at the edge portion of the manifold 220 during the second period of time is greater than the flow rate of the inlet gas 230 supplied through the manifold 220 during the second period of time.

In some embodiments, the ratio of the flow rate F2E of the exhaust gas 275a through the gas exhaust 290a at the edge portion of the manifold 220 during the second period to the flow rate F1E of the exhaust gas 275a through the gas exhaust 290a at the edge portion of the manifold during the first period ranges from about 1 to about 80, and in other embodiments, the ratio F2E/F1E ranges from about 2 to about 30. In some embodiments, during the second period of time, the ratio of the flow rate F2E of the exhaust gas 275a through the gas exhaust 290a at the edge portion of the manifold 220 to the flow rate F1 of the inlet gas 230 ranges from about 1 to about 80, and in other embodiments, the ratio F2E/F1 ranges from about 2 to about 30. In some embodiments, during the first period of time, the ratio of the flow rate F1 of the inlet gas 230 to the flow rate F1E of the exhaust gas 275a flowing through the gas exhaust 290a at the edge portion of the manifold is in the range from about 0.2 to about 5. In some embodiments, the ratio F1/F1E is about 1.

The flow rates of the inlet gas 230 and the flow rates of the outlet gas 275a outside the disclosed ranges or ratios may result in insufficient crosslinking of the exposed portions of the photoresist layer and insufficient removal of reaction byproducts. Similarly, lengths of the first and second time periods outside of the disclosed ranges or ratios may also result in insufficient crosslinking of the exposed portions of the photoresist layer and insufficient removal of reaction byproducts.

Another embodiment of the post-exposure bake operation S140 is shown in fig. 10A and 10B. In this embodiment, during the first period of time, the flow rate of the gas 230 supplied to the space above the photoresist layer 15 is in the range from about 1L/min to about 20L/min; and during the first period, an exhaust flow rate of the gas 275b through the gas exhaust 290b located in a central portion of the manifold 220 is in a range from about 1L/min to about 20L/min; while no gas is discharged through the gas exhaust 290A at the edge portion of the manifold 220 (flow rate=0), as shown in fig. 10A. Then, in fig. 10B, during the second period, the exhaust flow rate of the gas 275B through the gas exhaust 290B located at the center portion of the manifold 220 is in the range from about 10L/min to about 80L/min while the flow rate of the inlet gas 230 is maintained at about 1L/min to about 20L/min, and no exhaust gas flows out through the gas exhaust 290a located at the edge portion of the manifold 220. In some embodiments, the flow rate of the inlet gas 230 supplied to the space above the photoresist layer 15 is in the range from about 2L/min to about 10L/min; during the first period, the flow rate of the gas 275b through the gas exhaust 290b located in the central portion of the manifold 220 is in the range from 2L/min to 10L/min; and during the second period, the flow rate of the gas 275b through the gas exhaust 290b located at the central portion of the manifold 220 is in the range from 20L/min to 60L/min. In some embodiments, the flow rate of the exhaust gas 275b through the gas exhaust 290b located in the central portion of the manifold 220 during the second period of time is greater than the flow rate of the inlet gas 230 supplied through the manifold 220 during the second period of time.

In some embodiments, the ratio of the flow rate F2C of the exhaust gas 275b through the gas exhaust 290b located in the central portion of the manifold 220 during the second period of time to the flow rate F1C of the exhaust gas 275b through the gas exhaust 290b located in the central portion of the manifold during the first period of time ranges from about 1 to about 80, and in other embodiments, the ratio F2C/F1C ranges from about 2 to about 30. In some embodiments, during the second period of time, the ratio of the flow rate F2C of the exhaust gas 275b through the gas exhaust 290b located in the central portion of the manifold 220 to the flow rate F1 of the inlet gas 230 ranges from about 1 to about 80, and in other embodiments, the ratio F2C/F1 ranges from about 2 to about 30. In some embodiments, the ratio of the flow rate F1 of the inlet gas to the flow rate F1C of the exhaust gas 275b through the gas exhaust 290b located in the central portion of the manifold during the first period of time is in the range from about 0.2 to about 5. In some embodiments, the ratio F1/F1C is about 1.

The flow rates of the inlet gas 230 and the flow rates of the outlet gas 275b outside the disclosed ranges or ratios may result in insufficient crosslinking of the exposed portions of the photoresist layer and insufficient removal of reaction byproducts. Similarly, lengths of the first and second time periods outside of the disclosed ranges or ratios may also result in insufficient crosslinking of the exposed portions of the photoresist layer and insufficient removal of reaction byproducts.

The selectively exposed photoresist layer is then developed by applying a developer to the selectively exposed photoresist layer in operation S150. As shown in fig. 11, the developer 57 is supplied from the dispenser 62 to the photoresist layer 15. In some embodiments, in the case where the photoresist is a negative-tone resist (negative-tone resist), unexposed portions of the photoresist layer 52 are removed by the developer 57, and an opening pattern 55 is formed in the photoresist layer 15, thereby exposing the substrate 10, as shown in fig. 12.

In some embodiments, the opening pattern 55 in the photoresist layer 15 is extended into the layer or substrate 10 to be patterned to create an opening pattern 55' in the substrate 10 to transfer the pattern in the photoresist layer 15 into the substrate 10, as shown in fig. 13. The pattern is extended into the substrate by etching using one or more suitable etchants. In some embodiments, the portion of the photoresist layer 15 remaining after the development operation is at least partially removed during the etching operation. In other embodiments, after etching the substrate 10, the remaining photoresist layer 15 is removed by using an appropriate photoresist stripping solvent or by a photoresist ashing operation.

In some embodiments, the substrate 10 includes a single crystalline semiconductor layer on at least a surface portion thereof. The substrate 10 may comprise single crystal semiconductor materials such as, but not limited to Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb and InP. In some embodiments, the substrate 10 is a silicon layer of an SOI (silicon on insulator) substrate. In some embodiments, the substrate 10 is made of crystalline Si.

The substrate 10 may include one or more buffer layers (not shown) in its surface area. The buffer layer may gradually change the lattice constant from that of the substrate to that of the subsequently formed source/drain regions. The buffer layer may be formed of an epitaxially grown single crystal semiconductor material such as, but not limited to Si, ge, geSn, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb, gaN, gaP, and InP. In an embodiment, a silicon germanium (SiGe) buffer layer is epitaxially grown on silicon substrate 10. The germanium concentration of the SiGe buffer layer may be increased from 30 atomic percent of the bottom buffer layer to 70 atomic percent of the top buffer layer.

In some embodiments, the substrate 10 includes at least one metal, metal alloy, and metal nitride/sulfide/oxide/silicide (having the formula MX _a Wherein M is a metal and X is N, S, se, O, si and a is from about 0.4 to about 2.5). In some embodiments, the substrate 10 comprises titanium, aluminum, cobalt, ruthenium, titanium nitride, tungsten nitride, tantalum nitride, or a combination thereof.

In some embodiments, the substrate 10 includes a dielectric having at least silicon or metal oxide or nitride having the formula MX _b Wherein M is a metal or Si, X is N or O, and b is in the range of from about 0.4 to about 2.5. In some embodiments, the substrate 10 comprises silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, lanthanum oxide, or a combination thereof.

In some embodiments, substrate 10 refers to any underlying layer over which a resist layer is formed. The substrate 10 is then patterned using photolithography and etching operations.

The photoresist layer 15 is a photosensitive layer that is patterned by exposure to actinic radiation. Typically, the chemistry of the photoresist region that is hit by the incident radiation is changed in a manner that depends on the type of photoresist used. The photoresist layer 15 is either a positive resist or a negative resist. Positive resist refers to a photoresist material that becomes soluble to a developer when exposed to radiation (e.g., UV light), while unexposed (or less exposed) photoresist areas are insoluble to the developer. Negative resist, on the other hand, refers to a photoresist material that becomes insoluble to a developer when exposed to radiation, while unexposed (or less exposed) photoresist areas are soluble to a developer. Areas of negative resist that become insoluble upon exposure to radiation may become insoluble due to crosslinking reactions caused by exposure to radiation.

Whether the resist is positive or negative may depend on the type of developer used to develop the resist. For example, when the developer is an aqueous based developer (e.g., tetramethyl ammonium hydroxide (tetramethylammonium hydroxide, TMAH) solution), some positive photoresists provide positive patterns (i.e., the exposed areas are removed by the developer). On the other hand, when the developer is an organic solvent, the same photoresist provides a negative pattern (i.e., unexposed areas are removed by the developer). Furthermore, in the case of developing some negative photoresist with TMAH solution, the unexposed areas of the photoresist are removed by TMAH and, after development, the areas of the photoresist that crosslink upon exposure to actinic radiation remain on the substrate.

The resist composition according to the present disclosure is a metal-containing resist. In some embodiments, the photoresist layer 15 is a negative-working metallized photoresist that undergoes a crosslinking reaction upon exposure to radiation.

In some embodiments, the photoresist layer 15 is made of a metallized photoresist composition, including a first compound or first precursor and a second compound or second precursor combined in the vapor state. The first precursor or first compound is an organometallic compound having the formula: m is M _a R _b X _c As shown in fig. 14A, wherein M is at least one of Sn, bi, sb, in, te, ti, zr, hf, V, co, mo, W, al, ga, si, ge, P, as, Y, la, ce or Lu; and R is a substituted or unsubstituted alkyl, alkenyl or carboxylic acid group. In some embodiments, M is selected from the group consisting of Sn, bi, sb, in, te and combinations thereofA group of groups. In some embodiments, R is a C3-C6 alkyl, alkenyl, or carboxylic acid group. In some embodiments, R is selected from the group consisting of propyl, isopropyl, butyl, isobutyl, sec-butyl, tert-butyl, pentyl, isopentyl, sec-pentyl, tert-pentyl, hexyl, isohexyl, sec-hexyl, tert-hexyl, and combinations thereof. X is a ligand, ion or other moiety (moiety) that reacts with a second compound or second precursor; and in some embodiments 1.ltoreq.a.ltoreq.2, b.gtoreq.1, c.gtoreq.1, and b+c.ltoreq.5. In some embodiments, the alkyl, alkenyl, or carboxylic acid groups are substituted with one or more fluoro groups. In some embodiments, the organometallic precursor is a dimer (dimer), as shown in fig. 14A, wherein each monomer unit is linked by an amine group. Each monomer has the formula: m is M _a R _b X _c As defined above.

In some embodiments, R is alkyl, e.g., C _n H _2n+1 Wherein n is not less than 3. In some embodiments, R is fluorinated, e.g., of formula C _n F _x H _((2n+1)-x) . In some embodiments, R has at least one β -hydrogen or β -fluorine. In some embodiments, R is selected from the group consisting of isopropyl, n-propyl, t-butyl, isobutyl, n-butyl, sec-butyl, n-pentyl, isopentyl, t-pentyl, sec-pentyl, and combinations thereof.

In some embodiments, X is any moiety that is readily substituted with a second compound or second precursor to produce an M-OH moiety, e.g., a moiety selected from the group consisting of: amino groups including dialkylamino and monoalkylamino groups; an alkoxy group; carboxylic acid groups, halogen groups, and sulfonic acid groups. In some embodiments, the sulfonic acid groups are substituted with one or more amine groups. In some embodiments, the halogen group is one or more selected from the group consisting of F, cl, br, and I. In some embodiments, the sulfonic acid groups include substituted or unsubstituted C1-C3 groups.

In some embodiments, the first organometallic compound or first organometallic precursor includes a metallized core M ⁺ With ligand L attached to the metallized core M ⁺ As shown in fig. 14B. In some embodimentsMetallized core M ⁺ Is a metal oxide. In some embodiments, the ligand L comprises a C3-C12 aliphatic or aromatic group. Aliphatic or aromatic groups may be unbranched or branched, having cyclic or acyclic saturated pendent groups comprising 1-9 carbons, including alkyl groups, alkenyl groups, and phenyl groups. These branched groups may be further substituted with oxygen or halogen. In some embodiments, the C3-C12 aliphatic or aromatic groups include heterocyclic groups. In some embodiments, the C3-C12 aliphatic or aromatic groups are attached to the metal by ether or ester chains. In some embodiments, the C3-C12 aliphatic or aromatic groups include nitrite and sulfonate substituents.

In some embodiments, the organometallic precursor or organometallic compound comprises: secondary hexyltris (dimethylamino) tin, tertiary hexyltris (dimethylamino) tin, isohexyltris (dimethylamino) tin, n-hexyltris (dimethylamino) tin, secondary pentyltris (dimethylamino) tin, tertiary pentyltris (dimethylamino) tin, isopentyltis (dimethylamino) tin, n-pentyltris (dimethylamino) tin, sec-butyltris (dimethylamino) tin, tertiary butyltris (dimethylamino) tin, isobutyltis (dimethylamino) tin, n-butyltris (dimethylamino) tin, isopropyl tris (dimethylamino) tin, n-propyl tris (dimethylamino) tin, and similar alkyl (tri) (t-butoxy) tin compounds, including: sec-hexyltri (tert-butoxy) tin, tert-hexyltri (tert-butoxy) tin, isohexyltri (tert-butoxy) tin, n-hexyltri (tert-butoxy) tin, sec-pentyltri (tert-butoxy) tin, tert-pentyltri (tert-butoxy) tin, isopentylti (tert-butoxy) tin, n-pentyltri (tert-butoxy) tin, tert-butyltri (tert-butoxy) tin, isobutylti (butoxy) tin, n-butyltri (butoxy) tin, sec-butyltri (butoxy) tin, isopropyl tri (butoxy) tin, or n-propyl tri (butoxy) tin. In some embodiments, the organometallic precursor or organometallic compound is fluorinated. In some embodiments, the organometallic precursor or compound has a boiling point of less than about 200 ℃.

In some embodiments, the first compound or first precursor includes one or more unsaturated bonds that can coordinate with functional groups (e.g., hydroxyl groups) on the surface of the substrate or an intervening underlying layer to improve adhesion of the photoresist layer to the substrate or underlying layer.

In some embodiments, the second precursor or second compound is at least one of amino, borane, phosphine, or water. In some embodiments, the amino group has the formula N _p H _n X _m Wherein 0.ltoreq.n.ltoreq.3, 0.ltoreq.m.ltoreq.3, n+m=3 when p is 1, and n+m=4 when p is 2, and each X is halogen independently selected from the group consisting of F, cl, br and I. In some embodiments, the borane has formula B _p H _n X _m Wherein 0.ltoreq.n.ltoreq.3, 0.ltoreq.m.ltoreq.3, n+m=3 when p is 1, and n+m=4 when p is 2, and each X is halogen independently selected from the group consisting of F, cl, br and I. In some embodiments, the phosphane is of the formula P _p H _n X _m Wherein 0.ltoreq.n.ltoreq.3, 0.ltoreq.m.ltoreq.3, n+m=3 when p is 1, and n+m=4 when p is 2, and each X is halogen independently selected from the group consisting of F, cl, br and I.

Fig. 14B illustrates a metal precursor that reacts due to exposure to actinic radiation in some embodiments. Due to exposure to actinic radiation, the ligand group L is derived from the metallized core M of the metal precursor ⁺ And two or more metal precursor cores are bonded to each other.

Fig. 14C shows an example of an organometallic precursor according to an embodiment of the disclosure. In fig. 14C, bz is a phenyl group.

Fig. 15 illustrates a reaction of photoresist composition components as a result of exposure to actinic radiation and heating in accordance with an embodiment of the present disclosure. Fig. 15 illustrates an exemplary chemical structure of a photoresist layer at various stages of a photoresist patterning method according to an embodiment of the present disclosure. As shown in fig. 15, the photoresist composition includes an organometallic compound (e.g., snX ₂ R ₂ ) And a second compound (e.g., ammonia (NH) ₃ )). When the organometallic compound is combined with ammonia, the organometallic compound reacts with some of the ammonia in the gas phase to form an inverseA reaction product having an amine group attached to a metal (Sn) of an organometallic compound. The amine groups in the deposited photoresist layer have hydrogen bonds that can greatly increase the boiling point of the deposited photoresist layer and help prevent outgassing of the metal-containing photoresist material. In addition, the hydrogen bonding of amine groups helps control the effect of moisture on the photoresist layer quality.

Upon subsequent exposure to extreme ultraviolet radiation, the organometallic compound absorbs the extreme ultraviolet radiation and one or more organic R groups are separated from the organometallic compound to form an amino metal compound in the radiation exposed region. Then, in some embodiments, the metal amide is crosslinked by amine groups when a Post Exposure Bake (PEB) is performed, as shown in fig. 15. In some embodiments, the partial crosslinking of the metal amide occurs as a result of exposure to extreme ultraviolet radiation.

In some embodiments, the operation S110 of forming and coating the photoresist composition over the substrate is performed by a vapor deposition operation. In some embodiments, the vapor deposition operation includes Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD). In some embodiments, ALD includes plasma enhanced atomic layer deposition (PE-ALD); CVD includes plasma enhanced chemical vapor deposition (PE-CVD), metal organic chemical vapor deposition (MO-CVD), atmospheric pressure chemical vapor deposition (AP-CVD) and low pressure chemical vapor deposition (LP-CVD).

A resist layer deposition apparatus 500 according to some embodiments of the present disclosure is shown in fig. 16. In some embodiments, the deposition apparatus 500 is an ALD or CVD apparatus. The deposition apparatus 500 includes a vacuum chamber 505. A substrate support table 570 in the vacuum chamber 505 supports a substrate 510, such as a silicon wafer. In some embodiments, the substrate support table 570 includes a heater. In some embodiments, a first precursor or compound gas supply 520 and a carrier/purge gas supply 525 are connected to an inlet 530 in the chamber via a gas line 535, and a second precursor or compound gas supply 540 and a carrier/purge gas supply 525 are connected to another inlet 530 'in the chamber via another gas line 535'. The chamber is evacuated and excess reactants and reaction byproducts are removed by vacuum pump 545 via outlet 550 and exhaust line 555. In some embodiments, the flow rates or pulses of precursor gases and carrier/purge gases, the evacuation of excess reactants and reaction byproducts, the pressure within the vacuum chamber 505, and the temperature of the vacuum chamber 505 or wafer support table 570 are controlled by a controller 560 configured to control each of these parameters.

In some embodiments, depositing the photoresist layer includes combining the first compound or first precursor and the second compound or second precursor in a vapor state to form the photoresist composition. In some embodiments, the first compound or first precursor and the second compound or second precursor of the photoresist composition are introduced to the deposition chamber 505 (CVD chamber) via inlets 530, 530' at about the same time. In some embodiments, the first compound or first precursor and the second compound or second precursor are alternately introduced to the deposition chamber 205 (ALD chamber) via inlets 530, 530', i.e., first the first compound or precursor, then the second compound or precursor, and then the first compound or precursor, then the second compound or precursor, are alternately repeated.

In some embodiments, the deposition chamber temperature is in the range from about 30 ℃ to about 400 ℃ during the deposition operation, and in other embodiments, between about 50 ℃ to about 250 ℃. In some embodiments, the pressure in the deposition chamber is in a range from about 5mTorr to about 100Torr during the deposition operation, and in other embodiments, between about 100mTorr and about 10 Torr. In some embodiments, the plasma power is less than about 1000W. In some embodiments, the plasma power is in the range from about 100W to about 900W. In some embodiments, the flow rates of the first compound or precursor and the second compound or precursor are in the range from about 100sccm to about 1000 sccm. In some embodiments, the ratio of the flow rate of the organometallic compound precursor to the second compound or precursor is from 1:1 to about 1: 5. In some embodiments, an unsatisfactory photoresist layer is created with operating parameters outside of the above-described ranges. In some embodiments, the formation of the photoresist layer occurs in a single chamber (one-step layer formation (one-pot layer formation)).

In a CVD process according to some embodiments of the present disclosure, two or more gas streams (in separate inlet paths 530, 535 and 530', 535') of an organometallic precursor and a second precursor are introduced into a deposition chamber 505 of a CVD apparatus where they are mixed and reacted in the gas phase to form reaction products. In some embodiments, a separate injection inlet 230, 230' or dual hydrostatic head is used to introduce the flow. The deposition apparatus is configured such that streams of the organometallic precursor and the second precursor are mixed in the chamber, allowing the organometallic precursor and the second precursor to react to form a reaction product. Without limiting the mechanism, function, or utility of the present disclosure, it is believed that the molecular weight of the product of the gas phase reaction becomes heavy and then coalesces or otherwise deposits on the substrate 510.

In some embodiments, an ALD process is used to deposit the photoresist layer. During ALD, a layer is grown on the substrate 510 by exposing the surface of the substrate to alternating gaseous compounds (or precursors). In contrast to CVD, the precursor is introduced as a series of continuous, non-overlapping pulses. In each pulse, the precursor molecule reacts with the surface in a self-limiting manner such that once all of the reactive sites on the surface are consumed, the reaction is terminated. Thus, the maximum amount of material deposited on a surface after a single exposure to all precursors (a so-called ALD cycle) is determined by the nature of the precursor and surface interactions.

In an embodiment of the ALD process, in a first half reaction (first half reaction), the organometallic precursor is pulsed to deliver the metal-containing precursor to the surface of the substrate 510. In some embodiments, the organometallic precursor reacts with a suitable underlying species (e.g., OH or NH functional groups on the surface of the substrate) to form a new self-saturating surface. In some embodiments, the excess unused reactants and reaction byproducts are removed by applying a vacuum using a vacuum pump 545 and/or by flowing an inert purge gas. Then, in some casesIn an embodiment, the second precursor (e.g., ammonia (NH) ₃ ) Pulsed into the deposition chamber. NH (NH) ₃ Reacts with the organometallic precursor on the substrate to obtain a reaction product photoresist on the substrate surface. The second precursor also forms a self-saturating bond with the underlying reactive species to provide another self-limiting and saturated second half reaction (second half reaction). In some embodiments, a second purge is performed to remove unused reactants and reaction byproducts. The pulsing of the first precursor and the second precursor is alternated with an intervening purge operation until a desired thickness of the photoresist layer is reached.

In some embodiments, the photoresist layer 15 is formed to a thickness of about 5nm to about 50nm, and in other embodiments, about 10nm to 30nm. Those of ordinary skill in the art will recognize that other thickness ranges within the explicit ranges above are contemplated and are within the present disclosure. Based on the optical properties of the photoresist layer, the thickness can be estimated using non-contact methods of x-ray reflectivity and/or ellipsometry (ellipsometry). In some embodiments, each photoresist layer is relatively uniform in thickness for ease of processing. In some embodiments, the thickness of the deposited photoresist layer does not vary by more than ±25% from the average thickness, and in other embodiments, each photoresist layer thickness does not vary by more than ±10% from the average photoresist layer thickness. In some embodiments, such as high uniformity deposition on larger substrates, a 1 cm edge exclusion method (1 centimeter edge exclusion) may be used to evaluate the photoresist layer uniformity, i.e., not evaluate the layer uniformity of the coating portion within 1 cm of the edge. Those of ordinary skill in the art will recognize that other ranges within the explicit ranges above are contemplated and are within the present disclosure.

In some embodiments, the first and second compounds or precursors are delivered to the deposition chamber 505 along with a carrier gas. The carrier gas, purge gas, deposition gas, or other process gas may include nitrogen, hydrogen, argon, neon, helium, or combinations thereof.

In some embodiments, the organometallic compound includes tin (Sn), antimony (Sb), bismuth (Bi), indium (In), and/or tellurium (Te) as metal components, however, the present disclosure is not limited to these metals. In other embodiments, other suitable metals include titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), cobalt (Co), molybdenum (Mo), tungsten (W), aluminum (Al), gallium (Ga), silicon (Si), germanium (Ge), phosphorus (P), arsenic (As), yttrium (Y), lanthanum (La), cerium (Ce), tritium (Lu), or combinations thereof. Other metals may be substituted for or in addition to Sn, sb, bi, in and/or Te.

The particular metal used may have a significant impact on the absorption of the radiation. Thus, the metal composition may be selected based on the desired radiation and absorption cross-section. Tin, antimony, bismuth, tellurium and indium provide strong absorption of extreme ultraviolet light at 13.5 nm. Hafnium provides good absorption of electron beam and extreme UV radiation. The metal composition comprising titanium, vanadium, molybdenum or tungsten provides a strong absorption at longer wavelengths, for example providing sensitivity to ultraviolet light of 248nm wavelength.

In some embodiments, the resist layer 15 is formed by: the organometallic compound is mixed in a solvent to form a resist composition and the resist composition is dispensed onto the substrate 10. To aid in the mixing and dispensing of the photoresist, the solvent is selected based at least in part on the material selected for the metallic photoresist. In some embodiments, the solvent is selected such that the organometallic is uniformly dissolved into the solvent and distributed over the layer to be patterned.

In some embodiments, the photoresist exposure radiation is selected from the group consisting of CO ₂ The laser-excited Sn plasma produces extreme ultraviolet radiation (13.5 nm in wavelength). In other embodiments, ultraviolet radiation (including g-line (wavelength about 436 nm), i-line (wavelength about 365 nm)), extreme ultraviolet radiation, or an electron beam is used to selectively expose the photoresist layer. In some embodiments, in addition to CO ₂ The radiation source is selected from mercury vapor lamp, xenon lamp, carbon arc lamp, krF excimer laser (wavelength 248 nm), arF excimer laser (wavelength 193 nm), and F ₂ Excimer laser (wavelength 157 nm).

In some embodiments, exposure of the photoresist layer 15 uses immersion lithography (immersion lithography technique). In this technique, an immersion medium (not shown) is placed between the final optics and the photoresist layer, and exposure radiation 45 passes through the immersion medium.

In some embodiments, the photoresist developer 57 includes a solvent, and an acid or base. In some embodiments, the developer comprises one or more solvents selected from the group consisting of: n-butyl acetate, methyl n-pentanone, hexane, heptane, amyl acetate, ethylene glycol, propylene glycol monomethyl ether, propylene glycol diethyl ether, gamma-butyrolactone, cyclohexanone, ethyl lactate, methanol, ethanol, propanol, n-butanol, acetone, dimethylformamide, acetonitrile, isopropanol, and tetrahydrofuran. In some embodiments, the acid is one or more of the following: acetic acid, oxalic acid, formic acid, 2-hydroxypropionic acid, 2-hydroxysuccinic acid, citric acid, uric acid, trifluoromethanesulfonic acid, benzenesulfonic acid, ethanesulfonic acid, methanesulfonic acid, and maleic acid. In some embodiments, suitable bases for photoresist developer composition 57 include alkanolamines, triazoles, or ammonium based compounds. In some embodiments, suitable bases include: an organic base selected from the group consisting of monoethanolamine, monoisopropanolamine, 2-amino-2-methyl-1-propanol, 1H-benzotriazole, 1,2, 4-triazole, 1, 8-diazabicyclo undec-7-ene, tetramethylammonium hydroxide, tetraethylammonium hydroxide, tetrapropylammonium hydroxide, and tetrabutylammonium hydroxide, and combinations thereof; or an inorganic base selected from the group consisting of ammonium hydroxide, ammonium sulfamate, ammonium carbamate, and combinations thereof. In some embodiments, the base is selected from the group consisting of: monoisopropanolamine, 2-amino-2-methyl-1-propanol, 1H-benzotriazole, 1,2, 4-triazole, 1, 8-diazabicyclo undec-7-ene, and combinations thereof. In some embodiments, the developer further comprises water.

In some embodiments, the developer 57 is applied to the photoresist layer 15 using a spin-on process. In the spin coating process, a developer 57 is applied to the photoresist layer 15 from above the photoresist layer 15 as the photoresist-coated substrate rotates, as shown in fig. 11. In some embodiments, the developer 57 is supplied at a speed of between about 5ml/min and about 800ml/min, while the photoresist coated substrate 10 is rotated at a speed of between about 100rpm and about 2000 rpm. In some embodiments, the temperature of the developer is between about 10 ℃ and about 80 ℃. In some embodiments, the development operation lasts between about 30 seconds and about 10 minutes. In some embodiments, a plasma development operation is performed.

While the spin-coating process is one suitable method for developing the photoresist layer 15 after exposure, it is intended to be illustrative and not intended to limit the embodiments. Rather, any suitable development operation may alternatively be used, including dipping processes, puddling processes, and spraying methods. All such development operations are included within the scope of the embodiments.

During the development process, the developer 57 dissolves the radiation unexposed areas 52 of the negative photoresist to form a pattern 55, thereby exposing the surface of the substrate 10, leaving well-defined exposed photoresist areas 50, as shown in fig. 12, with improved definition compared to conventional negative photoresist lithography.

After the developing operation S150, the remaining developer is removed from the substrate covered with the patterned photoresist. In some embodiments, spin-dry process (spin-dry process) is used to remove the remaining developer, although any suitable removal technique may be used. After developing the photoresist layer 15 and removing the remaining developer, additional processing is performed while the patterned photoresist layers 50, 52 are in place. For example, in some embodiments, an etching operation is performed using dry etching or wet etching to transfer the pattern 55 of the photoresist layer to the underlying substrate 10 to form the recess 55', as shown in fig. 13. The substrate 10 has a different etch resistance than the photoresist layer 15. In some embodiments, the etchant is more selective to the substrate 10 (relative to the photoresist layer 15).

In some embodiments, the substrate 10 and the photoresist layer 15 include at least one etch resistant molecule. In some embodiments, the etch resistant molecule comprises a molecule having: low Onishi number structures, double bonds, triple bonds, silicon nitride, titanium nitride, aluminum oxide, silicon oxynitride, combinations thereof, and the like.

In some embodiments, a layer 60 to be patterned is provided over the substrate prior to forming the photoresist layer, as shown in fig. 17. In some embodiments, the layer 60 to be patterned is a metallization layer, or a dielectric layer, such as a passivation layer, disposed over the metallization layer. In embodiments where the layer to be patterned 60 is a metallization layer, the layer to be patterned 60 is formed from a conductive material using a metallization process and metal deposition techniques, including chemical vapor deposition, atomic layer deposition, and physical vapor deposition (sputtering). Likewise, if the layer to be patterned 60 is a dielectric layer, the layer to be patterned 60 is formed by dielectric layer formation techniques including thermal oxidation, chemical vapor deposition, atomic layer deposition, and physical vapor deposition.

The photoresist layer 15 is then selectively exposed to actinic radiation 45/97 to form exposed areas 50 and unexposed areas 52 in the photoresist layer, as shown in fig. 18A and 18B and described herein in connection with fig. 3A and 3B.

The substrate 580 coated with the exposed photoresist is then heated as described in connection with fig. 4A-10B.

As shown in fig. 19, the photoresist layer 15 is developed by dispensing a developer 57 from a dispenser 62 to form a photoresist opening pattern 55, as shown in fig. 20. The developing operation is similar to the operation explained herein with reference to fig. 11. In some embodiments, in the case where the photoresist is a negative resist, unexposed portions of the photoresist layer 52 are removed by the developer 57, and an opening pattern 55 is formed in the photoresist layer 15, thereby exposing the layer 60 to be patterned, as shown in fig. 20.

Then, as shown in fig. 21, the pattern 55 in the photoresist layer 15 is transferred to the layer to be patterned 60 using an etching operation, and the photoresist layer is removed, thereby forming the pattern 55 "in the layer to be patterned 60 (as explained with reference to fig. 13).

A method 600 of fabricating a semiconductor device is shown in fig. 22. In operation S610, a photoresist layer 15 is formed over the substrate 10. In operation S620, the photoresist layer 15 is selectively exposed to actinic radiation. Then, in operation S630, after the photoresist layer is selectively exposed to actinic radiation, the photoresist layer 15 is heated. In operation S640, during heating of the photoresist layer 15, a gas is flowed through the photoresist layer. In operation S640, when the gas flows through the photoresist layer, the flow is changed. In operation S650, the photoresist layer 15 is developed after heating to form the pattern 55 in the photoresist layer. In some embodiments, gas is supplied to the space above the photoresist layer 15 through a gas manifold 220, and the gas manifold has one or more gas exhausts located at an edge portion of the manifold or at a center portion of the manifold 220. In operation S660, during the first period, the gas is discharged at a first flow rate and through the gas exhaust at the center portion or the edge portion of the manifold 220. Then, in operation S670, during the second period, the gas is discharged at a second different flow rate or through a different gas exhaust (compared to operation S660).

Another method 700 of fabricating a semiconductor device is shown in the flowchart of fig. 23. In operation S710, a photoresist layer 15 is formed over the substrate 10. In operation S720, the photoresist layer 15 is patternwise (or selectively) exposed to actinic radiation. Then, in operation S730, after the photoresist layer is patternwise exposed to actinic radiation, the photoresist layer 15 is baked. In operation S740, during baking of the photoresist layer 15, a gas is flowed through the photoresist layer at a first flow rate. In operation S750, during a first period of time, gas is exhausted at a second flow rate through one or more gas exhausts 290a located at the periphery of the showerhead. Then, during the second period, the gas is discharged through one or more gas exhaust 290a located at the outer periphery of the showerhead at a third flow rate, wherein the third flow rate is greater than the second flow rate, in operation S760. In operation S770, the photoresist layer 15 is then developed after heating to form the pattern 55 in the photoresist layer.

Another method 800 of fabricating a semiconductor device is shown in the flowchart of fig. 24. In operation S810, a photoresist layer 15 is formed over the substrate 10. In operation S820, the photoresist layer 15 is patternwise (or selectively) exposed to actinic radiation. Then, in operation S830, after the photoresist layer is patternwise exposed to actinic radiation, the photoresist layer 15 is baked. In operation S840, during baking of the photoresist layer 15, a gas is flowed through the photoresist layer at a first flow rate. In operation S850, during the first period, gas is discharged through the gas exhaust gas located at the central portion of the manifold at the second flow rate. Then, during the second period, the gas is discharged through the gas exhaust gas located at the central portion of the manifold 220 at a third flow rate, wherein the third flow rate is greater than the second flow rate, in operation S860. In operation S770, the photoresist layer 15 is then developed after heating to form the pattern 55 in the photoresist layer.

Other embodiments include other operations before, during, or after the operations described above. In some embodiments, the disclosed methods include forming a fin field effect transistor (FinFET) structure. In some embodiments, a plurality of active fins are formed on a semiconductor substrate. These embodiments further include: etching the substrate through the openings of the patterned hard mask to form trenches in the substrate; filling the trench with a dielectric material; performing a Chemical Mechanical Polishing (CMP) process to form Shallow Trench Isolation (STI) features; and epitaxially growing or recessing the STI features to form fin-shaped active regions. In some embodiments, one or more gate electrodes are formed on a substrate. Some embodiments include forming gate spacers, doped source/drain regions, contacts for gate/source/drain features, and the like. In other embodiments, the target pattern is formed as a metal line in a multilayer interconnect structure. For example, metal lines may be formed in an interlayer dielectric (ILD) layer of a substrate that has been etched to form a plurality of trenches. The trenches may be filled with a conductive material, such as a metal; and the conductive material may be polished using a process such as Chemical Mechanical Planarization (CMP) to expose the patterned ILD layer to form metal lines in the ILD layer. The foregoing are non-limiting examples of devices/structures that can be fabricated and/or improved using the methods described herein.

In some embodiments, active components, such as diodes, field Effect Transistors (FETs), finfets, gate full surrounding field effect transistors (GAA FETs), metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other three-dimensional (3D) FETs, other memory cells, and combinations thereof, are formed in accordance with embodiments of the present disclosure.

In embodiments of the present disclosure, actinic radiation exposure dose reduction is achieved by using a sequential post-exposure bake (PEB) process. The exposure dose reduction is achieved by: the initial longer, lower flow rate purge is used during PEB followed by the shorter, higher flow rate purge. Exposure dose reduction is achieved by lower flow rate venting and, in some embodiments, chamber contamination is reduced by shorter time, higher flow rate venting. During most of the post-exposure bake process, the lower flow rate of the exhaust gas serves to retain more of the reactants in the photoresist film to enhance the crosslinking reaction. As a result, exposure dose and operating costs (cost of operation, coO) of the method according to embodiments of the present disclosure are significantly reduced.

In some embodiments of the present disclosure, in forming a pattern with a 30nm pitch, a reduction of up to 10% in exposure dose is achieved where the pattern has substantially the same Line Width Roughness (LWR) and Critical Dimension (CD) range as a pattern formed using a similar photolithographic method (without the sequential PEB venting process of the present disclosure). In some embodiments of the present disclosure, an improvement in critical dimensions of the photoresist pattern of up to about 7% is achieved as compared to a pattern formed by a similar photolithographic process that does not use the sequential PEB venting technique of the present disclosure, as shown after the development inspection. In addition, wafer bevel and wafer backside contamination levels are about the same as similar photolithographic techniques that do not use the sequential PEB exhaust techniques of the disclosure, as determined by chamber Sn Ion Chromatography (ICP).

An embodiment of the present disclosure is a method of manufacturing a semiconductor device, including: a photoresist layer comprising a photoresist composition is formed over a substrate. The photoresist layer is selectively exposed to actinic radiation. After selectively exposing the photoresist layer to actinic radiation, the photoresist layer is heated. During heating of the photoresist layer, a gas is flowed through the photoresist layer. The flow of gas is changed during heating of the photoresist layer. The photoresist layer is developed after heating the photoresist layer to form a pattern in the photoresist layer. In an embodiment, during heating, the photoresist layer is heated at a temperature in the range from 70 ℃ to 220 ℃. In an embodiment, during heating, the photoresist layer is heated at a temperature in the range from 150 ℃ to 190 ℃. In an embodiment, the photoresist layer is heated for 40 seconds to 200 seconds during heating. In an embodiment, during heating, the photoresist layer is heated for 65 seconds to 175 seconds. In an embodiment, during flowing gas through the photoresist layer, gas is supplied to a space above the photoresist layer through the manifold and is exhausted from the space. In an embodiment, the manifold includes a plurality of gas supply openings and one or more gas exhausts. In an embodiment, a plurality of gas supply openings are arranged in a showerhead configuration on a surface of the manifold. In an embodiment, the one or more gas exhausts are located in a central portion of the manifold or in an edge portion of the manifold. In an embodiment, during a first period of flowing gas through the photoresist layer, gas is discharged from only the gas discharge at the edge portion of the manifold, and then during a second period of flowing gas through the photoresist layer, gas is discharged from the gas discharge at the edge portion of the manifold and the gas discharge at the center portion of the manifold. In an embodiment, the first period of time is longer than the second period of time. In an embodiment, the first period of time is in the range from 40 seconds to 200 seconds and the second period of time is in the range from 2 seconds to 85 seconds. In an embodiment, the first period of time is in a range from 60 seconds to 115 seconds and the second period of time is in a range from 5 seconds to 60 seconds. In an embodiment, the flow rate of the gas supplied to the space is in a range from 1L/min to 20L/min, the flow rate of the gas exhaust gas passing through the edge portion of the manifold is in a range from 1L/min to 20L/min during the first period and the second period, and the flow rate of the gas exhaust gas passing through the center portion of the manifold is in a range from 10L/min to 80L/min during the second period. In an embodiment, the flow rate of the gas supplied to the space is in a range from 2L/min to 10L/min, the flow rate of the gas exhaust gas passing through the edge portion of the manifold is in a range from 2L/min to 10L/min during the first period and the second period, and the flow rate of the gas exhaust gas passing through the center portion of the manifold is in a range from 20L/min to 60L/min during the second period. In an embodiment, the flow rate of the gas exhaust through the gas exhaust located at the central portion of the manifold is greater than the flow rate of the gas exhaust through the gas exhaust located at the edge portion of the manifold during the second period. In an embodiment, the flow rate of the gas exhaust through the gas located in the central portion of the manifold during the second period is greater than the flow rate of the gas supplied through the manifold. In an embodiment, one or more exhaust gases are located at an edge portion of the manifold. In an embodiment, during a first period of flowing gas through the photoresist layer, gas is exhausted from the one or more gas exhausts at a first flow rate, and then during a second period of flowing gas through the photoresist layer, gas is exhausted from the one or more gas exhausts at a second flow rate, wherein the second flow rate is greater than the first flow rate. In an embodiment, the first period of time is longer than the second period of time. In an embodiment, the first period of time is in the range from 40 seconds to 200 seconds and the second period of time is in the range from 2 seconds to 85 seconds. In an embodiment, the first period of time is in a range from 60 seconds to 115 seconds and the second period of time is in a range from 5 seconds to 60 seconds. In an embodiment, the flow rate of the gas supplied to the space is in a range from 1L/min to 20L/min, and the flow rate of the gas discharged through the gas at the edge portion of the manifold is in a range from 1L/min to 20L/min during the first period, and in a range from 10L/min to 80L/min during the second period. In an embodiment, the flow rate of the gas supplied to the space is in a range from 2L/min to 10L/min, and the flow rate of the gas discharged through the gas at the edge portion of the manifold is in a range from 2L/min to 10L/min during the first period, and in a range from 20L/min to 60L/min during the second period. In an embodiment, an exhaust flow rate of the gas exhaust through the gas at the edge portion of the manifold during the second period is greater than a flow rate of the gas supplied to the space. In an embodiment, the gas exhaust is located in a central portion of the manifold. In an embodiment, during a first period of flowing gas through the photoresist layer, gas is exhausted from the gas exhaust at a first flow rate, and then during a second period of flowing gas through the photoresist layer, gas is exhausted from the gas exhaust at a second flow rate, wherein the second flow rate is greater than the first flow rate. In an embodiment, the first period of time is longer than the second period of time. In an embodiment, the first period of time is in the range from 40 seconds to 200 seconds and the second period of time is in the range from 2 seconds to 85 seconds. In an embodiment, the first period of time is in a range from 60 seconds to 115 seconds and the second period of time is in a range from 5 seconds to 60 seconds. In an embodiment, the flow rate of the gas supplied to the space is in a range from 1L/min to 20L/min, and the exhaust flow rate of the exhaust gas through the gas is in a range from 1L/min to 20L/min during the first period, and in a range from 10L/min to 80L/min during the second period. In an embodiment, the flow rate of the gas supplied to the space is in a range from 2L/min to 10L/min, and the exhaust flow rate of the exhaust gas through the gas is in a range from 2L/min to 10L/min during the first period, and in a range from 20L/min to 60L/min during the second period. In an embodiment, a flow rate of the gas exhaust through the gas at the edge portion of the manifold during the second period is greater than a flow rate of the gas supplied through the gas inlet. In an embodiment, the photoresist composition includes an organometallic compound.

Another embodiment of the present disclosure is a method of manufacturing a semiconductor device, including: a photoresist layer comprising a photoresist composition is formed over a substrate. The photoresist layer is patternwise exposed to actinic radiation. After patternwise exposing the photoresist layer to actinic radiation, baking the photoresist layer. During baking of the photoresist layer, a gas is flowed through the photoresist layer. During flowing of the gas through the photoresist layer, the gas is supplied to the space above the photoresist layer at a first flow rate from a gas shower head located above a major surface of the photoresist layer, and the gas is exhausted from the space above the photoresist layer through one or more gas exhausts located near the periphery of the shower head. The gas is discharged from the space above the photoresist layer at the second flow rate during the first period of time, and then the gas is discharged from the space above the photoresist layer at the third flow rate during the second period of time. The third flow rate is greater than the second flow rate. The photoresist layer is developed after baking the photoresist layer to form a pattern in the photoresist layer. In an embodiment, the ratio of the third flow rate to the second flow rate is in the range from greater than 1 to 80. In an embodiment, the ratio of the third flow rate to the second flow rate is in the range from 2 to 30. In an embodiment, the ratio of the first flow rate to the second flow rate is in the range from 0.2 to 5. In an embodiment, the first flow rate and the second flow rate are equal. In an embodiment, the ratio of the second period of time to the first period of time is in the range from 0.01 to less than 1. In an embodiment, the ratio of the second period of time to the first period of time is in the range from 0.04 to 0.5. In an embodiment, during baking, the photoresist layer is heated at a temperature in the range from 70 ℃ to 220 ℃.

Another embodiment of the present disclosure is a method of manufacturing a semiconductor device, including: a photoresist layer comprising a photoresist composition is formed over a substrate. The photoresist layer is patternwise exposed to actinic radiation. After patternwise exposing the photoresist layer to actinic radiation, baking the photoresist layer. During baking of the photoresist layer, a gas is flowed through the space above the photoresist layer. During flowing the gas through the photoresist layer, the gas is supplied to the space above the photoresist layer at a first flow rate from the plurality of first openings of the manifold located above the main surface of the photoresist layer, and the gas is discharged from the space above the photoresist layer through the second openings located in the central portion of the manifold. The gas is discharged from the space above the photoresist layer at the second flow rate during the first period of time, and then the gas is discharged from the space above the photoresist layer at the third flow rate during the second period of time. The third flow rate is greater than the second flow rate. The photoresist layer is developed after baking the photoresist layer to form a pattern in the photoresist layer. In an embodiment, the ratio of the third flow rate to the second flow rate is in the range from greater than 1 to 80. In an embodiment, the ratio of the third flow rate to the second flow rate is in the range from 2 to 30. In an embodiment, the ratio of the first flow rate to the second flow rate is in the range from 0.2 to 5. In an embodiment, the first flow rate and the second flow rate are equal. In an embodiment, the ratio of the second period of time to the first period of time is in the range from 0.01 to less than 1. In an embodiment, the ratio of the second period of time to the first period of time is in the range from 0.04 to 0.5. In an embodiment, during baking, the photoresist layer is heated at a temperature in the range from 70 ℃ to 220 ℃.

Another embodiment of the present disclosure is a semiconductor device manufacturing tool comprising: a processing chamber; and a wafer support disposed inside the processing chamber. The heating element is disposed inside the wafer support and the gas manifold is disposed above the wafer support. The gas manifold includes: a plurality of first openings in a surface of the gas manifold facing the wafer support, the plurality of first openings configured to direct a flow of gas through the first openings toward the wafer support; and one or more second openings configured to exhaust gases from the wafer support. One or more second openings are located in a peripheral portion of the gas manifold or in a central portion of the gas manifold. The controller is configured to control: the flow rate of the gas through the first opening; a flow rate of gas through the one or more second openings; and the temperature of the heating element. In an embodiment, a semiconductor device manufacturing tool includes a source of gas. In an embodiment, a semiconductor device manufacturing tool includes a first vacuum pump in communication with a process chamber. In an embodiment, the semiconductor device manufacturing tool includes a second vacuum pump in communication with the one or more second openings. In an embodiment, the controller is configured to control the flow of gas through the second openings such that during a first period of time when gas is exhausted from the wafer support, gas flows only through the second openings in the peripheral portion of the gas manifold, and then during a second period of time, gas flows through the second openings in the peripheral portion of the gas manifold and the second openings in the central portion of the gas manifold. In an embodiment, the first period of time is controlled to be longer than the second period of time. In an embodiment, the flow rate of the gas through the first opening is in the range from 1L/min to 20L/min; during the first and second time periods, a flow rate of the gas flowing through the second opening in the peripheral portion of the gas manifold is in a range from 1L/min to 20L/min; during a second period of time, the flow rate of the gas flowing through the second opening in the central portion of the gas manifold is in the range from 10L/min to 80L/min. In an embodiment, during the second period of time, the flow rate of the gas flowing through the second opening in the central portion of the gas manifold is greater than the flow rate of the gas flowing through the second opening in the peripheral portion of the gas manifold. In an embodiment, during the second period of time, a flow rate of the gas flowing through the second opening located at the central portion of the gas manifold is greater than a flow rate of the gas flowing through the first opening.

Another embodiment of the present disclosure is a semiconductor device manufacturing tool comprising: a chamber; and an electric heating plate disposed inside the chamber. The gas spray head is arranged above the electric heating plate. One or more gas exhausts are provided near the edge of the gas shower. The controller is configured to control: a first flow rate of gas through the showerhead to the hotplate; after the gas flows through the showerhead, the gas flows through one or more of the second and third flow rates of the gas exhaust; and the temperature of the electric heating plate. During a first period of time, the gas flows through the one or more exhaust gases at a second flow rate, and then during a second period of time, the gas flows through the one or more exhaust gases at a third flow rate. The third flow rate is greater than the second flow rate. In an embodiment, a semiconductor device manufacturing tool includes a source of gas. In an embodiment, a semiconductor device manufacturing tool includes a vacuum pump in communication with one or more gas exhausts. In an embodiment, the ratio of the third flow rate to the second flow rate is in the range from greater than 1 to 80. In an embodiment, the ratio of the first flow rate to the second flow rate is in the range from 0.2 to 5. In an embodiment, the ratio of the second period of time to the first period of time is in the range from 0.01 to less than 1.

Another embodiment of the present disclosure is an apparatus comprising: a chamber; and an electric heating plate disposed inside the chamber. The gas manifold is disposed above the electric heating plate. The gas manifold includes: a plurality of first openings in a surface of the manifold facing the electric hot plates, the plurality of first openings configured to direct gas flow through the first openings to the electric hot plates; and a second opening in the central portion configured to exhaust gas from the electric heating plate. The controller is configured to control: a first flow rate of gas flowing through the first opening to the electric plate; a second flow rate and a third flow rate of the gas discharged from the electric heating plate after the gas flows to the electric heating plate; and the temperature of the electric heating plate. During the first period, gas is discharged from the electric heating plate at a second flow rate, and then during the second period, gas is discharged from the electric heating plate at a third flow rate. The third flow rate is greater than the second flow rate. In an embodiment, the device comprises a vacuum pump in communication with the second opening. In an embodiment, the ratio of the third flow rate to the second flow rate is in the range from greater than 1 to 80. In an embodiment, the ratio of the first flow rate to the second flow rate is in the range from 0.2 to 5. In an embodiment, the ratio of the second period of time to the first period of time is in the range from 0.01 to less than 1.

The foregoing disclosure outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1. A method of manufacturing a semiconductor device, comprising: forming a photoresist layer comprising a photoresist composition over a substrate; selectively exposing the photoresist layer to actinic radiation; heating the photoresist layer after selectively exposing the photoresist layer to actinic radiation, flowing a gas through the photoresist layer during heating the photoresist layer, wherein the flow of the gas is altered during heating the photoresist layer; and developing the photoresist layer after heating the photoresist layer to form a pattern in the photoresist layer.

Example 2 the method of example 1, wherein during the heating, the photoresist layer is heated at a temperature in a range from 70 ℃ to 220 ℃.

Example 3. The method of example 1, wherein during the heating, the photoresist layer is heated for 40 seconds to 200 seconds.

Example 4. The method of example 1, wherein during flowing a gas through the photoresist layer, the gas is supplied to a space above the photoresist layer through a manifold comprising a plurality of gas supply openings and one or more gas exhaust gases, and is exhausted from the space.

Example 5. The method of example 4, wherein the one or more gas exhausts are located in a center portion of the manifold or an edge portion of the manifold.

Example 6 the method of example 5, wherein during a first period of flowing gas through the photoresist layer, the gas is exhausted from only the gas exhaust located at the edge portion of the manifold, and then during a second period of flowing gas through the photoresist layer, the gas is exhausted from the gas exhaust located at the edge portion of the manifold and the gas exhaust located at the center portion of the manifold.

Example 7. The method of example 6, wherein the first period of time is longer than the second period of time.

Example 8 the method of example 6, wherein the first period of time is in a range from 40 seconds to 200 seconds and the second period of time is in a range from 2 seconds to 85 seconds.

Example 9. The method of example 6, wherein: the flow rate of the gas supplied to the space is in a range from 1L/min to 20L/min, the flow rate of the gas exhaust gas through the gas exhaust gas located at the edge portion of the manifold is in a range from 1L/min to 20L/min during the first period and the second period, and the flow rate of the gas exhaust gas through the gas exhaust gas located at the center portion of the manifold is in a range from 10L/min to 80L/min during the second period.

Example 10. The method of example 4, wherein the one or more gas exhausts are located at an edge portion of the manifold.

Example 11 the method of example 10, wherein the gas is exhausted from the one or more gas exhaust gases at a first flow rate during a first period of flowing the gas through the photoresist layer, and then the gas is exhausted from the one or more gas exhaust gases at a second flow rate during a second period of flowing the gas through the photoresist layer, wherein the second flow rate is greater than the first flow rate.

Example 12. The method of example 4, wherein the gas exhaust is located in a central portion of the manifold.

Example 13 the method of example 12, wherein the gas is exhausted from the gas exhaust at a first flow rate during a first period of flowing the gas through the photoresist layer, and then the gas is exhausted from the gas exhaust at a second flow rate during a second period of flowing the gas through the photoresist layer, wherein the second flow rate is greater than the first flow rate.

Example 14. A method of manufacturing a semiconductor device, comprising: forming a photoresist layer comprising a photoresist composition over a substrate; patternwise exposing the photoresist layer to actinic radiation; after patternwise exposing the photoresist layer to actinic radiation, baking the photoresist layer, during baking the photoresist layer, flowing a gas through the photoresist layer, wherein during flowing a gas through the photoresist layer, the gas is supplied to a space above the photoresist layer from a gas shower head located above a major surface of the photoresist layer at a first flow rate, and the gas is exhausted from the space above the photoresist layer through one or more gas exhausts located near a periphery of the shower head, wherein the gas is exhausted from the space above the photoresist layer at a second flow rate for a first period of time, and then the gas is exhausted from the space above the photoresist layer at a third flow rate for a second period of time, wherein the third flow rate is greater than the second flow rate; and developing the photoresist layer after baking the photoresist layer to form a pattern in the photoresist layer.

Example 15 the method of example 14, wherein a ratio of the third flow rate to the second flow rate is in a range from greater than 1 to 80.

Example 16 the method of example 14, wherein a ratio of the first flow rate to the second flow rate is in a range from 0.2 to 5.

Example 17 the method of example 14, wherein a ratio of the second period of time to the first period of time is in a range from 0.01 to less than 1.

Example 18 a semiconductor device manufacturing tool, comprising: a processing chamber; a wafer support disposed inside the processing chamber; a heating element disposed inside the wafer support; a gas manifold disposed over the wafer support, wherein the gas manifold comprises: a plurality of first openings in a surface of the gas manifold facing the wafer support, the plurality of first openings configured to direct a flow of gas through the first openings to the wafer support, and one or more second openings configured to exhaust the gas from the wafer support, wherein the one or more second openings are located in a peripheral portion of the gas manifold or in a central portion of the gas manifold; and a controller configured to control: a flow rate of the gas through the first opening; a flow rate of the gas through the one or more second openings; and the temperature of the heating element.

Example 19 the semiconductor device manufacturing tool of example 18, wherein the controller is configured to control the flow of the gas through the second openings such that during a first period of time the gas is exhausted from the wafer support, the gas flows only through the second openings in the peripheral portion of the gas manifold, and then during a second period of time, the gas flows through the second openings in the peripheral portion of the gas manifold and the second openings in the central portion of the gas manifold.

Example 20 the semiconductor device manufacturing tool of example 19, wherein: the flow rate of the gas flowing through the first opening is in a range from 1L/min to 20L/min, the flow rate of the gas flowing through the second opening located in the peripheral portion of the gas manifold is in a range from 1L/min to 20L/min during the first period and the second period, and the flow rate of the gas flowing through the second opening located in the central portion of the gas manifold is in a range from 10L/min to 80L/min during the second period.

Claims

1. A method of manufacturing a semiconductor device, comprising:

Forming a photoresist layer comprising a photoresist composition over a substrate;

selectively exposing the photoresist layer to actinic radiation;

after selectively exposing the photoresist layer to actinic radiation, heating the photoresist layer,

during heating of the photoresist layer, a gas is flowed through the photoresist layer,

wherein the flow of the gas is changed during heating of the photoresist layer; and

the photoresist layer is developed after heating the photoresist layer to form a pattern in the photoresist layer.

2. The method of claim 1, wherein during the heating, the photoresist layer is heated at a temperature in a range from 70 ℃ to 220 ℃.

3. The method of claim 1, wherein the photoresist layer is heated for 40 seconds to 200 seconds during the heating.

4. The method of claim 1, wherein during flowing gas through the photoresist layer, the gas is supplied to a space above the photoresist layer through a manifold comprising a plurality of gas supply openings and one or more gas exhaust gases, and is exhausted from the space.

5. The method of claim 4, wherein the one or more gas exhausts are located in a central portion of the manifold or an edge portion of the manifold.

6. The method of claim 5, wherein during a first period of flowing gas through the photoresist layer, the gas is exhausted from only the gas exhaust at the edge portion of the manifold, and then during a second period of flowing gas through the photoresist layer, the gas is exhausted from the gas exhaust at the edge portion of the manifold and the gas exhaust at the center portion of the manifold.

7. The method of claim 6, wherein the first period of time is longer than the second period of time.

8. The method of claim 6, wherein the first period of time is in a range from 40 seconds to 200 seconds and the second period of time is in a range from 2 seconds to 85 seconds.

9. A method of manufacturing a semiconductor device, comprising:

patternwise exposing the photoresist layer to actinic radiation;

after the photoresist layer is patternwise exposed to actinic radiation, the photoresist layer is baked,

During baking of the photoresist layer, a gas is flowed through the photoresist layer,

wherein, during the flowing of the gas through the photoresist layer, the gas is supplied from a gas shower head located above the main surface of the photoresist layer to a space above the photoresist layer at a first flow rate, and

the gas is exhausted from the space above the photoresist layer through one or more gas exhausts located near the periphery of the showerhead,

wherein the gas is discharged from the space above the photoresist layer at a second flow rate during a first period of time, and then the gas is discharged from the space above the photoresist layer at a third flow rate during a second period of time,

wherein the third flow rate is greater than the second flow rate; and

the photoresist layer is developed after baking the photoresist layer to form a pattern in the photoresist layer.

10. A semiconductor device manufacturing tool, comprising:

a processing chamber;

a wafer support disposed inside the processing chamber;

a heating element disposed inside the wafer support;

a gas manifold disposed over the wafer support,

Wherein the gas manifold comprises:

a plurality of first openings in a surface of the gas manifold facing the wafer support, the plurality of first openings configured to direct a flow of gas through the first openings to the wafer support, and

one or more second openings configured to exhaust the gas from the wafer support,

wherein the one or more second openings are located in a peripheral portion of the gas manifold or in a central portion of the gas manifold; and

a controller configured to control:

a flow rate of the gas through the first opening;

a flow rate of the gas through the one or more second openings; and

the temperature of the heating element.