CN116997803A

CN116997803A - Special test pin for ink-jet printing

Info

Publication number: CN116997803A
Application number: CN202280021657.9A
Authority: CN
Inventors: A·帕蒂尔; 卫洪博; J·R·V·鲍特
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2021-04-06
Filing date: 2022-02-28
Publication date: 2023-11-03
Also published as: BR112023019777A2; EP4320449A1; WO2022217175A1; US20220320016A1; KR20230167036A; TW202249191A

Abstract

In one aspect, an apparatus includes a package (100). The package includes a substrate (104), a plurality of components (102) located on a top surface of the substrate, a plurality of ball pads (302) located on a bottom surface of the substrate, a plurality of balls (108), and a plurality of test pads (304) located on the bottom surface of the substrate. Individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads.

Description

Special test pin for ink-jet printing

Technical Field

Aspects of the present disclosure relate generally to semiconductor fabrication, and in particular, to eliminating a portion of a contact (e.g., ball or pin) left on an integrated circuit for testing purposes by inkjet printing dedicated test pins for testing.

Background

In semiconductor packages, dedicated connections (vias, etc.) are used to sense (e.g., test) a Power Distribution Network (PDN), a Power Management IC (PMIC), etc. In a single chip or multi-chip module, multiple dies are placed with multiple passive devices and other devices. The die may be located on a substrate or inside a package.

To test a semiconductor, the semiconductor is mounted on a test printed circuit board PCB and sensing is performed to check a voltage level, a current level, etc. at a specific point. Sensing is performed at points such as hard macros (specifying how the required logic elements are interconnected, and specifying the physical paths and wiring patterns between components), logic of the PMIC, logic of the application processor die, and so forth. A portion of a contact (e.g., a pin or ball) called a test pin is used to expose the point at which sensing is performed. Typically, about 9% of the contacts of the semiconductor are dedicated to the test pins.

After the test is completed, the test pins are no longer used. For example, when the semiconductor is used in manufacturing a product, the test pins are not used. Thus, since the test pins are only used during testing, a significant portion of the pins are wasted by dedicating a portion of the pins to the test pins. For semiconductor packages with a limited number of pins, this is a waste of available pins.

Disclosure of Invention

The following presents a simplified summary in relation to one or more aspects disclosed herein. Accordingly, the following summary is not to be considered an extensive overview of all contemplated aspects, nor is it to be considered as identifying key or critical elements of all contemplated aspects or as delineateing the scope associated with any particular aspect. Accordingly, the sole purpose of the summary below is to present some concepts related to one or more aspects related to the mechanisms disclosed herein in a simplified form prior to the detailed description that is presented below.

In a first aspect, an apparatus includes a package. The package includes a substrate, a plurality of components located on a top surface of the substrate, a plurality of ball pads located on a bottom surface of the substrate, a plurality of balls, and a plurality of test pads located on the bottom surface of the substrate. Individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads. In some aspects (e.g., prior to testing the package), individual test pins may be attached to individual ones of the plurality of test pads. In other aspects, a solder resist may be applied over individual ones of the plurality of test pads to prevent access to the individual test pads.

In a second aspect, a method of making a package may include attaching a component to a top surface of a substrate, forming a plurality of ball pads on a bottom surface of the substrate, and attaching a plurality of balls to the plurality of ball pads. Individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads. The method includes forming a plurality of test pads on a bottom surface of a substrate. In some aspects (e.g., prior to testing the package), individual test pins may be extruded on individual ones of the plurality of test pads. In other aspects, a solder resist may be applied over individual ones of the plurality of test pads to prevent access to the individual test pads.

Other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art based on the drawings and the detailed description.

Drawings

The drawings are presented to aid in describing various aspects of the disclosure and are provided solely for illustration of these aspects and not limitation thereof. A more complete understanding of the present disclosure may be obtained by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears. The same reference numbers in different drawings identify similar or identical items.

Fig. 1 is a block diagram illustrating a semiconductor with inkjet printed test pins according to various aspects of the present disclosure.

Fig. 2 is a block diagram illustrating mounting a semiconductor with inkjet printed test pins on a test PCB according to aspects of the present disclosure.

Fig. 3A, 3B, 3C, and 3D illustrate a portion of a process for producing a semiconductor including ball pads and test pads in accordance with aspects of the present disclosure.

Fig. 4A, 4B, and 4C illustrate the remainder of the process for producing a semiconductor, wherein test pins are extruded prior to attaching balls, according to aspects of the present disclosure.

Fig. 5A, 5B, and 5C illustrate the remainder of the process for producing a semiconductor, wherein test pins are extruded after attaching balls, according to aspects of the present disclosure.

Fig. 6A, 6B illustrate applying a solder resist during semiconductor fabrication while holding the ball attachment open and covering the pin attachment to enable the ball to be attached, in accordance with aspects of the present disclosure.

Fig. 7 illustrates a process including attaching a plurality of test pins to a plurality of test pads in accordance with aspects of the present disclosure.

Fig. 8 illustrates a process including printing test pins using inkjet printing according to aspects of the present disclosure.

Fig. 9 illustrates an exemplary mobile device in accordance with one or more aspects of the present disclosure.

Fig. 10 illustrates various electronic devices that may be integrated with an integrated device or a semiconductor device in accordance with one or more aspects of the present disclosure.

Detailed Description

Systems and techniques for ink-jet printing a plurality of test pins between normal contacts (e.g., pins or balls) of a package using conductive paste are disclosed. As used herein, the term "package" may refer to a device that includes one or more dies coupled to a substrate. In some aspects, the package may be configured as one or more functional modules or system-on-a-chip (SoC) devices. The height of the test pins is less than the height of the normal contacts. The balls (or pins) may have a height of between about 135um (microns) to about 155um, while the test pins may have a height of between about 30um to about 50 um. The test pins may be circular, oval, square, or rectangular in shape, and each may have a length between about 50um to 100um and a width between about 50um to 100 um. For ease of understanding, the test pins are illustrated as having a rectangular shape to distinguish the test pins from balls (having a circular or oval shape). The test pins may be rectangular (including square) or oval (including circular) to enable the test pins to be extruded into the available space. Systems and techniques may be used for semiconductors using Ball Grid Array (BGA) pitches of 350 microns or greater. The advantage of this approach is that all pins of the package can be used to provide functionality, rather than dedicating up to 9% of the pins for testing purposes. Additional pins may be used to provide new functionality that the manufacturer may use when using semiconductors in manufacturing products. Furthermore, the form factor of the package may be reduced by removing pins dedicated to testing.

Test pins are extruded on the substrate between the normal patterns for the contacts. The test pins replace dedicated test sense pins in conventional semiconductors. The test pins are inkjet printed to the substrate using a conductive paste. The test pins are soldered to a Printed Circuit Board (PCB) for testing the semiconductor by using (1) Land Grid Array (LGA) attachment for attaching the test pins to the test PCB and (2) BGA attachment mechanisms for contacts (e.g., pins or balls) of the package. Accordingly, test pins are generated for the semiconductor packages mounted on the test board for testing. When the semiconductor package is manufactured for use in a product, the test pins are not ink jet printed on the substrate. During fabrication, the test pads are covered (e.g., using a solder mask or the like), on which the test pins are extruded and used to connect to the internal sense lines. Internally, the test pads hang or float on the last metal layer. Thus, there are no extruded test pins in a semiconductor package designed for inclusion in a product. Thus, all normal contacts (e.g., pins or balls) may be used for functional purposes, as no normal contacts are reserved for testing purposes.

When a semiconductor package having extruded test pins is mounted on a test PCB, the test PCB has separate test attachment pads to connect to the extruded test pins. Using reflow or Surface Mount (SMT) attachment, the semiconductor package with the extruded test pins is mounted on the test PCB using the following 2 simultaneous processes: (a) BGA attachment mechanisms for normal pins or balls, and (b) LGA attachment for extruded test pins. Thus, a single reflow process is used to attach either the normal package pins or both the balls and the extruded test pins. Semiconductor package contacts (e.g., pins or balls) may be added before or after the test pins are extruded onto the substrate.

Aspects of the disclosure are provided in the following description and related drawings for various examples provided for purposes of illustration. Alternate aspects may be devised without departing from the scope of the disclosure. Furthermore, well-known elements of the present disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of the present disclosure.

The words "example" and/or "illustration" are used herein to mean "serving as an example, instance, or illustration. Any aspect described herein as "example" and/or "example" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspects of the disclosure" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation.

Those of skill in the art would understand that information and signals described below may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the following description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof, depending in part on the particular application, on the desired design, on the corresponding technology, and so forth.

Additionally, many aspects are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application Specific Integrated Circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Furthermore, the sequence of action(s) described herein may be considered to be embodied entirely within any form of non-transitory computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause or instruct an associated processor of a device to perform the functions described herein. Thus, the various aspects of the disclosure may be embodied in a number of different forms, all of which are contemplated to be within the scope of the claimed subject matter. Moreover, for each of the aspects described herein, the corresponding form of any such aspect may be described herein as, for example, "logic configured to" perform the described action.

As a first example, an apparatus (e.g., including a package, such as a system on a chip) includes a substrate, a plurality of components located on a top surface of the substrate, a plurality of ball pads located on a bottom surface of the substrate, a plurality of balls, a plurality of test pads located on a bottom surface of the substrate, and a plurality of test pins. Individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads, and individual test pins are attached to individual test pads of the plurality of test pads. The individual test pins are lower in height than the individual balls. Individual ones of the plurality of test pads are located between adjacent ones of the plurality of balls. The individual test pads are approximately equidistant from adjacent balls. Individual ones of the plurality of test pins are connected to one or more sense lines. A plurality of test pins are attached to a printed circuit board using a Land Grid Array (LGA) and a plurality of balls are attached to the printed circuit board using a Ball Grid Array (BGA). Individual ones of the plurality of test pins are configured to be accessed to test one or more parameters of one or more of: a Power Distribution Network (PDN), a Power Management IC (PMIC), or an application processor die. The package is included in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile phones, smart phones, personal digital assistants, fixed location terminals, tablet computers, wearable devices, internet of things (IoT) devices, laptop computers, servers, base stations, access points, radio Frequency (RF) modules, and devices in motor vehicles.

As a second example, a method of making a package includes: attaching the assembly to a top surface of the substrate, forming a plurality of ball pads on a bottom surface of the substrate, attaching a plurality of balls to the plurality of ball pads, forming a plurality of test pads located on the bottom surface of the substrate, and attaching a plurality of test pins to the plurality of test pads. Individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads, and individual test pins are attached to individual test pads of the plurality of test pads. The individual test pins are lower in height than the individual balls. The method may include performing an Organic Solderability Preservative (OSP) surface treatment or performing an electrolytic nickel-gold (Ni-Au) surface treatment (e.g., where a gold layer is plated over a nickel electroplated substrate). The method may include applying a solder resist to the pin attachment layer without covering the plurality of ball pads and the plurality of test pads. The method may include extruding and curing a plurality of test pins to the pin attachment layer substantially simultaneously. For example, individual test pins may be extruded and cured on top of individual ones of the plurality of test pads. The method may include attaching a plurality of balls to the pin attachment layer. For example, individual balls of the plurality of balls may be attached to individual ball pads of the plurality of ball pads. In some cases, the test pins may be extruded and cured before attaching the plurality of balls, while in other cases, the test pins may be extruded and cured after attaching the plurality of balls. Extruding and curing the plurality of test pins to the pin attachment layer substantially simultaneously may include extruding conductive paste using a nozzle of an inkjet printer to produce the plurality of test pins, and curing the plurality of test pins using a laser flash while extruding the plurality of test pins. The package may be mounted to a Printed Circuit Board (PCB) using a reflow process in which a plurality of test pins are attached to the printed circuit board using a Land Grid Array (LGA) attachment process while simultaneously attaching a plurality of balls to the printed circuit board using a Ball Grid Array (BGA) attachment process. Individual ones of the plurality of test pins are connected to one or more sense lines in the package. For example, the package may be mounted on a Printed Circuit Board (PCB) and individual test pins are used to access one or more sense lines. The one or more sense lines can be used to test one or more parameters of at least one of: a Power Distribution Network (PDN), a Power Management Integrated Circuit (PMIC), or an application processor die.

Fig. 1 is a block diagram illustrating a package 100 (e.g., semiconductor) with inkjet printed test pins according to various aspects of the present disclosure. As used herein, the term "package" refers to a device that includes one or more dies coupled to a substrate. In some aspects, the package may be configured as one or more functional modules or system-on-a-chip (SoC) devices. The package 100 includes a plurality of components 102 on top of a substrate 104. Solder resist 106 is located on a portion of the bottom surface of package 100. For example, where the solder resist 106 is not present, the bottom of the package 100 includes a plurality of balls 108 and a plurality of test pins 110. Each test pin 110 is located at approximately equal distances from adjacent balls 108. The test pins 110 enable access to sense lines 112 inside the package 100, thereby enabling testing of Power Distribution Networks (PDNs), power Management ICs (PMICs), and the like. For ease of understanding, the test pins 110 are illustrated as having a rectangular shape to distinguish from the balls 108 (having a circular or oval shape). However, it should be understood that the test pins 110 may have any type of geometry (e.g., rectangular, oval, etc.).

Each of the balls 108 may be used to provide functionality to the components of the package 100, wherein no balls 108 are reserved for sensing or testing. The balls 108 may be arranged in a conventional pattern associated with, for example, a Ball Grid Array (BGA) or other type of package. Of course, although balls 108 are illustrated in fig. 1, another type of contact, such as a pin, may be used to mount the package 100 to a Printed Circuit Board (PCB).

The test pins 110 are extruded onto the bottom of the package 100 using an inkjet printer using conductive paste either before the balls 108 are added or after the balls 108 are added to the package 100. The height of each test pin 110 is less than the height of each ball 108. The sense line 112 connects from the die/package (e.g., active device) to the test feature (e.g., for PDN, PMIC, etc.). In some cases, sense line 112 may be connected from a passive device (e.g., an inductor/capacitor) to a test feature. The sense line 112 is shown in a cross-sectional view of the package 100.

Thus, the test pins are squeezed out between contacts (e.g., balls or pins) of the package using an inkjet printer prior to testing, the test pins enabling access to internal sense lines to perform various measurements while testing the package. The advantage of using an inkjet printer to extrude test pins for testing is that all contacts of the package can be used to provide functionality and avoid the traditional approach of dedicating a portion (e.g., up to 9%) of the contacts to access the internal sense lines. In conventional approaches, reserving a portion of the contacts to access the internal sense lines results in "reserved" contacts that are not used when the package is incorporated into a product. The extruded test pins may be used with, for example, an Access Point (AP) module, a Radio Frequency (RF) module, or any processing module including PMIC systems. The extruded test pins can be used for single die packages with PDN test sense lines.

Fig. 2 is a block diagram 200 illustrating mounting a semiconductor with inkjet printed test pins on a test PCB in accordance with aspects of the present disclosure. To test the package 100, the package 100 may be mounted to a Printed Circuit Board (PCB) specifically designed for testing the package 100. The mounting process is performed as follows.

The balls 108 of the package 100 are aligned with ball sockets 204 on the PCB 202. Solder paste 208 is printed over each of the pin receptacles 206 in the openings of the solder resist 210 in the PCB 202. Each test pin 110 of the package 100 is soldered to a pin socket 206 using solder paste 208.

In a single reflow, the package 100 is mounted on the test PCB 202 using the following two simultaneous processes: (a) A Ball Grid Array (BGA) attachment mechanism 212 to attach the balls 108 to the ball sockets 204, and (b) a Land Grid Array (LGA) attachment mechanism 214 to attach the extruded test pins 110 to the pin sockets 206. Test pins 110 enable PCB 202 to access sense lines 112 to test various features of package 100. When the package 100 is used in manufacturing a product, the test pin 110 is not present, thereby preventing access to the sense line 112.

Thus, after the extruded test pins are added to the package, the package is mounted to the test PCB in a direct reflow process using both BGA and LGA attachment mechanisms, e.g., attaching the package with the test pins to the test PCB does not involve exotic, unusual, complex or expensive mechanisms.

Fig. 3A, 3B, 3C, and 3D illustrate a portion of a process for producing a semiconductor including ball pads and test pads in accordance with aspects of the present disclosure. The process may be performed when manufacturing a semiconductor package, such as package 100 of fig. 1 and 2.

Fig. 3A illustrates the construction of the substrate 104. The substrate 104 may include multiple layers (e.g., 2 to 20 or more layers in some cases). Each layer of substrate 104 is added by a number of processes, such as a cored substrate, a coreless substrate, an flavoured film build-up (ABF) process, and the like. The build-up of the substrate 104 may include building up each layer, such as lamination, patterning over Cu (copper), exposure, development, and the like. The build up of the substrate 104 can include adding sense lines 112 to the substrate 104.

Fig. 3B illustrates the addition of ball pads 302 and test pads 304. Test pad 304 enables access to sense line 112 in substrate 104. Fig. 3C illustrates the addition of a solder resist 106 (e.g., a solder mask) to a portion of the upper surface of the substrate 104. In particular, the solder resist 106 does not cover the ball pads 302 and does not cover the test pads 304 to enable the ball and test pins to be attached to the substrate 104 at later points in the process. Fig. 3D illustrates the addition of components 102 on opposite sides of ball pads 302 and test pads 304.

A portion of the process illustrated by fig. 3A, 3B, 3C, and 3D may be accomplished using the process illustrated in fig. 4A, 4B, and 4C or the process illustrated in fig. 5A, 5B, and 5C. For ease of understanding, sense line 112 is not illustrated in the remaining figures, but it should be understood that sense line 112 exists in fig. 4A, 4B, and 4C, and fig. 5A, 5B, and 5C.

Fig. 4A illustrates the use of an inkjet printer 402 to extrude conductive paste 404 using sintering to create test pins 110 on top of test pads 304. Sintering (also referred to as firing) is a process that includes compacting and forming solid blocks (e.g., each of the test pins 110) using the extruded conductive paste 404. The test pins 110 are preferably extruded after the Surface Mount Technology (SMT) process has been performed. For example, laser flash 406 is used to cure test pins 110 without using an oven. The test pins 110 are printed and cured substantially simultaneously so that each of the test pins 110 is capable of maintaining a vertical shape and geometry. The laser flash 406 uses photo-curing, i.e., a process in which the extruded conductive paste 404 is exposed to pulsed light from the laser flash 406 for about 1 millisecond (ms).

The height H1 406 of each of the test pins 110 is less than the height H2 408 of each of the balls 108. Fig. 4B illustrates the printing of solder paste 208 on each pin receptacle 206 prior to mounting the package 100 to the PCB 202. Fig. 4C illustrates the package 100 mounted to a test PCB 202, with each of the balls 108 attached to a corresponding ball socket 204 (e.g., using BGA attachment mechanism 212) and each of the test pins 110 attached to a corresponding pin socket 206 (e.g., using LGA attachment mechanism 214).

Fig. 5A, 5B, and 5C illustrate the remainder of the process for producing a semiconductor, wherein the test pins are extruded after the balls are attached, according to aspects of the present disclosure. Fig. 5A illustrates the attachment of each of the balls 108 to each of the ball pads 302.

Fig. 5B illustrates the use of an inkjet printer 402 to extrude conductive paste 404 using sintering to create test pins 110 on top of test pads 304. The test pins 110 are preferably extruded after the Surface Mount Technology (SMT) process has been performed. For example, laser flash 406 is used to cure test pins 110 without using an oven for curing. The test pins 110 are printed and cured substantially simultaneously so that each of the test pins 110 is capable of maintaining a vertical shape and geometry. The height H1 406 of each test pin 110 is less than the height H2 408 of each of the balls 108. Fig. 5B illustrates the placement of solder paste 208 on each pin receptacle 206 prior to mounting the package 100 to the PCB 202. Fig. 5C illustrates the package 100 mounted to the test PCB 202 with each of the balls 108 attached to a corresponding ball socket 204 (e.g., using BGA attachment mechanism 212) and each of the test pins 110 attached to a corresponding pin socket 206 (e.g., using LGA attachment mechanism)

Fig. 6A, 6B illustrate applying a solder resist during semiconductor fabrication while holding the ball attachment open and covering the pin attachment to enable the ball to be attached, in accordance with aspects of the present disclosure. Fig. 6A illustrates the application of the solder resist 106 during semiconductor fabrication such that the ball pads 302 are open (e.g., uncovered) and the test pads 304 are covered with the solder resist 106. This is done when manufacturing packages that are to be incorporated into products, for example (e.g., rather than attached to a test PCB for testing purposes). Fig. 6B illustrates the attachment of two of the balls 108 to two of the corresponding ball pads 302. Test pad 304 remains covered with solder resist 106, making sense lines (e.g., such as representative sense line 306 of fig. 3B) inaccessible.

In the flowcharts of fig. 7 and 8, each block represents one or more operations that may be implemented in hardware, software, or a combination thereof. In the context of software, the blocks represent computer-executable instructions that, when executed by one or more processors, cause the processors to perform the recited operations. Generally, computer-executable instructions include routines, programs, objects, modules, components, data structures, etc. that perform particular functions or implement particular abstract data types. The order in which the blocks are described is not intended to be construed as a limitation, and any number of the described operations may be combined in any order and/or in parallel to implement a process. For discussion purposes, the processes 700 and 800 are described above with reference to fig. 1, 2, 3A-3C, 4A-4C, 5A-5C, and 6A-6B, although other models, frameworks, systems, and environments may be used to implement the processes.

Fig. 7 illustrates a process 700 including attaching a plurality of test pins to a plurality of test pads in accordance with aspects of the present disclosure. The process may be performed as part of a semiconductor manufacturing process, which is described herein.

At 702, the process attaches a component to a top surface of a substrate. For example, in fig. 3D, component 102 is attached to substrate 104.

At 704, a plurality of ball pads are formed on a bottom surface of a substrate. At 706, the process attaches a plurality of balls to a plurality of ball pads (e.g., where individual balls are attached to individual ball pads). For example, in fig. 4B and 5A, individual balls 108 are formed and attached to individual ones of ball pads 302.

At 708, the process forms a plurality of test pads on a bottom surface of the substrate. For example, in fig. 3B, test pads 304 are formed on substrate 104. If the package is to be used in manufacturing a product, the process may cover the test pads 304 with the solder resist 106, as illustrated in FIG. 6A. If the package is to be used for testing, the process may extrude test pins 110 on test pads 304, as illustrated in FIGS. 4A and 5B.

Thus, a package with test pads is manufactured. Prior to testing the packages, an inkjet printer is used to extrude test pins between contacts (e.g., balls or pins) of the packages. The test pins enable access to the internal sense lines to determine various parameters when testing the package. A technical advantage of using an inkjet printer to extrude test pins for testing is that all of the contacts of the package can be used to provide functionality rather than dedicating a portion (e.g., up to 9%) of the contacts to access the internal sense lines. By not reserving a portion of the contacts to access the internal sense lines, all of the contacts can be used when the package is incorporated into a product. In some cases, not retaining a portion of the contacts may enable the number of contacts to be reduced, thereby reducing the form factor of the package, as a further technical advantage. As consumer products such as User Equipment (UE) shrink in size, the form factor of packages used in the UE may be reduced without degrading functionality. Alternatively, as a further technical advantage, the use of all contacts in the package may enable additional functionality to be provided. The extruded test pins may be used with, for example, an Access Point (AP) module, a Radio Frequency (RF) module, or any processing module including PMIC systems. For example, the extruded test pins may be used with a single die package having PDN test sense lines. After the test has been completed and the package is ready for manufacture, the test pads are covered with solder resist. When the package is manufactured for inclusion in a product (e.g., a user device), a technical advantage of covering the test pads with a solder resist is that the solder resist prevents access to the test pads and internal sense lines in the package.

Fig. 8 illustrates a process 800 including printing test pins using inkjet printing according to aspects of the present disclosure. The process may be performed as part of a semiconductor manufacturing process, which is described herein.

At 802, the process builds a substrate of a semiconductor, including adding a pin attachment layer, plating and patterning for sense lines and test pads. For example, in fig. 3B, a semiconductor is built using substrate 104 and adding a pin attachment layer (e.g., a final metal layer), copper (Cu) plating, and patterning. The process includes adding test pads 304 and ball pads 302.

At 804, the process deposits a solder mask without covering the ball pads and the test pads. At 806, the process surface treats the surface. For example, in fig. 3C, the solder resist 106 is added without covering the ball pads 302 and the test pads 304. The entire surface is surface-treated using, for example, an Organic Solderability Preservative (OSP) surface treatment, an electrolytic Ni-Au (nickel-gold) surface treatment (e.g., a gold layer, plated on top of a nickel electroplated substrate), or similar surface treatment.

At 808, the process adds the component and dicing assembly to the substrate. For example, in fig. 3D, component 102 is added to substrate 104.

In some aspects (e.g., extruding the test pins prior to attaching the balls), the process prints the test pins at a height H1 using inkjet printing at 810. At 812, the process attaches a ball with a height H2 (H1 < H2). For example, in fig. 4A and 4B, an inkjet printer 402 is used to extrude a conductive paste 404 using sintering to create test pins 110 over test pads 304. The test pins 110 are cured using a laser flash 406 substantially at the same time they are printed. After the test pins 110 have been printed and cured, each of the balls 108 is attached to a corresponding one of the ball pads 302.

In other aspects (e.g., extruding the test pins after attaching the balls), the process attaches the balls with a height H2 at 814. At 816, the process prints the test pins having a height H1 (H1 < H2) by using an inkjet printer (e.g., extruding the test pins using conductive paste). For example, in fig. 5A and 5B, each of the balls 108 is attached to a corresponding one of the ball pads 302. After attaching the balls 108, the inkjet printer 402 is used to extrude the conductive paste 404 using sintering to create the test pins 110 over the test pads 304. The test pins 110 are cured using a laser flash 406 substantially at the same time they are printed.

At 818, the process prints solder paste to the pin sockets on the test board. At 820, the semiconductor is attached to a test board. At 822, testing is performed using the test pins to access sense lines in the semiconductor. For example, in fig. 4B, 4C, 5B, 5C, solder paste 208 is applied to each of the pin receptacles 206 of the PCB 202. The package 100 is mounted to a test PCB 202 with each of the balls 108 attached to a corresponding ball socket 204 (e.g., using BGA attachment mechanism 212) and each of the test pins 110 attached to a corresponding pin socket 206 (e.g., using LGA attachment mechanism 214).

Thus, a package including the test pad is manufactured. Prior to testing the packages, an inkjet printer is used to extrude test pins between contacts (e.g., balls or pins) of the packages. The test pins enable access to the internal sense lines to determine various parameters when testing the package. A technical advantage of using an inkjet printer to extrude test pins is that all contacts of the package can be used to provide functionality, thereby avoiding dedicating a portion (e.g., up to 9%) of the contacts to access the internal sense lines. The size of the package may be reduced if fewer contacts are used or the manufacturer provides access to additional functionality via contacts previously reserved for testing. After the test is complete and the package is ready to be manufactured for inclusion in a customer product (e.g., user equipment), the test pads are covered with solder resist. The technical advantage of the solder resist is to prevent access to the test pads and the internal sense lines.

Fig. 9 illustrates an exemplary mobile device incorporating a system on a chip (SOC) 900 in accordance with some examples of the present disclosure. In some aspects, the mobile device of fig. 9 may be configured as a wireless communication device. As shown, the mobile device of fig. 9 includes a processor 901. The processor 901 may be communicatively coupled to the memory 932 via a link, which may be a die-to-die or chip-to-chip link. Processor 901 is a hardware device capable of executing logical instructions. The mobile device of fig. 9 also includes a display 928 and a display controller 926, wherein the display controller 926 is coupled to the processor 901 and the display 928.

In some aspects, fig. 9 can include a coder/decoder (CODEC) 934 (e.g., an audio and/or voice CODEC) coupled to the processor 901; a speaker 936 and a microphone 938 coupled to the CODEC 934; and wireless circuitry 940 (which may include modems, RF circuitry, filters, etc., which may be implemented using ball sockets 204 and pin sockets 206) coupled to wireless antenna 942 and processor 901.

In a particular aspect, where one or more of the above-described blocks are present, processor 901, display controller 926, memory 932, CODEC 934, and wireless circuitry 940 may be included in SOC 900, and SOC 900 may be implemented in whole or in part using pin receptacle 206 and ball receptacle 204 as disclosed herein. Input device 930 (e.g., a physical or virtual keyboard), power supply 944 (e.g., a battery), display 928, input device 930, speaker 936, microphone 938, wireless antenna 942, and power supply 944 may be external to SOC 900 and may be coupled to components of SOC 900 such as an interface or controller.

One or more of the components, such as processor 901, memory 932, display controller 926, radio 940, and codec 934, may be fabricated using the systems and techniques described herein, for example, using inkjet printed test pins to access internal sense lines of the component when the component is mounted on a test PCB for testing. When the assembly is manufactured for inclusion in a product (such as the mobile device of fig. 9), the test pins may not be printed.

It should be noted that although fig. 9 depicts a mobile device, the processor 901 and memory 932 may also be integrated into a set top box, music player, video player, entertainment unit, navigation device, personal Digital Assistant (PDA), fixed location data unit, computer, laptop computer, tablet computer, communications device, mobile phone, or other similar device.

Fig. 10 illustrates various electronic devices that may be integrated with any of the foregoing integrated devices or semiconductor packages, according to various examples of the present disclosure. For example, mobile phone device 1002, laptop computer device 1004, and fixed location terminal device 1006 may each be considered a general User Equipment (UE) and may include enclosure 1000 as described herein. Package 1000 may be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated Circuit (IC) packages, package on package devices described herein. The devices 1002, 1004, 1006 illustrated in fig. 10 are merely exemplary. Other electronic devices may also feature enclosure 1000, including but not limited to a set of devices (e.g., electronic devices), including mobile devices, hand-held Personal Communication Systems (PCS) units, portable data units such as personal digital assistants, global Positioning System (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smart phones, tablet computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), internet of things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

It may be noted that although specific frequencies, integrated Circuits (ICs), hardware, and other features are described in various aspects herein, alternative aspects may vary. That is, alternative aspects may utilize additional or alternative frequencies (e.g., other than the 60GHz and/or 28GHz bands), antenna elements (e.g., arrays of antenna elements having different sizes/shapes), scanning periods (including static and dynamic scanning periods), electronic devices (e.g., WLAN APs, cellular base stations, smart speakers, ioT devices, mobile phones, tablet computers, personal Computers (PCs), etc.), and/or other features. One of ordinary skill in the art will recognize such variations.

It should be appreciated that any reference herein to an element using a designation such as "first," "second," or the like generally does not limit the number or order of such elements. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to first and second elements does not mean that only two elements may be employed there, or that the first element must precede the second element in some way. Further, unless otherwise indicated, a set of elements may comprise one or more elements. Furthermore, the term used in the specification or claims in the form of "at least one of A, B or C" or "one or more of A, B or C" or "at least one of the group consisting of A, B and C" means "a or B or C or any combination of these elements. For example, this term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, etc.

Those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

As can be seen from the above detailed description, the different features are combined in an example. This manner of disclosure should not be understood as an intention of the example clauses to have more features than are expressly recited in each clause. Rather, aspects of the disclosure can include less than all of the features of a single disclosed example clause. Accordingly, the following clause requirements should be considered incorporated herein as if each clause itself were individually exemplified. Although each subordinate clause may reference a particular combination with one of the other clauses in each clause, the aspect(s) of the subordinate clause are not limited to a particular combination. It should be understood that other example clauses may also include combinations of aspect(s) of subordinate clauses with the subject matter of any other subordinate clauses or independent clauses, or combinations of any feature with other subordinate and independent clauses. Various aspects disclosed herein expressly include such combinations unless expressly stated or it can be readily inferred that a particular combination is not intended (e.g., contradictory aspects such as defining elements as both insulators and conductors). Furthermore, aspects of the clause may also be intended to be included in any other independent clause, even if the clause is not directly dependent on the independent clause. Implementation examples are described in the following numbered clauses:

Clause 1. A method of making a package, the method comprising: attaching the assembly to a top surface of the substrate; forming a plurality of ball pads on a bottom surface of a substrate; attaching a plurality of balls to the plurality of ball pads, wherein individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads; and forming a plurality of test pads on the bottom surface of the substrate.

Clause 2. The method of clause 1, further comprising: a plurality of test pins are attached to the plurality of test pads, wherein individual test pins are attached to individual ones of the plurality of test pads, and wherein individual test pins are lower in height than individual balls.

Clause 3 the method of clause 2, further comprising: applying a solder resist to the pin attachment layer, wherein the plurality of ball pads and the plurality of test pads are not covered by the solder resist; and extruding and curing the plurality of test pins to the pin attachment layer substantially simultaneously, wherein individual test pins are extruded and cured on top of individual ones of the plurality of test pads.

Clause 4. The method of clause 3, wherein extruding and curing the plurality of test pins to the pin attachment layer substantially simultaneously comprises: extruding the conductive paste using a nozzle of an inkjet printer to produce a plurality of test pins; and curing the plurality of test pins using a laser flash while the plurality of test pins are being extruded.

Clause 5 the method of any of clauses 2 to 4, wherein the package is mounted to a Printed Circuit Board (PCB) using a reflow process comprising: attaching a plurality of test pins to a printed circuit board using a Land Grid Array (LGA) attachment process; and attaching the plurality of balls to the printed circuit board using a Ball Grid Array (BGA) attachment process.

Clause 6 the method of any of clauses 2 to 5, wherein individual ones of the plurality of test pins are connected to one or more sense lines located in the package.

Clause 7 the method of clause 6, further comprising: mounting the package on a Printed Circuit Board (PCB); and accessing the one or more sense lines using one or more separate test pins.

Clause 8 the method of clause 7, further comprising: one or more parameters of at least one of a Power Distribution Network (PDN), a Power Management Integrated Circuit (PMIC), or an application processor die are tested using one or more sense lines.

The method of any of clauses 2-8, wherein each of the plurality of test pins has a height of between about 30 microns and about 50 microns.

Clause 10 the method of any of clauses 2-9, wherein the plurality of test pins have a shape that is generally circular, oval, square, or rectangular.

Clause 11 the method of any of clauses 2 to 10, wherein at least one test pin of the plurality of test pins is located between four adjacent balls of the plurality of balls.

The method of any one of clauses 1 to 11, further comprising: performing an Organic Solderability Preservative (OSP) surface treatment; or electrolytic nickel-gold (Ni-Au) surface treatment is performed in which a gold layer is plated on the nickel-plated substrate.

The method of any one of clauses 1-12, wherein each of the plurality of spheres has a height of between about 135 microns and about 155 microns.

Clause 14 the method of any of clauses 1 to 13, wherein the package comprises a system on a chip (SOC).

The method of any of clauses 1-14, wherein the package is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile phones, smart phones, personal digital assistants, fixed location terminals, tablet computers, wearable devices, internet of things (IoT) devices, laptop computers, servers, base stations, and motorized-based devices in motor vehicles.

Thus, it will be appreciated that, for example, an apparatus or any component of an apparatus may be configured (or made operable or adapted) to provide functionality as taught herein. This may be for example: by manufacturing (e.g., fabricating) a device or component such that it will provide functionality; programming a device or component such that it will provide functionality; or by using some other suitable implementation technique. As one example, an integrated circuit may be fabricated to provide the necessary functionality. As another example, an integrated circuit may be fabricated to support the necessary functionality and then configured (e.g., via programming) to provide the necessary functionality. As yet another example, the processor circuit may execute code to provide the necessary functionality.

Furthermore, the methods, sequences, and/or algorithms described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), flash memory, read-only memory (ROM), erasable Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An example storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor (e.g., cache memory).

While the foregoing disclosure shows various illustrative aspects, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The present disclosure is not intended to be limited to the specific illustrative examples. For example, the functions, steps and/or actions of the method claims in accordance with the aspects of the disclosure described herein need not be performed in any particular order unless otherwise indicated. Furthermore, although certain aspects may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims

1. An apparatus comprising a package, the package comprising:

a substrate;

a plurality of components located on a top surface of the substrate;

a plurality of ball pads located on a bottom surface of the substrate;

a plurality of balls, wherein individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads; and

a plurality of test pads is located on the bottom surface of the substrate.

2. The apparatus of claim 1, further comprising

A plurality of test pins, wherein individual test pins are attached to individual ones of the plurality of test pads and the individual test pins are lower in height than the individual balls.

3. The device of claim 2, wherein each of the plurality of test pins has a pin height between about 30 microns to about 50 microns.

4. The device of claim 3, wherein each sphere of the plurality of spheres has a sphere height between about 135 microns to about 155 microns.

5. The device of claim 2, wherein the plurality of test pins are formed from conductive paste.

6. The apparatus of claim 2, wherein the plurality of test pins are attached to a printed circuit board using a Land Grid Array (LGA), and wherein the plurality of balls are attached to the printed circuit board using a Ball Grid Array (BGA).

7. The apparatus of claim 2, wherein the individual test pins of the plurality of test pins are configured to be accessed to test one or more parameters of an application processor die.

8. The apparatus of claim 1, wherein a solder resist material covers individual ones of the plurality of test pads.

9. The apparatus of claim 1, wherein each test pad of the plurality of test pads has a generally circular, oval, square, or rectangular shape.

10. The apparatus of claim 1, wherein at least one test pad of the plurality of test pads is located between four adjacent balls of the plurality of balls.

11. The apparatus of claim 1, wherein individual ones of the plurality of test pads are connected to one or more sense lines in the package.

12. The apparatus of claim 1, wherein individual ones of the plurality of test pads are configured to be accessed to test one or more parameters of a Power Distribution Network (PDN).

13. The apparatus of claim 1, wherein individual ones of the plurality of test pads are configured to be accessed to test one or more parameters of a Power Management Integrated Circuit (PMIC).

14. The apparatus of claim 1, wherein the package comprises a system on a chip (SOC).

15. The device of claim 1, wherein the device is selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile phones, smart phones, personal digital assistants, fixed location terminals, tablet computers, wearable devices, internet of things (IoT) devices, laptop computers, servers, base stations, and devices in motor vehicles.

16. A method of making a package, the method comprising:

attaching the assembly to a top surface of the substrate;

forming a plurality of ball pads on a bottom surface of the substrate;

attaching a plurality of balls to a plurality of ball pads, wherein individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads; and

a plurality of test pads are formed on the bottom surface of the substrate.

17. The method of claim 16, further comprising:

attaching a plurality of test pins to the plurality of test pads, wherein individual test pins are attached to individual ones of the plurality of test pads, and wherein the individual test pins are lower in height than the individual balls.

18. The method of claim 17, further comprising:

applying a solder resist to the pin attachment layer, wherein the plurality of ball pads and the plurality of test pads are not covered by the solder resist; and

the plurality of test pins are extruded and cured to the pin attachment layer substantially simultaneously, wherein individual test pins are extruded and cured on top of individual ones of the plurality of test pads.

19. The method of claim 18, wherein extruding and curing the plurality of test pins to the pin attachment layer substantially simultaneously comprises:

extruding conductive paste using a nozzle of an inkjet printer to produce the plurality of test pins; and

the plurality of test pins are cured using a laser flash while the plurality of test pins are extruded.

20. The method of claim 17, wherein the package is mounted to a Printed Circuit Board (PCB) using a reflow process comprising:

attaching the plurality of test pins to the printed circuit board using a Land Grid Array (LGA) attachment process; and

the plurality of balls are attached to the printed circuit board using a Ball Grid Array (BGA) attachment process.

21. The method of claim 17, wherein the individual ones of the plurality of test pins are connected to one or more sense lines located in the package.

22. The method of claim 21, further comprising:

mounting the package on a Printed Circuit Board (PCB); and

the one or more sense lines are accessed using one or more separate test pins.

23. The method of claim 22, further comprising:

one or more parameters of at least one of a Power Distribution Network (PDN), a Power Management Integrated Circuit (PMIC), or an application processor die are tested using the one or more sense lines.

24. The method of claim 17, wherein each of the plurality of test pins has a height between about 30 microns to about 50 microns.

25. The method of claim 17, wherein the plurality of test pins have a generally circular, oval, square, or rectangular shape.

26. The method of claim 17, wherein at least one test pin of the plurality of test pins is located between four adjacent balls of the plurality of balls.

27. The method of claim 16, further comprising:

performing an Organic Solderability Preservative (OSP) surface treatment; or (b)

Electrolytic nickel-gold (Ni-Au) surface treatment is performed in which a gold layer is plated on a nickel-plated substrate.

28. The method of claim 16, wherein each sphere of the plurality of spheres has a height between about 135 microns and about 155 microns.

29. The method of claim 16, wherein the package comprises a system on a chip (SOC).

30. The method of claim 16, wherein the package is incorporated into an apparatus selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile phones, smart phones, personal digital assistants, fixed location terminals, tablet computers, wearable devices, internet of things (IoT) devices, laptop computers, servers, base stations, and motorized-based devices in motor vehicles.