CN116996592A - Network card, data transmission processing method and data receiving processing method - Google Patents

Network card, data transmission processing method and data receiving processing method Download PDF

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Publication number
CN116996592A
CN116996592A CN202311257727.3A CN202311257727A CN116996592A CN 116996592 A CN116996592 A CN 116996592A CN 202311257727 A CN202311257727 A CN 202311257727A CN 116996592 A CN116996592 A CN 116996592A
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China
Prior art keywords
data packet
network card
packet
trdp
layer protocol
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Granted
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CN202311257727.3A
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Chinese (zh)
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CN116996592B (en
Inventor
李召召
李彧
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Network Communication and Security Zijinshan Laboratory
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Network Communication and Security Zijinshan Laboratory
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12—Protocol engines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H04L69/161—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers

Abstract

The application relates to a network card. The network card comprises an FPGA chip, wherein the FPGA chip comprises a logic PL side and a hard core processor PS side, the PS side comprises a target processor, the PL side comprises an unloading engine circuit and a target bus, and the target processor and the unloading engine circuit are both connected with the target bus; the target processor is used for carrying out a first data processing flow of message analysis based on application layer software and a train real-time communication network standard TRDP layer protocol of the Ethernet; the unloading engine circuit is used for unloading the UDP layer protocol and the IP layer protocol from the PS side and carrying out message analysis on the second data processing flow based on the UDP layer protocol and the IP layer protocol; the target bus is used for transmitting data packets between the target processor and the offload engine circuit. By adopting the network card provided by the application, the data packet transmission efficiency can be improved, the time delay can be reduced, and the real-time performance of the TRDP network card can be effectively improved.

Description

Network card, data transmission processing method and data receiving processing method
Technical Field
The present application relates to the technical field of ethernet network cards, and in particular, to a network card, a data transmission processing method, and a data receiving processing method.
Background
In order to solve the bandwidth problem of the bus TCN network, the international electrotechnical commission in 2015 has introduced the Real-time communication network standard (TRDP, train Real-time Data Protocol) of trains based on ethernet, and then more and more suppliers begin to develop Real-time ethernet network cards for trains using TRDP as a core protocol.
In the prior art, the TRDP network card, that is, the ethernet network card using TRDP as a core protocol, mostly adopts a combination mode of arm+fpga.
However, the TRDP network card data packet transmission efficiency and the time delay of the combined mode of ARM+FPGA are lower, so that the real-time performance of the TRDP network card is poorer.
Disclosure of Invention
Based on this, it is necessary to provide a network card, a data transmission processing method and a data receiving processing method, which have higher transmission efficiency, shorter time delay and higher real-time performance, aiming at the technical problems.
In a first aspect, the present application provides a network card. The network card comprises an FPGA chip, wherein the FPGA chip comprises a logic PL side and a hard core processor PS side, the PS side comprises a target processor, the PL side comprises an unloading engine circuit and a target bus, and the target processor and the unloading engine circuit are both connected with the target bus; the target processor is used for carrying out a first data processing flow of message analysis based on application layer software and a train real-time communication network standard TRDP layer protocol of the Ethernet; the unloading engine circuit is used for unloading the UDP layer protocol and the IP layer protocol from the PS side and carrying out message analysis on the second data processing flow based on the UDP layer protocol and the IP layer protocol; the target bus is used for transmitting data packets between the target processor and the offload engine circuit.
In one embodiment, during a data transmission process, the target bus is specifically configured to send a TRDP transmission packet to the offload engine circuit, where the TRDP transmission packet is obtained by the target processor executing the first data processing flow on a first transmission packet; the offload engine circuit is specifically configured to execute the second data processing flow on the TRDP transmit data packet to obtain an IP transmit data packet.
In one embodiment, during the data receiving process, the target bus is specifically configured to send a UDP received data packet to the target processor, where the UDP received data packet is obtained by the offload engine circuit executing the second data processing flow on the first received data packet; the target processor is specifically configured to execute the first data processing procedure on the UDP received packet, so as to obtain an application layer received packet.
In one embodiment, the target processor is deployed with an operating system and a UDP offload engine UOE driver; in the process of data transmission, the target processor is specifically configured to call the UOE driver through the operating system, so that the UOE driver transmits the TRDP transmission data packet to the offload engine circuit through the target bus when the UOE driver is called; in the process of data receiving, the target processor is specifically configured to call the UOE driver through the operating system, so that the UOE driver obtains the UDP received data packet from the offload engine circuit through the target bus when the UOE driver is called.
In one embodiment, the offload engine circuit further performs an identification process on each received packet to determine a type of each packet, and preferentially sends the packet determined to be of the UOE type, stores the packet determined to be of the non-UOE type in the cache, and after the sending of the packet of the UOE type is completed, obtains the packet of the non-UOE type from the cache and sends the packet of the non-UOE type.
In one embodiment, the network card further comprises a MAC layer chip and a physical layer chip; in the process of data transmission, the MAC layer chip is used for acquiring the IP transmission data packet from the unloading engine circuit, carrying out encapsulation processing on the IP transmission data packet to obtain an MAC transmission data packet, and transmitting the MAC transmission data packet to the physical layer chip; in the process of data receiving, the MAC layer chip is configured to obtain an initial received data packet from the physical layer chip, perform decapsulation processing on the initial received data packet to obtain the MAC received data packet, and send the MAC received data packet to the offload engine circuit.
In a second aspect, the present application provides a data transmission processing method, which is applied to the network card in any one of the first aspects, and the method includes: acquiring a first transmission data packet, and determining a TRDP transmission data packet based on the first transmission data packet and a target processor included in the network card; transmitting the TRDP sending data packet to an unloading engine circuit in the network card by utilizing a target bus in the network card; and executing a second data processing flow based on a UDP layer protocol and an IP layer protocol on the TRDP sending data packet by using the unloading engine circuit to obtain an IP sending data packet, wherein the second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
In one embodiment, the determining the TRDP transmission packet based on the first transmission packet and the destination processor included in the network card includes: and executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on the Ethernet on the first transmission data packet by utilizing a target processor included in the network card to obtain the TRDP transmission data packet, wherein the first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
In a third aspect, the present application provides a data receiving and processing method, which is applied to the network card in any one of the first aspects, and the method includes: acquiring a first received data packet, and determining a UDP received data packet based on the first received data packet and an unloading engine circuit included in the network card; transmitting the UDP received data packet to a target processor in the network card by using a target bus in the network card; and executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on the Ethernet on the UDP received data packet by using the target processor to obtain an application layer received data packet, wherein the first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
In one embodiment, the determining the UDP received packet based on the first received packet and an offload engine circuit included in the network card includes: and executing a second data processing flow based on a UDP layer protocol and an IP layer protocol on the first received data packet by using an unloading engine circuit included in the network card to obtain the UDP received data packet, wherein the second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
The network card comprises an FPGA chip, wherein the FPGA chip comprises a logic PL side and a hard core processor PS side, the PS side comprises a target processor, the PL side comprises an unloading engine circuit and a target bus, and the target processor and the unloading engine circuit are connected with the target bus; the target processor is used for carrying out a first data processing flow of message analysis based on the application layer software and a train real-time communication network standard TRDP layer protocol of the Ethernet; the unloading engine circuit is used for unloading the UDP layer protocol and the IP layer protocol from the PS side and carrying out message analysis on the second data processing flow based on the UDP layer protocol and the IP layer protocol; the target bus is used for transmitting data packets between the target processor and the offload engine circuit. According to the network card provided by the application, the unloading engine circuit is utilized to realize that the UDP/IP layer protocol is unloaded from the PS side of the FPGA chip, and then the UDP/IP layer protocol is realized in the PL side of the FPGA chip in a hardware logic circuit mode, and the parallel processing characteristic of the logic circuit of the PL side of the FPGA chip is utilized to complete the data processing flow of the UDP/IP layer protocol within extremely short time delay, so that the participation of the target processor on the PS side of the FPGA chip in network card communication is reduced.
Drawings
FIG. 1 is a schematic diagram of a network card in one embodiment;
FIG. 2 is a schematic diagram of an offload engine circuit performing a transmit flow in one embodiment;
FIG. 3 is a flow chart of a data transmission processing method in one embodiment;
FIG. 4 is a flow chart of a data receiving and processing method in one embodiment;
FIG. 5 is a block diagram showing the structure of a data transmission processing apparatus in one embodiment;
fig. 6 is a block diagram of a data receiving processing method in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present disclosure, the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless explicitly defined otherwise.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
It will be understood that when an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
In order to solve the bandwidth problem of the bus TCN network, the international electrotechnical commission in 2015 has introduced the Real-time communication network standard (TRDP, train Real-time Data Protocol) of trains based on ethernet, and then more and more suppliers begin to develop Real-time ethernet network cards for trains using TRDP as a core protocol.
In the prior art, the TRDP network card, that is, the ethernet network card using TRDP as a core protocol, mostly adopts a combination mode of ARM (Acorn RISC Machine, microprocessor) +fpga (Field Programmable Gate Array ).
However, the TRDP network card data packet transmission efficiency and the time delay of the combined mode of ARM+FPGA are lower, so that the real-time performance of the TRDP network card is poorer.
Therefore, the embodiment of the application provides the network card with higher transmission efficiency, shorter time delay and higher instantaneity.
In one embodiment, as shown in FIG. 1, a network card 100 is provided, the network card 100 comprising: an FPGA chip 101, the FPGA chip 101 comprising: a hard core processor PS (Processing System ) side and PL (Programmable Logic, programmable logic) side.
Wherein the PS side includes a target processor 1011, the PL side includes an offload engine circuit 1012 and a target bus 1013, and the target processor 1011 and the offload engine circuit 1012 are connected to the target bus 1013; the target processor 1011 is configured to perform a first data processing procedure based on the application layer software 1014 and the TRDP layer protocol 1015, which is a standard for real-time communication network of ethernet; the offload engine circuit 1012 is configured to offload a UDP layer protocol and an IP layer protocol from the PS side, and perform a second packet parsing process based on the UDP layer protocol and the IP layer protocol; the target bus 1013 is used to transfer data packets between the target processor 1011 and the offload engine circuit 1012.
Alternatively, the network card 100 may be a TRDP network card, that is, an ethernet network card using TRDP as a core protocol.
Alternatively, the FPGA chip 101 refers to an integrated circuit chip based on a general-purpose logic array.
Alternatively, the target processor 1011 may be an ARM hard core processor, the ARM of FIG. 1 corresponds to the target processor 1011, the offload engine circuit 1012 may be a circuit including a UOE (UDP Offload Engine ) corresponding to the offload engine circuit 1012 of FIG. 1, the application layer software 1014 and TRDP layer protocol 1015 may be used to process data, the application layer of FIG. 1 corresponds to the application layer software 1014, and the TRDP layer protocol stack of FIG. 1 corresponds to the TRDP layer protocol 1015.
In an alternative embodiment of the application, the target bus 1013 is an AXI bus that can be used for simple low-throughput memory mapped communications, the AXI bus in fig. 1 being equivalent to the target bus 1013.
In one possible implementation, the connection of the target processor 1011 and the offload engine circuit 1012 to the target bus 1013 may be a wired connection.
The network card 100 includes an FPGA chip 101, and the FPGA chip 101 includes a hard core processor PS (Processing System ) side and a PL (Programmable Logic, programmable logic) side; wherein the PS side includes a target processor 1011, the PL side includes an offload engine circuit 1012 and a target bus 1013, and the target processor 1011 and the offload engine circuit 1012 are connected to the target bus 1013; the target processor 1011 is configured to perform a first data processing procedure for message parsing based on the application layer software 1014 and the ethernet train real-time communication network standard TRDP layer protocol 1015; the offload engine circuit 1012 is configured to offload a UDP layer protocol and an IP layer protocol from the PS side, and perform a second packet parsing process based on the UDP layer protocol and the IP layer protocol; the target bus 1013 is used to transfer data packets between the target processor 1011 and the offload engine circuit 1012. The network card provided by the application has the advantages that the unloading engine circuit is utilized to realize the unloading of the UDP layer protocol and the IP layer protocol from the PS of the FPGA chip, the UDP layer protocol and the IP layer protocol are realized on the PL side of the FPGA chip in a hardware logic circuit mode, the parallel processing characteristic of the logic circuit on the PL side of the FPGA chip is utilized, the data processing flow of the UDP/IP layer protocol can be completed within extremely short time delay, the participation of the target processor on the PS side of the FPGA chip in network card communication is reduced, and the network card provided by the application can improve the data packet transmission efficiency, reduce the time delay and effectively improve the real-time property of the TRDP network card.
In one embodiment, as shown in fig. 1, during data transmission, the target bus 1013 is specifically configured to send a TRDP transmission packet to the offload engine circuit 1012, where the TRDP transmission packet is obtained by the target processor 1011 performing the first data processing flow on a first transmission packet; the offload engine circuit 1012 is specifically configured to perform the second data processing flow on the TRDP transmit packet to obtain an IP transmit packet.
Optionally, in the process of data transmission, the first data processing flow may be based on analysis of data content by application layer software, or may be based on TRDP layer encapsulation of data by TRDP layer protocol.
Optionally, in the process of data transmission, the second data flow may be a network packet header added to the UDP layer protocol and the IP layer protocol, may be a calculated checksum, may be a data flow process, or may be a data encapsulation process.
In one embodiment, as shown in fig. 1, during data reception, the destination bus 1013 is specifically configured to send a UDP received packet to the destination processor 1011, where the UDP received packet is obtained by the offload engine circuit 1012 performing the second data processing flow on the first received packet; the target processor 1011 is specifically configured to perform the first data processing procedure on the UDP received packet to obtain an application layer received packet.
Optionally, in the process of data receiving, the first data processing flow may be based on the application layer software to parse the data content, or may be based on a TRDP layer protocol to perform TRDP layer decapsulation processing on the data.
Optionally, during the data receiving process, the second data flow may be a network packet header added to the UDP layer protocol and the IP layer protocol, may be a checksum calculation, may be a data flow processing, or may be a data decapsulation processing.
In one embodiment, as shown in FIG. 1, the target processor 1011 has an operating system 201 and a UOE driver 202 deployed therein.
Wherein, during data transmission, the target processor 1011 is specifically configured to call the UOE driver 202 through the operating system 201 to transmit the TRDP transmission data packet to the offload engine circuit 1012 through the target bus 1013 by the target processor 1011; during data reception, the target processor 1011 is specifically configured to call the UOE driver 202 via the operating system 201 to obtain the UDP received packet from the offload engine circuit 1012 via the target bus 1013.
In an alternative embodiment of the present application, the operating system 201 may be an embedded Linux operating system, and the Linux OS in fig. 1 corresponds to the operating system 201, and the UOE driver in fig. 1 corresponds to the UOE driver 202.
In one embodiment, as shown in fig. 1, the network card 100 further includes an interface circuit 102 and a backplane bus 103, the interface circuit 102 being connected to the backplane bus 103 and the target bus 1013, respectively.
In the process of data transmission, the interface circuit 102 is configured to obtain an initial transmission data packet from the backplane bus 1013, perform format processing on the initial transmission data packet to obtain the first transmission data packet matching the protocol format of the target bus 1013, and send an interrupt request to the target processor 1011, where the target processor 1011 is specifically configured to obtain the first transmission data packet through the target bus 1013 after receiving the interrupt request; during data reception, the interface circuit 102 is configured to obtain the application layer received data packet from the target processor 1011 via the target bus 1013, and send the application layer received data packet to the backplane bus 103.
Alternatively, the interface circuit 102 may be a circuit including a RapidIO interface module, which corresponds to the interface circuit 102 in fig. 1, and a serial backplane bus corresponds to the backplane bus 103 in fig. 1.
In an alternative embodiment of the present application, the backplane bus 103 is a RapidIO interface serial backplane bus, and by adopting the RapidIO interface serial backplane bus, the number of PCB wirings of the backplane communication signals can be reduced without affecting the transmission rate, and the PCB design of the backplane can be simplified.
In one possible implementation manner, during the data transmission process, the interface circuit 102 obtains an initial transmission data packet from the RapidIO interface serial backplane bus through an Rxn/p signal line, performs serial data decoding on the initial transmission data packet, converts the initial transmission data packet from serial to a first transmission data packet matching with the protocol format of the target bus 1013, converts the initial transmission data packet into an a format if the protocol format of the target bus 1013 is an a format, converts the initial transmission data packet into a B format if the protocol format of the target bus 1013 is a B format, and notifies the target processor 1011 on the PS side in an interrupt manner, that is, sends an interrupt request to the target processor 1011, and the operating system 201 in the target processor 1011 responds to the interrupt request to obtain the first transmission data packet through the target bus 1013.
In another possible implementation manner, during the data receiving process, the interface circuit 102 obtains the application layer received data packet from the target processor 1011 on the PS side through the target bus 1013, performs data processing on the application layer received data packet, and sends the application layer received data packet after the data processing to the RapidIO interface serial backplane bus through the Txn/p signal line.
In one embodiment, as shown in fig. 1, the target processor 1011 also has a back-plane driver 203 disposed therein, and the back-plane driver in fig. 1 corresponds to the back-plane driver 203.
Wherein, during the data transmission process, the target processor 1011 is specifically configured to call the back plane driver 203 to obtain the first transmission data packet from the interface circuit 102 through the target bus 1013 after receiving the interrupt request; during data reception, the target processor 1011 is specifically configured to invoke the back plane driver 203 to send the application layer received data packet to the interface circuit 102 via the target bus 1013.
In one possible implementation, during data transmission, after receiving the interrupt request, the operating system 201 in the target processor 1011 responds to the interrupt request by invoking the backplane driver 203 to obtain the first transmission data packet from the interface circuit 102 via the target bus 1013 in an interrupt handling function.
In another possible implementation, during data reception, the operating system 201 in the target processor 1011 invokes the back plane driver 203 to send the application layer received data packet to the interface circuit 102 via the target bus 1013.
In one embodiment, as shown in fig. 1, the network card 100 further includes a MAC layer chip 104 and a physical layer chip 105.
In the process of data transmission, the MAC layer chip 104 is configured to obtain the IP transmission data packet from the offload engine circuit 1012, perform encapsulation processing on the IP transmission data packet to obtain a MAC transmission data packet, and send the MAC transmission data packet to the physical layer chip 105; in the process of data reception, the MAC layer chip 104 is configured to acquire an initial received data packet from the physical layer chip 105, perform decapsulation processing on the initial received data packet to obtain the MAC received data packet, and send the MAC received data packet to the offload engine circuit 1011.
Alternatively, the MAC layer chip 104 may be a gigabit ethernet MAC chip, and the physical layer chip 105 may be a physical layer PHY chip, where the MAC in fig. 1 corresponds to the MAC chip 104 and the PHY in fig. 1 corresponds to the physical layer chip 105.
In one possible implementation, during the data transmission process, the MAC layer chip 104 obtains the IP transmission packet from the offload engine circuit 1011, encapsulates the IP transmission packet to obtain a MAC transmission packet, and sends the MAC transmission packet to the physical layer PHY chip 105 through the sgmii interface.
In another possible implementation, during the data reception process, the MAC layer chip 104 obtains an initial received data packet from the PHY layer chip 105 through the sgmii interface, performs decapsulation processing on the initial received data packet to obtain the MAC received data packet, and sends the MAC received data packet to the offload engine circuit 1011.
In one embodiment, during the data transmission process, the physical layer chip 105 is configured to convert the MAC transmission data packet into an optical-electrical signal for transmission; in the process of data reception, the physical layer chip 105 is used for performing conversion processing on the received photoelectric signal to obtain the initial received data packet.
In one possible implementation, during the data transmission process, the physical layer chip 105 converts the parallel data of the MAC transmission packet into serial stream data, encodes the data according to the encoding rule of the physical layer, and finally converts the data into analog signal for transmission.
In one possible implementation, during the data receiving process, the physical layer chip 105 first performs conversion processing on the received photoelectric signal, converts the photoelectric signal into a digital signal, and then performs data processing on the digital signal to obtain the initial received data packet.
In an alternative embodiment of the present application, as shown in fig. 2, the offload engine circuit 1012 is further configured to perform identification processing on each received packet to determine a type of each packet, send the packet determined to be a UOE type preferentially, store the packet determined to be a non-UOE type in a buffer, and after the sending of the packet of the UOE type is completed, obtain the packet of the non-UOE type from the buffer and send the packet of the non-UOE type.
Optionally, the UOE type data packets include IP send data packets and UDP send data packets.
In one possible implementation, as shown in fig. 2, fig. 2 is a schematic diagram of implementing a data transmission process based on two-layer arbitration and three-layer arbitration, in the data transmission process, if there is a case that an ICMP response module (ICMP response in fig. 2) and a UOE transmission module (UOE transmission in fig. 2) transmit data packets simultaneously, resulting in transmission collision, three-layer arbitration is performed, after three-layer arbitration, the UOE transmission module will preferentially transmit UDP transmission data packets to an IP layer protocol, the ICMP response module temporarily stores the ICMP response in an ICMP buffer, if there is a case that an ARP packet transmission module (ARP packet in fig. 2) and an IP packet transmission module (IP packet in fig. 2) transmit data packets simultaneously, two-layer arbitration is performed, after two-layer arbitration, the IP packet transmission module will preferentially transmit IP transmission data packets, the ARP packet sending module temporarily stores the ARP packet in an ARP buffer, in the data receiving process on the left side of fig. 2, where the receiving buffer module (the receiving buffer in fig. 2) is configured to receive an ethernet frame obtained after processing by using a MAC layer protocol, where the ethernet frame includes an IP packet type frame and an ARP packet type frame, if the "type" field of the ethernet frame is 0800, transmit the ethernet frame to the IP receiving module (the IP packet receiving in fig. 2) for further processing, and if the processing is determined to be a UDP received packet, transmit the UDP received packet to the UDP receiving module (the UOE receiving in fig. 2) for further processing, if the processing is determined to be an ICMP response, execute a corresponding procedure based on the ICMP response module, if the "type" field of the ethernet frame is 0806 "or 8035", the ethernet frame is transmitted to an ARP protocol processing module (ARP packet reception in fig. 2), and the ARP protocol processing module parses the ethernet frame to obtain an ARP received packet, determines whether the ARP received packet is an ARP request packet or an ARP response packet, if the ARP received packet is an ARP response packet, stores a destination IP MAC address carried therein in a local MAC list for querying for use when a subsequent network packet is transmitted, and if the ARP received packet is an ARP request packet, issues an ARP response packet with a local MAC to respond to a remote request.
In an alternative embodiment of the present application, in a data transmission process, the interface circuit 102 obtains an initial transmission data packet from the backplane bus 103, performs format processing on the initial transmission data packet to obtain the first transmission data packet matching the protocol format of the target bus 1013, and sends an interrupt request to the target processor 1011, the target processor 1011 calls the backplane driver 203 to obtain the first transmission data packet from the interface circuit 102 through the target bus 1013 after receiving the interrupt request, the target processor 1011 performs the first data processing flow on the first transmission data packet to obtain a TRDP transmission data packet, and then calls the UOE driver 202 to send the TRDP transmission data packet to the offload engine circuit 1012 through the target bus 1013, the offload engine circuit 1012 performs the second data processing flow on the TRDP transmission data packet to obtain an IP transmission data packet, the MAC layer chip 104 obtains the IP transmission data packet from the offload engine circuit 1012, performs encapsulation processing on the IP transmission data packet to obtain the MAC layer transmission data packet, and performs MAC layer conversion on the MAC layer transmission data packet to the MAC layer 105, and performs MAC layer transmission data packet to the MAC layer 105.
In one possible implementation, when executing a data transmission procedure based on the network card 100, the interface circuit 102 obtains an initial transmission data packet from the RapidIO interface serial backplane bus, serial data decodes the initial transmission data packet, serial converts the initial transmission data packet into a first transmission data packet matching the protocol format of the target bus 1013, and notifies the target processor 1011 on the PS side in an interrupt manner, after receiving the interrupt request, the operating system 201 in the target processor 1011 responds to the interrupt request, in an interrupt processing function, invokes the backplane driver 203 to obtain the first transmission data packet from the interface circuit 102 through the target bus 1013, the target processor 1011 executes the first data processing procedure on the first transmission data packet to obtain a TRDP transmission data packet, the UOE driver 202 is then invoked by the operating system 201 of the target processor 1011 to send the TRDP send data packet to the offload engine circuit 1012 via the target bus 1013, the offload engine circuit 1012 performs the second data processing flow on the TRDP send data packet to obtain an IP send data packet, the MAC layer chip 104 obtains the IP send data packet from the offload engine circuit 1012 and encapsulates the IP send data packet in a MAC layer to obtain a MAC send data packet, and sends the MAC send data packet to the physical layer chip 105 via the sgmii interface, the physical layer chip 105 converts parallel data of the MAC send data packet into serial stream data, encodes the data according to an encoding rule of a physical layer, and finally converts the data into analog signal for transmission.
In an alternative embodiment of the present application, during data reception, the photoelectric signal received by the physical layer chip 105 is converted to obtain the initial received data packet, the MAC layer chip 104 obtains the initial received data packet from the physical layer chip 105, the initial received data packet is decapsulated to obtain the MAC received data packet, and the MAC received data packet is sent to the offload engine circuit 1012, the offload engine circuit 1012 performs the second data processing procedure on the MAC received data packet to obtain the UDP received data packet, the operating system 201 invokes the UOE driver to obtain the UDP received data packet from the offload engine circuit 1012 through the target bus 1013, and transmits the UDP received data packet to the target processor 1011 through the target bus 1013, the target processor 1011 performs the first data processing procedure on the UDP received data packet to obtain the application layer received data packet, and the target processor 1011 invokes the back plane driver 203 to send the application layer received data packet to the interface circuit 102 through the target bus 1013, and the interface circuit 102 sends the application layer received data packet to the back plane bus.
In one possible implementation manner, when executing the data receiving process based on the network card 100, the physical layer chip 105 firstly performs conversion processing on the received photoelectric signal to convert the received photoelectric signal into a digital signal, then performs data processing on the digital signal to obtain the initial received data packet, the MAC layer chip 104 acquires the initial received data packet from the physical layer PHY chip 105 through the sgmii interface, performs decapsulation processing on the initial received data packet to obtain the MAC received data packet, and sends the MAC received data packet to the offload engine circuit 1012, the offload engine circuit 1012 performs the second data processing process on the MAC received data packet to obtain a UDP received data packet, the operating system 201 invokes the UOE driver to acquire the UDP received data packet from the offload engine circuit 1012 through the target bus 1013, and transmits the UDP received data packet to the target processor 1011 through the target bus 1013, the target processor 1011 performs the first data processing process on the UDP received data packet to obtain an application layer received data packet, and invokes the back plane driver 201 to send the back plane driver data packet 203 to the application layer interface to the back plane 102 for processing the application layer data packet.
In one embodiment, as shown in fig. 3, a data transmission processing method is provided, where the method is applied to the network card described in any one of the foregoing embodiments, and the method includes the following steps:
step 301, a first transmission data packet is acquired, and a TRDP transmission data packet is determined based on the first transmission data packet and a target processor included in the network card.
In an optional embodiment of the application, the determining, based on the first transmission data packet and a target processor included in the network card, the TRDP transmission data packet includes: and executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on the Ethernet on the first transmission data packet by utilizing a target processor included in the network card so as to obtain a TRDP transmission data packet.
The first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
Step 302, the TRDP transmission packet is transmitted to the offload engine circuit in the network card by using the destination bus in the network card.
Step 303, executing a second data processing flow based on the UDP layer protocol and the IP layer protocol on the TRDP transmission data packet by using the offload engine circuit, so as to obtain an IP transmission data packet.
The second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
In one embodiment, as shown in fig. 4, a data receiving and processing method is provided, where the method is applied to the network card described in any one of the foregoing embodiments, and the method includes the following steps:
step 401, acquire a first received data packet, and determine a UDP received data packet based on the first received data packet and an offload engine circuit included in the network card.
In an alternative embodiment, the determining the UDP received packet based on the first received packet and an offload engine circuit included in the network card includes: and executing a second data processing flow based on the UDP layer protocol and the IP layer protocol on the first received data packet by using an unloading engine circuit included in the network card so as to obtain the UDP received data packet.
The second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
Step 402, transmitting the UDP received data packet to a target processor in the network card by using a target bus in the network card.
Step 403, executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on ethernet on the UDP received data packet by using the target processor, so as to obtain the application layer received data packet.
The first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the same inventive concept, the embodiment of the application also provides a control device for realizing the control method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in the embodiment of one or more control devices provided below may be referred to the limitation of the control method hereinabove, and will not be repeated here.
In one embodiment, as shown in fig. 5, there is provided a data transmission processing apparatus 500, which includes an acquisition module 501, a first execution module 502, and a second execution module 503, wherein:
an obtaining module 501, configured to obtain a first sending data packet, and determine a TRDP sending data packet based on the first sending data packet and a target processor included in the network card;
a first execution module 502, configured to transmit the TRDP transmission packet to an offload engine circuit in the network card by using a target bus in the network card;
a second execution module 503, configured to execute a second data processing flow based on a UDP layer protocol and an IP layer protocol on the TRDP transmission data packet by using the offload engine circuit, so as to obtain an IP transmission data packet, where the second data processing flow is a packet parsing data processing flow based on the UDP layer protocol and the IP layer protocol.
In one embodiment, the obtaining module 501 is specifically configured to: and executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on the Ethernet on the first transmission data packet by utilizing a target processor included in the network card to obtain a TRDP transmission data packet, wherein the first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
In one embodiment, as shown in fig. 6, there is provided a data receiving and processing apparatus 600, which includes an acquisition module 601, a first execution module 602, and a second execution module 603, wherein:
an obtaining module 601, configured to obtain a first received data packet, and determine a UDP received data packet based on the first received data packet and an offload engine circuit included in the network card;
a first execution module 602, configured to transmit the UDP received packet to a target processor in the network card by using a target bus in the network card;
the second execution module 603 is configured to execute, by using the target processor, a first data processing flow based on application layer software and a TRDP layer protocol of an ethernet-based train real-time communication network standard on the UDP received data packet, so as to obtain an application layer received data packet, where the first data processing flow is a packet parsing data processing flow based on the application layer software and the TRDP layer protocol.
In one embodiment, the obtaining module 601 is specifically configured to: and executing a second data processing flow based on the UDP layer protocol and the IP layer protocol on the first received data packet by using an unloading engine circuit included in the network card to obtain the UDP received data packet, wherein the second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
The respective modules in the above-described control device may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of: acquiring a first transmission data packet, and determining a TRDP transmission data packet based on the first transmission data packet and a target processor included in the network card; transmitting the TRDP sending data packet to an unloading engine circuit in the network card by utilizing a target bus in the network card; and executing a second data processing flow based on a UDP layer protocol and an IP layer protocol on the TRDP sending data packet by utilizing the unloading engine circuit to obtain the IP sending data packet, wherein the second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
In one embodiment, the determining the TRDP transmission packet based on the first transmission packet and the destination processor included in the network card further comprises: and executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on the Ethernet on the first transmission data packet by utilizing a target processor included in the network card to obtain a TRDP transmission data packet, wherein the first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
In one embodiment, the computer program when executed by a processor performs the steps of: acquiring a first received data packet, and determining a UDP received data packet based on the first received data packet and an unloading engine circuit included in the network card; transmitting the UDP received data packet to a target processor in the network card by using a target bus in the network card; and executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on the Ethernet on the UDP received data packet by using the target processor to obtain an application layer received data packet, wherein the first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
In one embodiment, the determining the UDP received packet based on the first received packet and an offload engine circuit included in the network card, the computer program when executed by the processor further performs the steps of: and executing a second data processing flow based on the UDP layer protocol and the IP layer protocol on the first received data packet by using an unloading engine circuit included in the network card to obtain the UDP received data packet, wherein the second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
In one embodiment, a computer program product is provided comprising a computer program which, when executed by a processor, performs the steps of: acquiring a first transmission data packet, and determining a TRDP transmission data packet based on the first transmission data packet and a target processor included in the network card; transmitting the TRDP sending data packet to an unloading engine circuit in the network card by utilizing a target bus in the network card; and executing a second data processing flow based on a UDP layer protocol and an IP layer protocol on the TRDP sending data packet by utilizing the unloading engine circuit to obtain the IP sending data packet, wherein the second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
In one embodiment, the determining the TRDP transmission packet based on the first transmission packet and the destination processor included in the network card further comprises: and executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on the Ethernet on the first transmission data packet by utilizing a target processor included in the network card to obtain a TRDP transmission data packet, wherein the first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
In one embodiment, the computer program when executed by a processor performs the steps of: acquiring a first received data packet, and determining a UDP received data packet based on the first received data packet and an unloading engine circuit included in the network card; transmitting the UDP received data packet to a target processor in the network card by using a target bus in the network card; and executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on the Ethernet on the UDP received data packet by using the target processor to obtain an application layer received data packet, wherein the first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
In one embodiment, the determining the UDP received packet based on the first received packet and an offload engine circuit included in the network card, the computer program when executed by the processor further performs the steps of: and executing a second data processing flow based on the UDP layer protocol and the IP layer protocol on the first received data packet by using an unloading engine circuit included in the network card to obtain the UDP received data packet, wherein the second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims (10)

1. The network card is characterized by comprising an FPGA chip, wherein the FPGA chip comprises a logic PL side and a hard core processor PS side, the PS side comprises a target processor, the PL side comprises an unloading engine circuit and a target bus, and the target processor and the unloading engine circuit are connected with the target bus;
the target processor is used for carrying out a first data processing flow of message analysis based on application layer software and a train real-time communication network standard TRDP layer protocol of the Ethernet;
The unloading engine circuit is used for unloading the UDP layer protocol and the IP layer protocol from the PS side and carrying out a message analysis second data processing flow based on the UDP layer protocol and the IP layer protocol;
the target bus is used for transmitting data packets between the target processor and the offload engine circuit.
2. The network card of claim 1, wherein the network card,
in the process of data transmission, the target bus is specifically configured to transmit a TRDP transmission data packet to the offload engine circuit, where the TRDP transmission data packet is obtained by the target processor executing the first data processing flow on a first transmission data packet;
the offload engine circuit is specifically configured to execute the second data processing flow on the TRDP transmit data packet to obtain an IP transmit data packet.
3. The network card of claim 1, wherein the network card,
in the process of data receiving, the target bus is specifically configured to send a UDP received data packet to the target processor, where the UDP received data packet is obtained by the offload engine circuit executing the second data processing flow on the first received data packet;
the target processor is specifically configured to execute the first data processing procedure on the UDP received data packet, so as to obtain an application layer received data packet.
4. A network card according to claim 2 or 3, wherein the target processor is deployed with an operating system and a UDP offload engine UOE driver;
in the process of data transmission, the target processor is specifically configured to call the UOE driver through the operating system, so that the UOE driver transmits the TRDP transmission data packet to the offload engine circuit through the target bus when being called;
in the process of data receiving, the target processor is specifically configured to call the UOE driver through the operating system, so that the UOE driver obtains the UDP received data packet from the offload engine circuit through the target bus when the UOE driver is called.
5. The network card of claim 1, wherein the network card,
the unloading engine circuit is further used for identifying each received data packet to determine the type of each data packet, preferentially sending the data packet determined to be of the UOE type, storing the data packet determined to be of the non-UOE type into a cache, and acquiring and sending the data packet of the non-UOE type from the cache after the data packet of the UOE type is sent.
6. A network card according to claim 2 or 3, wherein the network card further comprises a MAC layer chip and a physical layer chip;
in the data transmission process, the MAC layer chip is configured to obtain the IP transmission data packet from the offload engine circuit, perform encapsulation processing on the IP transmission data packet to obtain a MAC transmission data packet, and send the MAC transmission data packet to the physical layer chip;
in the process of data reception, the MAC layer chip is configured to acquire an initial received data packet from the physical layer chip, perform decapsulation processing on the initial received data packet to obtain an MAC received data packet, and send the MAC received data packet to the offload engine circuit.
7. A data transmission processing method, applied to the network card according to any one of claims 1 to 6, comprising:
acquiring a first transmission data packet, and determining a TRDP transmission data packet based on the first transmission data packet and a target processor included in the network card;
transmitting the TRDP sending data packet to an unloading engine circuit in the network card by utilizing a target bus in the network card;
and executing a second data processing flow based on a UDP layer protocol and an IP layer protocol on the TRDP sending data packet by using the unloading engine circuit to obtain an IP sending data packet, wherein the second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
8. The method of claim 7, wherein the determining a TRDP transmit packet based on the first transmit packet and a destination processor included in the network card comprises:
and executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on the Ethernet on the first transmission data packet by utilizing a target processor included in the network card to obtain the TRDP transmission data packet, wherein the first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
9. A data receiving and processing method, wherein the method is applied to the network card according to any one of claims 1 to 6, and the method comprises:
acquiring a first received data packet, and determining a UDP received data packet based on the first received data packet and an unloading engine circuit included in the network card;
transmitting the UDP received data packet to a target processor in the network card by using a target bus in the network card;
and executing a first data processing flow based on application layer software and a train real-time communication network standard TRDP layer protocol based on the Ethernet on the UDP received data packet by using the target processor to obtain an application layer received data packet, wherein the first data processing flow is a message analysis data processing flow based on the application layer software and the TRDP layer protocol.
10. The method of claim 9, wherein said determining a UDP received packet based on said first received packet and an offload engine circuit included in said network card comprises:
and executing a second data processing flow based on a UDP layer protocol and an IP layer protocol on the first received data packet by using an unloading engine circuit included in the network card to obtain the UDP received data packet, wherein the second data processing flow is a message analysis data processing flow based on the UDP layer protocol and the IP layer protocol.
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