CN116995169A - LED epitaxial wafer, preparation method thereof and LED - Google Patents

LED epitaxial wafer, preparation method thereof and LED Download PDF

Info

Publication number
CN116995169A
CN116995169A CN202311244885.5A CN202311244885A CN116995169A CN 116995169 A CN116995169 A CN 116995169A CN 202311244885 A CN202311244885 A CN 202311244885A CN 116995169 A CN116995169 A CN 116995169A
Authority
CN
China
Prior art keywords
layer
type
light
epitaxial wafer
emitting diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202311244885.5A
Other languages
Chinese (zh)
Other versions
CN116995169B (en
Inventor
高虹
程龙
郑文杰
舒俊
张彩霞
印从飞
刘春杨
吕蒙普
胡加辉
金从龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangxi Zhao Chi Semiconductor Co Ltd
Original Assignee
Jiangxi Zhao Chi Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangxi Zhao Chi Semiconductor Co Ltd filed Critical Jiangxi Zhao Chi Semiconductor Co Ltd
Priority to CN202311244885.5A priority Critical patent/CN116995169B/en
Publication of CN116995169A publication Critical patent/CN116995169A/en
Application granted granted Critical
Publication of CN116995169B publication Critical patent/CN116995169B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials

Abstract

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and an LED, wherein the light-emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an N-type GaN layer, a stress release layer, an active layer, a P-type GaN layer and a composite P-type contact layer are sequentially arranged on the substrate; the composite P-type contact layer comprises an AlGaN/AlN superlattice layer, a GaN layer and a heterojunction hole induction layer which are sequentially laminated on the P-type GaN layer, wherein the heterojunction hole induction layer comprises P-type Al x Ga 1‑x N barrier layer and P type In y Ga 1‑y And the N cap layer, wherein the value range of x is 0.1-0.5, and the value range of y is 0.01-0.1. The LED epitaxial wafer provided by the invention can improve the current aggregation effect and the light-emitting area surfaceThe product improves the light extraction efficiency and enhances the reverse breakdown voltage resistance.

Description

LED epitaxial wafer, preparation method thereof and LED
Technical Field
The invention relates to the technical field of photoelectricity, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and an LED.
Background
The P electrode and the N electrode of the conventional LED are designed on the same side of the light-emitting surface of the chip, the P electrode is formed by an extremely thin transparent conductive layer (ITO) and a thick metal pad, and the P electrode with this structure is located directly above the light-emitting surface of the chip, and most of the current is injected from the P electrode into the active region (i.e., the light-emitting region) located below the P electrode, so most of the light generated from the active region is blocked by the opaque metal contact electrode, resulting in a decrease in light extraction efficiency. In addition, since the N-type GaN layer and the transparent conductive layer (ITO) have different resistivities, the N-GaN resistivity is much smaller than that of the transparent conductive layer (ITO), so that current flows more easily from the N-type GaN layer with low resistivity, i.e., the current is transmitted longitudinally from the P electrode to the N electrode through the N-type GaN layer, and finally, the current is concentrated around the P electrode, resulting in negative effects of current congestion, current breakdown, and the like. In summary, the N-GaN resistance and the collocation of the transparent conductive layer (ITO) directly affect the light emitting area and the current distribution effect of the diode.
Disclosure of Invention
The invention aims to solve the technical problem of providing a light-emitting diode epitaxial wafer which can improve the current aggregation effect, increase the area of a light-emitting area, improve the light extraction efficiency and enhance the reverse breakdown voltage resistance.
The invention also aims to provide a preparation method of the light-emitting diode epitaxial wafer, which has simple process and can stably prepare the light-emitting diode epitaxial wafer with good luminous efficiency.
In order to solve the technical problems, the invention provides a light-emitting diode epitaxial wafer, which comprises a substrate, wherein a buffer layer, an N-type GaN layer, a stress release layer, an active layer, a P-type GaN layer and a composite P-type contact layer are sequentially arranged on the substrate;
the composite P-type contact layer comprises an AlGaN/AlN superlattice layer, a GaN layer and a heterojunction hole induction layer which are sequentially laminated on the P-type GaN layer, wherein the heterojunction hole induction layer comprises P-type Al x Ga 1-x N barrier layer and P type In y Ga 1-y And the N cap layer, wherein the value range of x is 0.1-0.5, and the value range of y is 0.01-0.1.
In one embodiment, the AlGaN/AlN superlattice layer comprises a P-type AlGaN layer and a P-type AlN layer which are alternately laminated, and the alternating period number is 5-20;
the P-type doping concentration of the AlGaN/AlN superlattice layer is 1 multiplied by 10 17 atoms/cm 3 ~1×10 19 atoms/cm 3 。
In one embodiment, the AlGaN/AlN superlattice layer has a thickness of 5 nm-20 nm;
the thickness ratio of the P-type AlGaN layer to the P-type AlN layer is more than 2.
In one embodiment, the thickness of the GaN layer is 5 nm-25 nm.
In one embodiment, the heterojunction hole inducing layer has a thickness of 5nm to 25nm.
In one embodiment, the P-type Al x Ga 1-x N barrier layer and the P type In y Ga 1-y The thickness ratio of the N cap layer is less than or equal to 1/3.
In one embodiment, the heterojunction hole inducing layer has a P-type doping concentration of 1×10 18 atoms/cm 3 ~1×10 21 atoms/cm 3 。
In one embodiment, the P-type doping concentration of the heterojunction hole inducing layer is graded from low to high along the growth direction.
Correspondingly, the invention also provides a preparation method of the light-emitting diode epitaxial wafer, which comprises the following steps:
s1, preparing a substrate;
s2, sequentially depositing a buffer layer, an N-type GaN layer, a stress release layer, an active layer, a P-type GaN layer and a composite P-type contact layer on the substrate;
the composite P-type contact layer comprises an AlGaN/AlN superlattice layer, a GaN layer and a heterojunction hole induction layer which are sequentially laminated on the P-type GaN layer, wherein the heterojunction hole induction layer comprises P-type Al x Ga 1-x N barrier layer and P type In y Ga 1-y And the N cap layer, wherein the value range of x is 0.1-0.5, and the value range of y is 0.01-0.1.
Correspondingly, the invention further provides an LED, and the LED comprises the LED epitaxial wafer.
The implementation of the invention has the following beneficial effects:
the invention provides a light-emitting diode epitaxial wafer which is provided with a composite P-type contact layer with a specific structure, wherein the composite P-type contact layer comprises an AlGaN/AlN superlattice layer, a GaN layer and a heterojunction hole induction layer which are sequentially laminated on a P-type GaN layer, and the heterojunction hole induction layer comprises P-type Al x Ga 1-x N barrier layer and P type In y Ga 1-y And an N cap layer.
The AlGaN/AlN superlattice layer has higher energy system, forms a step energy system with the subsequent GaN layer and heterojunction hole induction layer, can improve the series resistance between the N-type GaN layer and the ITO, and is more prone to being transmitted from the ITO layer to the N electrode in the process of transmitting the current from the P electrode to the N electrode, so that the distribution range of carriers is improved, and the problem of current aggregation is effectively improved. On the other hand, the AlGaN/AlN superlattice layer adopts a superlattice structure to enhance the tunneling effect of carriers crossing the potential barrier and reduce the loss of working voltage.
In another aspect, the heterojunction hole-inducing layer comprises P-type Al x Ga 1-x N barrier layer and P type In y Ga 1-y N cap layer using P-type Al x Ga 1-x N barrier layer and P type In y Ga 1-y Piezoelectric polarization caused by strong spontaneous polarization effect between N cap layers and large lattice mismatch between the N cap layers forms two-dimensional hole gas at the heterojunction interface. The two are combined to form a high-concentration hole gas at the heterojunction interface, so that the capability of carriers to pass through the potential barrier through the tunneling effect is greatly improved, and meanwhile, the working voltage is reduced. Further, P type In y Ga 1-y The low band gap width of the N cap layer also reduces the work function of the P-type contact layer, lowering the schottky barrier height.
In conclusion, the light-emitting diode epitaxial wafer provided by the invention can improve the current aggregation effect, increase the area of a light-emitting area, improve the light extraction efficiency and enhance the reverse breakdown voltage resistance.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to the present invention;
fig. 2 is a flowchart of a method for preparing an led epitaxial wafer according to the present invention;
fig. 3 is a flowchart of step S2 of the method for manufacturing a light emitting diode epitaxial wafer according to the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
Unless otherwise indicated or contradicted, terms or phrases used herein have the following meanings:
in the present invention, "preferred" is merely to describe embodiments or examples that are more effective, and it should be understood that they are not intended to limit the scope of the present invention.
In the invention, the technical characteristics described in an open mode comprise a closed technical scheme composed of the listed characteristics and also comprise an open technical scheme comprising the listed characteristics.
In the present invention, the numerical range is referred to, and both ends of the numerical range are included unless otherwise specified.
In order to solve the above problems, the present invention provides a light emitting diode epitaxial wafer, as shown in fig. 1, comprising a substrate 1, wherein a buffer layer 2, an N-type GaN layer 3, a stress release layer 4, an active layer 5, a P-type GaN layer 6, and a composite P-type contact layer 7 are sequentially disposed on the substrate 1;
the composite P-type contact layer 7 comprises an AlGaN/AlN superlattice layer 71, a GaN layer 72 and a heterojunction hole inducing layer 73 sequentially laminated on the P-type GaN layer 6, wherein the heterojunction hole inducing layer 73 comprises P-type Al x Ga 1-x N barrier layer 731 and P type In y Ga 1-y The N cap layer 732, wherein x ranges from 0.1 to 0.5 and y ranges from 0.01 to 0.1.
The specific structure of the composite P-type contact layer 7 is as follows:
in one embodiment, the AlGaN/AlN superlattice layer 71 includes a P-type AlGaN layer and a P-type AlN layer alternately stacked, and the number of alternating periods is 5 to 20; the AlGaN/AlN superlattice layer 71 has a P-type doping concentration of 1×10 17 atoms/cm 3 ~1×10 19 atoms/cm 3 . Preferably, the AlGaN/AlN superlattice layer 71 has a P-type doping concentration of 5×10 17 atoms/cm 3 ~5×10 18 atoms/cm 3 . In one embodiment, the AlGaN/AlN superlattice layer 71 has a thickness of 5nm to 20nm; exemplary thicknesses of the AlGaN/AlN superlattice layer 71 are 6nm, 8nm, 10nm, 12nm, 14nm, 16nm, 18nm, but are not limited thereto; preferably, the thickness ratio of the P-type AlGaN layer to the P-type AlN layer is > 2. The AlGaN/AlN superlattice layer has higher energy system, forms a step energy system with the subsequent GaN layer and heterojunction hole induction layer, can improve the series resistance between the N-type GaN layer and the ITO, and is more prone to being transmitted from the ITO layer to the N electrode in the process of transmitting the current from the P electrode to the N electrode, so that the distribution range of carriers is improved, and the problem of current aggregation is effectively improved. On the other hand, the AlGaN/AlN superlattice layer adopts a superlattice structure to enhance the tunneling effect of carriers crossing the potential barrier and reduce the loss of working voltage.
In one embodiment, the thickness of the GaN layer 72 is 5nm to 25nm; exemplary thicknesses of the GaN layer 72 are 6nm, 8nm, 10nm, 12nm, 14nm, 16nm, 18nm, 20nm, 22nm, 24nm, but are not limited thereto. The GaN layer serves as a transition between the AlGaN/AlN superlattice layer and a subsequent heterojunction hole inducing layer.
In one embodiment, the thickness of the heterojunction hole inducing layer 73 is 5nm to 25nm; exemplary thicknesses of the heterojunction hole inducing layer 73 are 6nm, 8nm, 10nm, 12nm, 14nm, 16nm, 18nm, 20nm, 22nm, 24nm, but are not limited thereto. In one embodiment, the heterojunction hole inducing layer 73 has a P-type doping concentration of 1×10 18 atoms/cm 3 ~1×10 21 atoms/cm 3 . Preferably, the P-type doping concentration of the heterojunction hole inducing layer 73 is gradually changed from low to high along the growth direction. It should be noted that, the higher doping concentration near the electrode can improve the tunneling capability of the carrier and reduce the ohmic contact resistance. The doping concentration far away from the electrode is lower or undoped, the migration rate of carriers in the vertical direction of the composite P-type contact layer is reduced, the transverse expansion of the carriers is promoted, the current density aggregation right below the P electrode is reduced, the current distribution range is improved, and the negative effects of electrode light absorption, current breakdown and the like are reduced.
Further, the heterojunction hole inducing layer 73 comprises P-type Al x Ga 1-x N barrier layer 731 and P type In y Ga 1-y The N cap layer 732, wherein x ranges from 0.1 to 0.5 and y ranges from 0.01 to 0.1. Preferably, the value range of x is 0.15-0.45, and the value range of y is 0.02-0.09. Preferably, the P type Al x Ga 1-x N barrier layer 731 and the P type In y Ga 1-y The thickness ratio of the N cap layer 732 is 1/3 or less. At this ratio the P-type Al x Ga 1-x The N barrier layer has a relatively extremely thin structure, so that the N barrier layer is close to a full strain state, and the hole gas concentration at the heterojunction interface in the full strain state can reach a peak value more easily. The heterojunction hole induction layer utilizes P-type Al x Ga 1-x N barrier layer and P type In y Ga 1-y Piezoelectric polarization caused by strong spontaneous polarization effect between N cap layers and large lattice mismatch between the N cap layers forms two-dimensional hole gas at the heterojunction interface. The two are combined to form a high heterojunction interfaceThe concentration of the hole gas greatly improves the capability of carriers to pass through the potential barrier through the tunneling effect, and reduces the working voltage. Further, P type In y Ga 1-y The low band gap width of the N cap layer also reduces the work function of the P-type contact layer, lowering the schottky barrier height.
In conclusion, the light-emitting diode epitaxial wafer provided by the invention can improve the current aggregation effect, increase the area of a light-emitting area, improve the light extraction efficiency and enhance the reverse breakdown voltage resistance.
Correspondingly, the invention provides a preparation method of the light-emitting diode epitaxial wafer, as shown in fig. 2, comprising the following steps:
s1, preparing a substrate 1;
in one embodiment, the substrate can be sapphire substrate or SiO 2 One of a sapphire composite substrate, a silicon carbide substrate, a gallium nitride substrate and a zinc oxide substrate. Preferably, the substrate is a sapphire substrate which is widely used in the current LED production, and the sapphire substrate has the advantages of mature preparation process, low price, good chemical stability, good thermal stability and the like.
S2, sequentially depositing a buffer layer 2, an N-type GaN layer 3, a stress release layer 4, an active layer 5, a P-type GaN layer 6 and a composite P-type contact layer 7 on the substrate 1;
as shown in fig. 3, step S2 includes the steps of:
s21, depositing a buffer layer 2 on the substrate 1.
In one embodiment, an AlN buffer layer is deposited in the PVD application material, and the thickness of the buffer layer is 10 nm-30 nm.
S22, depositing an N-type GaN layer 3 on the buffer layer 2.
In one embodiment, the temperature of the reaction chamber is controlled to be 1000-1200 ℃, an N source and a Ga source are introduced, and SiH is introduced 4 Providing N-type doping, and growing an N-type GaN layer with the thickness of 2-3 mu m. Preferably, the Si doping concentration is 1×10 19 atoms/cm 3 ~1×10 20 atoms/cm 3 。
S23, depositing a stress release layer 4 on the N-type GaN layer 3.
In one embodiment, the temperature of the reaction chamber is controlled to 800-900 ℃, and the low-Si-doped InGaN layer and the low-Si-doped GaN layer are alternately grown periodically to serve as stress release layers. Preferably, the Si doping concentration is 1×10 15 atoms/cm 3 ~1×10 17 atoms/cm 3 。
S24, depositing an active layer 5 on the stress release layer 4.
The active layer 5 is an InGaN quantum well layer and an AlGaN quantum barrier layer which are alternately stacked, and the stacking period number is 6-12; the growth temperature of the InGaN quantum well layer is 750-880 ℃, the thickness of the InGaN quantum well layer is 2-5 nm, and the growth pressure of the InGaN quantum well layer is 50-300 torr; the growth temperature of the AlGaN quantum barrier layer is 800-900 ℃, the thickness of the AlGaN quantum barrier layer is 5-15 nm, and the growth pressure is 50-300 torr.
S25, depositing a P-type GaN layer 6 on the active layer 5.
In one embodiment, the temperature of the reaction chamber is controlled to be 800-980 ℃, an N source, a Ga source and a Mg source are introduced, the thickness of the deposited P-type GaN layer is controlled to be 50-80 nm, and the doping concentration of Mg is controlled to be 1 multiplied by 10 15 atoms/cm 3 ~1×10 18 atoms/cm 3 。
S26, depositing a composite P-type contact layer 7 on the P-type GaN layer 6.
The composite P-type contact layer comprises an AlGaN/AlN superlattice layer, a GaN layer and a heterojunction hole induction layer which are sequentially laminated on the P-type GaN layer, wherein the heterojunction hole induction layer comprises P-type Al x Ga 1-x N barrier layer and P type In y Ga 1-y And the N cap layer, wherein the value range of x is 0.1-0.5, and the value range of y is 0.01-0.1.
Correspondingly, the invention further provides an LED, and the LED comprises the LED epitaxial wafer. The photoelectric efficiency of the LED is effectively improved, and other items have good electrical properties.
The invention is further illustrated by the following examples:
example 1
The embodiment provides a light-emitting diode epitaxial wafer, which comprises a substrate, wherein a buffer layer, an N-type GaN layer, a stress release layer, an active layer, a P-type GaN layer and a composite P-type contact layer are sequentially arranged on the substrate;
the composite P-type contact layer comprises an AlGaN/AlN superlattice layer, a GaN layer and a heterojunction hole induction layer which are sequentially laminated on the P-type GaN layer, wherein the heterojunction hole induction layer comprises P-type Al x Ga 1-x N barrier layer and P type In y Ga 1-y And an N cap layer, wherein x is 0.3 and y is 0.05.
The P-type doping concentration of the AlGaN/AlN superlattice layer is 5 multiplied by 10 17 atoms/cm 3 The thickness is 15nm, and the thickness ratio of the P-type AlGaN layer to the P-type AlN layer is 2.5:1.
the thickness of the GaN layer was 10nm.
The thickness of the heterojunction hole induction layer is 10nm, and the P-type doping concentration is 5 multiplied by 10 along the growth direction 18 atoms/cm 3 Gradual change to 5X 10 20 atoms/cm 3 。
The P type Al x Ga 1-x N barrier layer and the P type In y Ga 1-y The thickness ratio of the N cap layer is 1:3.
example 2
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that: the thickness of the AlGaN/AlN superlattice layer is 10nm; the other steps are the same as in example 1.
Example 3
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that: the thickness ratio of the P-type AlGaN layer to the P-type AlN layer is 3:1, a step of; the other steps are the same as in example 1.
Example 4
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that: the P-type doping concentration of the heterojunction hole induction layer is 5 multiplied by 10 along the growth direction 19 atoms/cm 3 Gradual change to 5X 10 20 atoms/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the The other steps are the same as in example 1.
Example 5
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that: the thickness of the GaN layer is 5nm; the thickness of the heterojunction hole induction layer is 5nm; the other steps are the same as in example 1.
Example 6
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that: the P type Al x Ga 1- x N barrier layer and the P type In y Ga 1-y The thickness ratio of the N cap layer is 1:4, a step of; the other steps are the same as in example 1.
Comparative example 1
This comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that: a composite P-type contact layer was not provided, and the other was the same as in example 1.
The light emitting diode epitaxial wafers prepared in examples 1 to 6 and comparative example 1 were prepared into chips using the same chip process conditions, 300 LED chips were extracted, and tested at 120mA/60mA current, and the luminance improvement rate, ESD improvement rate and reverse voltage improvement amount of each example with respect to comparative example 1 were tested, and specific test results are shown in table 1.
From the above results, it can be seen from the test data of comparative examples 1 to 6 and 1 that the light emitting diode epitaxial wafer provided by the present invention has a composite P-type contact layer with a specific structure, wherein the composite P-type contact layer comprises an AlGaN/AlN superlattice layer, a GaN layer and a heterojunction hole inducing layer sequentially laminated on the P-type GaN layer, and the heterojunction hole inducing layer comprises a P-type Al layer x Ga 1-x N barrier layer and P type In y Ga 1-y And an N cap layer. The light-emitting diode epitaxial wafer can improve the current aggregation effect, increase the area of a light-emitting area, improve the light extraction efficiency and enhance the reverse breakdown voltage resistance.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, wherein a buffer layer, an N-type GaN layer, a stress release layer, an active layer, a P-type GaN layer and a composite P-type contact layer are sequentially arranged on the substrate;
the composite P-type contact layer comprises an AlGaN/AlN superlattice layer, a GaN layer and a heterojunction hole induction layer which are sequentially laminated on the P-type GaN layer, wherein the heterojunction hole induction layer comprises P-type Al x Ga 1-x N barrier layer and P type In y Ga 1-y And the N cap layer, wherein the value range of x is 0.1-0.5, and the value range of y is 0.01-0.1.
2. The light-emitting diode epitaxial wafer according to claim 1, wherein the AlGaN/AlN superlattice layer comprises a P-type AlGaN layer and a P-type AlN layer which are alternately laminated, and the number of alternating periods is 5 to 20;
the P-type doping concentration of the AlGaN/AlN superlattice layer is 1 multiplied by 10 17 atoms/cm 3 ~1×10 19 atoms/cm 3 。
3. The light-emitting diode epitaxial wafer according to claim 2, wherein the thickness of the AlGaN/AlN superlattice layer is 5 nm-20 nm;
the thickness ratio of the P-type AlGaN layer to the P-type AlN layer is more than 2.
4. The light-emitting diode epitaxial wafer of claim 1, wherein the GaN layer has a thickness of 5nm to 25nm.
5. The light-emitting diode epitaxial wafer of claim 1, wherein the heterojunction hole inducing layer has a thickness of 5nm to 25nm.
6. The light-emitting diode epitaxial wafer of claim 1, wherein the P-type Al x Ga 1-x N barrier layer and the P type In y Ga 1-y The thickness ratio of the N cap layer is less than or equal to 1/3.
7. The light-emitting diode epitaxial wafer of claim 1, wherein the heterojunction hole inducing layer has a P-type doping concentration of 1 x 10 18 atoms/cm 3 ~1×10 21 atoms/cm 3 。
8. The light-emitting diode epitaxial wafer of claim 7, wherein the P-type doping concentration of the heterojunction hole inducing layer is graded from low to high along the growth direction.
9. A method for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 8, comprising the following steps:
s1, preparing a substrate;
s2, sequentially depositing a buffer layer, an N-type GaN layer, a stress release layer, an active layer, a P-type GaN layer and a composite P-type contact layer on the substrate;
the composite P-type contact layer comprises an AlGaN/AlN superlattice layer, a GaN layer and a heterojunction hole induction layer which are sequentially laminated on the P-type GaN layer, wherein the heterojunction hole induction layer comprises P-type Al x Ga 1-x N barrier layer and P type In y Ga 1-y And the N cap layer, wherein the value range of x is 0.1-0.5, and the value range of y is 0.01-0.1.
10. An LED, characterized in that the LED comprises a light emitting diode epitaxial wafer according to any one of claims 1 to 8.
CN202311244885.5A 2023-09-26 2023-09-26 LED epitaxial wafer, preparation method thereof and LED Active CN116995169B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311244885.5A CN116995169B (en) 2023-09-26 2023-09-26 LED epitaxial wafer, preparation method thereof and LED

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311244885.5A CN116995169B (en) 2023-09-26 2023-09-26 LED epitaxial wafer, preparation method thereof and LED

Publications (2)

Publication Number Publication Date
CN116995169A true CN116995169A (en) 2023-11-03
CN116995169B CN116995169B (en) 2024-04-09

Family

ID=88521666

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311244885.5A Active CN116995169B (en) 2023-09-26 2023-09-26 LED epitaxial wafer, preparation method thereof and LED

Country Status (1)

Country Link
CN (1) CN116995169B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090065762A1 (en) * 2007-09-10 2009-03-12 Seoul Opto Device Co., Ltd. Light emitting diode with improved structure
US20100187494A1 (en) * 2006-12-04 2010-07-29 Electronics And Telecommunications Research I Institute Nitride semiconductor-based light emitting devices
CN103258964A (en) * 2008-05-16 2013-08-21 株式会社半导体能源研究所 Light-emitting element, electronic device, and light-emitting device
CN108831975A (en) * 2018-04-28 2018-11-16 华灿光电(苏州）有限公司 A kind of LED epitaxial slice and preparation method thereof
CN115050870A (en) * 2022-08-12 2022-09-13 江西兆驰半导体有限公司 GaN-based light emitting diode epitaxial wafer and preparation method thereof
CN115911201A (en) * 2022-11-21 2023-04-04 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100187494A1 (en) * 2006-12-04 2010-07-29 Electronics And Telecommunications Research I Institute Nitride semiconductor-based light emitting devices
US20090065762A1 (en) * 2007-09-10 2009-03-12 Seoul Opto Device Co., Ltd. Light emitting diode with improved structure
CN103258964A (en) * 2008-05-16 2013-08-21 株式会社半导体能源研究所 Light-emitting element, electronic device, and light-emitting device
CN108831975A (en) * 2018-04-28 2018-11-16 华灿光电(苏州）有限公司 A kind of LED epitaxial slice and preparation method thereof
CN115050870A (en) * 2022-08-12 2022-09-13 江西兆驰半导体有限公司 GaN-based light emitting diode epitaxial wafer and preparation method thereof
CN115911201A (en) * 2022-11-21 2023-04-04 江西兆驰半导体有限公司 Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode

Also Published As

Publication number Publication date
CN116995169B (en) 2024-04-09

Similar Documents

Publication Publication Date Title
CN102368519B (en) A kind of method improving semiconductor diode multiple quantum well light emitting efficiency
CN104409587B (en) A kind of InGaN base blue-green light LED epitaxial structure and growing method
TW200303621A (en) Indium gallium nitride separate confinement heterostructure light emitting devices
CN105206726A (en) LED structure and growth method thereof
CN109786529A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN114883462B (en) Light emitting diode epitaxial wafer and preparation method thereof
CN116014043B (en) Deep ultraviolet light-emitting diode epitaxial wafer, preparation method thereof and LED
JP2005056922A (en) Semiconductor light emitting element
JP7480300B2 (en) Epitaxial structure of micro light-emitting diode and its manufacturing method
CN115911201A (en) Light emitting diode epitaxial wafer, preparation method thereof and light emitting diode
CN117410406B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116960248B (en) Light-emitting diode epitaxial wafer and preparation method thereof
KR100738399B1 (en) Nitride semiconductor light emitting device
CN116364820B (en) LED epitaxial wafer, preparation method thereof and LED
CN206401345U (en) A kind of LED epitaxial slice
CN116885067A (en) Light-emitting diode epitaxial wafer and preparation method thereof
CN116598396A (en) LED epitaxial wafer, preparation method thereof and LED
KR101201641B1 (en) Transparent thin film, light emitting device comprising the same, and methods for preparing the same
CN116779736A (en) LED epitaxial wafer, preparation method thereof and LED
CN116845153A (en) High-light-efficiency light-emitting diode epitaxial wafer, preparation method and LED
CN116995169B (en) LED epitaxial wafer, preparation method thereof and LED
CN102332510A (en) Method for growing high-antistatic LED (light-emitting diode) by adopting metal organic compound vapor phase epitaxy technology
CN111490453B (en) GaN-based laser with step-doped lower waveguide layer and preparation method thereof
CN117810332B (en) Gallium nitride-based light-emitting diode epitaxial wafer and preparation method thereof
CN217086610U (en) LED structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant