CN116995026A - Deep trench isolation structure and preparation method thereof - Google Patents
Deep trench isolation structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 8
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
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- 238000005229 chemical vapour deposition Methods 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The application provides a deep trench isolation structure device and a preparation method thereof. The deep trench isolation structure includes: a substrate of a first conductivity type; a buried layer having a second conductivity type within the substrate; the first conductivity type is different from the second conductivity type; a first trench located within the substrate and extending from an upper surface of the substrate into the buried layer; a first conductive layer of a second conductivity type covering sidewalls of the first trench; a second trench located in the substrate and inside the first conductive layer; an isolation medium layer covering the side wall of the second groove; and the third groove is positioned in the substrate and positioned at the inner side of the isolation medium layer. In the deep trench isolation structure, the two different types of conductive layers and the isolation medium layer are arranged, so that the contact connection between the buried layer and the substrate can be realized while the isolation effect is high, the application range is wide, and the deep trench isolation structure can be popularized to more different technical platforms.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a deep trench isolation structure and a preparation method thereof.
Background
In chip design, DTI (Deep Trench oxide Isolation ) structures are a common isolation structure; the deep trench oxide isolation structure is formed by etching a deep trench and filling oxide, so as to achieve the effect of high-voltage isolation. However, the current deep trench oxidation isolation structure only has a high-voltage isolation function, has a single function and is limited in application range.
Disclosure of Invention
The application aims to provide a deep trench isolation structure and a preparation method thereof, which solve the problems of the isolation structure in the prior art that the isolation structure only has a high-voltage isolation function, single function, limited application range and the like.
In order to achieve the purpose of the application, the application provides the following technical scheme:
in a first aspect, there is provided a deep trench isolation structure comprising:
a substrate of a first conductivity type; a buried layer of a second conductivity type within the substrate, an upper surface of the buried layer having a spacing from an upper surface of the substrate, a lower surface of the buried layer having a spacing from a surface of the substrate; the first conductivity type is different from the second conductivity type;
a first trench located within the substrate and extending from an upper surface of the substrate into the buried layer;
a first conductive layer of a second conductivity type covering sidewalls of the first trench;
a second trench located within the substrate and inside the first conductive layer; the second groove penetrates through the buried layer from the upper surface of the substrate and extends into the substrate below the buried layer;
an isolation medium layer covering the side wall of the second groove;
the third groove is positioned in the substrate and positioned at the inner side of the isolation medium layer; the bottom of the third groove is lower than the bottom of the second groove;
and a second conductive layer of the first conductive type filling the third trench.
In one embodiment, the method further comprises:
the first hard mask layer is positioned on the upper surface of the substrate;
the second hard mask layer is positioned on the upper surface of the first hard mask layer; the first hard mask layer and the second hard mask layer are also provided with openings therein, the openings define the shape and the position of the top of the first trench and are communicated with the first trench; the first conductive layer also covers sidewalls of the opening.
In one embodiment, the first, second and third grooves are all annular grooves.
In one embodiment, the first conductivity type comprises a P-type and the second conductivity type comprises an N-type; or the first conductivity type comprises an N-type and the second conductivity type comprises a P-type.
In a second aspect, the present application further provides a method for preparing a deep trench isolation structure, where the method for preparing a deep trench isolation structure includes:
providing a substrate of a first conductivity type, wherein a buried layer of a second conductivity type is arranged in the substrate, the upper surface of the buried layer is spaced from the upper surface of the substrate, and the lower surface of the buried layer is spaced from the surface of the substrate; the first conductivity type is different from the second conductivity type;
forming a first groove, a second groove, a third groove, a first conductive layer of a second conductive type, an isolation medium layer and a second conductive layer of the first conductive type in the substrate; the first trench extends from the upper surface of the substrate into the buried layer; the first conductive layer covers the side wall of the first groove; the second groove is positioned on the inner side of the first conductive layer, penetrates through the buried layer from the upper surface of the substrate and extends into the substrate below the buried layer; the isolation medium layer covers the side wall of the second groove; the third groove is positioned on the inner side of the isolation medium layer, and the bottom of the third groove is lower than the bottom of the second groove.
In one embodiment, the forming a first trench, a second trench, a third trench, a first conductive layer of a second conductivity type, an isolation dielectric layer, and a second conductive layer of the first conductivity type in the substrate includes:
forming a patterned hard mask layer on the upper surface of the substrate, wherein an opening is formed in the patterned hard mask layer, and the opening is defined as the shape and the position of the first groove;
etching the substrate based on the patterned hard mask layer to form the first trench;
forming a first conductive material layer of a second conductive type, wherein the first conductive material layer covers the side wall of the first groove, the bottom of the groove, the side wall of the opening and the upper surface of the patterned hard mask layer;
removing the first conductive material layer at the bottom of the first groove;
continuing to etch the substrate to form the second groove;
forming an isolation dielectric material layer, wherein the isolation dielectric material layer covers the bottom of the second groove, the side wall of the second groove and the exposed surface of the first conductive material layer;
removing the isolation dielectric material layer at the bottom of the second groove, and continuing etching the substrate to form the third groove;
forming a second conductive material layer of the first conductive type, wherein the second conductive material layer fills the third groove and covers the exposed surface of the isolation dielectric material layer;
and removing the first conductive material layer, the isolation medium material layer, the second conductive material layer and part of the patterned hard mask layer on the patterned hard mask layer to obtain the first conductive layer, the isolation medium layer and the second conductive layer.
In one embodiment, the forming a patterned hard mask layer on the upper surface of the substrate includes:
forming a first hard mask layer on the upper surface of the substrate;
forming a second hard mask layer on the upper surface of the first hard mask layer;
forming a third hard mask layer on the upper surface of the second hard mask layer;
forming a patterned photoresist layer on the upper surface of the third hard mask layer;
and etching the third hard mask layer, the second hard mask layer and the first hard mask layer based on the patterned photoresist layer to obtain the patterned hard mask layer.
In one embodiment, after the etching the third hard mask layer, the second hard mask layer and the first hard mask layer based on the patterned photoresist layer to obtain the patterned hard mask layer, the method further includes:
and removing the patterned photoresist layer.
In one embodiment, the removing the first conductive material layer, the isolation dielectric material layer, the second conductive material layer, and a portion of the patterned hard mask layer on the patterned hard mask layer to obtain the first conductive layer, the isolation dielectric layer, and the second conductive layer includes:
and removing the first conductive material layer, the isolation medium material layer, the second conductive material layer and the third hard mask layer on the patterned hard mask layer by adopting a chemical mechanical polishing process to obtain the first conductive layer, the isolation medium layer and the second conductive layer.
In one embodiment, the first conductivity type comprises a P-type and the second conductivity type comprises an N-type; or the first conductivity type comprises an N-type and the second conductivity type comprises a P-type.
The deep trench isolation structure and the preparation method thereof provided by the application have the following beneficial effects:
in the deep trench isolation structure, the two different types of conductive layers and the isolation medium layer are arranged, so that the contact connection between the buried layer and the substrate can be realized while the isolation effect is high, the application range is wide, and the deep trench isolation structure can be popularized to more different technical platforms.
In the preparation method of the deep trench isolation structure, by arranging the two different types of conductive layers and the isolation medium layer, the contact connection between the buried layer and the substrate can be realized while the isolation effect is high, the application range is wide, and the method can be popularized to more different technical platforms.
Drawings
Figure 1 is a schematic cross-sectional structure of a deep trench isolation structure provided in one embodiment;
figure 2 is a flow chart of a method of fabricating a deep trench isolation structure in another embodiment;
fig. 3 is a flowchart of step S12 in a method of fabricating a deep trench isolation structure in another embodiment;
fig. 4 is a flowchart of step S121 in a deep trench isolation structure fabrication method in another embodiment;
fig. 5 is a schematic cross-sectional structure of a structure obtained in step S1214 in the method for fabricating a deep trench isolation structure in another embodiment;
fig. 6 is a schematic cross-sectional structure of the structure obtained in step S1215 in the method for fabricating a deep trench isolation structure in another embodiment;
fig. 7 is a schematic cross-sectional structure of the structure obtained in step S122 in the method for fabricating a deep trench isolation structure in another embodiment;
fig. 8 is a schematic cross-sectional structure of the structure obtained in step S123 in the method for fabricating a deep trench isolation structure in another embodiment;
fig. 9 is a schematic cross-sectional structure of the structure obtained in step S126 in the method for fabricating a deep trench isolation structure in another embodiment;
fig. 10 is a schematic cross-sectional structure of the structure obtained in step S128 in the method for fabricating a deep trench isolation structure in another embodiment;
fig. 11 is a schematic cross-sectional structure of a structure obtained in step S129 in the method for fabricating a deep trench isolation structure in another embodiment.
Description of the reference numerals
10. A substrate; 20. a buried layer; 30. a first trench; 40. a first conductive layer; 401. a first conductive material layer; 50. a second trench; 60. an isolation dielectric layer; 601. an isolation dielectric material layer; 70. a third trench; 80. a second conductive layer; 801. a second conductive material layer; 90 patterning the hard mask layer; 901. a first hard mask layer, 902, a second hard mask layer; 903. a third hard mask layer; 100. patterning the photoresist layer.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present application, a technical solution in an embodiment of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiment of the present application, and it is apparent that the described embodiment is only a part of the embodiment of the present application, but not all the embodiments. All other embodiments, based on the embodiments of the application, which a person skilled in the art would obtain without making any inventive effort, are within the scope of the application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus. The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In chip design, one of the most commonly used isolation means is to form a P-N-P structure or an N-P-N structure through two PN junctions, and the method is simple in process and can realize the isolation requirement of higher voltage by increasing the distance between N and N. However, as the aggressiveness of devices within integrated circuits increases, the distance between adjacent devices decreases, and the need for higher voltage isolation increases, which makes the limitations of isolation structures more apparent, for example: when the distance is smaller, a punch through (punch through) phenomenon is easy to occur, and when the distance is increased too much, the occupied area is too large, and in addition, the parasitic triode is formed, so that the isolation performance is also poor.
Another isolation approach is DTI (Deep Trench oxide Isolation ) structure is a common isolation structure; the deep trench oxide isolation structure is formed by etching a deep trench and filling oxide, so as to achieve the effect of high-voltage isolation. Namely, in the deep trench oxide isolation structure, deep trench oxide isolation is added between the N-N structure or the P-P structure to form an N-oxide-N isolation structure and a P-oxide-P isolation structure respectively. However, the current deep trench oxidation isolation structure only has a high-voltage isolation function, has a single function and is limited in application range.
Referring to fig. 1, the present application provides a deep trench isolation structure, which may include:
a substrate 10 of a first conductivity type; a buried layer 20 of a second conductivity type is provided in the substrate 10, an upper surface of the buried layer 20 having a space from an upper surface of the substrate 10, and a lower surface of the buried layer 20 having a space from a surface of the substrate 10; the first conductivity type is different from the second conductivity type; a first trench 30 located within the substrate 10 and extending from the upper surface of the substrate 10 into the buried layer 20; a first conductive layer 40 of a second conductive type covering sidewalls of the first trench 30; a second trench 50 located within the substrate 10 and inside the first conductive layer 40; the second trench 50 penetrates the buried layer 20 from the upper surface of the substrate 10 and extends into the substrate 10 below the buried layer 20; an isolation dielectric layer 60 covering sidewalls of the second trench 50; a third trench 70 located within the substrate 10 and inside the isolation dielectric layer 60; the bottom of the third trench 70 is lower than the bottom of the second trench 50; a second conductive layer 80 of the first conductivity type, the second conductive layer 80 filling the third trench 70.
In the deep trench isolation structure, the two different types of conductive layers (namely the first conductive layer 40 and the second conductive layer 80) and the isolation medium layer 60 are arranged in the deep trench, so that the contact connection between the buried layer and the substrate can be realized while the high-performance isolation effect is achieved, the application range is wide, and the deep trench isolation structure can be popularized to more different technical platforms; namely, the deep trench isolation structure realizes the high-performance isolation effect with isolation in the transverse direction and communication in the longitudinal direction.
As an example, the substrate 10 may include, but is not limited to, at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon-on-insulator (SOI, silicon On Insulator) substrate, a silicon-on-diamond (SOD, silicon on diamond) substrate, and a strained layer silicon substrate deposited on a silicon-germanium wafer.
As an example, the first conductivity type may include one of a P-type or an N-type, and the second conductivity type may include one of an N-type or a P-type; and the first conductivity type is different from the second conductivity type; specifically, in one example, the first conductivity type is P-type and the second conductivity type is N-type; in another example, the first conductivity type is N-type and the second conductivity type is P-type.
Specifically, the first conductive type substrate 10 may include one of a P-type substrate or an N-type substrate; in this embodiment, the substrate 10 is a silicon substrate, more specifically, the substrate 10 in this embodiment is a P-type silicon substrate.
As an example, the substrate 10 has a buried layer 20 of the second conductive type therein, an upper surface of the buried layer 20 having a space from an upper surface of the substrate 10, and a lower surface of the buried layer 20 having a space from a surface of the substrate 10; the buried layer 20 of the second conductive type may include one of an N-type buried layer or a P-type buried layer; in this embodiment, the buried layer 20 is an N-type buried layer.
Specifically, the mask layer 20 may be formed using, but not limited to, an ion implantation process.
As an example, the first trench 30 is located within the substrate 10 and extends from the upper surface of the substrate 10 into the buried layer 20; the shape of the first groove 30 may be set according to actual needs, and in this embodiment, the first groove 30 may be an annular groove.
As an example, the first conductive layer 40 of the second conductive type covers sidewalls of the first trench 30; the first conductive layer 40 may include, but is not limited to, doping one of a P-type dopant or an N-type dopant in germanium (Ge) or silicon (Si); specifically, the N-type dopant may include, but is not limited to, nitrogen (N), phosphorus (P), arsenic (As), or the like; the P-type dopant may include, but is not limited to, boron (B), gallium (Ga), or indium (In), etc.; in this embodiment, the first conductive layer 40 is a nitrogen doped silicon layer.
As an example, the second trench 50 is located within the substrate 10, and inside the first conductive layer 40; the second trench 50 penetrates the buried layer 20 from the upper surface of the substrate 10 and extends into the substrate 10 below the buried layer 20; the shape of the second groove 50 may be set according to actual needs, and in this embodiment, the second groove 50 may be an annular groove.
As an example, the isolation dielectric layer 60 covers the sidewalls of the second trench 50; the material of the isolation dielectric layer 60 may include, but is not limited to, an insulating material, for example, the material of the isolation dielectric layer 60 may include, but is not limited to, aluminum oxide (Al 2 O 3 ) Silicon oxide (SiO) x ) Silicon nitride (SiN) x ) Or silicon oxynitride (SiON) and the like; specifically, in the present embodiment, the isolation dielectric layer 60 is a silicon oxide layer.
As an example, the third trench 70 is located within the substrate 10 and inside the isolation dielectric layer 60; the bottom of the third trench 70 is lower than the bottom of the second trench 50; the shape of the third groove 70 may be set according to actual needs, and in this embodiment, the third groove 70 may be an annular groove.
As an example, the width of the third trench 70 may include, but is not limited to, 1 μm to 10 μm, for example, the width of the third trench 70 may be: 1 μm, 5 μm or 10 μm, etc.; the depth of the third trench 70 may include, but is not limited to, 10 μm to 300 μm, for example, the depth of the third trench 70 may be: 10 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm or 300 μm, etc.
As an example, the second conductive layer 80 of the first conductive type fills the third trench 70; the material of the second conductive layer 80 may include, but is not limited to, doping germanium or silicon with one of P-type dopant or N-type dopant; in this embodiment, the second conductive layer 80 is a boron doped polysilicon layer.
As an example, the first hard mask layer 901 is located on the upper surface of the substrate 10; the material of the first hard mask layer 901 may include, but is not limited to, silicon dioxide (SiO 2 ) Titanium nitride (TiN) or silicon nitride (SiN), etc.; in this embodiment, the material of the first hard mask layer 901 is silicon dioxide.
As an example, the second hard mask layer 902 is located on the upper surface of the first hard mask layer 901; the second hard mask layer 902 may include, but is not limited to, silicon carbonitride or silicon nitride, and in this embodiment, the material of the second hard mask layer 902 may be silicon nitride; the first hard mask layer 901 and the second hard mask layer 902 also have openings therein, which define the shape and position of the top of the first trench 30 and are in communication with the first trench 30; the shape of the opening can be set according to actual needs, and in this embodiment, the shape of the opening can be annular; the width of the opening may be, but is not limited to, 1 μm to 10 μm, for example, the width of the opening may be: 1 μm, 5 μm or 10 μm, etc.; the first conductive layer 40 covers the sidewalls of the opening.
Referring to fig. 2, the present application provides a method for preparing a deep trench isolation structure, which may include the following steps:
step S11: providing a substrate of a first conductivity type, wherein a buried layer of a second conductivity type is arranged in the substrate, the upper surface of the buried layer is spaced from the upper surface of the substrate, and the lower surface of the buried layer is spaced from the surface of the substrate; the first conductivity type is different from the second conductivity type;
step S12: forming a first groove, a second groove, a third groove, a first conductive layer of a second conductive type, an isolation medium layer and a second conductive layer of the first conductive type in the substrate; a first trench extending from an upper surface of the substrate into the buried layer; the first conductive layer covers the side wall of the first groove; the second groove is positioned at the inner side of the first conductive layer, penetrates through the buried layer from the upper surface of the substrate and extends into the substrate below the buried layer; the isolation medium layer covers the side wall of the second groove; the third groove is positioned on the inner side of the isolation medium layer, and the bottom of the third groove is lower than the bottom of the second groove.
In the preparation method of the deep trench isolation structure, the two different types of conductive layers (namely the first conductive layer and the second conductive layer) and the isolation medium layer are arranged in the deep trench, so that the contact connection between the buried layer and the substrate can be realized while the high-performance isolation effect is achieved, the application range is wide, and the method can be popularized to more different technical platforms; namely, the deep trench isolation structure realizes the high-performance isolation effect with isolation in the transverse direction and communication in the longitudinal direction; the deep trench isolation structure can realize high-voltage isolation among different devices, and meanwhile, the related photomask layers are reduced by adopting a self-aligned mode for the buried layer and the conductive layer, so that the deep trench isolation structure has wider application range and can be popularized to more different technical platforms.
In step S11, referring to step S11 in fig. 2 and fig. 5, a substrate 10 of a first conductivity type is provided, a buried layer 20 of a second conductivity type is provided in the substrate 10, an upper surface of the buried layer 20 is spaced from an upper surface of the substrate 10, and a lower surface of the buried layer 20 is spaced from a surface of the substrate 10; the first conductivity type is different from the second conductivity type.
As an example, the first conductive type substrate 10 may include, but is not limited to, at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon-on-insulator (SOI, silicon On Insulator) substrate, a silicon-on-diamond (SOD, silicon on diamond) substrate, and a strained layer silicon substrate deposited on a silicon-germanium wafer.
As an example, the first conductivity type may include one of a P-type or an N-type conductivity type, and is different from the second conductivity type; specifically, in one example, the first conductivity type is P-type and the second conductivity type is N-type; in another example, the first conductivity type is N-type and the second conductivity type is P-type.
In this embodiment, specifically, in one example, the first conductivity type is P-type, and the second conductivity type is N-type; in another example, the first conductivity type is N-type and the second conductivity type is P-type.
As an example, the buried layer 20 of the second conductive type may include, but is not limited to, one of an N-type buried layer or a P-type buried layer; in this embodiment, the mask layer 20 may be an N-type mask layer, and the N-type buried layer may be formed by implanting N-type dopants into the substrate 10, and in particular, the N-type dopants may include, but are not limited to, nitrogen (N), phosphorus (P), arsenic (As), or the like; the P-type buried layer may be formed by implanting or diffusing a P-type dopant into the substrate 10, and In particular, the P-type dopant may include, but is not limited to, boron (B), gallium (Ga), indium (In), or the like; in this embodiment, the buried layer 20 is an N-type buried layer.
In step S12, referring to step S12 in fig. 2 and fig. 3 to 11, a first trench 30, a second trench 50, a third trench 70, a first conductive layer 40 of a second conductive type, an isolation dielectric layer 60 and a second conductive layer 80 of the first conductive type are formed in the substrate 10; the first trench 30 extends from the upper surface of the substrate 10 into the buried layer; the first conductive layer 40 covers the sidewalls of the first trench 30; the second trench 50 is located inside the first conductive layer 40, penetrates the buried layer 20 from the upper surface of the substrate 10, and extends into the substrate 10 below the buried layer 20; the isolation dielectric layer 60 covers the sidewalls of the second trench 50; the third trench 70 is located inside the isolation dielectric layer 60, and the bottom of the third trench 70 is lower than the bottom of the second trench 50.
Specifically, referring to fig. 3 to 11, step S12 may include the following steps:
step S121: forming a patterned hard mask layer 90 on the upper surface of the substrate 10, wherein the patterned hard mask layer 90 has an opening therein, and the opening defines the shape and position of the first trench 30, as shown in fig. 6;
step S122: etching the substrate 10 based on the patterned hard mask layer 90 to form a first trench 30, as shown in fig. 7;
step S123: forming a first conductive material layer 401 of a second conductive type, the first conductive material layer 401 covering sidewalls of the first trench 30, a bottom of the first trench 30, sidewalls of the opening, and an upper surface of the patterned hard mask layer 90, as shown in fig. 8;
step S124: removing the first conductive material layer 401 at the bottom of the first trench 30;
step S125: continuing to etch the substrate 10 to form a second trench 50;
step S126: forming an isolation dielectric material layer 601, wherein the isolation dielectric material layer 601 covers the bottom of the second trench 50, the side wall of the second trench 50 and the exposed surface of the first conductive material layer 401, as shown in fig. 9;
step S127: removing the isolation dielectric material layer 601 at the bottom of the second trench, and continuing to etch the substrate 10 to form a third trench 70;
step S128: forming a second conductive material layer 801 of the first conductivity type, the second conductive material layer 801 filling the third trench 70 and covering the exposed surface of the isolation dielectric material layer 60, as shown in fig. 10;
step S129: the first conductive material layer 401, the isolation dielectric material layer 601, the second conductive material layer 801 and a portion of the patterned hard mask layer 90 on the patterned hard mask layer 90 are removed to obtain the first conductive layer 40, the isolation dielectric layer 60 and the second conductive layer 80, as shown in fig. 11.
As an example, referring to fig. 4 to 6, step S121 may include the steps of:
step S1211: forming a first hard mask layer 901 on the upper surface of the substrate 10;
step S1212: forming a second hard mask layer 902 on the upper surface of the first hard mask layer 901;
step S1213: forming a third hard mask layer 903 on the upper surface of the second hard mask layer 902;
step S1214: forming a patterned photoresist layer 100 on the upper surface of the third hard mask layer 903, as shown in fig. 5;
step S1215: the third hard mask layer 903, the second hard mask layer 902, and the first hard mask layer 901 are etched based on the patterned photoresist layer 100 to obtain a patterned hard mask layer 90, as shown in fig. 6.
As an example, the formation process of the first, second, and third hard mask layers 901, 902, and 903 may include, but is not limited to, a chemical vapor deposition method (CVD, chemical Vapor Deposition).
As an example, the patterned hard mask layer 90 may be one of a multi-layered structure or a single-layered structure, and the thickness of the patterned hard mask layer 90 may be set according to actual needs, and may include, but is not limited to, 10nm to 1000nm, for example, the thickness of the patterned hard mask layer 90 may be 10nm, 200nm, 400nm, 600nm, 800nm or 1000nm, etc. Specifically, in the present embodiment, the patterned hard mask layer 90 is a multi-layer structure including a patterned first hard mask layer 901, a patterned second hard mask layer 902, and a patterned hard mask layer 903; the patterned hard mask layer 90 may be obtained by photolithography, and dry etching processes. Patterning the hard mask layer 90 may prevent subsequent damage to the substrate 10 during etching to form the first trench 30, the second trench 50, and the third trench 70.
As an example, the patterned hard mask layer 90 has an opening (not shown), and the shape of the opening may be set according to actual needs, and in this embodiment, the shape of the opening may include, but is not limited to, a ring shape.
As an example, the width of the opening may be 1 μm to 10 μm, for example, may be 1 μm, 5 μm or 10 μm. The opening defines the shape and location of the first trench 30.
As an example, after step S1215, removing the patterned photoresist layer 100 may be further included; specifically, the patterned photoresist layer 100 may be removed using, but is not limited to, an ashing process.
As an example, the substrate 10 is etched based on the patterned hard mask layer 90 to form the first trench 30; specifically, in the present embodiment, the substrate 10 is etched using a dry etching process based on the patterned hard mask layer 90 to form the first trench 30.
As an example, in step S125 and step S127, the method of forming the first trench 50 and the second trench 70 may include, but is not limited to, a dry etching process.
As an example, in step S126, the forming process of the isolation dielectric material layer may employ, but is not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
In step S129, the first conductive material layer 401, the isolation dielectric material layer 601, the second conductive material layer 801 and a portion of the patterned hard mask layer 90 on the patterned hard mask layer 90 may be removed by, but not limited to, a chemical mechanical polishing process, so as to obtain the first conductive layer 40, the isolation dielectric layer 60 and the second conductive layer 80. Specifically, in this step, the removed portion of the patterned hard mask layer 90 may be the patterned third hard mask layer 903.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. A deep trench isolation structure, comprising:
a substrate of a first conductivity type; a buried layer of a second conductivity type within the substrate, an upper surface of the buried layer having a spacing from an upper surface of the substrate, a lower surface of the buried layer having a spacing from a surface of the substrate; the first conductivity type is different from the second conductivity type;
a first trench located within the substrate and extending from an upper surface of the substrate into the buried layer;
a first conductive layer of a second conductivity type covering sidewalls of the first trench;
a second trench located within the substrate and inside the first conductive layer; the second groove penetrates through the buried layer from the upper surface of the substrate and extends into the substrate below the buried layer;
an isolation medium layer covering the side wall of the second groove;
the third groove is positioned in the substrate and positioned at the inner side of the isolation medium layer; the bottom of the third groove is lower than the bottom of the second groove;
and a second conductive layer of the first conductive type filling the third trench.
2. The deep trench isolation structure of claim 1, further comprising:
the first hard mask layer is positioned on the upper surface of the substrate;
the second hard mask layer is positioned on the upper surface of the first hard mask layer; the first hard mask layer and the second hard mask layer are also provided with openings therein, the openings define the shape and the position of the top of the first trench and are communicated with the first trench; the first conductive layer also covers sidewalls of the opening.
3. The deep trench isolation structure of claim 1, wherein the first trench, the second trench, and the third trench are all annular trenches.
4. The deep trench isolation structure of any of claims 1-3, wherein the first conductivity type comprises a P-type and the second conductivity type comprises an N-type; or the first conductivity type comprises an N-type and the second conductivity type comprises a P-type.
5. A method for fabricating a deep trench isolation structure, comprising:
providing a substrate of a first conductivity type, wherein a buried layer of a second conductivity type is arranged in the substrate, the upper surface of the buried layer is spaced from the upper surface of the substrate, and the lower surface of the buried layer is spaced from the surface of the substrate; the first conductivity type is different from the second conductivity type;
forming a first groove, a second groove, a third groove, a first conductive layer of a second conductive type, an isolation medium layer and a second conductive layer of the first conductive type in the substrate; the first trench extends from the upper surface of the substrate into the buried layer; the first conductive layer covers the side wall of the first groove; the second groove is positioned on the inner side of the first conductive layer, penetrates through the buried layer from the upper surface of the substrate and extends into the substrate below the buried layer; the isolation medium layer covers the side wall of the second groove; the third groove is positioned on the inner side of the isolation medium layer, and the bottom of the third groove is lower than the bottom of the second groove.
6. The method of claim 5, wherein forming a first trench, a second trench, a third trench, a first conductive layer of a second conductivity type, an isolation dielectric layer, and a second conductive layer of the first conductivity type in the substrate comprises:
forming a patterned hard mask layer on the upper surface of the substrate, wherein an opening is formed in the patterned hard mask layer, and the opening is defined as the shape and the position of the first groove;
etching the substrate based on the patterned hard mask layer to form the first trench;
forming a first conductive material layer of a second conductive type, wherein the first conductive material layer covers the side wall of the first groove, the bottom of the groove, the side wall of the opening and the upper surface of the patterned hard mask layer;
removing the first conductive material layer at the bottom of the first groove;
continuing to etch the substrate to form the second groove;
forming an isolation dielectric material layer, wherein the isolation dielectric material layer covers the bottom of the second groove, the side wall of the second groove and the exposed surface of the first conductive material layer;
removing the isolation dielectric material layer at the bottom of the second groove, and continuing etching the substrate to form the third groove;
forming a second conductive material layer of the first conductive type, wherein the second conductive material layer fills the third groove and covers the exposed surface of the isolation dielectric material layer;
and removing the first conductive material layer, the isolation medium material layer, the second conductive material layer and part of the patterned hard mask layer on the patterned hard mask layer to obtain the first conductive layer, the isolation medium layer and the second conductive layer.
7. The method of claim 6, wherein forming a patterned hard mask layer on the upper surface of the substrate comprises:
forming a first hard mask layer on the upper surface of the substrate;
forming a second hard mask layer on the upper surface of the first hard mask layer;
forming a third hard mask layer on the upper surface of the second hard mask layer;
forming a patterned photoresist layer on the upper surface of the third hard mask layer;
and etching the third hard mask layer, the second hard mask layer and the first hard mask layer based on the patterned photoresist layer to obtain the patterned hard mask layer.
8. The method of claim 7, wherein the etching the third hard mask layer, the second hard mask layer, and the first hard mask layer based on the patterned photoresist layer to obtain the patterned hard mask layer, further comprises:
and removing the patterned photoresist layer.
9. The method of claim 7, wherein the removing the first conductive material layer, the isolation dielectric material layer, the second conductive material layer, and a portion of the patterned hard mask layer on the patterned hard mask layer to obtain the first conductive layer, the isolation dielectric layer, and the second conductive layer comprises:
and removing the first conductive material layer, the isolation medium material layer, the second conductive material layer and the third hard mask layer on the patterned hard mask layer by adopting a chemical mechanical polishing process to obtain the first conductive layer, the isolation medium layer and the second conductive layer.
10. The method of preparing a deep trench isolation structure of any of claims 5-9, wherein the first conductivity type comprises a P-type and the second conductivity type comprises an N-type; or the first conductivity type comprises an N-type and the second conductivity type comprises a P-type.
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