CN116991653A - Chip logic abnormality monitoring method and device and electronic equipment - Google Patents
Chip logic abnormality monitoring method and device and electronic equipment Download PDFInfo
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Abstract
The application provides a chip logic abnormality monitoring method, a chip logic abnormality monitoring device and electronic equipment, and relates to the technical field of unmanned aerial vehicle safety. The method for monitoring the logic abnormality of the chip comprises the following steps: firstly, acquiring operation information of a target chip in each operation period, wherein the operation information comprises first input data and first output data. And then, performing inverse operation on the first output data to obtain first reference data corresponding to the first input data. And finally, determining the logic abnormality of the target chip according to the first reference data and the first input data. Through the technical scheme, the execution logic of the chip inside the unmanned aerial vehicle can be monitored, logic abnormality of the chip can be found in time, and flight safety of the unmanned aerial vehicle is guaranteed.
Description
[ field of technology ]
The application relates to the technical field of unmanned aerial vehicle safety, in particular to a chip logic abnormality monitoring method, a device and electronic equipment.
[ background Art ]
In recent years, unmanned aerial vehicles are paid attention to due to the characteristics of small size, high flexibility, low cost, easiness in maintenance and the like, and are increasingly widely applied to the fields of express delivery, fire protection security, power grid security inspection, homeland resource survey and the like. The flight safety of the unmanned aerial vehicle is inseparable from the reliability of the chip. Therefore, the execution logic of each chip in the unmanned aerial vehicle is required to be monitored, so that logic abnormality of the chip can be found in time, and the flight safety of the unmanned aerial vehicle is ensured.
[ application ]
The embodiment of the application provides a chip logic abnormality monitoring method, device and electronic equipment, which are used for monitoring execution logic of an internal chip of an unmanned aerial vehicle and timely finding out logic abnormality of the chip.
In a first aspect, an embodiment of the present application provides a method for monitoring logic anomalies of a chip, including: acquiring operation information of a target chip in each operation period, wherein the operation information comprises first input data and first output data; performing inverse operation on the first output data to obtain first reference data corresponding to the first input data; and determining the logic abnormality of the target chip according to the first reference data and the first input data.
In one possible implementation manner, the operation information further includes algorithm information; performing inverse operation on the first output data to obtain first reference data corresponding to the first input data, where the first reference data includes: determining a reverse algorithm corresponding to a control algorithm of the target chip according to the algorithm information; and performing inverse operation on the first output data by using the inverse algorithm to obtain first reference data corresponding to the first input data.
In one possible implementation manner, determining the logic exception of the target chip according to the first reference data and the first input data includes: calculating a difference between the first reference data and the first input data; and detecting that the difference value is larger than a set threshold value, and determining that the target chip is logically abnormal.
In one possible implementation manner, the detecting that the difference value is greater than a set threshold value, and determining that the target chip is logically abnormal includes: detecting that the difference values are larger than a set threshold value in N continuous operation periods, and determining that the logic of the target chip is abnormal; wherein N is an integer greater than 1.
In one possible implementation manner, the number of the first input data is a plurality; detecting that the difference is greater than a set threshold, determining that the target chip is logically abnormal includes: and detecting that the difference value between at least one first input data and the corresponding first reference data is larger than a set threshold value, and determining that the logic of the target chip is abnormal.
In one possible implementation manner, after determining that the target chip is logically abnormal, the method further includes: generating alarm prompt information and/or opening the parachute.
In a second aspect, an embodiment of the present application provides a device for monitoring logic abnormality of a chip, where the device includes: the acquisition module is used for acquiring operation information of the target chip in each operation period, wherein the operation information comprises first input data and first output data; the calculation module is used for carrying out inverse operation on the first output data to obtain first reference data corresponding to the first input data; and the determining module is used for determining the logic abnormality of the target chip according to the first reference data and the first input data.
In one possible implementation manner, the operation information further includes algorithm information; the computing module is specifically configured to: determining a reverse algorithm corresponding to a control algorithm of the target chip according to the algorithm information; and performing inverse operation on the first output data by using the inverse algorithm to obtain first reference data corresponding to the first input data.
In one possible implementation manner, the determining module is specifically configured to calculate a difference value between the first reference data and the first input data; and detecting that the difference value is larger than a set threshold value, and determining that the target chip is logically abnormal.
In one possible implementation manner, the determining module is specifically configured to determine that the difference values in the N continuous operation periods are all greater than a set threshold value, and determine that the logic of the target chip is abnormal; wherein N is an integer greater than 1.
In one possible implementation manner, the number of the first input data is a plurality; the determining module is specifically configured to determine that the target chip logic abnormality is determined when detecting that a difference between at least one first input data and a corresponding first reference data is greater than a set threshold.
In one possible implementation manner, the apparatus further includes: and the execution module is used for generating alarm prompt information and/or opening the parachute after the determination module determines that the logic of the target chip is abnormal.
In a third aspect, an embodiment of the present application provides an electronic device, including: at least one processor; and at least one memory communicatively coupled to the processor, wherein: the memory stores program instructions executable by the processor, the processor invoking the program instructions capable of performing the method according to the first aspect.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium storing computer instructions that cause a computer to perform the method of the first aspect.
Through the technical scheme, the execution logic of the chip inside the unmanned aerial vehicle can be monitored, logic abnormality of the chip can be found in time, and flight safety of the unmanned aerial vehicle is guaranteed.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for monitoring logic anomalies of a chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a method for monitoring logic anomalies of a chip according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another method for monitoring logic anomalies of a chip according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a device for monitoring logic abnormality of a chip according to an embodiment of the present application;
fig. 5 is a schematic diagram of an electronic device according to an embodiment of the present application.
[ detailed description ] of the application
For a better understanding of the technical solution of the present application, the following detailed description of the embodiments of the present application refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The application can provide a chip logic abnormality monitoring system which can be deployed in any model of unmanned aerial vehicle. The system provided by the application can be used for executing the chip logic abnormality monitoring method provided by the application, so that the monitoring of the execution logic of each chip in the unmanned aerial vehicle is realized.
In practical application, different chips have different functional security levels. The higher the functional security level, the better the reliability of the chip and the lower the probability of logic anomalies. Therefore, in the application, in order to save the computing resource, the chip with the internal function safety level of the unmanned aerial vehicle not exceeding the level threshold can be monitored. The value of the grade threshold can be flexibly set according to the requirements.
Furthermore, based on the principle of the chip logic abnormality monitoring method provided by the application, the chip to be monitored also has the following characteristics: the forward and reverse solutions of the chip's own control algorithm are the same.
In the present application, a chip that satisfies the above conditions inside the unmanned aerial vehicle is referred to as a target chip. The target chip may be any function execution chip of the unmanned aerial vehicle, which is not limited in the present application. In the case that the number of the target chips is a plurality of, the monitoring method of each target chip is the same.
For convenience of description and understanding, the method for monitoring logic abnormality of a chip provided by the present application will be described below by taking any one of target chips as an example.
Fig. 1 is a flowchart of a method for monitoring logic abnormality of a chip according to an embodiment of the present application. As shown in fig. 1, the method for monitoring logic anomaly of a chip may include:
step 101, obtaining operation information of a target chip in each operation period, wherein the operation information comprises first input data and first output data.
In the embodiment of the application, one operation flow of the target chip to the data is called an operation period. Wherein each operation period corresponds to a set of operation information. Each set of operation information may include first input data, first output data, and algorithm information. Wherein the algorithm information may be used to characterize the control algorithm applied by the target chip. The number of the first input data and the first output data may be one or a plurality of the first input data and the first output data based on the difference of the control algorithms.
Step 102, performing inverse operation on the first output data to obtain first reference data corresponding to the first input data.
In the embodiment of the application, the chip logic abnormality monitoring system can be pre-stored with an algorithm mapping relation. The algorithm mapping relationship may include algorithm information of each target chip and corresponding inverse algorithm information.
After the operation information of the target chip is obtained, the inverse algorithm corresponding to the control algorithm of the target chip can be determined according to the algorithm information contained in the operation information. Specifically, the mapping relation of the algorithm can be queried according to the algorithm information, and the reverse algorithm corresponding to the control algorithm can be determined. Then, the inverse algorithm can be utilized to perform inverse operation on the first output data, so as to obtain first reference data corresponding to the first input data.
Step 103, determining the logic exception of the target chip according to the first reference data and the first input data.
Because the control algorithm of the target chip has the same characteristics of forward solution and reverse solution, under the condition that the logic of the target chip is normal and the calculation of the first output data is correct, the first reference data obtained by performing inverse operation on the first output data should be consistent with the first input data.
Based on the above description, in the embodiment of the present application, the logic exception of the target chip may be determined according to the first reference data and the first input data.
Specifically, a difference between the first reference data and the first input data may be calculated. If the obtained difference value is larger than the set threshold value, the deviation between the forward solution and the reverse solution is larger, and the calculation of the first output data by the target chip is wrong. At this time, the target chip logic exception may be determined. When the number of the first input data is plural, the logic abnormality of the target chip may be determined when the difference between at least one of the first input data and the corresponding first reference data is greater than the set threshold. Under the condition that the precision of the target chip tends to ideal precision, the value of the set threshold value is infinitely close to 0.
Further, in consideration of possible noise interference, an error may exist in performing abnormality determination on the chip logic only according to a single operation process of the target chip. Therefore, in another implementation, the difference between the first reference data and the first input data of the target chip can be determined in N consecutive operation periods. And when detecting that the difference values in the N continuous operation periods are all larger than the set threshold value, determining that the logic of the target chip is abnormal. Where N is an integer greater than 1, for example, it may be 5.
In yet another implementation, statistics may be performed on the number of times the difference is greater than a set threshold for a set period of time. If the accumulated times of the difference value larger than the set threshold value exceeds the times threshold in the set time period, the logic abnormality of the target chip can be determined. The values of the time threshold and the time threshold in the set time period can be flexibly set according to experience.
Further, after determining that the logic of the target chip is abnormal, in order to avoid safety accidents such as crash and the like of the unmanned aerial vehicle caused by the logic abnormality of the target chip, any one or a combination of the following emergency measures can be executed:
in one implementation, an alert prompt may be generated. The alarm prompt information can be used for prompting logic abnormality of the target chip. The alarm prompt information can be an audio prompt information and/or an indicator light prompt information and the like.
In another implementation, after determining that the logic of the target chip is abnormal, the parachute can be opened, so that safety guarantee is provided for the unmanned aerial vehicle.
In still another implementation manner, after determining that the logic of the target chip is abnormal, degradation of the corresponding function executed by the unmanned aerial vehicle can be controlled according to the function corresponding to the target chip. For example, when the function corresponding to the target chip is the control of the rotating speed of the propeller a, if the logic abnormality of the target chip is determined, the number of the propellers can be degraded, and the propeller a is controlled to stop running.
Through the technical scheme, the execution logic of the chip in the unmanned aerial vehicle can be monitored, and logic abnormality of the chip can be found in time. Meanwhile, under the condition that the logic abnormality of the chip is determined, emergency measures can be timely taken, so that the flight safety of the unmanned aerial vehicle is guaranteed. In addition, the method provided by the embodiment of the application has high operation efficiency and less occupation of calculation resources.
For convenience of understanding, in another embodiment of the present application, a specific example is used to describe the method for monitoring logic abnormality of a chip provided by the present application.
In one example, a rotational speed control chip having a target chip as a propeller is described as an example.
First, first input data, first output data and algorithm information of a rotating speed control chip of the propeller in each operation period can be obtained. Specifically, for a rotational speed control chip of the propeller, the first input data includes a desired torque and a desired tension; the first output data is the rotating speed of the propeller; the algorithm information is information of a rotation speed control algorithm. The desired moment and the desired pulling force are moment and pulling force required by the propeller under the current flight target respectively. The rotational speed of the propeller (i.e. the first output data) is the rotational speed required to achieve the desired torque and the desired pull.
Then, according to the information of the rotating speed control algorithm, a reverse algorithm of the rotating speed control algorithm can be determined, and the rotating speed of the propeller is reversely calculated by using the reverse algorithm, so that the reference moment and the reference tension are obtained.
Finally, the rotational speed control chip can be diagnosed according to the first difference value of the expected torque and the reference torque and the second difference value of the expected tension and the reference tension. It can be understood that, under the condition that the rotation speed control chip is logically normal, the reference torque obtained by performing inverse operation on the rotation speed of the propeller should be equal to the expected torque, and the obtained reference tension should be equal to the expected tension. Therefore, when the first difference is greater than the set threshold and/or the second difference is greater than the set threshold, the abnormal logic of the rotational speed control chip can be determined.
In another example, a motor control chip in which a target chip is a propeller is described as an example.
First, first input data, first output data and algorithm information of a motor control chip of the propeller in each operation period can be obtained. Specifically, as shown in fig. 2, for the motor control chip of the propeller, the first input data includes three-phase stationary current I 1 、I 2 、I 3 The method comprises the steps of carrying out a first treatment on the surface of the The first output data includes current I a 、I b The method comprises the steps of carrying out a first treatment on the surface of the The algorithm information is information of a motor control algorithm.
The inverse of the motor control algorithm may then be determined based on the information of the motor control algorithm. Further, as shown in FIG. 3, the current I may be controlled by a reverse motor control algorithm a 、I b Performing inverse operation to obtain reference three-phase stationary current I 1 ′、I 2 ′、I 3 ′。
Finally, according to the three-phase stationary current I 1 、I 2 、I 3 Reference three-phase quiescent current I 1 ′、I 2 ′、I 3 ' the rotational speed control chip is diagnosed. When I 1 And I 1 ' the difference is greater than a set threshold, and/or I 2 And I 2 ' the difference is greater than a set threshold, and/or I 3 And I 3 If the difference value is larger than the set threshold value, the logic abnormality of the rotating speed control chip can be determined.
The above description of two chip types is intended as an example only and should not be taken as limiting the embodiments of the present application. In the practical application process, the target chip can also be other functional chips of the unmanned aerial vehicle.
Fig. 4 is a schematic structural diagram of a device for monitoring logic abnormality of a chip according to an embodiment of the present application. As shown in fig. 4, the device for monitoring logic abnormality of a chip provided in the embodiment of the present application may include: an acquisition module 41, a calculation module 42 and a determination module 43.
The acquiring module 41 is configured to acquire operation information of the target chip in each operation period, where the operation information includes first input data and first output data.
The calculation module 42 is configured to perform an inverse operation on the first output data, so as to obtain first reference data corresponding to the first input data.
The determining module 43 is configured to determine a logic anomaly of the target chip according to the first reference data and the first input data.
In a specific implementation process, the operation information further includes algorithm information; the calculation module 42 is specifically configured to: determining a reverse algorithm corresponding to a control algorithm of the target chip according to the algorithm information; and performing inverse operation on the first output data by using an inverse algorithm to obtain first reference data corresponding to the first input data.
In a specific implementation, the determining module 43 is specifically configured to calculate a difference between the first reference data and the first input data; and determining that the logic abnormality of the target chip is determined by detecting that the difference value is larger than the set threshold value.
In a specific implementation process, the determining module 43 is specifically configured to determine that the difference values in N consecutive operation periods are all greater than a set threshold, and determine that the logic of the target chip is abnormal; wherein N is an integer greater than 1.
In a specific implementation, the number of the first input data is a plurality; the determining module 43 is specifically configured to determine that the target chip logic abnormality is determined when detecting that the difference between at least one first input data and the corresponding first reference data is greater than a set threshold.
In a specific implementation, the apparatus further includes: and the execution module 44 is used for generating alarm prompt information and/or opening the parachute after the determination module 43 determines that the logic of the target chip is abnormal.
Through the technical scheme, the execution logic of the chip inside the unmanned aerial vehicle can be monitored, logic abnormality of the chip can be found in time, and flight safety of the unmanned aerial vehicle is guaranteed.
Fig. 5 is a schematic diagram of an electronic device according to an embodiment of the present application, where, as shown in fig. 5, the electronic device may include at least one processor; and at least one memory communicatively coupled to the processor, wherein: the memory stores program instructions executable by the processor, and the processor calls the program instructions to execute the chip logic abnormality monitoring method provided by the embodiment of the application.
The electronic device may be a chip logic abnormality monitoring device, and the specific form of the electronic device is not limited in this embodiment.
Fig. 5 shows a block diagram of an exemplary electronic device suitable for use in implementing embodiments of the application. The electronic device shown in fig. 5 is only an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present application.
As shown in fig. 5, the electronic device is in the form of a general purpose computing device. Components of an electronic device may include, but are not limited to: one or more processors 410, a memory 430, a communication interface 420, and a communication bus 440 that connects the various system components, including the memory 430 and the processor 410.
The communication bus 440 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include industry Standard architecture (Industry Standard Architecture; hereinafter ISA) bus, micro channel architecture (Micro Channel Architecture; hereinafter MAC) bus, enhanced ISA bus, video electronics standards Association (Video Electronics Standards Association; hereinafter VESA) local bus, and peripheral component interconnect (Peripheral Component Interconnection; hereinafter PCI) bus.
Electronic devices typically include a variety of computer system readable media. Such media can be any available media that can be accessed by the electronic device and includes both volatile and nonvolatile media, removable and non-removable media.
Memory 430 may include computer system readable media in the form of volatile memory, such as random access memory (Random Access Memory; hereinafter: RAM) and/or cache memory. The electronic device may further include other removable/non-removable, volatile/nonvolatile computer system storage media. Although not shown in fig. 5, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a compact disk read only memory (Compact Disc Read Only Memory; hereinafter CD-ROM), digital versatile read only optical disk (Digital Video Disc Read Only Memory; hereinafter DVD-ROM), or other optical media) may be provided. In such cases, each drive may be coupled to communication bus 440 by one or more data medium interfaces. Memory 430 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the embodiments of the application.
A program/utility having a set (at least one) of program modules may be stored in the memory 430, such program modules including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules typically carry out the functions and/or methods of the embodiments described herein.
The electronic device may also communicate with one or more external devices (e.g., keyboard, pointing device, display, etc.), with one or more devices that enable a user to interact with the electronic device, and/or with any device (e.g., network card, modem, etc.) that enables the electronic device to communicate with one or more other computing devices. Such communication may occur through communication interface 420. Moreover, the electronic device may also communicate with one or more networks (e.g., local area network (Local Area Network; hereinafter: LAN), wide area network (Wide Area Network; hereinafter: WAN) and/or a public network, such as the Internet) via a network adapter (not shown in FIG. 5) that may communicate with other modules of the electronic device via the communication bus 440. It should be appreciated that although not shown in fig. 5, other hardware and/or software modules may be used in connection with an electronic device, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, disk arrays (Redundant Arrays of Independent Drives; hereinafter RAID) systems, tape drives, data backup storage systems, and the like.
The processor 410 executes various functional applications and data processing by running programs stored in the memory 430, for example, to implement the method for monitoring chip logic anomalies provided by the embodiment of the present application.
The embodiment of the application also provides a computer readable storage medium, which stores computer instructions for causing the computer to execute the chip logic anomaly monitoring method provided by the embodiment of the application.
Any combination of one or more computer readable media may be utilized as the above-described computer readable storage media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory; EPROM) or flash Memory, an optical fiber, a portable compact disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (Local Area Network; hereinafter: LAN) or a wide area network (Wide Area Network; hereinafter: WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order from that shown or discussed, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.
Claims (10)
1. The method for monitoring the logic abnormality of the chip is characterized by comprising the following steps of:
acquiring operation information of a target chip in each operation period, wherein the operation information comprises first input data and first output data;
performing inverse operation on the first output data to obtain first reference data corresponding to the first input data;
and determining the logic abnormality of the target chip according to the first reference data and the first input data.
2. The method of claim 1, wherein the operational information further comprises algorithm information; performing inverse operation on the first output data to obtain first reference data corresponding to the first input data, where the first reference data includes:
determining a reverse algorithm corresponding to a control algorithm of the target chip according to the algorithm information;
and performing inverse operation on the first output data by using the inverse algorithm to obtain first reference data corresponding to the first input data.
3. The method of claim 1, wherein determining the target chip logic anomaly from the first reference data and the first input data comprises:
calculating a difference between the first reference data and the first input data;
and detecting that the difference value is larger than a set threshold value, and determining that the target chip is logically abnormal.
4. The method of claim 3, wherein detecting that the difference is greater than a set threshold, determining that the target chip is logically abnormal comprises:
detecting that the difference values are larger than a set threshold value in N continuous operation periods, and determining that the logic of the target chip is abnormal;
wherein N is an integer greater than 1.
5. A method according to claim 3, wherein the first input data is a plurality of; detecting that the difference is greater than a set threshold, determining that the target chip is logically abnormal includes:
and detecting that the difference value between at least one first input data and the corresponding first reference data is larger than a set threshold value, and determining that the logic of the target chip is abnormal.
6. The method of claim 1, wherein after determining the target chip logic exception, the method further comprises:
generating alarm prompt information and/or opening the parachute.
7. A chip logic anomaly monitoring device, comprising:
the acquisition module is used for acquiring operation information of the target chip in each operation period, wherein the operation information comprises first input data and first output data;
the calculation module is used for carrying out inverse operation on the first output data to obtain first reference data corresponding to the first input data;
and the determining module is used for determining the logic abnormality of the target chip according to the first reference data and the first input data.
8. The apparatus of claim 7, wherein the apparatus further comprises:
and the execution module is used for generating alarm prompt information and/or opening the parachute after the determination module determines that the logic of the target chip is abnormal.
9. An electronic device, comprising:
at least one processor; and
at least one memory communicatively coupled to the processor, wherein:
the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the method of any of claims 1-6.
10. A computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1 to 6.
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| CN202210442264.7A CN116991653A (en) | 2022-04-25 | 2022-04-25 | Chip logic abnormality monitoring method and device and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117457583A (en) * | 2023-12-21 | 2024-01-26 | 北京智芯微电子科技有限公司 | Microparticle device, chip, electronic equipment, chip protection method, device and medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117457583A (en) * | 2023-12-21 | 2024-01-26 | 北京智芯微电子科技有限公司 | Microparticle device, chip, electronic equipment, chip protection method, device and medium |
| CN117457583B (en) * | 2023-12-21 | 2024-03-08 | 北京智芯微电子科技有限公司 | Microparticle device, chip, electronic equipment, chip protection method, device and medium |
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