CN116991320A - Three-dimensional flash memory data transmission delay optimization method, system, equipment and storage medium - Google Patents
Three-dimensional flash memory data transmission delay optimization method, system, equipment and storage medium Download PDFInfo
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- CN116991320A CN116991320A CN202310961407.XA CN202310961407A CN116991320A CN 116991320 A CN116991320 A CN 116991320A CN 202310961407 A CN202310961407 A CN 202310961407A CN 116991320 A CN116991320 A CN 116991320A
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000005457 optimization Methods 0.000 title claims description 20
- 238000013144 data compression Methods 0.000 claims abstract description 12
- 238000004590 computer program Methods 0.000 claims abstract description 9
- 230000005055 memory storage Effects 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1032—Simple parity
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides a method, a system, equipment and a storage medium for optimizing data transmission delay of a three-dimensional flash memory, which comprise the following steps: responding to a read request command sent by a host end, outputting a read execution command, wherein the read execution command is used for enabling a read voltage application module to apply read voltage to a corresponding flash memory page of a corresponding three-dimensional flash memory block so as to acquire target data; receiving target data compressed by a data compression module, decompressing and decoding the received data for error correction; and transmitting the decoded and error-corrected data to a host side. The system comprises functional modules which correspondingly realize the steps. Electronic equipment: the processor implements the method when executing the computer program stored in the memory. The storage medium stores a computer program that when executed by a processor performs a method. According to the invention, the problem that the data transmission load and the transmission delay are increased due to the large data volume of the data transmission in the existing three-dimensional flash memory storage system, so that the three-dimensional flash reading performance is affected can be solved.
Description
Technical Field
The invention belongs to the technical field of solid-state disk storage, and particularly relates to a method, a system, equipment and a storage medium for optimizing data transmission delay of a three-dimensional flash memory.
Background
The three-dimensional flash memory improves the storage capacity by increasing the number of storage layers, but the data stored in each unit is easily affected by factors such as interlayer interference and the like to cause the reduction of reliability, the number of bit errors is increased along with the increase of the storage density of the unit, the data in the storage unit needs to be read for a plurality of times in order to reduce the bit errors and improve the reliability, the result of the plurality of times of reading needs to be transmitted through a plurality of times of data, however, the transmission time delay is directly related to the reading times, and the data delay is greatly reduced in the reading performance of the three-dimensional flash memory storage system along with the increase of the reading times.
The data transmission delay is affected by the interface speed and the data quantity of each transmission besides the influence of the reading times, the data transmission operation of the existing three-dimensional flash memory is to directly transmit the result of each reading, the data quantity of each transmission is large, the burden of a transmission interface and the transmission delay are increased, and the reading performance of the three-dimensional flash memory storage system is not facilitated.
Disclosure of Invention
The invention aims to solve the problem that the data transmission load and the transmission delay are increased due to the large data quantity transmitted each time in the existing data transmission mode of the three-dimensional flash memory storage system, so that the reading performance of the three-dimensional flash memory storage system is affected.
In order to achieve the above object, the present invention provides a method, a system, a device and a storage medium for optimizing data transmission delay of a three-dimensional flash memory.
According to a first aspect of the present invention, there is provided a method for optimizing data transfer delay of a three-dimensional flash memory, comprising:
responding to a read request command sent by a host end, outputting a read execution command, wherein the read execution command is used for enabling a read voltage application module to apply read voltage to a corresponding flash memory page of a corresponding three-dimensional flash memory block so as to acquire target data;
receiving the target data compressed by the data compression module, decompressing and decoding the received data for error correction;
and transmitting the decoded and corrected data to the host side.
Alternatively, the flash page type to which the read voltage is applied includes high, middle and low pages, and the flash page has a size of 18KB.
Optionally, the data reading mode of the read voltage applying module on the flash memory page is sequential reading or random reading.
Alternatively, the read voltage applying module applies different numbers of read voltages for three flash memory page types, respectively.
Alternatively, the read voltage applied to the flash memory page is a hard read voltage or a soft read voltage.
Alternatively, the decoding algorithm used in the decoding error correction operation is a low density parity check code error correction algorithm.
According to a second aspect of the present invention, there is provided a three-dimensional flash memory data transmission delay optimization system, including a control module, a read voltage applying module, and a data compression module;
the control module is used for responding to a read request command sent by a host end and outputting a read execution command, the read execution command is used for enabling the read voltage applying module to apply read voltage to corresponding flash memory pages of corresponding three-dimensional flash memory blocks so as to acquire target data,
receiving the target data compressed by the data compression module, decompressing and decoding the received data for error correction,
and transmitting the decoded and corrected data to the host side.
According to a third aspect of the present invention, there is provided an electronic device comprising a processor and a memory, the processor implementing any one of the above-mentioned three-dimensional flash data transfer delay optimization methods when executing a computer program stored in the memory.
According to a fourth aspect of the present invention, there is provided a computer readable storage medium storing a computer program which, when executed by a processor, implements any one of the above three-dimensional flash memory data transfer delay optimization methods.
The invention has the beneficial effects that:
according to the three-dimensional flash memory data transmission delay optimization method, a read execution instruction is output in response to a read request command sent by a host end, and the read execution instruction is used for enabling a read voltage application module to apply read voltages to corresponding flash memory pages of corresponding three-dimensional flash memory blocks so as to obtain target data; receiving target data compressed by a data compression module, decompressing and decoding the received data for error correction; and transmitting the decoded and error-corrected data to a host side.
According to the invention, the target data quantity required to be transmitted after each time of reading the corresponding flash memory page is reduced to reduce transmission delay, the corresponding flash memory page is read through the reading execution instruction to obtain the target data, and then the result of each time of reading is compressed during transmission to reduce the data quantity of each time of transmission, so that the transmission pressure of a transmission interface is relieved, the purpose of reducing the transmission delay is achieved, the problem of high transmission delay caused by the existing data transmission operation is solved, and the reading performance of the three-dimensional flash memory storage system is improved.
The original data is recovered by decompressing and decoding the compressed target data for error correction, so that the problem that the compressed target data is possibly interfered by noise to generate errors is avoided, and the stability of data transmission is improved.
The three-dimensional flash memory data transmission delay optimizing system, the electronic equipment and the computer readable storage medium and the three-dimensional flash memory data transmission delay optimizing method belong to a general inventive concept, at least have the same beneficial effects as the three-dimensional flash memory data transmission delay optimizing method, and the beneficial effects are not repeated here.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The invention may be better understood by referring to the following description in conjunction with the accompanying drawings in which the same or similar reference numerals are used throughout the several drawings to designate the same or similar components.
FIG. 1 illustrates a flow chart of an implementation of a three-dimensional flash data transfer delay optimization method according to an embodiment of the invention;
fig. 2 shows a block diagram of a three-dimensional flash data transfer delay optimization system according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will more fully understand the technical solutions of the present invention, exemplary embodiments of the present invention will be described more fully and in detail below with reference to the accompanying drawings. It should be apparent that the following description of one or more embodiments of the invention is merely one or more of the specific ways in which the technical solutions of the invention may be implemented and is not intended to be exhaustive. It should be understood that the technical solution of the present invention may be implemented in other ways belonging to one general inventive concept, and should not be limited by the exemplary described embodiments. All other embodiments, which may be made by one or more embodiments of the invention without inventive faculty, are intended to be within the scope of the invention.
Examples: fig. 1 shows a flowchart of an implementation of a three-dimensional flash data transfer delay optimization method according to an embodiment of the present invention.
Referring to fig. 1, the method for optimizing data transmission delay of a three-dimensional flash memory according to an embodiment of the present invention includes:
responding to a read request command sent by a host end, outputting a read execution command, wherein the read execution command is used for enabling a read voltage application module to apply read voltage to a corresponding flash memory page of a corresponding three-dimensional flash memory block so as to acquire target data;
receiving target data compressed by a data compression module, decompressing and decoding the received data for error correction;
and transmitting the decoded and error-corrected data to a host side.
In particular, the three-dimensional flash memory data transmission delay optimizing method of the embodiment of the invention,
firstly, reading whole page data through reading voltage applied to a three-dimensional flash memory page, compressing the read data, transmitting the compressed data to a controller through an interface, decompressing the transmitted data, transmitting the decompressed data to a decoder for decoding and error correction, transmitting the decoded data to a host through the interface, and directly reducing data transmission delay by compressing the data quantity to be transmitted, so that the problem of high transmission delay caused by the existing data transmission operation can be solved. The compressed bit stream data is subject to noise interference and error, the original data is recovered by decompressing the data and decoding and correcting errors in the controller, the error rate of the dead data is increased, and the stability of data transmission is improved.
Specifically, in the embodiment of the invention, the length of the target data compressed by the data compression module depends on the compression algorithm and the data type, wherein the image data is easier to compress, and the compression effect is more obvious.
Further, in the embodiment of the present invention, the flash memory page type to which the read voltage is applied includes high, middle and low pages, and the flash memory page has a size of 18KB.
Still further, in the embodiment of the present invention, the data reading mode of the flash memory page by the reading voltage applying module is sequential reading or random reading.
Still further, in the embodiment of the present invention, the read voltage applying module applies different numbers of read voltages to the three flash memory page types, respectively.
Still further, in the embodiment of the present invention, the read voltage applied to the flash memory page is a hard read voltage or a soft read voltage.
Specifically, in the embodiment of the present invention, the hard read voltage or the soft read voltage is applied to the three flash page types respectively, depending on the number of bit errors of the three-dimensional flash page.
Still further, in the embodiment of the present invention, the decoding algorithm used in the decoding error correction operation is a low density parity check code error correction algorithm.
Correspondingly, on the basis of the three-dimensional flash memory data transmission delay optimization method, the embodiment of the invention also provides a three-dimensional flash memory data transmission delay optimization system.
Fig. 2 shows a block diagram of a three-dimensional flash data transfer delay optimization system according to an embodiment of the present invention. Referring to fig. 2, the three-dimensional flash memory data transmission delay optimization system according to an embodiment of the present invention includes a control module, a read voltage applying module, and a data compression module;
the control module is used for responding to a read request command sent by the host end, outputting a read execution command which is used for enabling the read voltage applying module to apply read voltage to the corresponding flash memory pages of the corresponding three-dimensional flash memory block so as to acquire target data,
receiving the target data compressed by the data compression module, decompressing, decoding and correcting the received data,
and transmitting the decoded and error-corrected data to a host side.
Correspondingly, on the basis of the three-dimensional flash memory data transmission delay optimization method of the embodiment of the invention, the embodiment of the invention also provides electronic equipment which comprises a processor and a memory, wherein the processor realizes any one of the three-dimensional flash memory data transmission delay optimization methods when executing a computer program stored in the memory.
Accordingly, on the basis of the three-dimensional flash memory data transmission delay optimization method of the embodiment of the invention, the embodiment of the invention provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program realizes any one of the three-dimensional flash memory data transmission delay optimization methods when being executed by a processor.
Although one or more embodiments of the present invention have been described above, it will be appreciated by those of ordinary skill in the art that the invention can be embodied in any other form without departing from the spirit or scope thereof. The above-described embodiments are therefore intended to be illustrative rather than limiting, and many modifications and substitutions will now be apparent to those of ordinary skill in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (9)
1. The data transmission delay optimization method for the three-dimensional flash memory is characterized by comprising the following steps of:
responding to a read request command sent by a host end, outputting a read execution command, wherein the read execution command is used for enabling a read voltage application module to apply read voltage to a corresponding flash memory page of a corresponding three-dimensional flash memory block so as to acquire target data;
receiving the target data compressed by the data compression module, decompressing and decoding the received data for error correction;
and transmitting the decoded and corrected data to the host side.
2. The method of claim 1, wherein the flash page type to which the read voltage is applied includes high, medium and low pages, and the flash page has a size of 18KB.
3. The method for optimizing data transmission delay of three-dimensional flash memory according to claim 2, wherein the data reading mode of the flash memory page by the read voltage application module is sequential reading or random reading.
4. The method of claim 2, wherein the read voltage applying module applies different numbers of read voltages to each of the three flash page types.
5. The method of claim 4, wherein the read voltage applied to the flash memory page is a hard read voltage or a soft read voltage.
6. The method according to claim 1, wherein the decoding algorithm used in the decoding error correction operation is a low density parity check code error correction algorithm.
7. The three-dimensional flash memory data transmission delay optimizing system is characterized by comprising a control module, a read voltage applying module and a data compression module;
the control module is used for responding to a read request command sent by a host end and outputting a read execution command, the read execution command is used for enabling the read voltage applying module to apply read voltage to corresponding flash memory pages of corresponding three-dimensional flash memory blocks so as to acquire target data,
receiving the target data compressed by the data compression module, decompressing and decoding the received data for error correction,
and transmitting the decoded and corrected data to the host side.
8. An electronic device comprising a processor and a memory, wherein the processor implements the three-dimensional flash data transfer delay optimization method of any one of claims 1-6 when executing a computer program stored in the memory.
9. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program which, when executed by a processor, implements the three-dimensional flash data transfer delay optimization method of any one of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310961407.XA CN116991320A (en) | 2023-08-01 | 2023-08-01 | Three-dimensional flash memory data transmission delay optimization method, system, equipment and storage medium |
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| CN202310961407.XA CN116991320A (en) | 2023-08-01 | 2023-08-01 | Three-dimensional flash memory data transmission delay optimization method, system, equipment and storage medium |
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| CN116991320A true CN116991320A (en) | 2023-11-03 |
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| CN202310961407.XA Pending CN116991320A (en) | 2023-08-01 | 2023-08-01 | Three-dimensional flash memory data transmission delay optimization method, system, equipment and storage medium |
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| CN (1) | CN116991320A (en) |
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