CN116991306A - Processing method of storage device, storage device and computer readable storage device - Google Patents
Processing method of storage device, storage device and computer readable storage device Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
- G06F3/0623—Securing storage systems in relation to content
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The application discloses a processing method of a storage device, which comprises the following steps: determining the quality of a storage block in a storage device; if all the storage blocks with the same physical number are good storage blocks, binding all the good storage blocks with the same physical number to form a binding storage block; and combining the remaining good storage blocks except the binding storage blocks of the storage device to form a combined storage block. The application also discloses a storage device and a computer readable storage device. By the mode, the storage device can increase the available capacity of the storage device product and improve the yield of mass production.
Description
Technical Field
The present application relates to the field of storage, and in particular, to a storage device processing method, a storage device, and a computer readable storage device.
Background
In a storage device applying FLASH, in order to improve the service performance of the storage device, multiple technologies are obtained by using FLASH storage, and physical blocks of multiple FLASH are combined together to form a large bound logic block for use. In general, physical blocks with the same physical block number in different planes are bound into one logical block under different CEs or the same CE, for example, four physical blocks of CE0plane 0 block2, CE0plane1 block2, CE1 plane0 block2, CE1 plane1 block2 are bound into a logical block2 for use. In the production of the storage device, the physical blocks are inevitably damaged, and when the logic blocks are bound, if the physical blocks with the same physical block number are damaged, the physical blocks corresponding to the physical block number cannot be bound into the logic blocks for use, and a stack of scattered available physical blocks is left. The scattered available physical blocks which can not be bound for use reduce the available capacity of the FLASH product, and the original qualified storage product is changed into a defective product with the available capacity which does not meet the requirement.
Disclosure of Invention
The application mainly aims to provide a processing method of a storage device, the storage device and a computer readable storage device, which can solve the technical problem of available capacity reduction caused by bad blocks in the storage device.
In order to solve the technical problems, the first technical scheme adopted by the application is as follows: there is provided a processing method of a storage device, the method comprising: determining the quality of a storage block in a storage device; if all the storage blocks with the same physical number are good storage blocks, binding all the good storage blocks with the same physical number to form a binding storage block; and combining the remaining good storage blocks except the binding storage blocks of the storage device to form a combined storage block.
In order to solve the technical problems, a second technical scheme adopted by the application is as follows: a storage device is provided. The storage means comprises a memory for storing program data and a processor connected to the memory for implementing the method as described in the first technical solution.
In order to solve the technical problems, a third technical scheme adopted by the application is as follows: a computer readable storage device is provided. The computer readable storage means stores program data executable by a processor to implement the method as described in the first aspect.
The beneficial effects of the application are as follows: different from the prior art, the method and the device determine the good and fast conditions of the storage blocks in the storage device, thereby determining the physical numbers of the bad storage blocks. While other good memory blocks with the same physical number as the bad memory blocks cannot be bound, further the good memory blocks bound into large logical blocks and the good memory blocks not bound can be determined. Good storage blocks which can be bound are bound, and good storage blocks which cannot be bound are combined to form a combined block for use, so that the unusable good storage blocks are changed into usable storage blocks again, the available capacity of the storage device is increased, and the mass production yield of the storage device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a first embodiment of a processing method of a memory device according to the present application;
FIG. 2 is a flow chart of a second embodiment of a processing method of a memory device according to the present application;
FIG. 3 is a schematic diagram of a combined memory block mapping table;
FIG. 4 is a schematic diagram of another configuration of a combined memory block mapping table;
FIG. 5 is a schematic diagram of another embodiment of a combined memory block mapping table;
FIG. 6 is a flowchart of a third embodiment of a processing method of a memory device according to the present application;
FIG. 7 is a flowchart of a processing method of a storage device according to a fourth embodiment of the present application;
FIG. 8 is a schematic diagram of a memory device according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a computer readable storage device according to an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first," "second," and the like in this disclosure are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a flowchart illustrating a processing method of a memory device according to a first embodiment of the present application. Which comprises the following steps:
s11: and determining the quality of the storage blocks in the storage device.
All FLASH physical memory blocks in the memory device are scanned, and whether the data can be read and written or not is determined according to the condition of each physical memory block. And each physical storage block has a corresponding number to indicate the position of the physical storage block, and a bad block table for indicating the position information of the bad physical storage block can be obtained according to the obtained good or bad conditions. Further, a good block table indicating all good physical storage block location information can also be obtained.
S12: if all the storage blocks with the same physical number are good storage blocks, binding all the good storage blocks with the same physical number to form a binding storage block.
And judging the physical numbers of the storage blocks, if all the storage blocks corresponding to a certain physical number are good storage blocks, binding all the storage blocks representing the physical number into a large logic block for use, and binding all the storage blocks under the physical number meeting the requirement to obtain the corresponding large logic block.
S13: and combining the remaining good storage blocks except the binding storage blocks of the storage device to form a combined storage block.
And removing the binding-completed storage blocks from the good block table, leaving good scattered storage blocks which cannot be bound, combining the scattered storage blocks in a new mode for use, completing the full utilization of the available capacity in the storage device, and improving the final available capacity of the storage device.
In an embodiment, the physical number of the bad memory block can be determined through the bad block table, other good memory blocks under the corresponding physical number are determined to be unbound scattered memory blocks, the scattered memory blocks are combined, and the good memory blocks under the other physical numbers are bound correspondingly.
By the embodiment, the good and fast conditions of the storage blocks in the storage device are determined, so that the physical number of the bad storage block is determined, and further the good storage blocks which are bound into large logic blocks and the good storage blocks which cannot be bound can be determined. Good storage blocks which can be bound are bound, and good storage blocks which cannot be bound are combined to form a combined block for use, so that the unusable good storage blocks are changed into usable storage blocks again, the available capacity of the storage device is increased, and the mass production yield of the storage device is improved.
Referring to fig. 2, fig. 2 is a flowchart illustrating a processing method of a memory device according to a second embodiment of the application. This method is a further extension of the above embodiments. Which comprises the following steps:
s21: a logical block table of bound memory blocks is generated.
And for the binding storage blocks generated by binding, the mapping relation between the binding storage blocks and each physical storage block is represented by a corresponding mapping table. The physical memory blocks typically have a wafer number, a plane number, and a physical number. The wafer number indicates what wafer the physical memory block is located on, the plane number indicates what plane the physical memory block is located on in the wafer, and the physical number further indicates what memory block the physical memory block is located under. The logical number of the binding storage block is the same as the physical number of the binding storage block. For example, taking two wafers as an example, the logical number of a binding memory block formed by binding memory blocks of CE0plane 0 block2, CE0plane1 block2, CE1 plane0 block2 and CE1 plane1 block2 is 2, and the physical number corresponding to the four memory blocks is the same.
S22: a combined block table of combined memory blocks is generated.
Similarly, for a combined memory block generated by combining, a mapping table is required to represent its corresponding mapping relationship. And because the physical numbers of the storage blocks in the combined storage block are different, a common physical number is introduced for the mapping relation of the combined storage block.
In one embodiment, the logical number of the combined memory block is the same as the common physical number of the combined memory block.
In one embodiment, the logical number of the combined memory block may be incremented immediately after the logical number of the largest bound memory block. For example, the logical number of the largest bound memory block is 100, the logical number of the first combined memory block is 101, the logical number of the second combined memory block is 102, and so on.
In an embodiment, the logical numbers of the combined memory blocks may be arbitrarily set, without any association between each other, as long as they can be distinguished from the logical numbers of the bound memory blocks.
S23: and determining the target storage block according to the received operation command, the logic block table and the combined block table.
The logic number of the binding storage block is different from the logic number of the combination storage block, so that the logic number in the logic block table or the combination block table can be confirmed according to the logic number in the operation command, and the target storage block can be further determined.
In a general case, the representation of the mapping relation for the combined memory block is to fill out the numbers of all the corresponding physical memory blocks under the combined memory block. For example, taking two wafers, two planes as an example, CE0plane 0 block2, CE0plane1 block2, CE1 plane0 block2, CE1 plane1 block5 are one combined memory block. The CE1 plane1 block5 replaces the original bad memory block CE1 plane1 block2. When the combined memory block is represented, the numbers of the four memory blocks need to be represented under the logical numbers of the combined memory block. The mapping relationship of the combined memory block needs to occupy a capacity of 8 bytes, indicating that the number of a memory block will occupy a capacity of 2 bytes. And for the case of larger and larger numbers of wafers and planes, the capacity required for representing the mapping relation of each combined memory block becomes larger and larger. For example, taking an eight wafer four plane as an example, representing a mapping of a combined memory block would require a capacity of 64 bytes. The size of the RAM used for storing the mapping relation in the storage device is limited, and when the data representing one combined memory block is too large, the storage device cannot represent all the combined memory blocks. Other combined memory blocks not shown are still unusable memory blocks.
Therefore, the mapping relation expression way of filling out all the storage block numbers is improved by using the common physical number. The combined block table comprises at least one mapping table of the combined storage block, and the mapping table represents the mapping relation between the logical number of the combined storage block and the corresponding physical storage block. Each mapping table includes a common physical number, at least one replacement wafer number, at least one replacement plane number, and at least one replacement physical number.
Referring to fig. 3, fig. 3 is a schematic diagram of a combined memory block mapping table.
Wherein A represents a common physical number, B represents a replacement wafer number, C represents a replacement plane number, and D represents a replacement physical number. The common physical number is the physical number of the combined memory block having the largest number of memory blocks.
Taking CE0plane 0 block2, CE0plane1 block2, CE1 plane0 block2, CE1 plane1 block5 as an example, the mapping relationship of the current combined memory blocks may be expressed as: the common physical number A is 2, the number of 2 in the numbers of blocks in the four memory blocks is the largest, the replacement wafer number B is 1, the replacement plane number C is 1, and the replacement physical number D is 5. If CE1 plane1 block2 is not a bad block, the combined memory block may be a binding memory block originally, its logic number is 2, and since CE1 plane1 block2 is damaged, the other three memory blocks become zero-scattered memory blocks, and CE1 plane1 block5 is replaced by CE1 plane1 block2 to be combined for further use, so CE1 plane1 block5 is regarded as a replacement memory block in the combined memory block, and its corresponding replacement wafer number, replacement plane number and replacement physical number are 115.
When expressed in this way, the common physical number a occupies 2 bytes, the replacement wafer number occupies 1byte, the replacement plane number occupies 1byte, the replacement physical number occupies 2 bytes, and the mapping relationship representing one combined memory block occupies only 6 bytes, which is reduced by 2 bytes compared with the way that the memory block numbers are fully filled. For a memory device with a larger number of wafers and planes, the data capacity occupied by the mapping relationship representing the combined memory blocks is reduced more. Therefore, the use of the common physical number and the representation mode of the replacement number can reduce the occupied capacity of the mapping table of the combined storage blocks, so that the storage device can store more mapping relations of the combined storage blocks under the same RAM, and reuse more scattered storage blocks.
Further, this representation may also be used when there are multiple replacement memory blocks in a certain combined memory block. Referring to fig. 4, fig. 4 is a schematic diagram of another structure of a combined memory block mapping table. Wherein A represents a common physical number, B represents a replacement wafer number, C represents a replacement plane number, D represents a replacement physical number, E represents a replacement wafer number, F represents a replacement plane number, and G represents a replacement physical number. The common physical number is the physical number of the combined memory block having the largest number of memory blocks.
Fig. 4 shows a representation when there are two replacement memory blocks in a combined memory block. Taking CE0plane 0 block2, CE0plane1 block3, CE1 plane0 block2 and CE1 plane1 block5 as examples, the common physical number is 2. The replacement memory blocks are CE0plane1 block3 and CE1 plane1 block5, the number corresponding to BCD is 013, and the number corresponding to EFG is 115. Although the mapping relation representing the combined memory block needs to occupy 10 bytes at this time, for a memory device with a large number of wafers and planes, the data capacity occupied by the mapping relation representation mode with all numbers filled in is still smaller.
Similar to the above two expressions, the combined block table may include a mapping table of at least one combined storage block, where the mapping table represents a mapping relationship of the combined storage block. The mapping table may include a common physical number, at least one replacement wafer number, at least one replacement plane number, and at least one replacement physical number. The number of the replacement wafer numbers and the number of the replacement plane numbers are the same as the number of the replacement physical numbers, and each group of the replacement wafer numbers, the replacement plane numbers and the replacement physical numbers correspond to a replacement memory block in the combined memory block.
Further, each pair of the replacement wafer number and the replacement plane number in the mapping table in the combined block table corresponds to at least one replacement physical number. In fig. 3, a pair of replacement wafer number and replacement plane number BC corresponds to a replacement physical number D, showing a replacement memory block. As shown in FIG. 5, FIG. 5 is a schematic diagram of a combined memory block mapping table. Wherein A represents a common physical number, B represents a replacement wafer number, C represents a replacement plane number, D represents a replacement physical number, and E represents a replacement physical number. The common physical number is the physical number of the combined memory block having the largest number of memory blocks.
Fig. 5 shows a representation when there are two replacement memory blocks in a combined memory block. Taking CE0plane 0 block2, CE1 plane1 block3, CE1 plane0 block2 and CE1 plane1 block5 as examples, the common physical number is 2. The replacement memory blocks are CE1 plane1 block3 and CE1 plane1 block5. The BCD corresponds to the number 113 and represents the replacement memory block CE1 plane1 block3, and the BCE corresponds to the number 115 and represents the replacement memory block CE1 plane1 block5. Unlike the alternative to replacing the memory blocks in fig. 4, the memory block selection in fig. 5 selects from the same plane of the same wafer, thereby reducing the replacement wafer number and the capacity occupation of the replacement plane number in the mapping table.
Referring to fig. 6, fig. 6 is a flowchart illustrating a processing method of a memory device according to a third embodiment of the application. The method is a further extension of step S22. Which comprises the following steps:
s31: the number of the memory block is determined.
And determining the storage block number of the scattered storage block. The number includes a wafer number, a plane number, and a physical number.
S32: and selecting the numbers based on a preset rule, and determining the storage blocks forming the combined storage block.
The preset rule is that the numbers of the memory blocks forming the combined memory block include all combinations of wafer numbers and plane numbers. I.e. each plane of each wafer comprises at least one memory block. Taking two wafers as an example, two planes are taken as the example, and in the CE0plane 0 block2, CE0plane1 block3, CE1 plane0 block2 and CE1 plane1 block5 combined storage blocks, a corresponding storage block exists in each plane of each wafer. Therefore, compared with the combined storage blocks in which the storage blocks are gathered in a certain wafer or a certain plane, the combined storage blocks have higher read-write performance.
Referring to fig. 7, fig. 7 is a flowchart illustrating a processing method of a storage device according to a fourth embodiment of the application. This method is a further extension of the above embodiments. Which comprises the following steps:
s41: the logical number of the operation target memory block is determined based on the received operation command.
And receiving an operation command, and determining a logic block needing to be operated and a corresponding logic number.
S42: it is determined whether a logical number exists in the combined block table.
And judging whether the logic block of the logic number is a combined storage block or a binding storage block, if the logic block is the combined storage block, executing the step S43, and if the logic block is the binding storage block, executing the step S44.
S43: and determining the storage block corresponding to the logic number in the combined block table as a target storage block.
And determining the storage blocks in the mapping table with the same common physical number as the logical number in the combined block table as target storage blocks needing to be operated.
S44: the logical number is converted to a physical number to determine the corresponding memory block as the target memory block.
When the operation object is determined to be the binding storage block, directly converting the logical number into the physical number of the storage block, and determining the corresponding target storage block according to the physical number.
S45: and operating the target storage block based on the operation command.
And performing read-write operation on the determined target storage block according to the operation command.
In the above embodiment, in order to facilitate management and to allow the storage device to have the best read-write performance, when determining the bound memory blocks and the combined memory blocks, the number of the respective memory blocks in the combined memory block is set to be the same as the number of the respective memory blocks in the bound memory blocks.
Fig. 8 is a schematic structural diagram of a memory device according to an embodiment of the application.
The storage device includes a processor 110, a memory 120.
The processor 110 controls the operation of the storage device, and the processor 110 may also be referred to as a CPU (Central Processing Unit ). The processor 110 may be an integrated circuit chip with processing capabilities for signal sequences. Processor 110 may also be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Memory 120 stores instructions and program data.
The processor 110 is coupled to the memory 120 to execute instructions to implement the methods provided by any embodiment and possible combinations of the processing methods of the storage device of the present application.
Fig. 9 is a schematic diagram of a computer readable storage device according to an embodiment of the application.
An embodiment of the readable storage device of the present application includes a memory 210, where the memory 210 stores program data that, when executed, implements the methods provided by any embodiment and possible combinations of the processing methods of the storage device of the present application.
The Memory 210 may include a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or a medium that may store program instructions, or may be a server that stores the program instructions, and the server may send the stored program instructions to other devices for execution, or may also self-execute the stored program instructions.
In summary, the application determines the physical number of the bad memory block by determining the good and fast conditions of the memory block in the memory device. While other good memory blocks with the same physical number as the bad memory blocks cannot be bound, further the good memory blocks bound into large logical blocks and the good memory blocks not bound can be determined. Good storage blocks which can be bound are bound, and good storage blocks which cannot be bound are combined to form a combined block for use, so that the unusable good storage blocks are changed into usable storage blocks again, the available capacity of the storage device is increased, and the mass production yield of the storage device is improved.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units of the other embodiments described above may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as stand alone products. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing description is only illustrative of the present application and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present application.
Claims (10)
1. A method of processing a storage device, the method comprising:
determining the quality of the storage blocks in the storage device;
if all the storage blocks with the same physical number are good storage blocks, binding all the good storage blocks with the same physical number to form a binding storage block;
and combining the remaining good storage blocks of the storage device except the binding storage blocks to form a combined storage block.
2. The method according to claim 1, wherein the method further comprises:
generating a logic block table of the binding storage block, wherein the logic number of the binding storage block is the same as the physical number of the binding storage block;
generating a combined block table of the combined storage blocks;
determining a target storage block according to the received operation command, the logic block table and the combined block table;
the logic number of the binding storage block is different from that of the combination storage block, and the target storage block is determined according to the received operation command and the logic number.
3. The method of claim 2, wherein the determining the target memory block from the received operation command, the logical block table, and the combined block table comprises:
determining a logic number of the operation object storage block based on the received operation command;
judging whether the logic number exists in the combined block table;
if yes, determining a storage block corresponding to the logic number in the combined block table as the target storage block;
if not, converting the logic number into the physical number to determine that the corresponding storage block is the target storage block;
and operating the target storage block based on the operation command.
4. The method of claim 2, wherein the combined block table comprises a mapping table of at least one of the combined memory blocks, each of the mapping tables of the combined memory blocks comprising a common physical number, at least one replacement wafer number, at least one replacement plane number, at least one replacement physical number.
5. The method of claim 4, wherein the number of the replacement wafer numbers, the replacement plane numbers, and the replacement physical numbers in the mapping table of the combined memory block are the same, wherein each set of the replacement wafer numbers, the replacement plane numbers, and the replacement physical numbers represents a memory block for replacement.
6. The method of claim 4, wherein each pair of the replacement wafer number and the replacement plane number in the mapping table of the combined memory block corresponds to at least one of the replacement physical numbers.
7. The method of claim 1, wherein combining the remaining good memory blocks of the memory device other than the bound memory block to form a combined memory block comprises:
determining the number of the good storage block, wherein the number comprises a wafer number, a plane number and a physical number;
selecting the numbers based on a preset rule, and determining storage blocks forming the combined storage block;
the preset rule is that the numbers of the storage blocks forming the combined storage block comprise all combination modes of the wafer numbers and the plane numbers.
8. The method of claim 2, wherein the number of memory blocks in the bound memory block is the same as the number of memory blocks in the combined memory block.
9. A storage device comprising a memory for storing program data and a processor coupled to the memory to implement the method of any one of claims 1-8.
10. A computer readable storage device storing program data executable by a processor to implement the method of any one of claims 1-8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210442511.3A CN116991306A (en) | 2022-04-25 | 2022-04-25 | Processing method of storage device, storage device and computer readable storage device |
| PCT/CN2022/092045 WO2023206605A1 (en) | 2022-04-25 | 2022-05-10 | Program running method for storage apparatus, and electronic device and readable storage apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210442511.3A CN116991306A (en) | 2022-04-25 | 2022-04-25 | Processing method of storage device, storage device and computer readable storage device |
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| CN116991306A true CN116991306A (en) | 2023-11-03 |
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| WO (1) | WO2023206605A1 (en) |
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| WO2009124320A1 (en) * | 2008-04-05 | 2009-10-08 | Fusion Multisystems, Inc. | Apparatus, system, and method for bad block remapping |
| CN101645310B (en) * | 2008-08-05 | 2013-09-18 | 深圳市朗科科技股份有限公司 | Flash memory equipment, method and system for managing flash memory |
| CN107562640B (en) * | 2016-06-30 | 2021-07-16 | 联想(北京)有限公司 | Information processing method, solid state disk and electronic equipment |
| CN106445408A (en) * | 2016-08-31 | 2017-02-22 | 深圳芯邦科技股份有限公司 | NAND flash memory management method, host, NAND flash memory reading and writing method, and NAND flash memory controller |
| CN111061655B (en) * | 2017-12-28 | 2022-06-17 | 贵阳忆芯科技有限公司 | Address translation method and device for storage device |
| CN112068777B (en) * | 2020-09-03 | 2023-08-18 | 深圳市硅格半导体有限公司 | Management method and system of data storage medium, terminal equipment and storage medium |
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- 2022-04-25 CN CN202210442511.3A patent/CN116991306A/en active Pending
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