CN116981263A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN116981263A
CN116981263A CN202311022681.7A CN202311022681A CN116981263A CN 116981263 A CN116981263 A CN 116981263A CN 202311022681 A CN202311022681 A CN 202311022681A CN 116981263 A CN116981263 A CN 116981263A
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epitaxial layer
layer
type
doping
semiconductor
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章纬
卜伟海
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North Ic Technology Innovation Center Beijing Co ltd
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North Ic Technology Innovation Center Beijing Co ltd
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Priority to CN202311022681.7A priority Critical patent/CN116981263A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/32—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the bipolar type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: the semiconductor substrate is provided with well regions and isolation structures which are alternately distributed, the isolation structures extend in the semiconductor substrate along the X direction, the surface of the semiconductor substrate is also provided with a grid structure extending along the Y direction, the X direction is perpendicular to the Y direction, and doped regions are formed in the well regions at two sides of the grid structure; the first epitaxial layer and the second epitaxial layer are sequentially positioned on part of the surface of the doped region, the doping type of the first epitaxial layer is opposite to that of the doped region, and the doping type of the second epitaxial layer is opposite to that of the first epitaxial layer; and the resistance change type memory structure is positioned above the second epitaxial layer. The application provides a semiconductor structure and a forming method thereof, wherein a PNP selector is formed between a source electrode, a drain electrode and a resistance change type memory structure, so that the area of a device can be reduced, and the integration of the device can be improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
The conventional variable resistance random access memory device is a single transistor single variable resistance (1T 1R) structure, in which the variable resistance structure is connected to the source of the transistor through a bottom pad plate, and a high dielectric constant material is stacked as an insulating layer and a metal top electrode plate, and is connected to a Bit Line (BL) through the top electrode plate and a metal connection Line. Therefore, the development of the related processes of the variable resistive element and the structure is required, and at least 2 additional masks are required to be added in the CMOS process, which is complicated and increases the cost.
Therefore, it is necessary to provide a more effective and reliable technical solution, which reduces the area of the device and improves the integration of the device.
Disclosure of Invention
The application provides a semiconductor structure and a forming method thereof, which can reduce the area of a device and improve the integration degree of the device.
One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein well regions and isolation structures which are alternately distributed are formed in the semiconductor substrate, the isolation structures extend in the semiconductor substrate along the X direction, a grid structure extending in the Y direction is also formed on the surface of the semiconductor substrate, the X direction is perpendicular to the Y direction, and doped regions are formed in the well regions at two sides of the grid structure; forming a first epitaxial layer and a second epitaxial layer on part of the surface of the doped region in sequence, wherein the doping type of the first epitaxial layer is opposite to that of the doped region, and the doping type of the second epitaxial layer is opposite to that of the first epitaxial layer; a resistance change type memory structure is formed over the second epitaxial layer.
In some embodiments of the present application, the doping type of the doped region is N-type, the doping type of the first epitaxial layer is P-type, the doping type of the second epitaxial layer is N-type, and the doped region, the first epitaxial layer and the second epitaxial layer form an NPN selector structure.
In some embodiments of the present application, the resistive random access memory structure includes a lower electrode, a resistive layer on a surface of the lower electrode, and an upper electrode on a surface of the resistive layer.
In some embodiments of the present application, the method for forming a semiconductor structure further includes: and forming a first contact structure and a first metal layer positioned on the surface of the first contact structure on the surface of the second epitaxial layer and the surfaces of the rest doped layers which are not formed with the first epitaxial layer and the second epitaxial layer, wherein the resistance change type memory structure is formed on the surface of the first metal layer.
In some embodiments of the application, the remaining doped layers not forming the first and second epitaxial layers are located outside the semiconductor substrate.
In some embodiments of the present application, the method for forming a semiconductor structure further includes: and forming a second contact structure and a second metal layer positioned on the surface of the second contact structure on the surface of the resistance change type memory structure.
In some embodiments of the present application, a method for sequentially forming a first epitaxial layer and a second epitaxial layer on a portion of a surface of the doped region includes: selective epitaxial processes and self-doping processes.
Another aspect of the present application also provides a semiconductor structure, comprising: the semiconductor substrate is provided with well regions and isolation structures which are alternately distributed, the isolation structures extend in the semiconductor substrate along the X direction, the surface of the semiconductor substrate is also provided with a grid structure extending along the Y direction, the X direction is perpendicular to the Y direction, and doped regions are formed in the well regions at two sides of the grid structure; the first epitaxial layer and the second epitaxial layer are sequentially positioned on part of the surface of the doped region, the doping type of the first epitaxial layer is opposite to that of the doped region, and the doping type of the second epitaxial layer is opposite to that of the first epitaxial layer; and the resistance change type memory structure is positioned above the second epitaxial layer.
In some embodiments of the present application, the doping type of the doped region is N-type, the doping type of the first epitaxial layer is P-type, the doping type of the second epitaxial layer is N-type, and the doped region, the first epitaxial layer and the second epitaxial layer form an NPN selector structure.
In some embodiments of the present application, the resistive random access memory structure includes a lower electrode, a resistive layer on a surface of the lower electrode, and an upper electrode on a surface of the resistive layer.
In some embodiments of the present application, the semiconductor structure further comprises: the resistive random access memory comprises a first contact structure and a first metal layer, wherein the first contact structure is positioned on the surface of the second epitaxial layer, and the surfaces of the rest doped layers which are not formed with the first epitaxial layer and the second epitaxial layer, the first metal layer is positioned on the surface of the first contact structure, and the resistive random access memory structure is positioned on the surface of the first metal layer.
In some embodiments of the application, the remaining doped layers not forming the first and second epitaxial layers are located outside the semiconductor substrate.
In some embodiments of the present application, the semiconductor structure further comprises: a second contact structure positioned on the surface of the resistance change type memory structure and a second metal layer positioned on the surface of the second contact structure.
The application provides a semiconductor structure and a forming method thereof, wherein a PNP selector is formed between a source electrode, a drain electrode and a resistance change type memory structure, so that the area of a device can be reduced, and the integration of the device can be improved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description only and are not intended to limit the scope of the application, as other embodiments may equally well accomplish the inventive intent in this disclosure. It should be understood that the drawings are not to scale.
Wherein:
fig. 1 to 6 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the application.
Detailed Description
The following description provides specific applications and requirements of the application to enable any person skilled in the art to make and use the application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the application is described in detail below with reference to the examples and the accompanying drawings.
Fig. 1 to 6 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure according to an embodiment of the application. The method for forming the semiconductor structure according to the embodiments of the present application is described in detail below with reference to the accompanying drawings.
Referring to fig. 1 and 2, wherein fig. 1 is a top view and fig. 2 is a longitudinal sectional view taken along the broken line A-A of fig. 1. A semiconductor substrate 100 is provided, well regions 110 and isolation structures 120 are alternately distributed in the semiconductor substrate 100, the isolation structures 120 extend in an X direction in the semiconductor substrate 100, a gate structure 130 extending in a Y direction is further formed on the surface of the semiconductor substrate 100, the X direction is perpendicular to the Y direction, and doped regions 140 are formed in the well regions 110 at two sides of the gate structure 130. In some embodiments of the present application, the reverse may be true, i.e., the gate structure 130 extends in the X-direction and the isolation structure 120 extends in the Y-direction. Note that fig. 1 only shows a partial region of the semiconductor substrate 100.
In some embodiments of the present application, the material of the semiconductor substrate 100 comprises (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the above.
In some embodiments of the present application, the well region 110 is formed by performing an ion implantation process in the semiconductor substrate 100. The doping type of the well region 110 is, for example, N-type or P-type. The well region 110 constitutes a Word Line (WL) in the X direction.
In some embodiments of the present application, the isolation structure 120 extends into the semiconductor substrate 100 through the well region 110. The material of the isolation structure 120 is, for example, silicon oxide.
In some embodiments of the present application, the gate structure 130 includes: the semiconductor device comprises a metal gate, work function layers (work function layer) arranged on two sides and the bottom of the metal gate, capping layers (capping layers) arranged on two sides and the bottom of the work function layers, a high dielectric constant layer arranged on the bottom of the capping layers, a gate oxide layer arranged on the bottom of the high dielectric constant layer, and side walls arranged on the gate oxide layer, the high dielectric constant layer and the side walls of the capping layers.
In some embodiments of the present application, the doping type of the doped region 140 is the same as the doping type of the well region 110, and the doping type of the doped region 140 is, for example, N-type or P-type. The doping concentration of the doped region 140 is higher than the doping concentration of the well region 110. The doped region 140 serves as a source and drain on both sides of the gate structure 130.
Referring to fig. 3, a first epitaxial layer 141 and a second epitaxial layer 142 are sequentially formed on a portion of the surface of the doped region 140, wherein the doping type of the first epitaxial layer 141 is opposite to that of the doped region 140, and the doping type of the second epitaxial layer 142 is opposite to that of the first epitaxial layer 141.
In some embodiments of the present application, the remaining doped layer 140, where the first epitaxial layer 141 and the second epitaxial layer 142 are not formed, is located outside the semiconductor substrate 100. The drawings of the present application only show a partial region of the semiconductor substrate 100. In practice, the semiconductor substrate 100 is divided into several chip regions, each of which is subsequently diced into chips. In each chip region, the part of the doped region 140 formed with the first and second epitaxial layers 141 and 142 is located in the middle, and the rest of the doped regions 140 not formed with the first and second epitaxial layers 141 and 142 are located at the outermost side of the chip region to surround the part of the doped regions 140 formed with the first and second epitaxial layers 141 and 142. Specifically, the positions of the partially doped regions 140 where the first epitaxial layer 141 and the second epitaxial layer 142 are formed correspond to the positions where the resistance change type memory structure is formed in the design.
In some embodiments of the present application, the doping type of the doped region 140 is N-type, the doping type of the first epitaxial layer 141 is P-type, the doping type of the second epitaxial layer 142 is N-type, and the doped region 140, the first epitaxial layer 141 and the second epitaxial layer 142 form an NPN selector structure. The gate structure is a gate structure that can be used to isolate each NPN selector. In other embodiments of the present application, the doping type of the doped region 140 may be P-type, the doping type of the first epitaxial layer 141 is N-type, the doping type of the second epitaxial layer 142 is P-type, and the doped region 140, the first epitaxial layer 141 and the second epitaxial layer 142 form a PNP selector structure according to the variation of the doping type of the well region 110.
In some embodiments of the present application, the method of forming the first epitaxial layer 141 and the second epitaxial layer 142 includes an In-situ selective epitaxial growth process (In-situ selective epitaxy). In some embodiments of the present application, the method for sequentially forming the first epitaxial layer 141 and the second epitaxial layer 142 on a portion of the surface of the doped region 140 includes: selective epitaxial processes and self-doping processes.
Referring to fig. 4, a first contact structure 150 and a first metal layer 160 on the surface of the first contact structure 150 are formed on the surface of the second epitaxial layer 142 and the surface of the remaining doped layer 140 where the first epitaxial layer 141 and the second epitaxial layer 142 are not formed. The resistance change memory structure is formed on the surface of the first metal layer 160. It should be noted that, all the drawings of the present application are simplified structures, and the unfilled portions in the drawings are actually dielectric layers, which are omitted for the sake of brevity.
In some embodiments of the present application, the surface of the second epitaxial layer 142 and the surface of the doped region 140 are flush with the top surface of the first metal layer 160 and the first contact structure 150.
In some embodiments of the present application, the material of the first contact structure 150 comprises tungsten or copper. The material of the first metal layer 160 includes tungsten or copper.
Referring to fig. 5, a resistive memory structure 170 is formed over the second epitaxial layer 142 (specifically, the surface of the first metal layer 160 over the second epitaxial layer 142). Each resistance change memory structure 170 is connected to an NPN selector to effect bipolar operation.
The application is exemplified only by a resistive memory structure. In practice, the technical solution of the present application is not limited to resistance variable memory structures (RRAM), but may be magneto-resistance variable random access memory devices (MRAM), phase-change random access memory devices (PCRAM), ferroelectric variable random access memory devices (FeRAM), and other related random access memory devices that can form electric/magneto-resistance changes.
In some embodiments of the present application, the resistance change memory structure 170 includes a lower electrode 171, a resistance change layer 172 on a surface of the lower electrode 171, and an upper electrode 173 on a surface of the resistance change layer 172. The lower electrode 171 and the upper electrode 173 are metal materials, such as aluminum. The material of the resistive layer 172 comprises a high dielectric constant material, which may be a single layer structure (HfO 2 ，Ta 2 O 5 ，Al 2 O 3 ) Or a double layer Structure (SiO) 2 /HfO 2 ，HfO 2 /SiO 2 ，SiO 2 /Al 2 O 3 ，Al 2 O 3 /SiO 2 ，Ta 2 O 5 /Al 2 O 3 ) Or a more layered structure stacked from the above materials. The resistive memory structure is a conventional device structure in the semiconductor field and will not be described in detail herein.
Referring to fig. 6, a second contact structure 180 and a second metal layer 190 on the surface of the second contact structure 180 are formed on the surface of the resistance change memory structure 170. The second metal layer 190 is connected in the Y direction and constitutes a bit line (BL: bit line).
In some embodiments of the present application, the material of the second contact structure 180 includes tungsten or copper. The material of the second metal layer 190 includes tungsten or copper.
The technical scheme of the application aims at improving the variable resistance random access memory component and designs and manufactures the variable resistance random access memory component by utilizing a deep buried gate process (compatible with DRAM). The source electrode and the drain electrode of the transistor structure are used as the components of the NPN selector of the variable resistance random access memory component, so that the area can be further reduced and the component integration degree can be improved.
According to the technical scheme, a selective epitaxial process and a self-doping process technology are utilized, a first epitaxial layer and a second epitaxial layer are sequentially formed on a source electrode and a drain electrode of a transistor structure, then an NPN Selector structure (1S) is formed by combining the source electrode and the drain electrode, and then a Resistive memory structure (1R) is connected to form a 1S1R variable resistance random access memory (1S 1 RReRAM).
The technical scheme of the application can realize bipolar operation (positive bias setting (set), negative bias resetting (reset)) by utilizing the bidirectional conduction characteristic of the NPN selector, and the design can further reduce the area of a minimum cell (bit cell) to 3F 2 The integration of components can be effectively improved.
According to the technical scheme, the opening voltage and the current of the NPN selector can be respectively adjusted by adjusting the thickness and the doping concentration of the first epitaxial layer and the second epitaxial layer, and the operation range and the application of the 1S1R ReRAM can be improved.
The application provides a method for forming a semiconductor structure, which forms a PNP selector between a source electrode, a drain electrode and a resistance change type memory structure, so that the area of a device can be reduced, and the integration of the device can be improved.
Embodiments of the present application also provide a semiconductor structure, as shown with reference to fig. 1 and 6, including: a semiconductor substrate 100, in which well regions 110 and isolation structures 120 are alternately distributed, the isolation structures 120 extend in an X direction in the semiconductor substrate 100, a gate structure 130 extending in a Y direction is further formed on the surface of the semiconductor substrate 100, the X direction is perpendicular to the Y direction, and doped regions 140 are formed in the well regions 110 on two sides of the gate structure 130; the first epitaxial layer 141 and the second epitaxial layer 142 are sequentially located on a part of the surface of the doped region 140, the doping type of the first epitaxial layer 141 is opposite to that of the doped region 140, and the doping type of the second epitaxial layer 142 is opposite to that of the first epitaxial layer 141; a resistive memory structure 170 is located over the second epitaxial layer 142. In some embodiments of the present application, the reverse may be true, i.e., the gate structure 130 extends in the X-direction and the isolation structure 120 extends in the Y-direction.
In some embodiments of the present application, the material of the semiconductor substrate 100 comprises (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the above.
In some embodiments of the present application, the well region 110 is formed by performing an ion implantation process in the semiconductor substrate 100. The doping type of the well region 110 is, for example, N-type or P-type. The well region 110 constitutes a Word Line (WL) in the X direction.
In some embodiments of the present application, the isolation structure 120 extends into the semiconductor substrate 100 through the well region 110. The material of the isolation structure 120 is, for example, silicon oxide.
In some embodiments of the present application, the gate structure 130 includes: the semiconductor device comprises a metal gate, work function layers (work function layer) arranged on two sides and the bottom of the metal gate, capping layers (capping layers) arranged on two sides and the bottom of the work function layers, a high dielectric constant layer arranged on the bottom of the capping layers, a gate oxide layer arranged on the bottom of the high dielectric constant layer, and side walls arranged on the gate oxide layer, the high dielectric constant layer and the side walls of the capping layers.
In some embodiments of the present application, the doping type of the doped region 140 is N-type or P-type, which is the same as the doping type of the well region 110. The doping concentration of the doped region 140 is higher than the doping concentration of the well region 110. The doped region 140 serves as a source and drain on both sides of the gate structure 130.
In some embodiments of the present application, the remaining doped layer 140, where the first epitaxial layer 141 and the second epitaxial layer 142 are not formed, is located outside the semiconductor substrate 100. The drawings of the present application only show a partial region of the semiconductor substrate 100. In practice, the semiconductor substrate 100 is divided into several chip regions, each of which is subsequently diced into chips. In each chip region, the part of the doped region 140 formed with the first and second epitaxial layers 141 and 142 is located in the middle, and the rest of the doped regions 140 not formed with the first and second epitaxial layers 141 and 142 are located at the outermost side of the chip region to surround the part of the doped regions 140 formed with the first and second epitaxial layers 141 and 142. Specifically, the positions of the partially doped regions 140 where the first epitaxial layer 141 and the second epitaxial layer 142 are formed correspond to the positions where the resistance change type memory structure is formed in the design.
In some embodiments of the present application, the doping type of the doped region 140 is N-type, the doping type of the first epitaxial layer 141 is P-type, the doping type of the second epitaxial layer 142 is N-type, and the doped region 140, the first epitaxial layer 141 and the second epitaxial layer 142 form an NPN selector structure. The gate structure is a gate structure that can be used to isolate each NPN selector. In other embodiments of the present application, the doping type of the doped region 140 may be P-type, the doping type of the first epitaxial layer 141 is N-type, the doping type of the second epitaxial layer 142 is P-type, and the doped region 140, the first epitaxial layer 141 and the second epitaxial layer 142 form a PNP selector structure according to the variation of the doping type of the well region 110.
With continued reference to fig. 6, the semiconductor structure further includes: the resistive memory structure 170 is located on the surface of the first metal layer 160, and the first contact structure 150 is located on the surface of the second epitaxial layer 142 and the surface of the remaining doped layer 140 where the first epitaxial layer 141 and the second epitaxial layer 142 are not formed, and the first metal layer 160 is located on the surface of the first contact structure 150. It should be noted that, all the drawings of the present application are simplified structures, and the unfilled portions in the drawings are actually dielectric layers, which are omitted for the sake of brevity.
In some embodiments of the present application, the surface of the second epitaxial layer 142 and the surface of the doped region 140 are flush with the top surface of the first metal layer 160 and the first contact structure 150.
In some embodiments of the present application, the material of the first contact structure 150 comprises tungsten or copper. The material of the first metal layer 160 includes tungsten or copper.
With continued reference to fig. 6, a resistive memory structure 170 is formed over the second epitaxial layer 142 (and in particular, the surface of the first metal layer 160 over the second epitaxial layer 142). Each resistance change memory structure 170 is connected to an NPN selector to effect bipolar operation.
The application is exemplified only by a resistive memory structure. In practice, the technical solution of the present application is not limited to resistance variable memory structures (RRAM), but may be magneto-resistance variable random access memory devices (MRAM), phase-change random access memory devices (PCRAM), ferroelectric variable random access memory devices (FeRAM), and other related random access memory devices that can form electric/magneto-resistance changes.
In some embodiments of the present application, the resistance change memory structure 170 includes a lower electrode 171, a resistance change layer 172 on a surface of the lower electrode 171, and an upper electrode 173 on a surface of the resistance change layer 172. The lower electrode 171 and the upper electrode 173 are metal materials, such as aluminum. The material of the resistive layer 172 comprises a high dielectric constant material, which may be a single layer structure (HfO 2 ，Ta 2 O 5 ，Al 2 O 3 ) Or a double layer Structure (SiO) 2 /HfO 2 ，HfO 2 /SiO 2 ，SiO 2 /Al 2 O 3 ，Al 2 O 3 /SiO 2 ，Ta 2 O 5 /Al 2 O 3 ) Or a more layered structure stacked from the above materials. The resistive memory structure is a conventional device structure in the semiconductor field and will not be described in detail herein.
With continued reference to fig. 6, the semiconductor structure further includes: a second contact structure 180 located on a surface of the resistance change memory structure 170, and a second metal layer 190 located on a surface of the second contact structure 180. The second metal layer 190 is connected in the Y direction and constitutes a bit line (BL: bit line).
In some embodiments of the present application, the material of the second contact structure 180 includes tungsten or copper. The material of the second metal layer 190 includes tungsten or copper.
The technical scheme of the application aims at improving the variable resistance random access memory component and designs and manufactures the variable resistance random access memory component by utilizing a deep buried gate process (compatible with DRAM). The source electrode and the drain electrode of the transistor structure are used as the components of the NPN selector of the variable resistance random access memory component, so that the area can be further reduced and the component integration degree can be improved.
According to the technical scheme, a selective epitaxial process and a self-doping process technology are utilized, a first epitaxial layer and a second epitaxial layer are sequentially formed on a source electrode and a drain electrode of a transistor structure, then an NPN Selector structure (1S) is formed by combining the source electrode and the drain electrode, and then a Resistive memory structure (1R) is connected to form a 1S1R variable resistance random access memory (1S 1R ReRAM).
The technical scheme of the application can realize bipolar operation (positive bias setting (set), negative bias resetting (reset)) by utilizing the bidirectional conduction characteristic of the NPN selector, and the design can further reduce the area of a minimum cell (bit cell) to 3F 2 The integration of components can be effectively improved.
According to the technical scheme, the opening voltage and the current of the NPN selector can be respectively adjusted by adjusting the thickness and the doping concentration of the first epitaxial layer and the second epitaxial layer, and the operation range and the application of the 1S1R ReRAM can be improved.
The application provides a semiconductor structure and a forming method thereof, wherein a PNP selector is formed between a source electrode, a drain electrode and a resistance change type memory structure, so that the area of a device can be reduced, and the integration of the device can be improved.
In view of the foregoing, it will be evident to those skilled in the art after reading this disclosure that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present description describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (13)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein well regions and isolation structures which are alternately distributed are formed in the semiconductor substrate, the isolation structures extend in the semiconductor substrate along the X direction, a grid structure extending in the Y direction is also formed on the surface of the semiconductor substrate, the X direction is perpendicular to the Y direction, and doped regions are formed in the well regions at two sides of the grid structure;
forming a first epitaxial layer and a second epitaxial layer on part of the surface of the doped region in sequence, wherein the doping type of the first epitaxial layer is opposite to that of the doped region, and the doping type of the second epitaxial layer is opposite to that of the first epitaxial layer;
a resistance change type memory structure is formed over the second epitaxial layer.
2. The method of claim 1, wherein the doping region has an N-type doping, the first epitaxial layer has a P-type doping, the second epitaxial layer has an N-type doping, and the doping region, the first epitaxial layer, and the second epitaxial layer form an NPN selector structure.
3. The method of forming a semiconductor structure of claim 1, wherein the resistive random access memory structure comprises a lower electrode, a resistive layer on a surface of the lower electrode, and an upper electrode on a surface of the resistive layer.
4. The method of forming a semiconductor structure of claim 1, further comprising: and forming a first contact structure and a first metal layer positioned on the surface of the first contact structure on the surface of the second epitaxial layer and the surfaces of the rest doped layers which are not formed with the first epitaxial layer and the second epitaxial layer, wherein the resistance change type memory structure is formed on the surface of the first metal layer.
5. The method of forming a semiconductor structure of claim 4, wherein remaining doped layers not forming the first epitaxial layer and the second epitaxial layer are located outside the semiconductor substrate.
6. The method of forming a semiconductor structure of claim 1, further comprising: and forming a second contact structure and a second metal layer positioned on the surface of the second contact structure on the surface of the resistance change type memory structure.
7. The method for forming a semiconductor structure according to claim 1, wherein the method for sequentially forming the first epitaxial layer and the second epitaxial layer on a part of the surface of the doped region comprises: selective epitaxial processes and self-doping processes.
8. A semiconductor structure, comprising:
the semiconductor substrate is provided with well regions and isolation structures which are alternately distributed, the isolation structures extend in the semiconductor substrate along the X direction, the surface of the semiconductor substrate is also provided with a grid structure extending along the Y direction, the X direction is perpendicular to the Y direction, and doped regions are formed in the well regions at two sides of the grid structure;
the first epitaxial layer and the second epitaxial layer are sequentially positioned on part of the surface of the doped region, the doping type of the first epitaxial layer is opposite to that of the doped region, and the doping type of the second epitaxial layer is opposite to that of the first epitaxial layer;
and the resistance change type memory structure is positioned above the second epitaxial layer.
9. The semiconductor structure of claim 8, wherein the doping region is N-type in doping type, the first epitaxial layer is P-type in doping type, the second epitaxial layer is N-type in doping type, and the doping region, the first epitaxial layer, and the second epitaxial layer comprise an NPN selector structure.
10. The semiconductor structure of claim 8, wherein the resistive random access memory structure comprises a lower electrode, a resistive switching layer on a surface of the lower electrode, and an upper electrode on a surface of the resistive switching layer.
11. The semiconductor structure of claim 8, further comprising: the resistive random access memory comprises a first contact structure and a first metal layer, wherein the first contact structure is positioned on the surface of the second epitaxial layer, and the surfaces of the rest doped layers which are not formed with the first epitaxial layer and the second epitaxial layer, the first metal layer is positioned on the surface of the first contact structure, and the resistive random access memory structure is positioned on the surface of the first metal layer.
12. The semiconductor structure of claim 11, wherein the remaining doped layers not forming the first epitaxial layer and the second epitaxial layer are located outside the semiconductor substrate.
13. The semiconductor structure of claim 8, further comprising: a second contact structure positioned on the surface of the resistance change type memory structure and a second metal layer positioned on the surface of the second contact structure.
CN202311022681.7A 2023-08-14 2023-08-14 Semiconductor structure and forming method thereof Pending CN116981263A (en)

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