CN116978935A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN116978935A
CN116978935A CN202310464379.0A CN202310464379A CN116978935A CN 116978935 A CN116978935 A CN 116978935A CN 202310464379 A CN202310464379 A CN 202310464379A CN 116978935 A CN116978935 A CN 116978935A
Authority
CN
China
Prior art keywords
gate
gate structure
over
layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310464379.0A
Other languages
Chinese (zh)
Inventor
林大钧
曹志彬
张志豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/899,021 external-priority patent/US20240014256A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN116978935A publication Critical patent/CN116978935A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Semiconductor structures and methods of forming the same are provided. The semiconductor structure includes a substrate, a first active region, a second active region and a third active region on the substrate, a first gate structure over a channel region of the first active region, a second gate structure over a channel region of the second active region, a tri-gate structure over a channel region of the third active region, a first cap layer over the first gate structure, a second cap layer over the second gate structure and a third cap layer over the third gate structure. The second gate structure has a height less than the first gate structure or the third gate structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present application relate to the field of semiconductor technology, and more particularly, to semiconductor structures and methods of forming the same.
Background
The semiconductor Integrated Circuit (IC) industry has experienced a rapid growth. During the development of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) typically increases, while the geometry (i.e., the smallest component (or line) that a manufacturing process can create) decreases. Such a scaling down process generally provides benefits by improving production efficiency and reducing associated costs. However, this scaling down is also accompanied by an increase in the complexity of device design and fabrication in which these ICs are integrated, and similar developments in device fabrication are required to achieve these advances.
The gate replacement process may be used to fabricate multi-gate transistors, such as fin field effect transistors (finfets) or multi-bridge channel (MBC, gate replacement) transistors. Taking FinFET fabrication as an example, a dummy gate is first formed on a channel region of a semiconductor fin structure and gate spacers are formed along sidewalls of the dummy gate. The dummy gate is then removed and replaced with a metal gate structure that includes a gate dielectric layer and a work function layer. In some processes, the metal gate structure is recessed to allow room for a dielectric cap layer to protect the metal gate during subsequent self-aligned contact formation. While existing multi-gate transistors and processes for forming them are generally adequate for their intended use, they are not satisfactory in all respects.
Disclosure of Invention
According to an aspect of an embodiment of the present application, there is provided a semiconductor structure including: a substrate; the first active region, the second active region and the third active region are positioned above the substrate; a first gate structure over the channel region of the first active region; a second gate structure over the channel region of the second active region; a third gate structure over the channel region of the third active region; the first cap layer is positioned above the first grid structure; the second cap layer is positioned above the second grid structure; and a third cap layer over the third gate structure, wherein the height of the second gate structure is less than the height of the first gate structure or the height of the third gate structure.
According to another aspect of an embodiment of the present application, there is provided a method of forming a semiconductor structure, comprising: a workpiece is received. The workpiece comprises: the first, second and third active regions are located over the substrate, the first gate structure is located over the channel region of the first active region, the second gate structure is located over the channel region of the second active region, and the third gate structure is located over the channel region of the third active region. The method of forming a semiconductor structure further includes: selectively recessing the second gate structure; after selectively recessing, recessing the first gate structure, the second gate structure, and the third gate structure to form a first gate recess over the first gate structure, a second gate recess over the second gate structure, and a third gate recess over the third gate structure; depositing a dielectric cap layer over the first, second and third gate recesses after recessing; and after deposition, planarizing the workpiece to reduce the thickness of the dielectric cap layer.
According to yet another aspect of an embodiment of the present application, there is provided a method of forming a semiconductor structure, comprising: a workpiece is received. The workpiece comprises: the first grid structure is located above the first area, the first grid structure comprises a first work function metal layer, the second grid structure is located above the second area, the second grid structure comprises the first work function metal layer, the third grid structure is located above the third area, and the third grid structure comprises the second work function metal layer. The method of forming a semiconductor structure further includes: recessing the first, second and third gate structures to form first, second and third gate recesses; depositing a dielectric cap layer over the first, second and third gate recesses after recessing; and planarizing the workpiece to reduce the thickness of the dielectric cap layer after the depositing, wherein recessing includes etching the third gate structure faster such that the third gate recess is deeper than the first gate recess or the second gate recess.
Drawings
The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a flow chart of a method of fabricating transistors with different threshold voltages in accordance with aspects of the present disclosure.
Fig. 2-7 are partial schematic cross-sectional views of a workpiece at different stages of manufacture, such as those associated with the method of fig. 1, in accordance with aspects of the present disclosure.
Fig. 8 is a flow chart of a method of fabricating transistors with different threshold voltages in accordance with aspects of the present disclosure.
Fig. 9-11 are partial schematic cross-sectional views of a workpiece at different stages of manufacture, such as those associated with the method of fig. 8, in accordance with aspects of the present disclosure.
Fig. 12 is a flow chart of a method of fabricating transistors with different threshold voltages in accordance with aspects of the present disclosure.
Fig. 13-16 are partial schematic cross-sectional views of a workpiece at different stages of manufacture, such as those associated with the method of fig. 12, in accordance with aspects of the present disclosure.
Fig. 17 is a flow chart of a method of fabricating transistors with different threshold voltages in accordance with aspects of the present disclosure.
Fig. 18-23 are partial schematic cross-sectional views of a workpiece at different stages of manufacture, such as those associated with the method of fig. 17, in accordance with aspects of the present disclosure.
Fig. 24 is a flow chart of a method of fabricating transistors with different threshold voltages in accordance with aspects of the present disclosure.
Fig. 25-30 are partial schematic cross-sectional views of a workpiece at different stages of manufacture, such as those associated with the method of fig. 24, in accordance with aspects of the present disclosure.
Fig. 31 is a flow chart of a method of fabricating transistors with different threshold voltages in accordance with aspects of the present disclosure.
Fig. 32-40 are partial schematic cross-sectional views of a workpiece at different stages of manufacture, such as those associated with the method of fig. 31, in accordance with aspects of the present disclosure.
Fig. 41 shows a line graph summarizing the effect of remaining gate height and the presence of a selective metal layer on n-type metal oxide transistor (NMOS) threshold voltage (Vts).
Fig. 42 shows a line graph summarizing the effect of remaining gate height and the presence of a selective metal layer on p-type metal oxide transistor (NMOS) threshold voltage (Vts).
Fig. 43 representatively illustrates how all embodiments of the present disclosure are readily implemented to MBC transistors.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, for ease of description, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly.
Furthermore, when "about," "approximately," etc. are used to describe a number or range of numbers, the term is intended to include numbers within a reasonable range, which is considered to be variations inherent in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing components having the described number dependent characteristics (characteristics), the number or range of numbers includes a reasonable range of the described numbers, e.g., within +/-10% of the described numbers. For example, those skilled in the art know that a material layer having a thickness of "about 5nm" can comprise a size range of 4.25nm to 5.75nm with a manufacturing tolerance of +/-15% associated with depositing the material layer. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
As Integrated Circuit (IC) technology has evolved towards smaller technology nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCE). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed on more than one side of the channel region. Fin field effect transistors (FinFET) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become the dominant and promising candidates for high performance and low leakage applications. Finfets have elevated channels that are wrapped on multiple sides by gates (e.g., gate wraps top and sidewalls of a "fin" of semiconductor material extending from a substrate). MBC transistors have a gate structure that may extend partially or completely around the channel region to provide access to the channel region on two or more sides. MBC transistors may also be referred to as wrap gate transistors (SGT, (surrounding gate transistor) or gate-all-around) transistors because their gate structure surrounds the channel region.
Self-aligned contact techniques facilitate the formation of contacts for smaller multi-gate transistor structures. To allow for self-aligned formation of the contact structure, a self-aligned cap layer may be formed over the metal gate structure of the multi-gate device. The formation of such a self-aligned cap layer includes recessing the metal gate structure to form a recess and depositing a dielectric cap in the recess. The present disclosure provides processes and structures for forming transistors of different threshold voltages. It has been observed that the gate recess process may consume some threshold voltage determining species, such as aluminum. For example, when threshold voltage modulation is involved, aluminum consumption during gate recessing may adversely affect the n-type and p-type transistors. Embodiments of the present disclosure include different methods of different recessed gate structures to achieve different threshold voltages for different transistors.
Various aspects of the disclosure will now be described in more detail with reference to the accompanying drawings. Fig. 1, 8, 12, 17, 24, and 31 are flowcharts of methods 100, 300, 400, 500, 600, and 700 for fabricating semiconductor devices of different threshold voltages. Each of the methods 100, 300, 400, 500, 600, and 700 are merely examples and are not intended to limit the present disclosure to what is explicitly described in such methods. Additional steps may be provided before, during, and after the methods 100, 300, 400, 500, 600, or 700, and some of the steps described may be removed, replaced, or eliminated for additional embodiments. For the sake of brevity, not all of the steps are described in detail herein. The method 100 will be described in connection with partial cross-sectional views of a workpiece 200 as shown in fig. 2-7. The method 300 will be described below in connection with the partial cross-sectional view of the workpiece 200 shown in fig. 9-11. The method 400 will be described below in connection with the partial cross-sectional views of the workpiece 200 shown in fig. 13-16. The method 500 will be described below in connection with partial cross-sectional views of the workpiece 200 shown in fig. 18-23. The method 600 will be described below in connection with the partial cross-sectional views of the workpiece 200 shown in fig. 25-30. The method 700 will be described below in connection with the partial cross-sectional view of the workpiece 200 shown in fig. 32-40. Since the semiconductor device will be formed from the workpiece 200, the workpiece 200 may be referred to as the semiconductor device 200, depending on the context. Further, in the present disclosure, like reference numerals refer to like parts unless otherwise specified.
Referring to fig. 1 and 2, the method 100 includes a block 102 in which a workpiece 200 includes a first transistor structure 12 over a first region 10, a second transistor structure 22 over a second region 20, and a third transistor structure 32 over a third region 30. Alternatively, in some embodiments, the substrate 202 includes a bulk substrate (e.g., including silicon) and one or more material layers disposed on the bulk substrate. For example, the one or more material layers may include a semiconductor layer stack having various semiconductor layers (e.g., heterostructures) disposed on a bulk substrate, wherein the semiconductor layer stack is subsequently patterned to form fins. The semiconductor layer may comprise any suitable semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), other suitable semiconductor materials, or combinations thereof. Depending on the design requirements of semiconductor device 200, the semiconductor layers may include the same or different materials, etch rates, atomic percentages of components, weight percentages of components, thicknesses, and/or configurations. Alternatively or additionally, the bulk substrate 202 and/or one or more material layers include: another elemental semiconductor such as germanium (Ge); compound semiconductors such as silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide; alloy semiconductors such as silicon germanium (SiGe), silicon phosphorus carbide (SiPC), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), gallium aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP); other III-V materials; other group II-V materials; or a combination thereof. Alternatively, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate may be fabricated by oxygen ion implantation isolation (SIMOX, separation by implantation of oxygen), wafer bonding, and/or other suitable methods. The substrate 202 may include different regions designated for forming different devices. In the illustrated embodiment, the substrate 202 includes a first region 10, a second region 20, and a third region 30. Although not explicitly shown in the figures, the first region 10, the second region 30 and the third region 30 may be disposed side by side or adjacent on the substrate 202.
As shown in fig. 2, the workpiece 200 further includes a first transistor structure 12 over the first region 10, a second transistor structure 22 over the second region 20, and a third transistor structure 32 over the third region 30. For ease of illustration, each of the first transistor structure 12, the second transistor structure 22, and the third transistor structure 32 are formed on a fin 204, the fin 204 being formed from the substrate 202 or a semiconductor layer deposited on the substrate 202. On each of the first region 10, the second region 20, and the third region 30, the fin 204 includes a channel region 204C sandwiched between two source/drain regions 204 SD. In the first region 10, the first transistor structure 12 includes a first gate structure 220 wrapped around a channel region 204C, the channel region 204C being disposed between two source/drain features 206 formed on a source/drain region 204 SD. In the second region 20, the second transistor structure 22 includes a second gate structure 222 wrapped around the channel region 204C, the channel region 204C being disposed between two source/drain features 206 formed on the source/drain region 204 SD. In the third region 30, the third transistor structure 32 includes a third gate structure 224 wrapped around the channel region 204C, the channel region 204C being disposed between two source/drain features 206 formed on the source/drain region 204 SD. Each of the first gate structure 220, the second gate structure 222, and the third gate structure 224 is defined between two gate spacer layers 230. The first transistor structure 12, the second transistor structure 22, and the third transistor structure 32 further include a Contact Etch Stop Layer (CESL) 232 and an interlayer dielectric (ILD) layer 234 disposed on the source/drain features 206.
Fins 204, as well as other similar fins on substrate 202, may be formed using one or more photolithographic processes and one or more etching processes. In some embodiments, fin 204 may be formed using a single patterning process or multiple patterning processes. Examples of multiple patterning processes include a Double Pattern Lithography (DPL) process (e.g., a photolithography-etch-lithography (LELE) process, a self-aligned double patterning (SADP) process, a dielectric spacer patterning (SIDP) process, other double patterning processes, or a combination thereof), a triple pattern fabrication process (e.g., a photolithography-etch-lithography-etch (lelelele) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (sarp) process), or a combination thereof. To form fin 204, a fin top hard mask layer is deposited on substrate 202, and then a patterned fin top hard mask layer is formed. The patterned fin top hard mask layer is then used as an etch mask to etch the substrate 202 (or semiconductor layer stack thereon) to form the fin 204. The fin top hard mask layer may be a single layer or multiple layers. In some cases, the fin top hard mask layer may include silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, or other suitable dielectric materials.
In some embodiments, a gate replacement process may be employed to form the first transistor structure 12, the second transistor structure 22, and the third transistor structure 32. In an example gate replacement process, a dummy gate stack is formed on channel region 204C in first region 10, second region 20, and third region 30. The dummy gate stack serves as a placeholder to undergo various processes and is to be removed and replaced by a first gate structure 220, a second gate structure 222, and a third gate structure 224. The dummy gate stack may include a dummy dielectric layer and a dummy electrode layer on the dummy dielectric layer. In some embodiments, the dummy dielectric layer may include silicon oxide, and the dummy electrode layer may include polysilicon (poly-Si). The dummy dielectric layer may be formed on fin 204 using a Chemical Vapor Deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, a thermal oxidation process, or other suitable process. The dummy electrode layer may be deposited on the dummy dielectric layer using a CVD process, an ALD process, or other suitable process. To pattern the dummy dielectric layer and the dummy electrode layer into a dummy gate stack, a gate top hard mask layer may be deposited over the dummy electrode layer using a CVD process, an ALD process, or other suitable process. The gate top hard mask layer is then patterned to act as an etch mask to etch the dummy electrode layer and dummy dielectric layer to form a dummy gate stack.
The gate spacer layer 230 may be deposited using ALD, CVD, or other suitable methods. In some embodiments, the gateThe pole spacer layer 230 may include carbon oxynitride, carbon doped silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Source/drain features 206 may be epitaxially formed and selectively formed from the surface of source/drain recesses formed in source/drain regions 204 SD. Suitable epitaxial processes may include Vapor Phase Epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular Beam Epitaxy (MBE), and/or other suitable processes. The epitaxial growth process of source/drain feature 206 may use a gaseous precursor that interacts with the composition of substrate 202 and fin 204. The source/drain features 206 may have different compositions depending on the conductivity type of the transistor structure. When the transistor structure in the semiconductor device 200 is n-type, the source/drain features 206 may comprise silicon (Si) and may be doped with n-type dopants, such As phosphorus (P) or arsenic (As). When the transistor structure in the semiconductor device 200 is p-type, the source/drain features 206 may comprise silicon germanium (SiGe) and may be doped with p-type dopants, such as boron (B), boron difluoride (BF 2 ) Or gallium (Ga). Although not explicitly shown in fig. 2, source/drain feature 206 may include two or more epitaxial layers. For example, each of the source/drain features 206 may include a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer doped with the same type of dopant but different doping concentrations to reduce defect density and contact resistance. In one embodiment, source/drain features 206 may include phosphorus doped silicon (Si: P) when an n-type FinFET is desired, and boron doped silicon germanium (SiGe: B) when a P-type FinFET is desired.
As shown in fig. 2, CESL232 is formed prior to formation of ILD layer 234. In some examples, CESL232 includes silicon nitride, silicon oxynitride, and/or other materials known in the art. CESL232 may be formed by ALD, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and/or other suitable deposition processes. An ILD layer 234 is then deposited over CESL 232. In some embodiments, ILD layer 234 comprises a material such as Tetraethoxysilane (TEOS), undoped silicate glass, or doped silicon oxide, doped silicon oxide such as borophosphosilicate glass (BPSG), fused Silica Glass (FSG), phosphosilicate glass, boron doped silicate glass (BSG), and/or other suitable dielectric materials. ILD layer 234 may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after the ILD layer 234 is formed, the workpiece 200 may be annealed to improve the integrity (integrity) of the ILD layer 234.
After ILD layer 234 is formed, the dummy gate stack is replaced with first gate structure 220, second gate structure 222, and third gate structure 224. The dummy gate stack is removed from the workpiece 200 by a selective etching process. Removing the dummy gate stack forms a gate trench over the channel region 204C in the first region 10, the second region 20, and the third region 30. After the dummy gate stack is removed, first gate structure 220, second gate structure 222, and third gate structure 224 are deposited on workpiece 200 to encapsulate channel region 204C in first region 10, second region 20, and third region 30. Each of the first gate structure 220, the second gate structure 222, and the third gate structure 224 includes an interfacial layer 207 and a gate dielectric layer 208 over the channel region 204C. Wherein interfacial layer 207 is over channel region 204C and gate dielectric layer 208 is over interfacial layer 207. In some embodiments, the interface layer 207 comprises silicon oxide and may be formed by a pre-cleaning process. Example pre-cleaning processes may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and/or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The preclean process oxidizes the exposed surfaces of channel region 204C to form interface layer 207. A gate dielectric layer 208 is then deposited over the interfacial layer 207 using ALD, CVD, and/or other suitable methods. In one embodiment, the gate dielectric layer 208 may comprise hafnium oxide. Alternatively, the gate dielectric layer 208 may include other high-K dielectrics, such as titanium oxide (TiO 2 ) Hafnium zirconium oxide (HfZrO), tantalum oxide (Ta) 2 O 5 ) Zirconia silicon (HfSiO) 4 ) Zirconium oxide (ZrO) 2 ) Zirconia silica (ZrSiO) 2 ) Lanthanum oxide (La) 2 O 3 ) Alumina (Al) 2 O 3 ) Hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, sr) TiO 3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. After depositing the gate dielectric layer 208, a gate dielectric layer 208 is depositedWork function layers in the first region 10, the second region 20 and the third region 30 are deposited above.
The first gate structure 220, the second gate structure 222, and the third gate structure 224 may include different work function layers according to designs. For example, the first gate structure 220 and the second gate structure 222 include an n-type work function layer 210, and the third gate structure 224 includes a p-type work function layer 212. The n-type work function layer 210 may include titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum aluminum carbide (TaAlC), titanium aluminum carbide (TiAlC), silicon doped tantalum aluminum carbide (TaAlC: si), silicon doped titanium aluminum carbide, or a combination thereof. The p-type work function layer 212 may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or tantalum carbide (TaC). Although not explicitly shown, each of the first, second, and third gate structures 220, 222, 224 may further include a metal fill layer on the n-type work function layer 210 or the p-type work function layer 212. The metal fill layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), other refractory metals, or other suitable metallic materials, or combinations thereof.
Referring to fig. 1, 3, and 4, the method 100 includes a block 104 in which the second gate structure 222 of the second transistor structure 22 is selectively recessed. The selective recessing at block 104 may include using a photolithography and etching process. In the embodiment shown in fig. 3, a first patterned etch mask 235 is formed on the workpiece 200 to cover the first region 10 and the third region 30 to expose the second region 20. The first patterned etch mask 235 may be a photoresist layer or a combination of photoresist and hard mask layer. The hard mask layer may comprise silicon oxide, silicon nitride, or a combination thereof. With the first pattern etch mask 235 in place, the workpiece 200 is subjected to a dry etch process that etches the second gate structure 222 faster than the gate spacer layer 230, CESL 232, and ILD layer 234, as shown in fig. 4. In some embodiments, the dry etching process at block 104 may include a chlorine-containing species (e.g., BCl 3 、SiCl 4 、Cl 2 ) Fluorine-containing species (e.g. CF 4 Or SF (sulfur hexafluoride) 6 ) Bromine-containing substances (e.g. HBr), oxygen (O) 2 ) Or nitrogen (N) 2 ). In some example dry etching processes, boron trichloride (BCl) 3 ) May be between about 0 standard cubic centimeters per minute (SCCM) and about 1000SCCM, chlorine (Cl) 2 ) May be between about 0SCCM and about 1000SCCM, hydrogen bromide (HBr) may be between about 0SCCM and about 400SCCM, silicon tetrachloride (SiCl) 4 ) May be between about 0SCCM and about 100SCCM, oxygen (O) 2 ) May be between about 0SCCM and about 100SCCM, nitrogen (N) 2 ) May be between about 0SCCM and about 100SCCM, carbon tetrafluoride (CF) 4 ) May be at a flow rate of about 0SCCM and about 100SCCM, and sulfur hexafluoride (SF 6 ) May be between about 0SCCM and about 50 SCCM. In some embodiments, the Radio Frequency (RF) power of the dry etching process may be between 300W and 1800W and the bias power of the dry etching process may be between 0W and 100W. As shown in fig. 4, the recess at block 104 forms a leading recess 240 in the second gate structure 222. After the formation of the lead grooves 240, the first patterned etching mask 235 on the first region 10 and the third region 30 is removed by ashing or selective etching, or the like. At this stage, the height of the second gate structure 222 is smaller than the heights of the first gate structure 220 and the third gate structure 224 due to the formation of the lead groove 240.
Referring to fig. 1 and 5, the method 100 includes a block 106 in which a first gate structure 220 of the first transistor structure 12, a second gate structure 222 of the second transistor structure 22, and a third gate structure 224 of the third transistor structure 32 are blanket (global) recessed to form a first gate recess 242, a second gate recess 243, and a third gate recess 244. After removing the first patterned etch mask 235, the first gate structure 220, the second gate structure 222, and the third gate structure 224 are subjected to the same global etching process at block 106. The global etching process may include similar chemicals and conditions as the dry etching process at block 104. In other words, the operations at blocks 104 and 106 substantially etch the second gate structure 222 twice, while the first gate structure 220 and the third gate structure 224 are etched once. The blanket etch at block 106 forms a first gate recess 242 over the first gate structure 220, extends the leading recess 240 further into the second gate structure 222 to form a second gate recess 243, and forms a third gate recess 244 over the third gate structure 224. As shown in fig. 5, the first gate groove 242 has a first depth D1, the second gate groove 243 has a second depth D2, and the third gate groove 244 has a third depth D3. In the illustrated embodiment, the second depth D2 is greater than the first depth D1 or the third depth D3. The first depth D1 may be very similar to the third depth D1 because the global etching process at block 106 etches the n-type work function layer 210 and the p-type work function layer 212 at substantially the same rate. In contrast, since the second depth D2 is larger, the height of the second gate structure 222 is smaller than the height of the first gate structure 220 or the third gate structure 224. The second gate structure 222 is subjected to an additional etch in terms of the consumption of the work function layer. As a result, the threshold voltage determining material (such as aluminum) in the second gate structure 222 is consumed more. Since both the first transistor structure 12 and the second transistor structure 22 are n-type transistor structures, the second transistor structure 22 may have a higher threshold voltage due to the additional consumption of aluminum in the second gate structure 222.
Referring to fig. 1 and 6, the method 100 includes a block 108 in which a cap layer 250 is deposited over the first, second, and third gate recesses 242, 243, 244. In some embodiments, cap layer 250 may include silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbide, aluminum oxide, zirconium silicate (ZrSiO) 4 ) Hafnium silicate (HfSiO) 4 ) Hafnium oxide or zirconium oxide. Because cap layer 250 serves to protect the gate structure during the formation of a self-aligned contact (SAC), cap layer 250 may also be referred to as SAC cap layer 250 or contact hard mask 250. Thereafter, a planarization process, such as a CMP process, may be performed to remove excess material over ILD layer 234, thereby making the top surfaces of cap layer 250, CESL 232, and ILD layer 234 coplanar.
Referring to fig. 1 and 7, the method 100 includes a block 110 in which source/drain contacts 260 are formed. Operations at block 110 may include forming source/drain contact openings through ILD layer 234 and CESL 232, forming a silicide layer 256 over source/drain features 206, and forming a metal fill layer 258 over silicide layer 256. In some embodiments, the cap layer 250, the gate spacer layer 230, and the CESL 232 are utilized to protect the gate structures (i.e., the first gate structure 220, the second gate structure 222, and the third gate structure 224), and the workpiece 200 is anisotropically etched to form source/drain contact openings exposing the source/drain features 206 in the first region 10, the second region 20, and the third region 30. Because of the self-aligned nature, here, the operations at block 110 do not use photolithographic techniques. In other words, block 110 does not use a photomask.
In the illustrated embodiment, to reduce contact resistance, silicide layer 256 may be formed on exposed surfaces of source/drain feature 206 by depositing a metal precursor layer over source/drain feature 206 and performing an annealing process to effect silicidation between the metal precursor layer and source/drain feature 206. Suitable metal precursor layers may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). Silicide layer 256 may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi).
After the silicide layer 256 is formed, a metal fill layer 258 may be deposited into the contact openings to form source/drain contacts 260. The metal filling layer may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), or tantalum nitride (TaN). As shown in fig. 7, a silicide layer 256 is disposed between the source/drain features 206 and a metal fill layer 258. Silicide layer 256 and metal filler layer 258 over source/drain features 206 may be collectively referred to as source/drain contacts 260. In the illustrated embodiment, the sidewalls of the source/drain contacts 260 are in direct contact with the CESL 232. After depositing the metal fill layer 258, the workpiece 200 is planarized to remove excess material so that the top surfaces of the source/drain contacts 260, CESL 232, and cap layer 250 are coplanar, as shown in fig. 7.
Still referring to fig. 7. As shown by the dashed lines across the first gate structure 220, the second gate structure 222, and the third gate structure 224, the gate heights of the first gate structure 220 and the third gate structure 224 are greater than the gate height of the second gate structure 222 by a gate height difference E. Likewise, the cap layer 250 over the second gate structure 222 is also thicker than the cap layer 250 over the first gate structure 220 or the third gate structure 224 by a gate height difference E. In some cases, the gate height difference E may be between about 3nm and about 14 nm.
Fig. 8 illustrates a method 300. As described below, method 300 differs from method 100 in that method 300 achieves different gate recess depths through different gate recess rates for different gate structures, rather than through photolithography.
Reference is made to fig. 8 and 2. The method 300 includes a block 302 in which the workpiece 200 includes a first transistor structure 12 over a first region 10, a second transistor structure 22 over a second region 20, and a third transistor structure 32 over a third region 30. The operations at block 302 are substantially similar to the operations at block 102 described in connection with fig. 2. Accordingly, a detailed description of the operations at block 302 is omitted for brevity.
Referring to fig. 8 and 9, the method 300 includes a block 304 in which the first gate structure 220 of the first transistor structure 12, the second gate structure 222 of the second transistor structure 22, and the third gate structure 224 of the third transistor structure 32 are fully recessed to form a first gate recess 242, a second gate recess 243, and a third gate recess 244. In some embodiments, the global etching process at block 304 may include similar chemicals as the dry etching process at block 104, but may implement lower RF (radio frequency) power and weaker bias to increase etch selectivity. In some alternative embodiments, the global etching process at block 304 is configured to etch the n-type work function layer 210 and the p-type work function layer 212 at different rates. For example, since the p-type work function layer 212 tends to include metal nitride, the blanket etch process at block 304 may be made to etch metal nitride at a greater rate or a lesser rate. In the embodiment shown in fig. 9, the global etching process at block 304 may etch the p-type work function layer 212 faster than the n-type work function layer. Accordingly, the third gate groove 244 may be deeper than the first gate groove 242 or the second gate groove 243. As shown in fig. 9, the first gate groove 242 has a first depth D1, the second gate groove 243 has a second depth D2, and the third gate groove 244 has a third depth D3. In the illustrated embodiment, the first depth D1 and the second depth D2 are substantially the same or the same, and the third depth D3 is greater than the first depth D1 or the second depth D2. In some alternative embodiments in which the blanket etch process etches the n-type work function layer 210, the third depth D3 will be the smallest of the three. The greater the depth D3 of the third gate recess, the lower the threshold voltage of the third transistor structure 32 in terms of material consumption in the work function layer.
Referring to fig. 8 and 10, the method 300 includes a block 306 in which a cap layer 250 is deposited over the first, second, and third gate recesses 242, 243, 244. The operations of block 306 are substantially similar to the operations of block 108 as described in fig. 6. Accordingly, a detailed description of the operation of block 306 is omitted for brevity. It is noted, however, that after planarization, the cap layer 250 over the third gate structure 224 is thickest, while the cap layer 250 over the first gate structure 220 and the second gate structure 222 have the same thickness.
Reference is made to fig. 8 and 11. The method 300 includes a block 308 in which the source/drain contacts 260 are formed. The operations at block 308 are substantially similar to the operations at block 110 described in connection with fig. 7. Accordingly, a detailed description of the operation of block 308 is omitted for brevity. As shown by the dashed lines crossing the first gate structure 220, the second gate structure 222, and the third gate structure 224 in fig. 11, the gate heights of the first gate structure 220 and the second gate structure 222 are higher than the gate height of the third gate structure 224 by a gate height difference E. Likewise, the cap layer 250 on the third gate structure 224 is also thicker than the cap layer 250 on the first gate structure 220 or the second gate structure 222 by the gate height difference E. In some cases, the gate height difference E may be between about 3nm and about 14 nm.
Fig. 12 illustrates a method 400. As described below, the method 400 includes forming the selective metal layer 270 prior to depositing the cap layer 250. A selective metal layer 270 is selectively deposited on the recessed gate structure to reduce gate resistance. It has been observed that implementing the selective metal layer 270 can effectively reduce the threshold voltage of the p-type transistor. The implementation of the selective metal layer 270 for an n-type transistor tends to produce the opposite result.
Reference is made to fig. 12 and 2. The method 400 includes a block 402 in which the workpiece 200 includes a first transistor structure 12 over a first region 10, a second transistor structure 22 over a second region 20, and a third transistor structure 32 over a third region 30. The operations at block 402 are substantially similar to the operations at block 102 described in connection with fig. 2. Accordingly, a detailed description of the operations at block 402 is omitted for brevity.
Referring to fig. 12 and 13, method 400 includes a block 404 in which first gate structure 220 of first transistor structure 12, second gate structure 222 of second transistor structure 22, and third gate structure 224 of third transistor structure 32 are fully recessed to form first gate recess 242, second gate recess 243, and third gate recess 244. The operations at block 404 are substantially similar to the operations at block 106 described in connection with fig. 5. Accordingly, a detailed description of the operation of block 404 is omitted for brevity. Unlike the one shown in fig. 5, the first, second and third gate grooves 242, 243 and 244 in fig. 13 have the same depth since the gate structure is not first selectively recessed. That is, the first depth D1, the second depth D2, and the third depth D3 in fig. 13 are substantially the same.
Referring to fig. 12 and 14, the method 400 includes a block 406 in which a selective metal layer 270 is deposited over the first gate structure 220, the second gate structure 222, and the third gate structure 224. In some embodiments, the selective metal layer 270 may include titanium (Ti), tantalum (Ta), aluminum (Al), molybdenum (Mo), tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), zirconium (Zr), combinations thereof, or conductive compounds thereof. In some examples, the selective metal layer 270 may include a titanium-containing compound, such as titanium nitride (TiN), or a tantalum-containing compound, such as tantalum nitride (TaN). The selective metal layer 270 may be selectively deposited on a conductive surface, such as the surface of the n-type work function layer 210, the p-type work function layer 212, or a metal fill layer (not shown), by Atomic Layer Deposition (ALD) or Plasma Enhanced ALD (PEALD). For example, when the selective metal layer 270 includes titanium nitride, the deposition of the selective metal layer 270 may include using tetra (dimethylamino) titanium (TDMAT) and ammonia (NH) 3 ) Or titanium tetrachloride (Ti)Cl 4 ) And ammonia gas. In some embodiments, the selective metal layer 270 may have a thickness between about 1nm and about 8 nm. When the thickness of the selective metal layer 270 is less than 1nm, the threshold voltage shift effect of the selective metal layer 270 may not be detected. When the thickness of the selective metal layer 270 is greater than 8nm, the selective metal layer 270 may replace the cap layer 250 too much to provide sufficient protection for the gate structure.
Referring to fig. 12 and 15, the method 400 includes a block 408 in which a cap layer 250 is deposited over the first gate recess 242, the second gate recess 243, and the third gate recess 244. The operations at block 408 are substantially similar to the operations at block 108 described in connection with fig. 6. Accordingly, a detailed description of the operation of block 408 is omitted for brevity. Unlike that shown in fig. 6, the operation at block 408 deposits a cap layer 250 over the selective metal layer 270 on each of the first gate structure 220, the second gate structure 222, and the third gate structure 224.
Referring to fig. 12 and 16, the method 400 includes a block 410 in which the source/drain contacts 260 are formed. The operations at block 410 are substantially similar to the operations at block 110 described in connection with fig. 7. Accordingly, a detailed description of the operation of block 410 is omitted for brevity. Unlike the illustration of fig. 7, the first gate structure 220, the second gate structure 222, and the third gate structure 224 in fig. 16 have the same gate height.
Fig. 17 illustrates a method 500. As described below, method 500 incorporates the formation of selective metal layer 270 associated with method 400 into method 100.
Referring to fig. 17 and 2, method 500 includes block 502 in which workpiece 200 includes first transistor structure 12 over first region 10, second transistor structure 22 over second region 20, and third transistor structure 32 over third region 30. The operations at block 502 are substantially similar to the operations at block 102 described in connection with fig. 2. Accordingly, a detailed description of the operations at block 502 is omitted for brevity.
Referring to fig. 17, 18, and 19, method 500 includes block 504 in which second gate structure 222 of second transistor structure 22 is selectively recessed. The operations at block 504 are substantially similar to the operations at block 104 described in connection with fig. 3 and 4. Accordingly, a detailed description of the operations at block 504 is omitted for brevity. Fig. 18 and 19 are similar to fig. 3 and 4, and the description of fig. 3 and 4 applies substantially to fig. 18 and 19.
Reference is made to fig. 17 and 20. The method 500 includes a block 506 in which the first gate structure 220 of the first transistor structure 12, the second gate structure 222 of the second transistor structure 22, and the third gate structure 224 of the third transistor structure 32 are fully recessed to form a first gate recess 242, a second gate recess 243, and a third gate recess 244. The operations at block 506 are substantially similar to the operations at block 106 described in connection with fig. 5. Accordingly, a detailed description of the operations in block 506 is omitted for brevity. Fig. 20 is similar to fig. 5, and the description of fig. 5 applies basically to fig. 20 as well. It is noted that the relationship among the first depth D1, the second depth D2, and the third depth D3 in fig. 5 is also applicable to the corresponding items in fig. 20.
Referring to fig. 17 and 21, method 500 includes block 508 in which a selective metal layer 270 is deposited over first gate structure 220, second gate structure 222, and third gate structure 224. The operations at block 508 are substantially similar to the operations at block 406 described in connection with fig. 14. Accordingly, a detailed description of the operations at block 508 is omitted for brevity. However, it should be noted that the gate heights of the first gate structure 220, the second gate structure 222, and the third gate structure 224 in fig. 21 are different from those in fig. 14.
Referring to fig. 17 and 22, method 500 includes block 510 in which a cap layer 250 is deposited over first gate recess 242, second gate recess 243, and third gate recess 244. The operations at block 510 are substantially similar to the operations at block 408 described in connection with fig. 15.
Referring to fig. 17 and 23, method 500 includes block 512 in which source/drain contacts 260 are formed. The operations of block 512 are substantially similar to the operations of block 410 described in connection with fig. 16.
Fig. 24 illustrates a method 600. As described below, method 600 includes more than one selective gate recess process to recess the gate structures individually to achieve modulation of threshold voltages between different transistor structures.
Referring to fig. 24 and 2, method 600 includes block 602 in which workpiece 200 includes first transistor structure 12 over first region 10, second transistor structure 22 over second region 20, and third transistor structure 32 over third region 30. The operations at block 602 are substantially similar to the operations at block 102 described in connection with fig. 2. Accordingly, a detailed description of the operations at block 602 is omitted for brevity.
Referring to fig. 24, 25 and 26, the method 600 includes a block 604 in which the second gate structure 222 of the second transistor structure 22 is selectively recessed to form a second gate recess 243. The operations at block 604 are substantially similar to the operations at block 104 described in connection with fig. 3 and 4. Accordingly, a detailed description of the operations in block 604 is omitted for brevity. Fig. 25 and 26 are similar to fig. 3 and 4, and the description of fig. 3 and 4 applies substantially to fig. 25 and 26. Instead of the leading recess 240, the operation of forming the second gate recess 243 at block 604 does not have a further recessing process for the second gate structure 222.
Referring to fig. 24, 27 and 28, method 600 includes block 606 in which first gate structure 220 of first transistor structure 12 and third gate structure 224 of third transistor structure 32 are selectively recessed to form first gate recess 242 and third gate recess 244. Similar to the selective recess at block 604, the selective recess at block 606 may include using a photolithography and etching process. In the embodiment shown in fig. 27, a second pattern etch mask 236 is formed over the workpiece 200 to cover the second region 20 to expose the first region 10 and the third region 30. The second patterned etch mask 236 may be a photoresist layer or a combination of photoresist and hard mask layer. The hard mask layer may comprise silicon oxide, silicon nitride, or a combination thereof. With the second pattern etch mask 236 in place, the workpiece 200 is dry etched, which etches the first gate structure 220 and the third gate structure 224 faster than the gate spacer layer 230, the CESL 232, and the ILD layer 234, as shown in fig. 27. In some embodiments, the dry etching process at block 606 may include a chlorine-containing species (e.g., BCl 3 、SiCl 4 、Cl 2 ) Fluorine-containing species (e.g. CF 4 Or SF (sulfur hexafluoride) 6 ) Bromine-containing substances (e.g. HBr), oxygen (O) 2 ) Or nitrogen (N) 2 ). In some example dry etching processes, boron trichloride (BCl) 3 ) May be between about 0 standard cubic centimeters per minute (SCCM) and about 1000SCCM, chlorine (Cl) 2 ) May be between about 0SCCM and about 1000SCCM, hydrogen bromide (HBr) may be between about 0SCCM and about 400SCCM, silicon tetrachloride (SiCl) 4 ) May be between about 0SCCM and about 100SCCM, oxygen (O) 2 ) May be between about 0SCCM and about 100SCCM, nitrogen (N) 2 ) May be between about 0SCCM and about 100SCCM, carbon tetrafluoride (CF) 4 ) May be at a flow rate of about 0SCCM and about 100SCCM, sulfur hexafluoride (SF 6 ) May be between about 0SCCM and about 50 SCCM. In some embodiments, the Radio Frequency (RF) power of the dry etching process at block 606 may be between 300W and 1800W and the bias power of the dry etching process may be between 0W and 100W. As shown in fig. 27, the recess at block 606 forms a first gate recess 242 over the first gate structure 220 and a third gate recess 244 over the third gate structure 224. After the first and third gate grooves 242 and 243 are formed, the second pattern etching mask 236 on the second region 20 is removed, for example, by ashing or selective etching or the like.
In some embodiments, shown in fig. 28, the selective recessing is performed at block 606 such that the first gate recess 242 and the third gate recess 244 are deeper than the second gate recess 243. In fig. 28, the first gate groove 242 has a first depth D1, the second gate groove 243 has a second depth D2, and the third gate groove 244 has a third depth D3. In the illustrated embodiment, the second depth D2 is less than the first depth D1 or the third depth D3, and the first depth D2 may be very similar to the third depth D1 since the recess at block 606 etches the n-type work function layer 210 and the p-type work function layer 212 at substantially the same rate. In contrast, since the first depth D1 is greater, the height of the second gate structure 222 is greater than the height of the first gate structure 220 or the third gate structure 224. The first gate structure 220 and the third gate structure 224 are subjected to additional etching in terms of the consumption of the work function layer. As a result, the threshold voltage determining material (such as aluminum) in the first gate structure 220 is consumed more. Since both the first transistor structure 12 and the second transistor structure 22 are n-type transistor structures, the first transistor structure 12 may have a higher threshold voltage due to the additional consumption of aluminum in the first gate structure 220.
Referring to fig. 24 and 29, the method 600 includes a block 608 in which a cap layer 250 is deposited over the first gate recess 242, the second gate recess 243, and the third gate recess 244. The operations at block 608 are substantially similar to the operations at block 108 described in connection with fig. 6. Accordingly, a detailed description of the operation of block 608 is omitted for brevity. Fig. 29 is similar to fig. 6, and the description of fig. 6 basically applies to fig. 29 as well. As shown in fig. 29, the cap layer 250 over the first gate structure 220 and the third gate structure 224 is thicker than the cap layer 250 over the second gate structure 222.
Referring to fig. 24 and 30, method 600 includes block 610 in which source/drain contacts 260 are formed. The operations at block 610 are substantially similar to the operations at block 110 described in connection with fig. 7. Accordingly, a detailed description of the operation of block 610 is omitted for brevity. Fig. 30 is similar to fig. 7, and the description of fig. 7 applies basically to fig. 30 as well. As shown by the dashed lines across the first gate structure 220, the second gate structure 222, and the third gate structure 224, the gate height of the second gate structure 222 is higher than the gate heights of the first gate structure 220 and the third gate structure 224 by a gate height difference E.
Referring to fig. 31 and 32, method 700 includes block 702 in which workpiece 200 includes first transistor structure 12 over first region 10, second transistor structure 22 over second region 20, and third transistor structure 32 over third region 30. The workpiece 200 shown in fig. 32 is similar in many respects to the workpiece 200 shown in fig. 2. However, unlike the workpiece 200 in fig. 2, the workpiece 200 in fig. 32 does not include the n-type work function layer 210 or the p-type work function layer 212 formed over the channel region 204C of the first region 10, the second region 20, and the third region 30. In contrast, the workpiece 200 of fig. 32 includes a first gate trench 221 over the first region 10, a second gate trench 223 over the second region 20, and a third gate trench 225 over the third region 30. Each of the first gate trench 221, the second gate trench 223, and the third gate trench 225 exposes the gate dielectric layer 208 disposed on the interfacial layer 207.
Referring to fig. 31 and 33, the method 700 includes block 704 in which a dipole induction layer 209 is deposited over the gate dielectric layer 208. In some embodiments, dipole induction layer 209 comprises aluminum oxide, zirconium oxide, zinc oxide, yttrium oxide, or lanthanum oxide. Among these materials, alumina and zirconia may create dipole moments that tend to lower the threshold voltage of p-type devices, while zinc oxide, yttrium oxide, or lanthanum oxide may create dipole moments that tend to lower the threshold voltage of n-type devices. Dipole induction layer 209 may be deposited using ALD, remote Plasma ALD (RPALD), or CVD. In some cases, the thickness of the dipole induction layer 209 may be between aboutAnd about->Between them. As shown in fig. 32, the dipole induction layer 209 may be conformally deposited over the surfaces of the gate dielectric layer 208, ILD layer 234, CESL 232 and gate spacer layer 230.
Reference is made to fig. 31 and 34. The method 700 includes block 706, wherein the annealing process 800 is performed on the workpiece 200. In some embodiments, the annealing process 800 includes a temperature between about 500 ℃ and about 900 ℃ to cause diffusion from the dipole induction layer 209 into the gate dielectric layer 208. The annealing process 800 may be a rapid thermal annealing (RTA, rapid thermal anneal) process, a laser spike annealing process, a flash annealing process, or a furnace annealing process. After the annealing process 800 is performed, the gate dielectric layer 208 becomes a dipole gate dielectric layer 208'.
Referring to fig. 31 and 34, the method 700 includes a block 708 in which the excess dipole induction layer 209 is removed. At block 708, to make room for the n-type work function layer 210 and the p-type work function layer 212, the excess dipole induction layer 209 is removed after the annealing process 800 of block 706. In some embodimentsFor example, the excess dipole induction layer 209 may be removed using a dry etching process or a wet etching process. The excess wet etch process may include the use of phosphoric acid. An example dry etching process may include the use of boron trichloride (BCl) 3 ) Chlorine (Cl) 2 ) Or nitrogen (N) 2 )。
Referring to fig. 31 and 35, the method 700 includes a block 710 in which a gate electrode is formed over the first gate trench 221, the second gate trench 223, and the third gate trench 225. In some embodiments shown in fig. 35, an n-type work function layer 210 is deposited over the first gate trench 221 and the second gate trench 223, and a p-type work function layer 212 is deposited over the third gate trench 225. As such, the first gate structure 220 and the second gate structure 222 include the n-type work function layer 210, while the third gate structure 224 includes the p-type work function layer 212. The n-type work function layer 210 may include titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum aluminum carbide (TaAlC), titanium aluminum carbide (TiAlC), silicon doped tantalum aluminum carbide (TaAlC: si), silicon doped titanium aluminum carbide, or a combination thereof. The p-type work function layer 212 may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or tantalum carbide (TaC). Although not explicitly shown, each of the first gate structure 220, the second gate structure 222, and the third gate structure 224 may further include a metal fill layer over the n-type work function layer 210 or the p-type work function layer 212. The metal fill layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), other refractory metals, or other suitable metallic materials, or combinations thereof. The metal fill layer and the respective work function layer may be collectively referred to as a gate electrode.
Referring to fig. 31, 36, and 37, method 700 includes block 712, wherein second gate structure 222 of second transistor structure 22 is selectively recessed. The operation of block 712 is substantially similar to the operation of block 104 described in connection with fig. 3 and 4. Accordingly, a detailed description of the operation of block 712 is omitted for brevity. Fig. 36 and 37 are similar to fig. 3 and 4, and the description of fig. 3 and 4 applies substantially to fig. 36 and 37. Note that each of the first gate structure 220, the second gate structure 222, and the third gate structure 224 in fig. 37 includes a dipole gate dielectric layer 208'.
Refer to fig. 31 and 38. The method 700 includes a block 714 in which the first gate structure 220 of the first transistor structure 12, the second gate structure 222 of the second transistor structure 22, and the third gate structure 224 of the third transistor structure 32 are fully recessed to form a first gate recess 242, a second gate recess 243, and a third gate recess 244. The operations at block 714 are substantially similar to the operations at block 106 described in connection with fig. 5. Accordingly, a detailed description of the operation of block 714 is omitted for brevity. Unlike that shown in fig. 5, each of the first, second and third gate structures 220, 222 and 224 in fig. 37 includes a dipole gate dielectric layer 208'.
Referring to fig. 31 and 39, the method 700 includes a block 716 in which a cap layer 250 is deposited over the first gate recess 242, the second gate recess 243, and the third gate recess 244. The operations of block 716 are substantially similar to the operations of block 108 described in connection with fig. 6. Accordingly, a detailed description of the operation of block 716 is omitted for brevity. Fig. 39 is similar to fig. 6, and the description of fig. 6 basically applies to fig. 39 as well.
Referring to fig. 31 and 40, method 700 includes block 718 in which source/drain contacts 260 are formed. The operations at block 718 are substantially similar to the operations at block 110 described in connection with fig. 7. Accordingly, a detailed description of the operation of block 718 is omitted for brevity. Fig. 40 is similar to fig. 7, and the description of fig. 7 applies basically to fig. 40 as well. As shown by the dashed lines across the first gate structure 220, the second gate structure 222, and the third gate structure 224, the gate height of the second gate structure 222 is smaller than the gate heights of the first gate structure 220 and the third gate structure 224 by a gate height difference E. In some cases, the gate height difference E may be between about 3nm and about 14 nm.
The effect of the gate height and the presence of the selective metal layer 270 with respect to the n-type work function layer 210 or the p-type work function 212 can be summarized in the line diagrams of fig. 41 and 42. Reference is first made to fig. 41. When the goal is to provide NMOS (i.e., n-type FinFET or n-type MBC transistor) with different threshold voltages, the remaining gate height of the gate structure with n-type work function layer 210 is proportional to the decrease in threshold voltage. The presence of the selective metal layer 270 over the n-type work function layer 210 has the effect of increasing the threshold voltage. When the p-type work function layer 212 is used for the gate structure, the threshold voltage increases. When the selective metal layer 270 is formed over the p-type work function layer 212, the threshold voltage of the NMOS increases more. It is noted that, in general, the recessing of the n-type work function layer or the p-type work function layer has the effect of increasing the threshold voltage level of the NMOS.
Reference is then made to fig. 42. When the goal is to provide PMOS with different threshold voltages (i.e., p-type FinFET or p-type MBC transistors), the remaining gate height of the gate structure with p-type work function layer 212 is proportional to the threshold voltage increase. The presence of the selective metal layer 270 over the p-type work function layer 212 has the effect of lowering the threshold voltage. When the n-type work function layer 210 is used for the gate structure, the threshold voltage increases. The threshold voltage of the PMOS increases more when the selective metal layer 270 is formed over the n-type work function layer 210. It should be noted that in general, the recessing of the n-type work function layer or the p-type work function has the effect of lowering the threshold voltage level of the PMOS.
While the operations in methods 100, 300, 400, 500, 600, and 700 are described with reference to finfets, it should be understood that various methods and processes may be applied to MBC transistors. For example, fig. 43 shows a first MBC transistor 12', a second MBC transistor 22', and a third MBC transistor 32' formed using the method 100. The first MBC transistor 12' includes a first MBC gate structure 2200 wrapped around each nanostructure 2040. The nanostructures 2040 are vertically stacked above the channel region 204C in the first region 10. Along the Y-direction, the nanostructures 2040 extend between two MBC source/drain features 2060. Along the Y-direction, first MBC gate structure 2200 is spaced apart from MBC source/drain features 2060 by a plurality of internal spacer features 2075. Second MBC transistor 22' includes a second MBC gate structure 2202 wrapped around each nanostructure 2040. The nanostructures 2040 are vertically stacked above the channel region 204C in the second region 20. Along the Y-direction, the nanostructures 2040 extend between two MBC source/drain features 2060. Along the Y-direction, second MBC gate structure 2202 is spaced apart from MBC source/drain features 2060 by a plurality of internal spacer features 2075. The third MBC transistor 32' includes a third MBC gate structure 2204 wrapped around each nanostructure 2040. The nanostructures 2040 are vertically stacked on the channel region 204C in the third region 30. Along the Y-direction, the nanostructures 2040 extend between two MBC source/drain features 2060. Along the Y-direction, a third MBC gate structure 2204 is spaced apart from MBC source/drain features 2060 by a plurality of internal spacer features 2075. Each of the first MBC gate structure 2200, the second MBC gate structure 2202, and the third MBC gate structure 2204 includes a gate dielectric layer 208 wrapped around each nanostructure 2040. As shown by the dashed lines across the first MBC gate structure 2200, the second MBC gate structure 2202, and the third MBC gate structure 2204, the gate height of the second MBC gate structure 2202 is less than the gate heights of the first MBC gate structure 2200 and the third MBC gate structure 2204 by a gate height difference E. In some cases, the gate height difference E may be between about 3nm and about 14 nm.
The present disclosure provides many different embodiments. In one embodiment, a semiconductor structure is provided. The semiconductor structure includes a substrate, a first active region, a second active region, and a third active region on the substrate, a first gate structure over a channel region of the first active region, a second gate structure over a channel region of the second active region, a third gate structure over a channel region of the third active region, a first cap layer over the first gate structure, a second cap layer over the second gate structure, and a third cap layer over the third gate structure. The height of the second gate structure is smaller than the height of the first gate structure or the height of the third gate structure.
In some embodiments, the first gate structure and the second gate structure comprise an n-type work function metal layer and the third gate structure comprises a p-type work function metal layer. In some embodiments, the n-type work function metal layer comprises TiAlC, taAlC, silicon doped TiAlC, or silicon doped TaAlC, and the p-type work function metal layer comprises TiN, taN, WCN, tiSiN or TaSiN. In some examples, the semiconductor structure further comprises: a first selective metal layer disposed between the first gate structure and the first cap layer; a second selective metal layer disposed between the second gate structure and the second cap layer; and a third selective metal layer disposed between the third gate structure and the third cap layer. The first, second, and third selective metal layers comprise Ti, ta, al, mo, W, co, cu, ru, mo or Zr. In some embodiments, the first, second, and third cap layers comprise silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride carbide, silicon oxycarbide, aluminum oxide, zirconium silicate, hafnium oxide, or zirconium oxide. In some embodiments, the semiconductor structure further comprises: a first gate dielectric layer disposed between the first active region and the n-type work function metal layer; and a second gate dielectric layer disposed between the third active region and the p-type work function metal layer. In some embodiments, the first gate dielectric layer comprises lanthanum, zinc, or yttrium and the second gate dielectric layer comprises aluminum or zirconium. In some embodiments, the thickness of the third cap layer is greater than the thickness of the first cap layer or the thickness of the second cap layer.
In another embodiment, a method is provided. The method comprises the following steps: receiving a workpiece comprising a first active region, a second active region, and a third active region on a substrate, a first gate structure over a channel region of the first active region, a second gate structure over a channel region of the second active region, and a third gate structure over a channel region of the third active region; selectively recessing the second gate structure; after selectively recessing, recessing the first gate structure, the second gate structure, and the third gate structure to form a first gate recess over the first gate structure, a second gate recess over the second gate structure, and a third gate recess over the third gate structure; depositing a dielectric cap layer over the first, second and third gate recesses after recessing; and after deposition, planarizing the workpiece to reduce the thickness of the dielectric cap layer.
In some embodiments, selectively recessing the second gate structure includes: forming a patterned photoresist layer over the first gate structure and the second gate structure to expose the second gate structure; and etching the second gate structure using the patterned photoresist layer as an etch mask. In some embodiments, each of the first gate structure and the second gate structure includes an n-type work function metal layer, a third gate The structure includes a p-type work function metal layer. In some examples, the n-type work function metal layer comprises TiAlC, taAlC, silicon doped TiAlC, or silicon doped TaAlC, and the p-type work function metal layer comprises TiN, taN, WCN, tiSiN or TaSiN. In some cases, the dielectric cap layer comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbide, aluminum oxide, zirconium silicate, hafnium oxide, or zirconium oxide. In some embodiments, the method further comprises depositing a selective metal layer over the first gate recess, the second gate recess, and the third gate recess prior to depositing the dielectric cap layer. The selective metal layer includes Ti, ta, al, mo, W, co, cu, ru, mo or Zr. In some cases, recessing includes using BCl 3 、Cl 2 、HBr、SiCl 4 、O 2 、N 2 、CF 4 Or SF (sulfur hexafluoride) 6 . In some embodiments, the recess includes a power of between about 300W and about 1800W. In some embodiments, the recess includes a bias power between about 0W and about 100W.
In another embodiment, a method is provided. The method includes receiving a workpiece, the workpiece comprising: a first gate structure over the first region, the first gate structure comprising a first work function metal layer, a second gate structure over the second region, the second gate structure comprising a first work function metal layer, and a third gate structure over the third region, the third gate structure comprising a second work function metal layer; recessing the first, second and third gate structures to form first, second and third gate recesses; depositing a dielectric cap layer over the first, second and third gate recesses after recessing; and after deposition, planarizing the workpiece to reduce the thickness of the dielectric cap layer. The recessing includes etching the third gate structure faster such that the third gate recess is deeper than the first gate recess or the second gate recess.
In some embodiments, the first work function metal layer comprises TiAlC, taAlC, silicon doped TiAlC, or silicon doped TaAlC, and the second work function metal layer comprises TiN, taN, WCN, tiSiN or TaSiN. In some cases, the method may further include depositing a selective metal layer over the first gate recess, the second gate recess, and the third gate recess prior to depositing the dielectric cap layer. The selective metal layer includes Ti, ta, al, mo, W, co, cu, ru, mo or Zr.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor structure, comprising:
a substrate;
a first active region, a second active region, and a third active region over the substrate;
A first gate structure located over a channel region of the first active region;
a second gate structure over a channel region of the second active region;
a third gate structure located over a channel region of the third active region;
a first cap layer over the first gate structure;
a second cap layer over the second gate structure; and
a third cap layer over the third gate structure,
wherein the height of the second gate structure is smaller than the height of the first gate structure or the height of the third gate structure.
2. The semiconductor structure of claim 1,
wherein the first gate structure and the second gate structure comprise an n-type work function metal layer,
wherein the third gate structure includes a p-type work function metal layer.
3. The semiconductor structure of claim 2,
wherein the n-type work function metal layer comprises TiAlC, taAlC, silicon doped TiAlC or silicon doped TaAlC,
wherein the p-type work function metal layer comprises TiN, taN, WCN, tiSiN or TaSiN.
4. The semiconductor structure of claim 1, further comprising:
a first selective metal layer disposed between the first gate structure and the first cap layer;
A second selective metal layer disposed between the second gate structure and the second cap layer; and
a third selective metal layer disposed between the third gate structure and the third cap layer,
wherein the first, second, and third selective metal layers comprise Ti, ta, al, mo, W, co, cu, ru, mo or Zr.
5. The semiconductor structure of claim 1, wherein the first, second, and third cap layers comprise silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, aluminum oxide, zirconium silicate, hafnium oxide, or zirconium oxide.
6. The semiconductor structure of claim 2, further comprising:
a first gate dielectric layer disposed between the first active region and the n-type work function metal layer; and
and a second gate dielectric layer disposed between the third active region and the p-type work function metal layer.
7. The semiconductor structure of claim 6,
wherein the first gate dielectric layer comprises lanthanum, zinc, or yttrium,
wherein the second gate dielectric layer comprises aluminum or zirconium.
8. The semiconductor structure of claim 1, wherein a thickness of the third cap layer is greater than a thickness of the first cap layer or a thickness of the second cap layer.
9. A method of forming a semiconductor structure, comprising:
receiving a workpiece, the workpiece comprising:
a first active region, a second active region, and a third active region, over the substrate,
a first gate structure over a channel region of the first active region,
a second gate structure over the channel region of the second active region, and
a third gate structure located over a channel region of the third active region;
selectively recessing the second gate structure;
after selectively recessing, recessing the first gate structure, the second gate structure, and the third gate structure to form a first gate recess over the first gate structure, a second gate recess over the second gate structure, and a third gate recess over the third gate structure;
depositing a dielectric cap layer over the first, second, and third gate recesses after recessing; and
after the deposition, the workpiece is planarized to reduce the thickness of the dielectric cap layer.
10. A method of forming a semiconductor structure, comprising:
receiving a workpiece, the workpiece comprising:
A first gate structure over the first region, the first gate structure comprising a first work function metal layer,
a second gate structure over the second region, the second gate structure including a first work function metal layer, and
a third gate structure over the third region, the third gate structure comprising a second work function metal layer;
recessing the first, second and third gate structures to form first, second and third gate recesses;
depositing a dielectric cap layer over the first gate recess, the second gate recess, and the third gate recess after the recessing; and
after the deposition, planarizing the workpiece to reduce the thickness of the dielectric cap layer,
wherein the recessing includes etching the third gate structure faster such that the third gate recess is deeper than the first gate recess or the second gate recess.
CN202310464379.0A 2022-07-08 2023-04-26 Semiconductor structure and forming method thereof Pending CN116978935A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US63/359,284 2022-07-08
US63/393,489 2022-07-29
US17/899,021 US20240014256A1 (en) 2022-07-08 2022-08-30 Threshold voltage modulation by gate height variation
US17/899,021 2022-08-30

Publications (1)

Publication Number Publication Date
CN116978935A true CN116978935A (en) 2023-10-31

Family

ID=88477358

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310464379.0A Pending CN116978935A (en) 2022-07-08 2023-04-26 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN116978935A (en)

Similar Documents

Publication Publication Date Title
US11532735B2 (en) Self-aligned epitaxy layer
CN109427776B (en) Self-aligned structure for semiconductor device, semiconductor structure and forming method thereof
US11411090B2 (en) Contact structures for gate-all-around devices and methods of forming the same
CN106816381B (en) Semiconductor device and method for manufacturing the same
TWI666728B (en) Semiconductor device and manufacturing method thereof
US9865709B2 (en) Selectively deposited spacer film for metal gate sidewall protection
CN111243959B (en) Semiconductor device and method for manufacturing the same
KR102548662B1 (en) Field-effect transistor device with gate spacer structure
TWI795748B (en) Method of manufacturing a semiconductor device and a semiconductor device
TWI784512B (en) Semiconductor device and method of forming the same
TWI707407B (en) Method of manufacturing a semiconductor device and a semiconductor device
US20220285512A1 (en) Semiconductor Device With Gate Isolation Features And Fabrication Method Of The Same
TWI770748B (en) Semiconductor devices and methods for manufacturing the same
KR20220043843A (en) Etch profile control of gate contact opening
US20240014256A1 (en) Threshold voltage modulation by gate height variation
CN116978935A (en) Semiconductor structure and forming method thereof
US20240014292A1 (en) Gate-top dielectric structure for self-aligned contact
KR102501422B1 (en) Semiconductor device and manufacturing method thereof
CN116978952A (en) Semiconductor structure and forming method thereof
TW202329254A (en) Semiconductor device and method for forming the same
KR20230158405A (en) Under epitaxy isolation structure
KR20220043840A (en) Etch profile control of via opening

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination