CN116978860A - Integrated circuit device including backside power rail and method of forming the same - Google Patents

Integrated circuit device including backside power rail and method of forming the same Download PDF

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Publication number
CN116978860A
CN116978860A CN202310478465.7A CN202310478465A CN116978860A CN 116978860 A CN116978860 A CN 116978860A CN 202310478465 A CN202310478465 A CN 202310478465A CN 116978860 A CN116978860 A CN 116978860A
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China
Prior art keywords
layer
forming
etch stop
insulator
contact plug
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CN202310478465.7A
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Chinese (zh)
Inventor
郑明勋
洪元赫
曹健浩
黄寅灿
徐康一
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from US17/936,106 external-priority patent/US20230352408A1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN116978860A publication Critical patent/CN116978860A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure relates to integrated circuit devices and methods of forming the same. Methods of forming integrated circuit devices may include providing first and second active regions, an isolation layer, and first and second sacrificial stacks. The first sacrificial stack structure and the second sacrificial stack structure may contact the first active region and the second active region, and each of the first sacrificial stack structure and the second sacrificial stack structure may include a channel layer and a sacrificial layer. The method may further include forming an etch stop layer on the isolation layer, replacing portions of the first sacrificial stack structure and the second sacrificial stack structure with first source/drain regions and second source/drain regions, forming a front contact including a front contact plug, forming a back insulator, and forming a back contact plug in the isolation layer and the back insulator. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.

Description

Integrated circuit device including backside power rail and method of forming the same
Technical Field
The present disclosure relates generally to the field of electronics, and more particularly, to integrated circuit devices including backside power rails.
Background
Various structures of integrated circuit devices and methods of forming the same have been proposed to simplify the middle-or back-end-of-line (MOL) portions of device fabrication, thereby improving the degree of integration of the devices. For example, the back side power rails may simplify the BEOL portion of device fabrication. However, the integrated circuit device may include high aspect ratio contacts that electrically connect elements on the front and back sides of the substrate when including the back side power rails.
Disclosure of Invention
According to some embodiments of the invention, a method of forming an integrated circuit device may include providing a substrate including a front surface and a back surface opposite the front surface. The first and second active regions, the isolation layer, and the first and second sacrificial stacks may be provided on a front surface of the substrate, the isolation layer may be between the first and second active regions, the first and second sacrificial stacks may contact upper surfaces of the first and second active regions, respectively, and the first and second sacrificial stacks may each include a channel layer and a sacrificial layer. The method may further include forming an etch stop layer on an upper surface of the isolation layer; replacing portions of the first sacrificial stack structure and the second sacrificial stack structure with first source/drain regions and second source/drain regions, respectively; forming a front contact contacting the first source/drain region, wherein the front contact may include a front contact plug between the first source/drain region and the second source/drain region; forming a back insulator on a lower surface of the isolation layer; and a back contact plug formed in the isolation layer and the back insulator and contacting a lower surface of the front contact plug. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.
According to some embodiments of the present invention, a method of forming an integrated circuit device may include providing a substrate on which a front structure is provided. The substrate may include a front surface and a back surface opposite the front surface, and the front structure may include first and second active regions protruding from the front surface of the substrate, an isolation layer between the first and second active regions, an etch stop layer on the isolation layer, first and second channel layers on the first and second active regions, respectively, first and second source/drain regions on the first and second active regions and contacting the first and second channel layers, respectively, and a gate structure crossing the first and second channel layers and the isolation layer. The method may further include forming a front contact contacting the first source/drain region; forming a back side insulator after forming the front contact, wherein an isolation layer may be between the etch stop layer and the back side insulator; and a back contact plug formed in the isolation layer and the back insulator and contacting the front contact.
According to some embodiments of the present invention, an integrated circuit device may include a first active region and a second active region spaced apart from each other in a first horizontal direction; first and second source/drain regions overlapping the first and second active regions, respectively; an isolation layer between the first active region and the second active region; a first insulator on the spacer layer between the first source/drain region and the second source/drain region; an etch stop layer between the isolation layer and the first insulator; a front contact in the first insulator and contacting the first source/drain region, wherein the front contact may include a front contact plug between the first source/drain region and the second source/drain region; a back side insulator, wherein the isolation layer is between the etch stop layer and the back side insulator; and a back contact plug in the back insulator and the isolation layer and contacting the front contact plug. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.
Drawings
Fig. 1 is a layout of an integrated circuit device according to some embodiments.
Fig. 2A and 2B are cross-sectional views of an integrated circuit device, taken along lines A-A and B-B, respectively, in fig. 1, according to some embodiments.
Fig. 3 is a flow chart of a method of forming an integrated circuit device according to some embodiments.
Fig. 4-12, 13A, 13B, and 14-21 are diagrams illustrating methods of forming integrated circuit devices according to some embodiments.
Fig. 22 and 23 each illustrate a cross-sectional view of an integrated circuit device taken along line A-A in fig. 1, according to some embodiments.
Fig. 24A and 24B each illustrate the IR region in fig. 2A, according to some embodiments.
Detailed Description
The formation of the high aspect ratio contact may involve an etching process for forming a deep, narrow opening in the insulator and a deposition process for forming a conductive layer in the deep, narrow opening. Various defects may occur during these processes. For example, the bottom of the opening may be undesirably narrow or may not expose the underlying conductor, resulting in a poor electrical connection between the contact subsequently formed in the opening and the underlying conductor. Furthermore, it may be difficult to completely fill deep, narrow openings with a conductive layer, and cavities may be formed in high aspect ratio contacts. The cavity may increase the resistance of the high aspect ratio contact.
According to some embodiments of the present invention, instead of a single high aspect ratio contact, two contacts may be formed separately, each having a relatively low aspect ratio, and the two contacts may be electrically connected to each other to function as a single contact. Thus, defects associated with the formation of high aspect ratio contacts may be reduced.
Fig. 1 is a layout of an integrated circuit device according to some embodiments, and fig. 2A and 2B are cross-sectional views of the integrated circuit device according to some embodiments taken along lines A-A and B-B, respectively, in fig. 1. In fig. 1, several elements in fig. 2A and 2B, such as elements of the Back End Structure (BES) 48, are not shown for simplicity of the drawing.
Referring to fig. 1, 2A and 2B, the integrated circuit device may include an active region 12 (e.g., a first active region 12_1 and a second active region 12_2 that are directly adjacent to each other). The active regions 12 may be spaced apart from each other in a first direction X (also referred to as a first horizontal direction) and may extend longitudinally in a second direction Y (also referred to as a second horizontal direction). As used herein, "two elements a immediately adjacent to each other" (or similar language) means that no other element a is located between the two elements a. The active region 12 may comprise one or more semiconductor materials, such as Si, ge, siGe, gaP, gaAs, siC, siGeC and/or InP. In some embodiments, active region 12 may include Si.
As shown in fig. 1, in a top view, the isolation layer 11 may surround the active regions 12, and may include portions thereof each that may be between directly adjacent active regions 12 and may separate those active regions 12 from each other. The first direction X and the second direction Y may be perpendicular to each other and may be parallel to the upper surface of the isolation layer 11. As used herein, "upper surface of element a" may refer to the surface of element a facing the BES 48.
The channel layer 13 (e.g., the first channel layer 13_1 and the second channel layer 13_2) may be provided. In some embodiments, a plurality of channel layers 13 stacked in the third direction Z (also referred to as a vertical direction) may be provided on a single active region 12, and may vertically overlap the single active region 12. For example, three first channel layers 13_1 may be provided on the first active region 12_1 and may vertically overlap the first active region 12_1, as shown in fig. 2B. Various numbers (e.g., one, two, or more than three) of channel layers 13 may be stacked on a single active region 12. The third direction Z may be perpendicular to the first direction X and the second direction Y.
For example, each channel layer 13 may include semiconductor material(s) (e.g., si, ge, siGe, gaP, gaAs, siC, siGeC and/or InP). In some embodiments, each channel layer 13 may be a nanoplate (which may have a thickness in the range of about 1nm to about 100nm in the third direction Z) or may be a nanowire (which may have a circular cross-section having a diameter in the range of about 1nm to about 100 nm).
A pair of source/drain regions 14 spaced apart from each other in the second direction Y may be provided on a single active region 12 and may contact the single active region 12. The first source/drain region 14_1 and the third source/drain region 14_3 may be provided on the first active region 12_1 and may contact the first active region 12_1. The source/drain regions 14 may comprise, for example, semiconductor material (e.g., si, ge, siGe, gaP, gaAs, siC, siGeC and/or InP) and may optionally comprise impurities (e.g., B, P or As).
Gate structure 18 may be provided on active region 12. The gate structure 18 may span the active region 12 and may be provided on the channel layer 13. The gate structure 18 may surround the channel layer 13 as shown in fig. 2B. Although the gate structure 18 is shown as a single layer, the gate structure 18 may include multiple layers. For example, the gate structure 18 may include a gate electrode and a gate insulator. Each gate insulator may be provided between a gate electrode and the channel layer 13. For example, the gate electrode may include a semiconductor layer (e.g., a polysilicon layer), a work function layer (e.g., a TiC layer, a TiAl layer, a TiAlC layer, or a TiN layer), and/or a metal layer (e.g., a tungsten layer, an aluminum layer, or a copper layer), and the gate insulator may include a silicon oxide layer and/or a high-k material (e.g., al 2 O 3 、HfO 2 、ZrO 2 、HfZrO 4 、TiO 2 、Sc 2 O 3 、Y 2 O 3 、La 2 O 3 、Lu 2 O 3 、Nb 2 O 5 Or Ta 2 O 5 )。
The first active region 12_1, the first channel layer 13_1, the first and third source/drain regions 14_1 and 14_3, and the portion of the gate structure 18 interposed between the first and third source/drain regions 14_1 and 14_3 may constitute a first transistor, and the second active region 12_2, the second channel layer 13_2, the second and fourth source/drain regions 14_2 and 14_4, and the portion of the gate structure 18 interposed between the second and fourth source/drain regions 14_2 and 14_4 may constitute a second transistor.
The first insulator 10 may be provided on the isolation layer 11 and the active region 12, and the source/drain region 14 may be provided in the first insulator 10. The first insulator 10 may electrically isolate adjacent source/drain regions 14 from each other and may electrically isolate the gate structure 18 from the source/drain regions 14.
The etch stop layer 16 may be provided between directly adjacent active regions 12 (e.g., the first active region 12_1 and the second active region 12_2) and on portions of the isolation layer 11 that are located between those active regions 12. The etch stop layer 16 may contact the upper surface of the isolation layer 11 and may contact the immediately adjacent active region 12. In some embodiments, the length of the etch stop layer 16 in the second direction Y may be similar or identical to the length of the active region 12 in the second direction Y, as shown in fig. 1. Accordingly, the etch stop layer 16 may be provided on and may contact the entire upper surface of the portion of the isolation layer 11 located between the directly adjacent active regions 12, and the etch stop layer 16 may include a portion overlapping the gate structure 18, as shown in fig. 2B. In some embodiments, the etch stop layer 16 may contact the gate structure 18 (e.g., a lower surface of the gate structure 18), as shown in fig. 2B. For example, the etch stop layer 16 may include silicon nitride and/or silicon oxynitride and may have a thickness in the third direction Z in the range of about 0.5nm to about 15 nm.
Referring to fig. 2A, the uppermost surface 16U of the etch stop layer 16 may not protrude upward beyond the lower surface of the source/drain region 14. Thus, the etch stop layer 16 may not include portions interposed between immediately adjacent source/drain regions 14. When the etch stop layer 16 includes a portion interposed between immediately adjacent source/drain regions 14, if the etch stop layer 16 has a dielectric constant higher than that of the first insulator 10, parasitic capacitance between those adjacent source/drain regions 14 may increase.
Referring to fig. 2A and 2B, an upper surface of the etch stop layer 16 may include a recess 16R. In some embodiments, a center 16C of the recess 16R in the first direction X may be aligned with a center 11C of a portion of the isolation layer 11 between the active regions 12.
Front contacts 22 and source/drain contacts 24 may be provided in the first insulator 10. The front contact 22 may contact the first source/drain region 14_1 and may be located at a portion (also referred to as a front contact plug 22P) between the first source/drain region 14_1 and the second source/drain region 14_2. The front contact 22 may electrically connect the first source/drain region 12_1 to a Back Side Power Distribution Network (BSPDN) 60. The front contact 22 may be electrically connected to a power source having a voltage (e.g., positive, zero, or ground voltage) through the BSPDN 60, and the first source/drain region 12_1 may be electrically connected to the power source through the front contact 22.
Source/drain contacts 24 may contact source/drain regions 14. The source/drain contacts 24 may electrically connect the source/drain regions 14 to elements of the BES 48 (e.g., the first conductor 42).
The BES 48 may be provided on the first insulator 10. The BES 48 may be formed by the BEOL portion of the device manufacturing process and/or the passivation process. The BES 48 may include a second insulator 40 and a first conductor 42 in the second insulator 40. For example, the first conductor 42 may be a via contact or wire (e.g., a metal line). The second conductor 44 may be provided on the first conductor 42. The second conductor 44 may be a wire (e.g., a metal wire). A top layer 46 may be provided over the second conductor 44. The top layer 46 may include an insulating layer, conductive elements (e.g., via contacts and wires), and/or passivation layers (e.g., polyimide).
The integrated circuit device may also include a back insulator 50 and back contacts, which may include back contact plugs 52 and back power rails 54. A back insulator 50 may be formed on a lower surface of each of the active region 12 and the isolation layer 11. The back contact plug 52 and the back power rail 54 may be provided in the back insulator 50. The back contact plug 52 may contact the back power rail 54.
An upper portion of the back contact plug 52 may be between the first active region 12_1 and the second active region 12_2. The width of the back contact plug 52 in the first direction X may be narrower than the distance between the first active region 12_1 and the second active region 12_2 in the first direction X. Accordingly, the back contact plug 52 may be spaced apart from the first and second active regions 12_1 and 12_2. An upper portion of the back contact plug 52 may be in the isolation layer 11, and the isolation layer 11 may be interposed between the back contact plug 52 and the first active region 12_1 and between the back contact plug 52 and the second active region 12_2.
The front contact plug 22P (e.g., a lower surface of the front contact plug 22P) may contact the back contact plug 52 (e.g., an upper surface of the back contact plug 52). In some embodiments, the interface between front contact plug 22P and back contact plug 52 may be in etch stop layer 16, and a portion (e.g., lower portion) of front contact plug 22P and a portion (e.g., upper portion) of back contact plug 52 may be in etch stop layer 16, as shown in fig. 2A. In some embodiments, the width of the front contact plug 22P in the first direction X may be non-uniform along the third direction Z and may increase as the distance from the back contact plug 52 in the third direction Z increases. The width of the back contact plug 52 in the first direction X may be non-uniform along the third direction Z and may increase as the distance from the front contact plug 22P in the third direction Z increases.
Referring back to fig. 1, the widest width of the back power rail 54 in the second direction Y may be wider than the widest width of the back contact plug 52 in the second direction Y. In some embodiments, the back power rail 54 may extend longitudinally in the second direction Y, and the width of the back power rail 54 in the second direction Y may be wider than the width of the first active region 12_1 in the second direction Y.
The integrated circuit device may include a plurality of back side power rails 54 electrically connected to the BSPDN 60. BSPDN 60 may include an insulating layer and conductive elements (e.g., via contacts and wires).
Each of the isolation layer 11, the first insulator 10, the second insulator 40, and the back side insulator 50 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and/or a low-k material. The low-k material may include, for example, fluorine doped silica, organosilicate glass, carbon doped oxide, porous silica, porous organosilicate glass, spin-on organic polymer dielectric, or spin-on silicon-based polymer dielectric.
Each of the front contact 22, the source/drain contact 24, the first conductor 42, the second conductor 44, the back contact plug 52, and the back power rail 54 may include, for example, al, W, co, ru and/or Mo.
Fig. 3 is a flow chart of a method of forming an integrated circuit device according to some embodiments. Fig. 4-12, 13A, 13B, and 14-21 are diagrams illustrating methods of forming integrated circuit devices according to some embodiments. Specifically, fig. 4 to 9, 11, 13A and 14 to 21 are sectional views taken along a line A-A in fig. 1, 13B is a sectional view taken along a line B-B in fig. 1, and fig. 10 and 12 are plan views.
Referring to fig. 3-5, a method of forming an integrated circuit device may include providing a substrate on which a sacrificial stack structure is provided (block 1100). Referring to fig. 4, an initial channel layer 13L and an initial sacrificial layer 4L may be formed on a substrate 2. The initial channel layers 13L and the initial sacrificial layers 4L are alternately stacked on the substrate 2. A mask pattern 6 may be formed on the initial sacrificial layer 4L. The initial sacrificial layer 4L may include a material different from the initial channel layer 13L and may have an etching selectivity with respect to the initial channel layer 13L. For example, the initial sacrificial layer 4L may include SiGe. The mask pattern 6 may include, for example, a photoresist material and/or a hard mask material (e.g., silicon nitride).
Referring to fig. 5, the initial channel layer 13L, the initial sacrificial layer 4L, and the substrate 2 may be etched using the mask pattern 6 as an etching mask to form an active region 12 protruding from the front surface FS of the substrate 2 and to form sacrificial stack structures 15, each including the channel layer 13 and the sacrificial layer 4. The isolation layer 11 may be formed between directly adjacent active regions 12. The substrate 2 may comprise a back surface BS opposite to the front surface FS. The sacrificial stack structures 15 may contact the upper surfaces of the active regions 12, respectively.
Referring to fig. 3 and 6-9, an etch stop layer may be formed (block 1200). Referring to fig. 6, an initial etch stop layer 16L may be formed on the structure shown in fig. 5. An initial etch stop layer 16L may be formed on a surface (e.g., an upper surface and an opposite side surface) of the sacrificial stack structure 15 and on an upper surface of the isolation layer 11. In some embodiments, the initial etch stop layer 16L may have a uniform thickness along the surface of the sacrificial stack structure 15 and the upper surface of the isolation layer 11. The initial etch stop layer 16L may contact the surface of the sacrificial stack structure 15 and the upper surface of the isolation layer 11. The initial etch stop layer 16L may not completely fill the space between the sacrificial stack structures 15 and may define the space between the sacrificial stack structures 15.
An initial filler layer 8L may be formed on the initial etch stop layer 16L. The initial filler layer 8L may fill the space between the sacrificial stacked structures 15, which is defined by the initial etch stop layer 16L. The preliminary filler layer 8L may be a material that can be formed by a coating process (e.g., a spin coating process) so that the preliminary filler layer 8L can fill a space even when the space is narrow. For example, the initial filler layer 8L may include a material including carbon and may have etching selectivity with respect to the initial etching stop layer 16L, the channel layer 13, and the sacrificial layer 4.
Referring to fig. 7, an upper portion of the initial filler layer 8L may be removed by a process (e.g., a dry etching process, a wet etching process, and/or a Chemical Mechanical Polishing (CMP) process) to form the filler layer 8. The upper surface of the filler layer 8 may be lower than the uppermost portion of the initial etch stop layer 16L and the upper surface of the sacrificial stack structure 15. Accordingly, a portion of the initial etch stop layer 16L and a portion of the sacrificial stack structure 15 may protrude upward beyond the upper surface of the filler layer 8.
Referring to fig. 8, the initial etch stop layer 16L may be etched to form the etch stop layer 16. The portion of the initial etch stop layer 16L under the filler layer 8 may not be etched. The etch stop layer 16 may expose opposite side surfaces of the sacrificial stack structure 15. In some embodiments, the initial etch stop layer 16L may be etched until the entire opposite side surface of the sacrificial stack structure 15 is exposed.
Referring to fig. 9, the filler layer 8 may be removed. In some embodiments, the etching process for the initial etch stop layer 16L may be stopped when the uppermost surface of the initial etch stop layer 16L is higher than the lower surface of the filler layer 8. Thus, the uppermost surface of the etch stop layer 16 may be higher than the lower surface of the filler layer 8, as shown in fig. 8. Thus, the upper surface of the etch stop layer 16 may include a recess 16R. The etch stop layer 16 may include an uppermost end 16U that is not farther from the substrate 2 than the upper surface of the active region 12, and thus the etch stop layer 16 may not include a portion interposed between the source/drain regions 14.
Referring to fig. 3 and 10 through 12, 13A and 13B, source/drain regions and gate structures may be formed (block 1300). Referring to fig. 10, a mask layer 17 may be formed on the sacrificial stacked structure 15. The mask layer 17 may expose the first portion 15_1 of the sacrificial stack structure 15 and may cover the second portion 15_2 of the sacrificial stack structure 15. In some embodiments, the sacrificial stack structure 15 and the etch stop layer 16 may have the same or similar width in the second direction Y, as shown in fig. 10.
Referring to fig. 11, the first portion 15_1 of the sacrificial stacked structure 15 may be replaced with a source/drain region 14. For example, the first portion 15_1 of the sacrificial stack structure 15 may be etched to expose the second portion 15_2 (e.g., a sidewall of the second portion 15_2) of the sacrificial stack structure 15, and then the source/drain regions 14 may be formed by an epitaxial growth process using the channel layer 13 of the second portion 15_2 of the sacrificial stack structure 15 as a seed layer.
Referring to fig. 12, 13A and 13B, a first insulator 10 may be formed on the source/drain region 14. The first insulator 10 may include a gate opening 10op exposing a portion of the second portion 15_2 of the sacrificial stacked structure 15. The sacrificial layer 4 of the second portion 15_2 of the sacrificial stack structure 15 may be removed through the gate opening 10op so that the etch stop layer 16 and the channel layer 13 of the second portion 15_2 of the sacrificial stack structure 15 may be exposed to the gate opening 10op, as shown in fig. 13B. Referring back to fig. 2B, a gate structure 18 may be formed in the gate opening 10op.
Referring to fig. 3 and 14-16, a front contact may be formed (block 1400). Referring to fig. 14, an opening OP may be formed in the first insulator 10. The opening OP may be formed by etching a portion of the etch stop layer 16 and the first insulator 10. The openings OP may include a first opening OP1 exposing the first source/drain region 14_1 and a second opening OP2 exposing the second source/drain region 14_2. The first opening OP1 may be formed by etching the first insulator 10 until the etch stop layer 16 is exposed, and then a portion of the etch stop layer 16 may be etched. Thus, the etch stop layer 16 may serve as an etch stop layer when forming the first opening OP 1. In some embodiments, the first opening OP1 may expose the etch stop layer 16, and the etch stop layer 16 may define a lower portion of the first opening OP1, as shown in fig. 14. Although not shown in fig. 14, an etching mask pattern may be formed on the first insulator 10 to cover a portion of the first insulator 10 while forming the opening OP, and the etching mask pattern may be removed after forming the opening OP. Etchant(s) and process conditions that allow selective etching of the first insulator 10 relative to the source/drain regions 14 may be used so that the source/drain regions 14 may not be etched when forming the openings OP.
Referring to fig. 15, a conductive layer 21 may be formed in the opening OP and on the first insulator 10. Although the conductive layer 21 is shown as a single layer, in some embodiments, the conductive layer 21 may include multiple layers sequentially formed on the first insulator 10. For example, the conductive layer 21 may include an adhesive layer (e.g., a conductive layer including W, cr, ti, and/or Ni), a barrier layer (e.g., a conductive layer including TiN, taN, and/or AlN), and/or a metal layer sequentially formed on the first insulator 10.
Referring to fig. 16, the conductive layer 21 may be removed until the first insulator 10 is exposed to form front contacts 22 and source/drain contacts 24. The conductive layer 21 may be removed by an etching process and/or a CMP process. In some embodiments, the upper surfaces of each of the front contact 22 and the source/drain contact 24 may be coplanar with each other. The front contact 22 and the source/drain contact 24 may be formed by the same process described with reference to fig. 14-16, rather than a separate process for each of the front contact 22 and the source/drain contact 24. Thus, the MOL portion of the integrated circuit device fabrication may be relatively simple.
Referring to fig. 17, a BES 48 structure may be formed on the front contact 22 and the source/drain contact 24.
Referring to fig. 3 and 18, a lower portion of a substrate (substrate 2 in fig. 17) may be removed (block 1500). The structure shown in fig. 17 may be flipped (e.g., inverted), and the lower portion of the substrate 2 may be removed by performing, for example, a grinding process, an etching process, and/or a CMP process on the back surface (back surface BS in fig. 17) of the substrate 2. The lower portion of the substrate 2 may be removed until the isolation layer 11 is exposed.
Referring to fig. 19, in some embodiments, active region 12 may be etched to be recessed with respect to isolation layer 11.
Referring to fig. 3, 20, and 21, a back contact may be formed (block 1600). Referring to fig. 20, a back insulator 50 may be formed on the isolation layer 11, and a back opening BOP1 and a linear opening BOP2 may be formed in the back insulator 50 and the isolation layer 11. The back opening BOP1 may be connected to the linear opening BOP2 and may be between the front contact 22 and the linear opening BOP2. The back surface opening BOP1 may be formed by etching the back surface insulator 50 and the isolation layer 11 until the etching stop layer 16 is exposed, and then a portion of the etching stop layer 16 may be etched until the front contact plug 22p is exposed. Thus, the etch stop layer 16 may also be used as an etch stop layer when forming the backside opening BOP 1. In some embodiments, the backside opening BOP1 may expose the etch stop layer 16, and the etch stop layer 16 may define a portion (e.g., an upper portion) of the backside opening BOP 1.
Referring to fig. 21, a back contact plug 52 may be formed in the back opening BOP1, and a back power rail 54 may be formed in the linear opening BOP 2. The back contact plugs 52 and the back power supply rails 54 may be formed by forming conductive layers in the back openings BOP1 and the linear openings BOP 2. Although the back contact plugs 52 and the back power rails 54 are shown as a single layer, in some embodiments, the back contact plugs 52 and the back power rails 54 may include multiple layers formed sequentially on the back insulator 50. For example, the back contact plugs 52 and the back power rails 54 may include an adhesion layer (e.g., a conductive layer including W, cr, ti, and/or Ni), a barrier layer (e.g., a conductive layer including TiN, taN, and/or AlN), and/or a metal layer formed sequentially on the back insulator 50. Referring back to fig. 2a, a bspdn 60 may be formed on the back side power rail 54.
Fig. 22 and 23 each illustrate a cross-sectional view of an integrated circuit device taken along line A-A in fig. 1, according to some embodiments. The structure shown in fig. 22 and 23 may be similar to the structure shown in fig. 2A, except for the shape of the etch stop layer 16.
Referring to fig. 22, the upper surface of the etch stop layer 16 may be planar and may not include a recess (e.g., recess 16R in fig. 2A). During the process described with reference to fig. 8, the structure shown in fig. 22 may be formed by etching the etch stop layer 16 until the upper surface of the etch stop layer 16 becomes coplanar with the lower surface of the filler layer 8.
Referring to fig. 23, the upper surface of the etch stop layer 16 may include a protrusion 16P protruding into the first insulator 10. During the process described with reference to fig. 8, the structure shown in fig. 23 may be formed by etching the etch stop layer 16 until the upper surface of the portion of the etch stop layer 16 not covered by the filler layer 8 becomes lower than the lower surface of the filler layer 8.
Fig. 24A and 24B each illustrate the IR region in fig. 2A, according to some embodiments. Referring to fig. 24A, only a portion of the back contact plug 52 may be in the etch stop layer 16, while the front contact plug 22P may not be in the etch stop layer 16. Therefore, the interface between the front contact plug 22P and the back contact plug 52 may not be in the etch stop layer 16. The structure shown in fig. 24A may be formed by stopping the etching process for the first insulator 10 when the etching stop layer 16 is exposed during the process described with reference to fig. 14, so that the first opening OP1 may not be formed in the etching stop layer 16.
Referring to fig. 24B, only a portion of the front contact plug 22P may be in the etch stop layer 16, while the back contact plug 52 may not be in the etch stop layer 16. Therefore, the interface between the front contact plug 22P and the back contact plug 52 may not be in the etch stop layer 16. The structure shown in fig. 24B may be formed by performing an etching process for the first insulator 10 and the etch stop layer 16 during the process described with reference to fig. 14 until the isolation layer 11 is exposed, so that the first opening OP1 may extend through the etch stop layer 16.
Integrated circuit devices according to embodiments described herein may provide various advantages. For example, a contact structure connecting an element formed on the front side of a substrate (e.g., source/drain regions 14 in fig. 2A) and an element formed on the back side of the substrate (e.g., back side power rail 54 in fig. 2A) may include two contacts, each having a relatively low aspect ratio and formed by a separate process. Thus, defects associated with high aspect ratio contact structures may be reduced. Furthermore, a single etch stop layer (e.g., etch stop layer 16 in fig. 2A) may be used as the etch stop layer during two etching processes (e.g., one for opening OP in fig. 14 and the other for backside opening BOP1 in fig. 20) instead of two separate etch stop layers. Still further, the etch stop layer (e.g., etch stop layer 16 in fig. 2A) may not include portions interposed between adjacent source/drain regions, and thus the etch stop layer may not increase parasitic capacitance between those source/drain regions.
Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the disclosure, and thus the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout.
Example embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized example embodiments and intermediate structures of example embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments herein should not be construed as limited to the particular shapes illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.
It should also be noted that in some alternative implementations, the functions/acts noted in the flowcharts may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the functionality of a given block of the flowchart and/or block diagram may be divided into a plurality of blocks, and/or the functionality of two or more blocks of the flowchart and/or block diagram may be at least partially integrated. Finally, other blocks may be added/inserted between the blocks shown, and/or blocks/operations may be omitted, without departing from the scope of the invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," comprising, "" includes "and/or" including "of … …, and/or" including … …, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element is referred to as being "coupled to," "connected to," or "responsive to" another element, it can be directly coupled to, connected to, or responsive to the other element or be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly coupled to," "directly connected to," or "directly responsive to" another element, or "directly on" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Furthermore, the symbol "/" (e.g., when used with the term "source/drain") will be understood to be equivalent to the term "and/or".
It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element could be termed a second element without departing from the teachings of the present embodiment.
For ease of description, spatially relative terms, such as "under … …," "under … …," "lower," "over … …," "upper," and the like, may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" additional elements or features would then be oriented "over" the additional elements or features. Thus, the term "under … …" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or in another orientation), and the spatial relationship descriptors used herein interpreted accordingly.
Many different embodiments are disclosed herein in connection with the above description and the accompanying drawings. It will be understood that each combination and sub-combination of these embodiments described and illustrated literally will be overly repeated and confusing. Accordingly, the specification (including the drawings) should be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, as well as of the manner and process by which they are made and used, and should support claims to any such combination or subcombination.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present application. Accordingly, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
The present application claims priority from U.S. provisional application No. 63/336,335 entitled "INTEGRATED CIRCUIT DEVICES INCLUDING REVERSE VIA BACKSIDE POWER RAIL AND METHODS OF FORMING THE SAME (integrated circuit device including reverse-path back-side power rail and method of forming same)" filed on us pto at month 29 of 2022, the disclosure of which is incorporated herein by reference in its entirety.

Claims (20)

1. A method of forming an integrated circuit device, the method comprising:
providing a substrate comprising a front surface and a back surface opposite the front surface, wherein first and second active regions, an isolation layer, and first and second sacrificial stacks are provided on the front surface of the substrate, and wherein the isolation layer is between the first and second active regions, the first and second sacrificial stacks contact upper surfaces of the first and second active regions, respectively, and the first and second sacrificial stacks each comprise a channel layer and a sacrificial layer;
forming an etch stop layer on an upper surface of the isolation layer;
replacing portions of the first and second sacrificial stacks with first and second source/drain regions, respectively;
forming a front contact contacting the first source/drain region, wherein the front contact includes a front contact plug between the first source/drain region and the second source/drain region;
forming a back insulator on a lower surface of the isolation layer; and
Forming a back contact plug in the isolation layer and the back insulator and contacting a lower surface of the front contact plug,
wherein at least one of a portion of the front contact plug and a portion of the back contact plug is in the etch stop layer.
2. The method of claim 1, wherein forming the etch stop layer comprises:
forming an initial etch stop layer on the first and second sacrificial stacks and the isolation layer;
forming an initial filler layer on the initial etch stop layer;
etching the initial filler layer, thereby forming a filler layer between the first and second sacrificial stacks on the initial etch stop layer, wherein a portion of the initial etch stop layer and portions of the first and second sacrificial stacks protrude upward beyond an upper surface of the filler layer; then
The initial etch stop layer is etched, forming the etch stop layer and exposing side surfaces of the first and second sacrificial stacks.
3. The method of claim 1, wherein forming the front contact comprises:
forming a first insulator on the first and second source/drain regions and the etch stop layer;
etching the first insulator and the etch stop layer to form a first opening in the first insulator, wherein the first opening exposes the etch stop layer; and
the front contact plug is formed in the first opening.
4. The method of claim 1, further comprising forming source/drain contacts to contact the second source/drain region,
wherein forming the front contact and the source/drain contact comprises:
forming a first insulator on the first and second source/drain regions and the etch stop layer;
etching the first insulator and the etch stop layer to form a first opening and a second opening in the first insulator, wherein the first opening and the second opening expose the first source/drain region and the second source/drain region, respectively, and the first opening also exposes the etch stop layer;
forming a conductive layer in the first opening and the second opening and on the first insulator; and
The conductive layer is removed until the first insulator is exposed, thereby forming the front contact in the first opening and the source/drain contact in the second opening.
5. The method of claim 1, wherein forming the back contact plug comprises:
etching the back insulator and the isolation layer to form a back opening in the back insulator and the isolation layer; and
and forming the back contact plug in the back opening.
6. The method of claim 5, wherein forming the backside opening comprises etching a portion of the etch stop layer.
7. The method of claim 1, further comprising forming a back side power rail,
wherein forming the back contact plug and the back power rail comprises:
etching the back insulator and the isolation layer to form a line-shaped opening in the back insulator and a back opening in the back insulator and the isolation layer and between the line-shaped opening and the front contact plug; and
a back conductive layer is formed in the back opening and the line-shaped opening, thereby forming the back contact plug in the back opening and the back power rail in the line-shaped opening.
8. The method of claim 1, further comprising, after forming the front contact plug and before forming the back insulator, removing a lower portion of the substrate until the lower surface of the isolation layer is exposed.
9. The method of claim 1, wherein the portions of the first and second sacrificial stacks are first portions, and the first and second sacrificial stacks each further comprise a second portion, and
the method also includes forming a gate structure that spans the first and second active regions and the etch stop layer, wherein forming the gate structure includes replacing the sacrificial layer of the second portions of the first and second sacrificial stack structures with portions of the gate structure.
10. The method of claim 1, wherein an uppermost end of the etch stop layer is not farther from the substrate than the upper surfaces of the first and second active regions.
11. The method of claim 1, wherein the portion of the front contact plug and the portion of the back contact plug are in the etch stop layer.
12. The method of claim 1, wherein a width of the back contact plug increases with increasing distance from the front contact plug.
13. A method of forming an integrated circuit device, the method comprising:
providing a substrate, a front structure provided on the substrate, wherein the substrate comprises a front surface and a back surface opposite the front surface, and wherein the front structure comprises first and second active regions protruding from the front surface of the substrate, an isolation layer between the first and second active regions, an etch stop layer on the isolation layer, first and second channel layers on the first and second active regions, respectively, first and second source/drain regions on the first and second active regions and contacting the first and second channel layers, respectively, and a gate structure spanning the first and second channel layers and the isolation layer; and
forming a front contact contacting the first source/drain region;
forming a back insulator after forming the front contact, wherein the isolation layer is between the etch stop layer and the back insulator; and
And a back contact plug formed in the isolation layer and the back insulator and contacting the front contact.
14. The method of claim 13, wherein forming the back contact plug comprises:
etching the back insulator and the isolation layer to form a back opening in the back insulator and the isolation layer; and
and forming the back contact plug in the back opening.
15. The method of claim 13, wherein at least one of a portion of the front contact and a portion of the back contact plug is in the etch stop layer.
16. The method of claim 15, wherein the etch stop layer comprises a portion between the gate structure and the isolation layer.
17. An integrated circuit device, comprising:
a first active region and a second active region spaced apart from each other in a first horizontal direction;
first and second source/drain regions overlapping the first and second active regions, respectively;
an isolation layer between the first active region and the second active region;
a first insulator on the isolation layer between the first source/drain region and the second source/drain region;
An etch stop layer between the isolation layer and the first insulator;
a front contact in the first insulator and contacting the first source/drain region, wherein the front contact includes a front contact plug between the first source/drain region and the second source/drain region;
a back side insulator, wherein the isolation layer is between the etch stop layer and the back side insulator; and
a back contact plug in the back insulator and the isolation layer and contacting the front contact plug,
wherein at least one of a portion of the front contact plug and a portion of the back contact plug is in the etch stop layer.
18. The integrated circuit device of claim 17, wherein an interface between the front contact plug and the back contact plug is in the etch stop layer.
19. The integrated circuit device of claim 17, further comprising:
a first channel layer and a second channel layer on the first active region and the second active region, respectively, and contacting the first source/drain region and the second source/drain region, respectively; and
a gate structure spanning the first and second channel layers and the spacer layer,
Wherein the etch stop layer comprises a portion between the gate structure and the isolation layer.
20. The integrated circuit device of claim 17, wherein a width of the back contact plug in the first horizontal direction increases with increasing distance from the front contact plug.
CN202310478465.7A 2022-04-29 2023-04-28 Integrated circuit device including backside power rail and method of forming the same Pending CN116978860A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US63/336,335 2022-04-29
US17/936,106 US20230352408A1 (en) 2022-04-29 2022-09-28 Integrated circuit devices including backside power rail and methods of forming the same
US17/936,106 2022-09-28
KR10-2023-0024581 2023-02-23

Publications (1)

Publication Number Publication Date
CN116978860A true CN116978860A (en) 2023-10-31

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Application Number Title Priority Date Filing Date
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Country Link
CN (1) CN116978860A (en)

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