CN1169785A - Method and apparatus for correcting errors of disk-drive cmulator - Google Patents

Abstract

An error correction system (10) is provided for correcting up to two bits per sector stored in a solid state non-volatile memory (12) which emulates a disk drive. The error correction system (10) includes an ECC/remainder generator (100), a bank of remainder registers (102), and a calculation circuit (104), all under supervision of a controller (106). During a write-to-memory operation, error correction system (10) generates ECC bytes for storage in the memory (12). In a write operation, an entire sector acquired from memory (12) is used to generate ECC check remainder bytes REM0-REM3. The check remainder bytes REM0-REM3 are utilized to generates syndromes S1, S3 and a factor SB, the syndromes in turn being used to obtain either one or two error location positions ( alpha L1, alpha L2).

Description

The error correction method of disk drive emulator and device

The application is called the Zook of " multipurpose error correction calculation circuit " in the part continuation application of the U.S. Patent application (sequence number 08/306,918) of submission on September 16th, 1994; The latter is called the Zook of " Galois field inverting " in the part continuation application of the U.S. Patent application (sequence number 08/147,758) of submission on November 4th, 1994, by reference they all is combined in this.

The present invention relates to computer technology, relate more specifically to have the solid-state disk drive emulator of improved error correction.

Computer system extensively adopts hard disk drive for the high capacity storage.Yet disc driver is heavy, needs complicated read/write electron device, and adopts the high-precision motion mechanical part that occurs integrity problem easily.Moreover disk drive needs a large amount of electric power, therefore uses not quite satisfactory in portable computer.

Such as the violent raising of the storage density of non-volatile solid state memory equipment such as flash EEPROM, allow the solid-state disk drive simulation disk drive for high capacity storage in the computer system.The nonvolatile solid state disk drive is similar to disc driver, even also can keep data after power supply disconnects.For disc driver, so because short-access storage does not have moving component is cheap and more reliable.Moreover solid-state disk drive uses less complicated read/write electron device and consumes less power.Usually, the PCMCIA plug-in unit with flash EEPROM comprise into compact with portable set in.Therefore, solid-state disk drive more is applicable to such as special applications such as portable computers.

Significantly, adopt solid-state disk to have some shortcomings, thereby avoided making disc driver out-of-date.For example, storage huge amount data (several hundred million byte) ratio is cheap far in solid-state drive in disc driver.And has only the limited life-span and in that the wiping of certain number of times/can be insecure write cycle (being generally for 1,000 to 10,000 cycle) afterwards such as solid-state memories such as flash EEPROMs.Another shortcoming is can make solid-state disk drive more unreliable from the mistake that the storage unit of damaging or the storage unit of sewing produce.

A kind of method that overcomes the mistake that the storage unit of damage causes is disclosed in 5,297, No. 148 United States Patent (USP)s that are presented to people such as Harari.The Harari patent disclosure with the method for the replacing damaged storage unit of redundancy unit.Storage is connected to the address of the unit of damage on the fault pointer of substituting unit in fault graph.During unit that access each time damages, use good data to replace its bad data from substituting unit.Yet the shortcoming of this method is only to carry out during manufacture the fault reflection and does not remedy out of order unit during normal running.Moreover, the failure rate in the flash EEPROM equipment with wipe/increase of write cycle increases.

The soft error that traditional error correction (ECC) of common employing disc driver compensates becomes damage after after a while the unit wrong and that sew that the unit caused causes.Yet disk ECC system optimizes for the mistake relevant with magnetic recording.The train of impulses mistake (some sequential bits) of the different length that the mistake in the magnetic recording is normally caused by the defective in the magnetic medium.Traditional ECC system adopts complicated error correction algorithm to correct these mistakes.Thereby realize that these algorithms need take electricity and expensive complicated circuit.Moreover, be used for detecting inherent considerable stand-by period amount in the complicated algorithm of the mistake relevant and can slow down total access time of equipment with correction and magnetic recording.

Obviously different with mistake and disc driver that solid-state disk drive is relevant.Usually, one or two s' mistake appears in each sector of solid-state disk drive.These mistakes are usually by defective unit (hard error) or sew the unit (soft error) of a period of time and cause.In order to correct usually one of each sector related with short-access storage or two s' mistake, the complicated error correction algorithm of employing the correction mistake relevant with magnetic medium is a poor efficiency.

Therefore, catalogue of the present invention for the improved flash EEPROM solid-state disk drive that can be used as non-volatile memory device in computer system is provided.Another purpose is for reducing the complicacy and the stand-by period of the type of correcting usually each sector one related with the flash EEPROM of the memory element that is used as solid-state disk drive or two bit-errors.

Provide each sector that is used for correcting the solid-state, non-volatile memory (12) that is stored in the emulated disk driver to reach two error correction system (10).This error correction system (10) comprises an ECC/ remainder generator 100, one group of remainder register (102) and counting circuit (104), and they are entirely under the monitoring of a controller (106).In write store operating period, error correction system (10) generates for the ECC byte that is stored in the storer (12).In write operation, use generates ECC verification remainder byte REM from the whole sector that storer (12) obtains ₀-REM ₃Utilize verification remainder byte REM ₀-REM ₃Generate syndrome S ₁, S ₃An and factor S _B, utilize this syndrome to obtain one or two error unit position (α again ^L1, α ^L2).Mathematical computations circuit (104) not only generates syndrome S ₁, S ₃With factor S _BAnd error unit position (α ^L1, α ^L2), also the address of product dislocation mistake in the sector (L1-64[complement code], L2-64[complement code]).

Illustrate in the description more specifically of preferred embodiment in the accompanying drawings from below, above-mentioned and other purpose of the present invention, feature will come into plain view with advantage, in the accompanying drawing with reference to character at all identical parts of each view middle finger.Accompanying drawing there is no need in proportion, shows on the principle of the present invention but focus on.

Fig. 1 is the synoptic diagram that comprises the solid-state disk drive of a microcontroller, disk controller, dish analogue system, two digit pulse string error correction systems and memory array.

Fig. 2 is the schematic block diagram that is included in the error correction system in the solid-state disk drive of Fig. 1.

Fig. 3 is the schematic block diagram that is included in the ECC/ remainder generator in the error correction system of Fig. 2.

Fig. 4 is the schematic block diagram that is included in one group of remainder register in the error correction system of Fig. 2.

Fig. 5 A is the schematic block diagram that is included in the first of the counting circuit in the error correction system of Fig. 2.

Fig. 5 B is the schematic block diagram that is included in the second portion of the counting circuit in the error correction system of Fig. 2.

Fig. 6 is the schematic block diagram that is included in the multiplier circuit in the counting circuit of Fig. 5 A.

Fig. 7 is the process flow diagram of error correction system performed total step in write operation of exploded view 2.

Fig. 8 is the process flow diagram of error correction system performed total step in read operation of exploded view 2.

Fig. 9 illustrates the data layout of the memory array of being made up of the row of the row of track and sector.

Figure 10 determines the process flow diagram of total step performed in the operation for the logarithm in the read operation of showing the error correction system that is included in Fig. 2.

Figure 11 determines the process flow diagram of more detailed step performed in the operation for the logarithm in the read operation of showing the error correction system that is included in Fig. 2.

Fig. 1 illustrates the summary of solid-state disk drive 6 of the present invention.Traditional disk controller 4 provides the interface between solid-state drive and the host computer system.Disk controller 4 can be any suitable controller, comprises such as can be from California Milpitas the model C L-SH350 that Cirrus Logic company buys.Microcontroller 2 is that disk controller 4 and dish emulator 8 are set up initial operational parameters.Microcontroller 4 is also coordinated to transmit based on the order of dish and the data of being to and from main frame.Dish emulator 8 provides simulation disk drive essential dish control signal.Its receives from the typical control signal of disk controller 4 with microcontroller 2, such as the road of wanting read/write and sector number, and handles these orders so that from/the data of asking to memory array 12 read/write of flash EEPROM equipment.One or two error correction systems 10 detect and correct the mistake that is caused by the storage unit of damaging or leak.For the control of solid-state disk drive and comprehensive discussion of emulation, the United States Patent (USP) (patent No. 5,291,584) referring to " hard disk emulation mode and the device " by name that be presented to people such as Challa is combined in this with its content by reference.

In solid-state disk drive, the data layout with memory array 12 is formatted into the capable array that is listed as with the sector in the road shown in Fig. 9 usually.The road is capable to show concentric road on the disk with list of sectors.As mentioned above, damage in the flash EEPROM memory array or leakage unit can cause one of each sector or two bit-errors.Error correction system 10 comprises the error correction algorithm that is specially adapted to correct these or two bit-errors.

Fig. 2 illustrates this error correction system 10 and comprises an ECC/ remainder generator 100; One group of remainder register 102; One counting circuit 104; An and controller 106.8 bit data bytes on the line 107 are acted on the input end 0 of ECC remainder generator 100 and MUX110.Discuss ECC/ remainder generator in more detail with reference to Fig. 3.As finding after this, ECC/ remainder generator 100 generates four 8 ECC bytes, and they are outputed on the input end 1 of MUX110 on online 112.

Mention error correction system 10 once more and must in 512 byte sector, locate mistake up to two.Owing to must locate one one bit-errors by 14 polynomial expressions in this case, correct essential two 14 polynomial expressions of two one bit-errors.Because 2 * 14 long-pending to equal 28 be not 8 multiple, so select 32 as the length of code generator polynomial and correspondingly as the various registers of after this describing, especially with reference to computer circuits 104.Thereby the code generator polynomial is following two 14 polynomial expressions and amassing of 4 polynomial expressions: G (X)=(X ¹⁴+ X ¹⁰+ X ⁹+ X ⁶+ X ⁵+ X ⁴+ X ¹) (X ¹⁴+ X ⁶+ X ⁵+ X ²+ 1) (X ⁴+ 1)

=(X ³²+ X ²⁷+ X ²⁴+ X ²³+ X ²²+ X ¹⁵+ X ¹²+ X ⁷+ X ²+ 1) 4 polynomial generations draw 4 location factor S _BGeneration, it is significant in the operation of verification error correction system 10.

Moreover error correction system 10 adopts the code towards the position, though input wherein data and from the ECC byte of wherein output with the byte form.

ECC/ remainder generator 100 is to be connected on 102 groups of the remainder registers with four remainder output buss 116.Discuss remainder register group 102 in more detail with reference to Fig. 4.Article one, an output line 118 is connected remainder register group 102 on the counting circuit 104.Discuss counting circuit 104 in more detail with reference to Fig. 5 A and 5B.

The operation of controller 106 monitoring and sequencing error correction system 10, and correspondingly be connected to ECC/ remainder generator 100 with control bus 120; Remainder register group 102; And on each of counting circuit 104.Though there is no need to illustrate at this, the timing to the various selection signals of MUX and operation that should understand after this to be discussed is that the control line by total component part that is designated as control bus 120 provides.

A kind of function of counting circuit 104 reaches two mistake for location in acting on a sectors of data of error correction system 10.Correspondingly, the some signals of counting circuit 104 outputs are given controller 106, comprising NO ERRORS (inerrancy) signal; UNC signal (sector that expression can not be corrected); Signal L1-64[complement code] (it provides the address of first error bit in the sector); And signal L2-64[complement code] (it provides the address of second error bit in the sector).As after this discussing, the error bit location subvalue L1 and the L2 that are generically and collectively referred to as " L " are 12 place values, high 9 error bytes that are used for locating the sector; Low 3 error bits that are used for locating error byte.

Structure: ECC remainder generator

As after this described, ECC/ remainder generator 100 generates ECC remainder byte generating the ECC byte during the write operation during read operation.In write operation, utilize ECC remainder byte to generate syndrome S ₁With S ₃, the latter is used to determine error bit location subvalue L1 and L2 again.

As among Fig. 3 in more detail shown in, ECC/ remainder generator 100 comprises four ECC/ remainder registers 140 ₀-140 ₃One group of totalizer 142; With door 144; And linear logic number generator 146.Totalizer 142 ₃First end be connected and enter on the data line 107; Totalizer 142 ₃Second input end be connected register 140 ₃Output terminal on.Totalizer 142 ₃Output terminal be connected with door 144 first input end on, connect into the signal ECC that receives self-controller 106 with second input end of door 144.Be connected on the input end of linear logic number generator 146 with the output terminal of door 144.

The linear logic number generator is one group of logical block, comprises to be used for according to from the input signal that receives with door 144 XOR gate in the specific output signal of bus 152 outputs.How table 1 illustrates according to the output signal to the input signal derivation bus 152 of linear logic number generator 146.First group of 8 row of table 1 are used to generate bus 152 ₃Output signal, second group 8 of table 1 row are used to generate bus 152 ₂Output signal, the 3rd group 8 of table 1 row are used to generate bus 152 ₁Output signal, the 4th group 8 of table 1 row are used to generate bus 152 ₀Output signal.First row of each group are corresponding to the most significant digit of output signal, and last row of each group are corresponding to the lowest order of output signal.XOR is indicated together with the position, position of the input signal that generates output signal in " 1 " in each row.For example, for bus 152 ₃On output signal, output signal the position 7 be by the XOR input signal the position 4 and 7 generations.Being familiar with present technique person can the fine circuit that utilizes table 1 to constitute the desired output of generation table 1.

Linear logic number generator 146 has four output buss 152 ₀-152 ₃Each linear logic output bus 152 is 8 buses.Linear logic output bus 152 ₁-152 ₃Be connected to totalizer 142 ₀-142 ₂First input end on.Linear logic output bus 152 ₀Be connected ECC/ remainder register 104 ₀An input end on.

Each register 140 ₀-140 ₃Output terminal be connected to corresponding totalizer 142 ₀-142 ₃Second input end on.In addition, register 140 ₀-140 ₃Output terminal be connected to remainder output bus 116 ₀-116 ₃On.Totalizer 142 ₀-142 ₂Output terminal be connected to register 140 ₁-140 ₃Input end on.Thereby register 140 is connected and composed shift register, be moved out to MUX110 for being transferred to storer 12 on the ECC byte (after ECC generates) online 112 that makes it to generate therein.This respect, as after this discussing, ECC/ remainder generator 100 is at register 140 ₀The middle ECC byte ECC that generates ₀, at register 140 ₁Middle the 2nd ECC byte ECC that generates ₁, at register 140 ₂Middle the 3rd ECC byte ECC that generates ₂, and at register 140 ₃Middle the 4th ECC byte ECC that generates ₃

Structure: remainder register

Illustrate in greater detail remainder register group 102 among Fig. 4.More specifically, group 102 comprises four 8 bit shift register 102 ₀-102 ₃, for example with dashed lines frame in Fig. 4 plays register 102 ₀And 102 ₂With register 102 ₂Be imagined as and have 6 low portions and two high-order portions.MUX160 ₂Feed-in register 102 ₂Low portion the position 5, MUX160 ₂Input end 0 be connected register 102 ₂The position 6 on.With register 102 ₀Be imagined as and have four low portions and four high-order portions.MUX160 ₀Feed-in register 102 ₀Low portion the position 3, MUX160 ₀Input port be connected register 102 ₀The position 4 on.

Remainder output bus 116 ₃One 8 place value (walking abreast) is loaded into remainder register 102 ₃In.Remainder output bus 116 ₂6 low levels connect into (walking abreast) and load remainder register 102 ₂(6) low portion.Remainder output bus 116 ₂Two high positions connect into (walking abreast) and load remainder register 102 ₂(two) high-order portion.Remainder output bus 116 ₁(walking abreast) loads one 8 place value to remainder register 102 ₁In.Remainder output bus 116 ₀Four low levels connect into (walking abreast) and load remainder register 102 ₀(four) low portion.Remainder output bus 116 ₀Four high positions connect into (walking abreast) and load remainder register 102 ₀(four) high-order portion.

As with shown in the bottom of Fig. 4 mode was made up, remainder register group 102 is also referred to as SREG3, SREG1 and SREGB register.Register SREG3 comprises register 102 ₃And register 102 ₂6 low levels; Register SREG1 comprises register 102 ₂Two high positions, register 102 ₁All the position and registers 130 ₀Four low levels; Register SREGB is a register 102 ₀Four high positions.SREG1 is labeled as the final storage that is used for than positron S1 especially; Register SREG3 is used for storage than positron S ₃And register SREGB is used for packing factor S _BIn order to feed out the value that is stored among SREGB, SREG1 and the SREG3, line SREGB (0) is connected register 102 ₀The position 4 on; Line SREG1 (0) is connected register 102 ₁The position 6 on; And line SREG3 (0) is connected register 102 ₃The position 0 on.

Structure: counting circuit

The counting circuit 104 that illustrates in greater detail among Fig. 5 A comprises three elementary work registers; Register 400 (also claiming register R1) specifically; Register 401 (also claiming register R2); And register 402 (also claiming register R3).Each register 400,401 and 402 is 14 bit shift register, though not necessarily must utilize whole 14 in the operation each time.

As after this seeing, carry out multiple mathematical operation on the item of counting circuit 104 in being stored in register 400,401 and 402.As an example, circuit 104 is carried out the multiplication of first (being stored in the register 400 with the β basis representation) and second (being stored in the register 401 with the α basis representation) continually, and will amass and output to (with the β basis representation) in the register 402.As another example, carry out linear transformation with the content of register 400 and 401.Further again, circuit 104 is carried out its conversion and is asked down.

The further details of counting circuit 104 is described below and also can understands in the disclosed similar circuit the U.S. Patent application of submitting on September 16th, 1994 (procurator's document number 1777-11) from the Zook of " multipurpose error correction calculation circuit " by name, by reference this patented claim is combined in this.

Counting circuit 104 comprises an inner product circuit 404, and it is obtained the inner product of register 400 and 401 and exports a serial bit signal IP.Inner product signal IP by or the door 406 the transmission be provided as enabling signal act on one group with the door 426 on.Everybody of register 402 is connected in the group 426 on the input end of a correspondence and door.The output terminal with door that is included in the group 426 is connected on " B " input end of the corresponding totalizer in the totalizer group 428.The position of register 401 is connected on correspondence " A " input end of totalizer group 426.

Register 400,401 and 402 has and is respectively applied for the switching system 430,431 and 432 of loading data selectively.The conversion of data (serial always) is advanced register 400 and is subjected to switching system 430 controls.Switching system 430 comprises MUX430A and 430B.The output terminal of MUX430B is connected on the data input end of register 400.The data input end of MUX430B is connected on the output terminal of MUX430A.Other data input pin of MUX430A is connected on line FULL_FIELD, R3_OUT, SREG1 (0) [seeing Fig. 4] and the SREG3 (0) [seeing Fig. 4].

The data input pin of MUX 430A is connected on the feedback system 436, and the latter provides the feedback product for full word segment value or son field value.Particularly, feedback system 436 comprises the XOR gate 436B that is used for that register 400 be multiply by the XOR gate 436A of a full word section feedback constant and is used for register 400 be multiply by a son field constant.The field generator polynomial of being utilized is depended in the position, position of door 436A and 436B XOR.In the example that illustrates, full word section generator polynomial is X ¹⁴+ X ¹⁰+ X ⁹+ X ⁶+ X ⁵+ X ⁴+ 1 and the son field generator polynomial is X ⁷+ X ⁵+ X ³+ X+1.Thereby position 0,4,5,6,9 and 10 is connected to XOR gate 436A; Position 7,8,10 and 12 is connected to XOR gate 436B.The output terminal of XOR gate 436A is connected to first data input pin of MUX430A; The output terminal of XOR gate 436B is connected to second data input pin of MUX430A.

Data load in the register 401 via switching system 431.Switching system 431 comprises loaded in parallel MUX431A; Serial loads MUX431B; And preposition MUX431C.The output terminal of loaded in parallel MUX431A is connected on everybody of register 401.A serial input pin of register 401 is connected serial and loads on the output terminal of MUX431B.But being connected serial loads selection wire on the input end of MUX431B and comprises output line from MUX431C; Line R3_OUT; Line SREG1 (0) [seeing Fig. 4]; And line SREG3 (0) [seeing Fig. 4].

Counting circuit 104 also comprises LIN440.In the illustrated embodiment, LIN440 is for wherein storing the ROM of look-up table, comprise be used for as execution as described in after this be used for " y " linear combination look-up table and be used to seek look-up table for the value of using at linear combinatorial operation, this computing draws the son field element X of wrong indicator ₁, X ₀LIN440 is that output is carried out the value of the linear combination that is used for " y " or exported the selection signal that the son field value depends on that slave controller 106 acts on thereon.On one of parallel input end that is connected loaded in parallel MUX431A of 14 output terminals of LIN440.

As mentioned above, loaded in parallel MUX431A data input end is connected on the output terminal of LIN440.Second data input pin of MUX431A connects into the also line output that receives totalizer group 428.

Data load in the register 402 via switching system 432.Switching system 431 comprises loaded in parallel MUX432A; Serial loads MUX432B; And preposition MUX432C.First data input pin of MUX432A is connected on the position of register 402; Second data input pin of MUX432A is connected on the output terminal of multiplier circuit 450.

Multiplier circuit 450 can be participated in division arithmetic selectively; Participate in the base conversion; Maybe will import wherein value (from register 402 loaded in parallel) and multiply by α or α ³From Fig. 6, can understand the structure of multiplier circuit 450.How the upper section of Fig. 6 illustrates the input of multiplier and output terminal connected into and multiply by α; How the below of Fig. 6 partly illustrates the input of multiplier and output terminal connected into multiply by α ³Multiply by α ³Occur in during the syndrome generation, therefore the control signal ENA DIV of effect draws via inner MUX output α during syndrome generates ³Long-pending.The output terminal of multiplier circuit 450 is connected on the input end of MUX432A.

The serial of register 402 loads input end and is connected on the output terminal of serial bit load registers 432B.The first input end of MUX432B is connected on the output terminal of MUX432C.Second input end of MUX432B be connected or door 406 output terminal on.The first input end of preposition MUX432C is connected on the feedback circuit 460; Second input end of preposition MUX432C connects online SREG1 (0) and goes up [seeing Fig. 4].

Feedback circuit 460 comprises and door 462 and XOR gate 464.XOR gate 464 is connected on the position 1,3,6 and 7 of register 402.The output terminal of XOR gate 464 be connected with door 462 first input end on.Be connected on the enabling signal with second input end of door 462.

A syndrome also is shown among Fig. 5 A takes place and door 470, its first end connects on the online SREG3 (0), and its second end connects into and receives syndrome start-up control signal ENA DIV.Be connected on the input end of XOR gate 436A with the output terminal of door 470.

The position 0 and 13 of register 402 is connected on first and second data input pin of MUX472.The output terminal of MUX472 is connected on the first input end of XOR gate 474.Second input end of XOR gate 474 connects into and receives a control signal.The output terminal of XOR gate 474 connects on the online R3-OUT, and the latter is connected on register 400 and 401 via MUX430B and 431B respectively.

As shown in Fig. 5 B, counting circuit 104 also comprises a LOG ROM480; Totalizer 482 and 484; Totalizer input MUX486 and 488; Not gate 490; And comprise the accumulator registers 500 of low bit accumulator 500L and upper accumulator 500H.Will from register 402 the position 7-13 data parallel be loaded among the LOG ROM480.7 output terminals of LOG ROM480 are connected on the first input end and not gate 490 of MUX488.The output terminal of MUX488 is connected on the B input end of totalizer 484.Second input end of totalizer 484 is connected on the output terminal of upper accumulator 500H.The output terminal of upper accumulator 500H also is connected on the first input end of MUX486; Second input end of MUX486 is connected on the output terminal of low bit accumulator 500L.The output terminal of MUX486 is connected on the first input end of totalizer 482, and second input end of totalizer 482 is connected on the output terminal of not gate 490.The output terminal of totalizer 482 is connected on the data input pin of low bit accumulator 500L.The output terminal of totalizer 484 is connected on the data input pin of upper accumulator 500H." carry " output needle of totalizer 482 is connected on " carry is gone into " input pin of totalizer 484.

Operation: general introduction

Error correction system 10 participates in writing and read operation (such as the operation that information stores is stored in the information in the nonvolatile memory 12 to nonvolatile memory 12 and visit).Writing a sector in storer 12, reaching 512 data bytes nearly, 4 header bytes are transferred to error correction system 10.Utilize these 512 data bytes of a sector and reach 4 header bytes, error correction system 10 generates 4 ECC bytes.Reading in the canned data from nonvolatile memory 12, the ECC/ remainder generator 100 of error correction system 10 utilizes these 512 data bytes, 4 header bytes and 4 ECC bytes to generate ECC verification remainder.Counting circuit 104 utilizes ECC verification remainder to generate syndrome S ₁With S ₃And then utilize syndrome S ₁, S ₃Judging the whether inerrancy of this sector, is to have one or two error bits in the sector, and one or two error bit position in this sector (L1-64[complement code] with L2-64[complement code]).

Operation: write operation

In write operation, the data of 512 bytes (titled with the title of 4 bytes nearly) are acted on not only arrive the MUX110 end but also arrive on the line 107 of error correction system 10.The data (titled with reaching 4 header bytes) that act on the MUX110 are transferred to nonvolatile memory 12.

When a new sector acted on the line 107 that arrives error correction system 10, removing comprised register 140 and sends an ECC generation enabling signal ECC to door 144 (step 7-2) at all interior registers (seeing step 7-1 among Fig. 7) and by controller 106.

Header byte is shown step 7-3 and data byte is affacting error correction system 10, arrives totalizer 142 particularly ₃First input end on (see figure 3).The input data are treated as binary value polynomial expression D (X), and wherein each byte provides 8 coefficients to D (X).The position 0 of each byte is the highest ordered coefficients from each byte.For write operation, D (X) comprises behind the available header byte with data byte.ECC/ remainder generator 100 launches the ECC polynomial expression.

ECC (X)=D (X) X ³²Mod G (X) thus each sector can be as in a code word C (X) write non-volatile memory 12, wherein

C(X)＝D(X)X ³²+ECC(X)。

Thereby according to above, 512 byte datas of step 7-3 description effect (titled with 4 byte header nearly) are to totalizer 142 ₃On, byte of each clock.Along with the effect of each byte, the byte that enters is by totalizer 142 ₃Add (XOR) current register 140 that is stored in ₃In byte.Because door 144 is connected (seeing step 7-2) by the ECC signal, from totalizer 142 ₃And act on the linear logic number generator 146.

As discussed above, according to input 8 bit patterns wherein, linear logic number generator 146 is at its output bus 152 ₀-152 ₃Last output byte.The signal of linear logic number generator 146 outputs is to determine uniquely at each clock for each output bus 152.Output bus 152 ₁-152 ₃On signal act on totalizer 142 respectively ₀-142 ₂Input end on.Output bus 152 ₀On signal act on register 140 ₀Input end on.Along with each clock, summation (XOR) is input to the signal of totalizer 142 and loads in separately the downstream register 140 (being to be positioned at the right side of totalizer 142 or the register of outgoing side among Fig. 3).

Input in the above described manner and by 100 computings of ECC/ remainder generator after all data bytes and the header byte (step 7-3), at step 7-4, controller 106 closes swap signal ECC, represents to have finished the generation of four ECC bytes.At this moment, four ECC byte ECC ₃, ECC ₂, ECC ₁, ECC ₀Lay respectively at register 140 ₃-140 ₀In.At step 7-5, go out the content of register 140 as the ECC byte shift of this sector then.For ECC byte ECC ₃, ECC ₂, ECC ₁, ECC ₀Can right shift go out register 140 ₃-140 ₀, at first with byte ECC ₃Byte position 0 act on (for outputing to nonvolatile memory 12) on the line 112 that arrives MUX110.A thereby ECC byte ECC ₃High order R (X) coefficient from the high order end of R (X) and in each ECC byte is the position 0 of this byte.Along with byte ECC ₃Register 140 is shifted out ₃, the right shift of ECC byte makes ECC byte ECC ₀, ECC ₁, ECC ₂Then lay respectively at register 140 ₁-140 ₃In.Byte ECC ₂Then be shifted out, byte ECC is followed in the back in the continuous clock period ₁With ECC ₀

Thereby when the write operation of finishing shown in Fig. 7, ECC/ remainder generator 100 has generated and has exported four ECC byte ECC ₃, ECC ₂, ECC ₁, ECC ₀, these ECC bytes are followed in sector data byte back and are outputed to nonvolatile memory 12.

Read operation

(be illustrated among Fig. 8 prevailingly) in read operation, the ECC/ remainder generator 100 of error correction system 10 utilizes 512 data bytes, 4 header bytes and 4 ECC bytes to generate 4 ECC verification remainder bytes.Counting circuit 104 utilizes ECC verification remainder to generate syndrome S ₁With S ₃Further utilize syndrome S ₁, S ₃Judge the whether inerrancy of this sector, still two error bits are arranged in the sector, and one or two fault address in the sector (the L1-64[complement code] and the L2-64[complement code]).

Now more specifically referring to each step of Fig. 8, at step 8-1, with all register zero clearings of error correction system 10.At step 8-2, signal is taken place in " ECC " connect, to enable and door 144.

At step 8-3, byte-by-byte ground will act on from the sector that nonvolatile memory 12 obtains on the error correction system 10, arrive totalizer 142 particularly ₃ Line 107 on.R (X) is the polynomial expression that receives when reading the sector, R (X)=C (X)+E (X), and wherein C (X) is for wanting to be stored in former sector in the nonvolatile memory 12, and E (X) is the wrong polynomial expression of the sector that received.In execution in step 8-3, draw remainder polynomid REM (X), wherein

REM(X)＝R(X)X ³²mod?G(X)

＝E(X)X ³²mod?G(X)。Thereby,, comprise ECC byte all bytes and be input in the ECC/ remainder generator 100 in interior sector at step 8-3.With the top similar syndrome generating mode of describing with reference to step 7-4, totalizer 142 is with the byte and the register 140 that enter on the line 107 ₃The content addition, and will with (via with door 144) output to linear logic number generator 146.Utilize table 1 in the manner described before, linear logic number generator 146 is output signal on bus 152.Directly with bus 152 ₀On signal loading advance register 140 ₀In, (respectively by totalizer 142 ₀-142 ₂) with bus 152 ₁-152 ₃On signal and the former meaningful XOR respectively of upstream register 140 to generate new value for being stored in register 140 ₁-140 ₃In.When step 8-3 finishes, register 140 ₀-140 ₃In will comprise ECC verification remainder byte REM ₀, REM ₁, REM ₂, REM ₃

At step 8-4, respectively in bus 116 ₀-116 ₃Go up verification remainder byte REM ₀-REM ₃Loaded in parallel is advanced remainder register 102 ₀-102 ₃In.At step 8-5, generate syndrome S then ₁, S ₃And factor S _B

Syndrome S ₁, S ₃And factor S _BGenerate as follows:

S ₁＝R(X)X ³²| _X＝α＝REM(α)

S ₃＝R(X)X ³²| _X＝α ³＝REM(α ³)

S _B＝REM(X)mod(X ⁴+1)

Generate syndrome S at step 8-5 ₁, S ₃And factor S _BIn, connection syndrome generates with door 470 and will arrive each register 400,401 and 402 from 32 place value serial feeds of register 102 (exporting on the online SREG3 (0)).To 32 clocks, with feedback mask register 400,401 and 402.The feedback of register 400 applies with XOR gate 436A, and the feedback of register 401 10 applies from it, and the feedback of register 402 is the α that provided by α multiplier 450 ³Multiplication applies.When 32 clocks finish, syndrome S ₁With S ₃Lay respectively in register 400 and 402, and factor S _BThen be arranged in register 401.

At step 8-7, whether verification syndrome S ₁=syndrome S ₃=factor S _B=0.If the verification of step 8-7 is sure, controller 106 knows that this sector does not comprise mistake and finishes location of mistake and correction operation.Otherwise, handle and proceed with step 8-9.

At step 8-9, " C " is as follows for calculated value: " C " that describe counting circuit 104 in more detail calculates, and ask at substep 8-9 (1) and have bad luck calculation, thereby with 1/S ₁Load in the register 401.In this is asked down, register 400 (packet content S ₁) receive 13 feedback clocks, after this in register 401, draw (with the α basis representation) reciprocal quantity.

After the asking down of substep 8-9 (1),, will measure 1/S in substep 8-9 (2) ₁(with the α basis representation) moves in the register 402.To measure 1/S at substep 8-9 (3) ₁Convert β basis representation and end in register 400.In substep 8-9 (4), with the amount 1/S in the register 400 ₁(with the β basis representation) multiply by the amount 1/S in the register 401 ₁(with the α basis representation) will amass [the 1/S that represents with β ₁ ²] be created in the register 402.Then in substep 8-9 (5), with the content of the register 402 [1/S that represents with β ₁ ²] deliver to register 400 for the amount 1/S that further uses in the register 401 ₁[with the α basis representation] multiplies each other (substep 8-9 (6)), produces the long-pending 1/S that represents with β in register 402 ₁ ³In substep 8-9 (7), with the content [1/S that β represents of register 402 ₁ ³] deliver to register 400 and the value that will be stored among the register SREG3 (is S ₃) load register 401.At substep 8-9 (8) content of register 400 and 401 is multiplied each other, thus in register 402 formation product S ₃/ S ₁ ³[β represents].To amass S at substep 8-9 (9) ₃/ S ₁ ³[β represents] moves on to register 400 and adds α ° (1) thereon, thereby the expression formula of above-mentioned " C " is in register 400.

Whether " vestige " of judging " C " at step 8-10 (trace) (" tr ") is zero.The judgement of step 8-10 is taked and will be stored in position 4 and 8 methods that add together of " C " in the register 400.If the vestige of " C " is zero, then controller 106 signals of output (at step 8-11) illustrate that this sector can not correct.

Suppose the vestige non-zero of " C ", then whether the value in step 8-12 verification " C " is zero.If the value of " C " is zero, controller 106 knows to have only a mistake in (8-13 represents by step) this sector, and position (α that should mistake ^L1) be syndrome S ₁

If C is not equal to zero, controller 106 knows that this sector has two mistakes (to have position alpha ^L1With α ^L2).At definite errors present value α ^L1With α ^L2Before, must find a y to make

y ²+y+c＝0

At step 8-14, state the position that linear combination draws y by taking off:

y _k=∑ _ja _{K, j}C _jWhen step 8-14 line taking combination, should remember that " C " is stored in the register 400.Thereby, in order to obtain linear combination, to each clock circulation, must be with " a _{K, j}" a suitable value load in the register 401." a _{K, j}" value obtain from LIN440." a from LIN440 output _{K, j}" occurrence can learn with reference to table 2.For example, be a _{0, j}Last row of output table 2, one of the top of last row is a _0,0Be a _{1, j}The second last row of output table 2, for 14 and each and the like, constitute the summation of " y ".The linear combination of y [α basis representation] is created in the register 402.

After step 8-14 has determined y, in just having the situation of two mistakes in the sector, step 8-15 counting circuit 104 calculates α ^L1Particularly, in the situation of two mistakes, α ^L1Indicate by step 8-15:

α ^L1＝S ₁y。Certainly in the situation of a mistake, α ^L1Be defined as S ₁(, seeing step 8-12 and 8-13) as top definite.In the situation of a mistake, with S ₁Move on in the register 402.

Integrating step 8-15, at substep 8-15 (1) with syndrome S ₁(β represents) moves in the register 400.To be worth y (α basis representation) moves in the register 401.At substep 8-15 (2) register 400 and 401 is multiplied each other then, in register 402, generate α as a result ^L1=S ₁Y (β represents).In substep 8-15 (3), with α ^L1=S ₁Y is kept at (see figure 4) among the register SREG3.

Step 8-16 comprises definite α ^L2, particularly, α ^L2=S ₁+ α ^L1Thereby, at substep 8-16 (1) with syndrome S ₁Copy to the register 401 from register SREG1.In substep 8-16 (2),, thereby in register 402, obtain α as a result with register 401 and 402 additions ^L2=S ₁+ α ^L1(β represents).In substep 8-16 (3), with α as a result ^L2=S ₁+ α ^L1Be stored in the register 400.

Like this, being two bit-errors situations when having finished step 8-15 and 8-16, just determined α ^L1With α ^L2Value.At step 8-17, by determining log α ^L1With log α ^L2And determine that L1 reaches (being two error situations) L2.From the logarithm operation that reference Figure 10 discusses in more detail, can understand the details that this logarithm is determined.

Result as the logarithm of step 8-17 is determined finally obtains one 14 bit address value for each error bit.Only utilize 12 in the address, wherein the position 4-11 of address value represents that the position 0-3 of makeing mistakes byte and the address value of sector expresses the error bit in the wrongly written character joint.

Suitable bit address order in the value of step 8-18 controller 106 verification L1 and L2 judges that whether this sector can correct and provide about error bit is in data or the status information in ECC or title.Carrying out both also use value L1 and L2 of usage factor SB (generating together) of verification middle controller 106 with syndrome.Particularly, controller 106 observes that L1 determine with the lowest order of L2 and the correspondence of factor S B.This one side, for an error situation, controller 106 is judged S _BWhether equal X ^L1mod4For two error situations, S is confirmed in controller 106 verifications _BEqual X ^L1mod4+ X _L2mod4

In order in physical addressing, to use, the L1 that obtains at step 8-17 and the value of L2 should be placed suitable precedence preface.Thereby at step 8-19 by the register that wherein stores L1 and L2 is carried out supplement and L1 and L2 is placed suitable order.

When step 8-19 has determined available misaddress, in step 8-20 controller 106 indication inverse values L1-64[complement codes] error bit of (and the value L2-64[complement code in two error situations]) indication.If the error bit of address L1 indication is " 1 ", then controller 106 instructions are " 0 " with this bit flipping in the storer 12.Certainly this is unique other value that this potential energy has.Identical correction is carried out in position to address L2 indication in two error situations.

Operation: logarithm is determined

Described among Figure 10 and definite errors present value α ^L1With α ^L2The relevant general step of logarithm.Not that α is shown individually ^L1With α ^L2Logarithm determine that Figure 10 illustrates and is used for determining a representative location of mistake subvalue α ^L(it may be α ^L1Or α ^L2) the step of logarithm.

Logarithm determines to comprise usually the look-up table of consulting such as being stored in the storer.In view of determining such as α ^LThe logarithm of 14 amounts like this comprises inquiry great look-up table this fact, the present invention at step 10-1 with errors present value α ^LConvert its son field to and represent, be i.e. two the 7 plain X of bit ₁With X ₀After this as error correction system 10 determined value J as described in the step 10-2, wherein

J＝log(α _sX ₁ ²+α _s ⁴⁹X ₁X ₀+X ₀ ²)。Then at step 10-3, according to X ₁, X ₀Value select a value K.Value J and K that utilization is determined at step 10-2 and 10-3, at the value L of the following definite searching of step 10-4:

L＝(129J+127K)64mod(127×129)。

Discuss the concrete operations of counting circuit 104 in the step of Figure 10 of the logarithm of actual computation errors present value in more detail referring now to Figure 11.Step 10-1 is described with α ^LConvert its son field to and represent to comprise use field production:

F _s(X)=X ²+ α _s ⁴⁹X+ α _sWherein use from GF (2 ⁷) coefficient, GF (2 ⁷) the field production be

X ⁷+ X ⁵+ X ³+ X+1 is α wherein _sBe GF (2 ⁷) fundamental element.Can be with address α ^LShow to convert to from its full word segment table and comprise from GF (2 ⁷) element to X ₁, X ₀Son field represent.X ₁, X ₀The position be by getting α ^LThe linear combination of position obtain.The linear combination of generation as discussed above " y " (seeing step 8-14), LIN440 participates in determining son field element X ₁, X ₀Linear combination.

Counting circuit is guaranteed α at the beginning ^L1Be arranged in register 400 so that can begin linear combination operation.At substep 10-2, control LIN440 output can be used in α then ^L1Generate X ₁With X ₀Linear combination in a sequence 14 place values.

Table 3 is depicted as the son field value X in the substep 10-2 generation example illustrated ₁With X ₂And output to 14 place values of register 401.Register 401 is obtained 14 different place values (from the different lines of table 3) in each clock of linear combination.This is, utilizes last row of table 3 at first clock of linear combination, and second clock utilizes the second last row, and by that analogy, and along with each linear combination, carry-out bit IP is shifted in the register 402.After seven clocks, comprise X in high 7 of register 402 ₁(seeing Fig. 1 step 11-1).

As step 10-2 is mentioned, counting circuit 104 is for determining that J works, wherein

J=log (α _sX ₁ ²+ α _s ⁴⁹X ₁X ₀+ X ₀ ²) formula 1.J also can be expressed as $J=\log \left({\mathrm{<figure-callout\; id="1"\; label="X"\; filenames="A9519674600341.png,A9519674600351.png"\; state="\{\{state\}\}">X</figure-callout>}}_1^2(\mathrm{\&alpha;}+{\mathrm{\&alpha;}}^{49}\frac{X_0}{{\mathrm{<figure-callout\; id="1"\; label="X"\; filenames="A9519674600341.png,A9519674600351.png"\; state="\{\{state\}\}">X</figure-callout>}}_1},+{\left(\frac{X_0}{X_1}\right)}^2)\right)$ Formula 2 $J=2\mathrm{<figure-callout\; id="1"\; label="log\; X"\; filenames="A9519674600341.png,A9519674600351.png"\; state="\{\{state\}\}">log</figure-callout>}{X}_{}{}_1+\log (\mathrm{\&alpha;}+{\mathrm{\&alpha;}}^{49}\frac{X_0}{{\mathrm{<figure-callout\; id="1"\; label="X"\; filenames="A9519674600341.png,A9519674600351.png"\; state="\{\{state\}\}">X</figure-callout>}}_1}+{\left(\frac{X_0}{X_1}\right)}^2)$ Formula 3 $J=2\mathrm{<figure-callout\; id="1"\; label="log\; X"\; filenames="A9519674600341.png,A9519674600351.png"\; state="\{\{state\}\}">log</figure-callout>}{X}_{}{}_1\mathrm{mod}127+\log (\mathrm{\&alpha;}+\frac{X_0}{X_1}({\mathrm{\&alpha;}}^{49}+\frac{X_0}{X_1}))$ Formula 4

Referring to formula 4, order

TERM1＝2logX ₁mod127

TERM2＝X ₀/X ₁

TERM3＝(α ⁴⁹+X ₀/X ₁)

TERM4＝(X ₀/X ₁)(α ⁴⁹+X ₀/X ₁)

TERM5＝α+(X ₀/X ₁)(α ⁴⁹+X ₀/X ₁)

TERM6=log[α+(X ₀/ X ₁) (α ⁴⁹+ X ₀/ X ₁)] utilize item above to define the following operation that counting circuit 104 is described.

11-1 has generated X in step ₁(be arranged in the high position of register 402) afterwards, at step 11-2 with X ₁Deliver to controller 106 and whether remove to judge X ₁=0.If X ₁=0, controller is provided with sign LOG_FLAG (step 11-3).Because X ₁=0, the expression formula of J (seeing formula 1) is simplified to:

J=logX ₀ ²Formula 5

Also will comprise X at step 11-4 ₁7 high-order loaded in parallel of register 402 advance LOG RAM480 for determining log (X ₁).At step 11-42, determine log (X with reference to the look-up table among the LOG RAM480 ₁).Particularly, table 4 illustrates 128 kinds of 7 logarithm value may importing to LOG RAM480, the output of the first behavior input value 0000000 of table 4, and the output of second behavior value 0000001 of table 4, and by that analogy.If judge X at step 11-2 ₁Be zero, LOG RAM480 is logX ₁Output valve 0.

Basically with the step 11-4 while, when second group of 7 clock of linear combination finishes, in the high position of register 402, generate son field X ₀(step 11-5) and with son field value X ₁Displacement is advanced in the low level of register 402.Then, if sign LOG_FLAG is not provided with (as judging at step 11-6) as yet, counting circuit 104 carries out the task according to more difficult definite J of formula 4.Otherwise, the simplification expression formula of the J that in step 11-7 counting circuit 104 employing formulas 5, proposes.

At step 11-7, counting circuit 104 is with son field element X ₀(now in the high position of register 402) sends among the LOG ROM480.The high position of register 402 can loaded in parallel be advanced among the LOG ROM480.In order to find out logX ₀, LOG ROM480 utilizes its look-up table 4, then with log X ₀Value sends among the totalizer 500H.In order to draw logX ₀ ², only need be shifted (owing to logX for multiply by 2 totalizer 500H ₀ ²=2logX ₀).

Referring to totalizer 500, wherein all produce computing that carries go out signal and cause add " 1 " on totalizer 500.Thereby totalizer 500 is realized the computing of mod (127 * 129) all the time.

In the situation that sign LOG_FLAG is not provided with, counting circuit 104 is carried out the step 11-8 to 11-20 shown in Figure 11.

As shown in step 11-8, the value log (X that step 11-4 is definite ₁) send to the high order end (position 7-13) (promptly arriving totalizer 500H) of totalizer 500.

At step 11-9, in totalizer ACC_H (being totalizer 500H), obtain TERM1 by shifting accumulator ACC-H (so that content be multiply by 2), and if be shifted out one at the end of totalizer ACC_H, then on the low level of ACC_H, add " 1 ".For the log X that in step 11-8, puts into totalizer ACC_H ₁Value, when step 11-9 finished, it (was 2logX that this value becomes TERM1 ₁).

Constitute X at step 11-10 ₁Inverse (be 1/X ₁).Be used to generate X having finished ₁With X ₀Linear combination the time, the value X ₁In the low level of register 402.Preparing X ₁Inverse in, with X ₁(see figure 4) in the low level of immigration register SREG1.For computing reciprocal, will be worth X ₁From register SREG1 is shifted into register 400.At step 11-10, carry out 6 clocks of computing reciprocal, the son field feedback (utilizing XOR gate 436B) of 6 clocks is followed in the back.When 12 clocks asking the 11-10 of falling the step finished, the high order end of register 401 comprised 1/X ₁(α represents).

When with X ₁When copying to the low level (being expressed as SIL) of register SREG1, with X ₀Copy to the high position (being expressed as SIH) of register SREG1 from the high position of register 402.

When having finished step 11-10, it (is X that counting circuit has been ready to generate TERM2 at step 11-11 ₀/ X ₁).Thereby, with X ₀Be displaced to the register 400 from the high position of register SREG1.Carry out multiplication on the value of counting circuit 104 in register 400 and 401, represent to amass X with β ₀/ X ₁Output to register 402 (high position).

Obtain in order to carry out multiplication

TERM4=(X ₀/ X ₁) (α ⁴⁹+ X ₀/ X ₁) one of the parenthesized factor must be β basis representation and another is the α basis representation.Counting circuit 104 so far has obtained an X ₀/ X ₁, but just in the β basis representation.In order to produce the multiplication of TERM4, also must draw the item X of α basis representation ₀/ X ₁Therefore, at step 11-12, carry out the X that the conversion of β to α base obtains the α basis representation ₀/ X ₁

Before execution in step 11-12, with the X of β basis representation ₀/ X ₁Be stored in the high order end of register 402.In step 11-12, with the X of β basis representation ₀/ X ₁Be displaced in the low order end of register 402.Utilize XOR gate 406 feedback (utilizing the position 1,3,5 and 7 of register 402) then, timing register 402 is so that generate the X of α basis representation (but reverse precedence preface) in its high position ₀/ X ₁Thereby when step 11-12 finishes, the X that the low order end of register 402 (promptly low 7) has the β basis representation ₀/ X ₁The high order end of register 402 (being high 7) then has the X of α basis representation (but reverse precedence preface) ₀/ X ₁As the result of step 11-12, obtained the X of α basis representation ₀/ X ₁, but for useful in drawing TERM3, promptly

TERM3=(α ⁴⁹+ X ₀/ X ₁) factor X ₀/ X ₁Bit pattern must put upside down (because it is to be stored in the high order end of register 402 with the precedence preface of falling).In order to place factor X with correct precedence preface ₀/ X ₁(α basis representation), at step 11-13, register 402 loaded in parallel α multipliers 450 and during from the input loaded in parallel register 402 of multiplier 450 in each of 7 clock period cut off the feedback to α multiplier and register 402.In each clock position 13 the content serial of register 402 loaded in the register 401, the result obtains (the α basis representation) factor X of correct precedence preface in register 401 ₀/ X ₁The structure of the α multiplier 450 of such computing shown in Fig. 4.

Like this, the computing of step 11-13 is equivalent to moving to left of register 402, makes it order with position 13, position 12 etc. from wherein reading a 13-7, this means with precedence preface 0,1 ..., 6 read factor X ₀/ X ₁(α basis representation).Thereby factor X with correct precedence preface ₀/ X ₁(α basis representation) reads into register 401 and with factor X ₀/ X ₁(β basis representation) is shifted in the high position of register 402 after moving on in the register 400.

At step 11-14, controller 106 outputs are added to factor X ₀/ X ₁α on (α basis representation) ⁴⁷Value (α basis representation).Then at step 11-15, can be with multiplication factor α ⁴⁷+ X ₀/ X ₁(in register 400 with the α basis representation) multiply by factor X ₀/ X ₁(in register 402 with the β basis representation) and in register 402, draw long-pending (being TERM4) (β basis representation).

At step 11-16, in order to obtain TERM5, promptly

TERM5=α+(X ₀/ X ₁) (α ⁴⁹+ X ₀/ X ₁) and α is added on the TERM4.In order to obtain TERM5, controller 106 is placed on constant value 010000 in the high position of register 401 and for the content addition of register 401 and 402 and connection signal FORCE_IP, the result forms TERM5 in register 401.

After in step 11-16, having formed TERM5, get its logarithm at step 11-17.In order to do like this, TERM5 is loaded in the register 402.If sign LOG_FLAG is not set, then the parallel LOGROM480 that is applied to of the TERM5 in the high position of register 402 is gone up (seeing Fig. 5 B).LOG ROM480 utilizes table 4 to generate corresponding to the logarithm of input signal as look-up table and exports.As the result of step 11-17, from LOGROM480 output TERM6, promptly

TERM6＝log[α+(X ₀/X ₁)(α ⁴⁹+X ₀/X ₁)]。

At step 11-18 (step 11-14 exports from LOG ROM480) TERM6 is added to and is stored in the ACC_H (being totalizer 500H)

TERM1=2logX ₁On the mod127, produce searching value J whereby.

As the expression formula of L, promptly

Shown in L=(129J+127K) 64mod (127 * 129), J (now in ACC_H) must be multiply by 129.Like this, though at step 11-18 (for X ₁≠ 0) still be (for X at step 11-17 ₁=0) draws J, this multiplication takes place at step 11-19.Particularly, will be understood that a value takes advantage of and multiply by 128 and will amass that to be added on the original value be the same again with 129.To do in order finishing like this, in step 11-19 duplicates the J value among the ACC_H (being register 500H) into register ACC-L (being register 500L), thereby in the compound register 500 129J to be arranged.

The J value is a required factor of determined value L just.Pointed as the front to step 10-3, determine that another required value of L is " K ".

At step 11-20, determine K according to following method:

If K=0 is X ₁=0

If 1 X ₁≠ 0 and X ₀=0

F (X ₀/ X ₁) if X ₁≠ 0 and X ₀≠ 0 f (X wherein ₀/ X ₁)=log (y ₁α+y ₀) and log be with α be the end and obtain and y from look-up table ₁, y ₀Be feasible

log(y ₁α+y ₀)＜129

And

y ₀/ y ₁=X ₀/ X ₁Set up from GF (2 ⁷) only element right.For X ₁≠ 0 and X ₂Each of ≠ 0 is to X ₁, X ₀There is a pair of y ₁, y ₀

If 11-16 determines K=0 in step, then finished the calculating (L=129J, L is arranged in register 500 after step 11-16) of L basically.

If X ₁Be not equal to zero, then utilize LOG ROM480 to generate f (X as mentioned above ₀/ X ₁).If 0＜K＜128 then K will be the output of LOG ROM480.The output K of LOGROM480 is illustrated in the table 5.Table 5 is the same with table 4 list all 128 kinds inputs (since 0 increase progressively the input value order, value is arranged in row continuously, and arranges continuously to the top of next column from the bottom of row, as shown in table 4 and 5).

At step 11-21, K be multiply by 127.Step 11-21 utilizes this fact of 127 * K=128K-K.Thereby, be to add K and from the low order end (being ACC_L) of totalizer 500, subtract K on by high order end (ACC_H that has promptly comprised J) to finish at totalizer 500 at the multiplication of step 11-18.In conjunction with subtraction, load 7 zero in the 7 place value fronts of K, this amount is by not gate 490 supplements (promptly 1 become 0 and 0 become 1).Whole 14 place values after the supplement are added to totalizer 500 deduct K to finish.Thereby totalizer 500 has (129J+127K) mod (127 * 129) when step 11-21 finishes.Because all computings that go out for the generation carry are added in one " 1 " on the totalizer 500 as mentioned above, so a mod (127 * 129) is included in the totalizer 500.

At step 11-22,7 outputs of getting L from the position, it is equivalent to multiply by 64.Can find out now and draw desired value L-64[complement code].Subtraction (being finished by above-mentioned computing) former is because remove 32 ECC and 32 pre-multiplications.

Will be understood that in conjunction with the step among situation Figure 11 of two mistakes in the sector and carry out for each is wrong.After this, shown in step 8-18, go up the verification of execution scope in L value (being L1 and L2); The L value is placed to available addressing order (step 8-19); And go up execution in position and correct with the address L1 (and the L2 in two error situations) that determines by error correction system 10.

Though this open in detail with preferred embodiment has been described, for person skilled in the art person, obviously can make therein on the various forms with details on change and do not break away from its spirit and scope.

Table 1

The linear logic tables of data

00001001 11000000?10010000?10000101

00010011 10000001?00100001?00001010

00100111 00000010?01000010?00010100

01001110 00000100?10000100?00101000

10011100 00001001?00001000?01010000

00110001 11010010?10000000?00100101

01100011 10100101?00000000?01001010

11000111 01001010?00000000?10010100

Table 2

Generate the LIN output valve of the linear combination of y

01101000101110

00111010111100

00111010111110

11111000111100

01010010010100

10110101100000

11111000110110

00101111000000

10010000000010

11001010011000

10010000111000

00111111110100

11010110100100

01011010011100

Table 3

Generate son field element X ₁With X ₀The LIN output valve of linear combination

10000000000000

00000001000000

01000001110010

01110011101001

01101001000001

01000000100010

00100010110101

00110100111011

10111010010010

00010011011111

01011110010011

00010011001001

01001001001000

11001000000001

Table 4

LOG ROM0000000 0000011 0000010 00101111111110 1010011 0011101 11100000010011 1010101 1100100 11001111111101 1011101 1010010 01101100010010 1000100 1010100 11100010000110 0100001 1010110 11010000100111 1011011 0100010 11010011111100 0111001 1011100 11010100101011 0001001 00010100010001 0111110 10000110000101 1001000 01000000111011 1000010 11101101001010 0011111 01100110100110 0100100 10110101111011 0001100 01110000011010 1110101 11100110101010 1001110 00101010101110 0110010 00010001100001 1011001 01111010010000 1111001 10011000000100 0011000 01100001011110 0110111 10001111000101 1110010 10000010111010 1101011 11011100111111 0000000 00111101001001 0010100 11001010100101 0000111 10101110001101 0101000 01000111001111 0101100 00010111111010 0111100 11101110011001 1001011 01101001101100 0011011 11101000000001 0101111 00101100101001 1100010 10011010101101 1011111 01100010011100 1000110 11011111100011 1000000 11001101100000 0001110 10110000001111 1010000 11110001010001 1101101 0110101

Table 5

LOG ROM0000001 1011000 0100000 01011110110100 0010001 1110101 11101111100111 0111001 0010101 11111111110010 1100010 1101011 01110111011010 0010000 1000001 00110100111100 1001111 1000010 00011110100001 0110001 1011110 00000000000111 0011101 0011011 10011011010001 1010100 1001110 11000000110101 1101101 0101010 11110101001010 0001110 0101011 01001110100101 0011000 0000100 10001010110110 0001011 1001000 01101110011001 1111001 0011111 10111000111000 1010101 0101001 01100000100010 0001001 1110000 10011001100011 1000100 1010000 10010011111110 0010010 1100100 10111110111110 1000111 1110001 10010110100110 1010011 0110010 11010001111011 1101100 11100111011001 0010110 11010011011101 1100001 01011010010111 0001100 00101001111100 0100011 10000110011100 1100110 10110111110100 1000000 00111101101110 0111111 00000110000010 0101100 01001001000110 1111000 11010101010010 1110110 00001100001010 0001000 01010001010110 0111010 00011011111101 0101110 00100110110011 0111101 00001011010111 1101111 1100101

Claims (55)

1. one kind is used for the solid-state disk drive that simulation disk drive is operated, and comprising:

(a) disk controller is used for providing disk interface to host computer system; And

(b) solid-state disk drive emulator, the response disk drive is translated into compatible solid-state order with disk command; And

(c) a solid storage device array is used to store the non-volatile computer data; And

(d) error correction system, response solid storage device array can correct reaching two by the damage in the memory array or sew the mistake that the unit causes.

2. the solid-state disk drive described in the claim 1, wherein this solid-state memory array comprises the flash EEPROM storer.

3. the solid-state disk drive described in the claim 1, wherein:

(a) this solid-state memory array configurations becomes the row and the row of memory cell; And

(b) road of line display disk and comprise the row of sector; And

(c) nearly two bit-errors occur in the sector.

4. the solid-state disk drive described in the claim 1, wherein this error correction system adopts each code towards the position of handling a byte.

5. the error correction system of the solid-state disk drive of an operation that is used for simulation disk drive, this error correction system comprises:

An ECC/ remainder generator sequentially receives the byte of a sector, and generates the ECC byte and generate verification remainder byte in write operation in read operation;

One group of remainder register wherein is loaded with verification remainder byte;

A counting circuit, the content of serial received remainder register group is to generate two syndromes.

6. the error correction system of claim 5, wherein this remainder register group loaded in parallel has verification remainder byte.

7. the error correction system of claim 6, wherein this remainder register group comprises that loaded in parallel has four eight bit registers of verification remainder byte, wherein these four eight bit registers connect into as a serial shift register operation, and wherein generated after two syndromes, these two syndrome serials are loaded in the low level of serial shift register into.

8. the error correction system of claim 5, wherein the content of this counting circuit serial received remainder register group is used to generate two syndromes and a scope verification factor.

9. the error correction system of claim 8, wherein this error correction system is utilized long-pending 32 code generator polynomials of two 14 polynomial expressions and 4 polynomial expressions, and wherein these 4 polynomial expressions are used for the formation range verification factor.

10. the error correction system of claim 8, wherein this counting circuit utilizes this scope verification factor to come the validity of the performed correction of verification error correction system.

11. the error correction system of claim 5, wherein this error correction system adopts long-pending 32 code generator polynomials of two 14 polynomial expressions and 4 polynomial expressions.

12. the error correction system of claim 11, wherein two 14 polynomial first are polynomial expression (X ¹⁴+ X ¹⁰+ X ⁹+ X ⁶+ X ⁵+ X ⁴+ X ¹), wherein two 14 polynomial second is polynomial expression (X ¹⁴+ X ⁶+ X ⁵+ X ²+ 1), reaching wherein, these 4 polynomial expressions are polynomial expression (X ⁴+ 1).

13. the error correction system of claim 5, wherein this counting circuit comprises the first counter register group and the second counter register group, and wherein this first counter register group and this second counter register group have a feedback circuit, and wherein the content serial-shift of remainder register group are advanced respectively that this first counter register group and the second counter register group are used for generating first syndrome and generate second syndrome in the second counter register group in the first counter register group.

14. the error correction system of claim 13, wherein this counting circuit calculation expression

S wherein ₁Be first syndrome, S ₃Be second syndrome, and α ° be 1, and wherein this counting circuit utilization is calculated C and is determined error number in the sector.

15. the error correction system of claim 14, wherein the vestige function of counting circuit calculating C judges whether this sector can correct.

16. the error correction system of claim 13, wherein this counting circuit utilizes first syndrome to determine at least the first location of mistake subvalue.

17. the error correction system of claim 16, wherein this counting circuit utilizes formula α ^L1=S ₁Y determines the first location of mistake subvalue α ^L1, S wherein ₁Be then y but of first syndrome by the line taking combination

y _K=∑ _jα _{K, j}C _jMake y ²+ y+c=0 finds, and reaches wherein a _{K, j}Value be in the linear search table that is stored in the counting circuit to be comprised.

18. the error correction system of claim 17, wherein this counting circuit utilizes formula α ^L2=S ₁+ α ^L1Determine the second location of mistake subvalue α ^L2

19. the error correction system of claim 16, wherein this counting circuit comprises that the 3rd batch total calculates register, and wherein the content serial-shift of remainder register group is advanced the 3rd batch total and calculate and be used for generating the scope verification factor that the 3rd batch total is calculated register in the register.

20. the error correction system of claim 19, wherein this counting circuit utilizes at least one location of mistake subvalue to judge in the sectors of data part whether an error bit is arranged.

21. the error correction system of claim 16, wherein this counting circuit logarithm of getting at least one location of mistake subvalue is determined misaddress.

22. the error correction system of claim 21, wherein this counting circuit loads into first batch total with this at least one location of mistake subvalue and calculates in the register, and wherein this counting circuit comprises:

Be used to generate the device of a sequential value;

A linear combination circuit generates linear combination X1 in the register and with the first class value sequence and at least one error locator linear combination in order to calculate at second batch total, wherein is included in figure place among the X1 is included in figure place in the error locator half;

Determine log (X ₁) be stored in a look-up table in the storer;

Wherein with this linear combination circuit linear combination second class value sequence to generate linear combination X ₀, wherein be included in X ₀In figure place be included in half of figure place in the error locator; And

Wherein this look-up table is determined log (X ₀).

23. the error correction method of the solid-state disk drive of an operation that is used for simulation disk drive, this error correction method comprises:

Sequentially receive the byte of a sector and in write operation, generate the ECC byte and in read operation, generate verification remainder byte;

With one group of remainder register of verification remainder byte load;

Be input to the content serial of remainder register group in the counting circuit and in read operation, generate two syndromes with this counting circuit.

24. the error correction method of claim 23, wherein this remainder register group loads with verification remainder byte parallel.

25. the error correction method of claim 24, wherein this remainder register group comprises four eight bit registers that load with verification remainder byte parallel, and wherein this method also comprises:

Operating these four eight bit registers as serial shift register is used for its content into counting circuit that is shifted; And

Generate after two syndromes, these two syndrome serials are loaded in the low level of this serial shift register into.

26. the error correction method of claim 23 also comprises:

The content serial of remainder register group is input in the counting circuit; And

Utilize counting circuit to generate two syndromes and a scope verification factor.

27. the error correction method of claim 26, wherein this error correction method uses long-pending 32 code generator polynomials of two 14 polynomial expressions and 4 polynomial expressions, and wherein these 4 polynomial expressions are used to the formation range verification factor.

28. whether the error correction method of claim 26 also comprises and utilizes at least one location of mistake subvalue to come the decision error position in this sectors of data part.

29. the error correction method of claim 23, wherein this error correction method uses long-pending 32 code generator polynomials of two 14 polynomial expressions and 4 polynomial expressions.

30. the error correction method of claim 29, wherein first in these two 14 polynomial expressions is polynomial expression (X ¹⁴+ X ¹⁰+ X ⁹+ X ⁶+ X ⁵+ X ⁴+ X ¹), wherein second in these two 14 polynomial expressions is polynomial expression (X ¹⁴+ X ⁶+ X ⁵+ X ²+ 1), reaching wherein, these 4 polynomial expressions are polynomial expression (X ⁴+ 1).

31. the error correction method of claim 23 also comprises:

The content serial of remainder register group is displaced to first batch total that constitutes counting circuit is calculated register and second batch total is calculated in each group of register; And

In first batch total calculation register, generate first syndrome and calculate generation second syndrome in the register at second batch total.

32. the error correction method of claim 31 also comprises and utilizes counting circuit to come calculation expression

S wherein ₁Be first syndrome, S ₃Be second syndrome, and α ° is 1; And

Utilize counting circuit to calculate C to judge the error number in this sector.

33. the error correction method of claim 32 comprises that also a vestige function that utilizes counting circuit to calculate C is to judge whether this sector can correct.

34. the error correction method of claim 31 also comprises and utilizes counting circuit to determine at least the first location of mistake subvalue with first syndrome.

35. the error correction method of claim 34, wherein this counting circuit utilizes formula α ^L1=S ₁Y determines the first location of mistake subvalue α ^L1, S wherein ₁Be that the first syndrome y then is by the line taking combination

y _k=∑ _jα _{K, j}C _jMake y ²+ y+c=0 finds out, and reaches wherein α _{K, j}Value be to obtain in the linear search table from be included in counting circuit.

36. the error correction method of claim 35 also comprises and utilizes counting circuit formula α ^L2=S ₁+ α ^L1Determine the second location of mistake subvalue α ^L2

37. the error correction method of claim 34 comprises that also the content serial with the remainder register group is displaced in the 3rd batch total calculation register that is included in this counting circuit for calculating the formation range verification factor in the register at the 3rd batch total.

38. the error correction method of claim 37 comprises that also the operational computations circuit utilizes this at least one location of mistake subvalue to come the decision error position whether in this sectors of data part.

39. the error correction method of claim 34 comprises that also the operational computations circuit gets this at least one location of mistake subvalue's logarithm and determine misaddress whereby.

40. the error correction method of claim 39, wherein the operational computations circuit logarithm of getting this at least one location of mistake subvalue comprises:

This at least one location of mistake subvalue is loaded into first batch total to be calculated in the register;

Generate the value of a sequence;

Generate linear combination X in the register in order to calculate at second batch total ₁,, wherein be included in X with the first class value sequence and this at least one error locator linear combination ₁In figure place be included in half of figure place in this error locator;

The look-up table that visit is stored in the storer is determined log (X ₁);

In order to generate linear combination X ₀,, wherein be included in X with the second class value sequence and this at least one error locator linear combination ₀In figure place be included in half of figure place in this error locator; And

Visit this look-up table and determine log (X ₀).

41. the error correction method of claim 23, wherein this counting circuit is used for:

The content serial of remainder register group is received first batch total that constitutes counting circuit calculates register and second batch total and calculates to calculate in each group of register and at first batch total and generate first syndrome in the register and calculate generation second syndrome in the register at second batch total;

The content serial of remainder register group is received the 3rd batch total calculates in the register and generates a scope verification factor;

Judge whether this sector can correct;

Judge the error number in this sector;

Utilize first syndrome to determine one first location of mistake subvalue;

Determine the second location of mistake subvalue;

Get the first location of mistake subvalue and the second location of mistake subvalue's logarithm and determine wrong address in this sector whereby.

42. the error correction method of claim 41, wherein the error number in the sector is to pass through calculation expression

Determine, wherein S ₁Be first syndrome, S ₃Be that second syndrome and α ° are 1.

43. the error correction method of claim 41, wherein this counting circuit utilizes formula α ^L1=S ₁Y determines the first location of mistake subvalue α ^L1, S wherein ₁Be that the first syndrome y then is by the line taking combination

y _k=∑ _jα _{K, j}C _jMake y ²+ y+c=0 finds out, and reaches wherein α _{K, j}Value be that linear search table from be included in counting circuit obtains.

44. the error correction method of claim 41, wherein this counting circuit utilizes formula α ^L2=S ₁+ α ^L1Determine the second location of mistake subvalue α ^L2

45. the error correction method of claim 41, the logarithm of wherein getting at least one location of mistake subvalue comprises:

This at least one location of mistake subvalue is loaded into first batch total to be calculated in the register;

Generate the value of a sequence;

Calculate with first group of sequential value and this at least one error locator linear combination so that at second batch total and to generate linear combination X in the register ₁, wherein be included in X ₁In figure place be included in half of figure place in the error locator;

Visit is stored in look-up table in the storer to determine log (X ₁);

With second group of sequential value and at least one error locator linear combination so that generate linear combination X ₀, wherein be included in X ₁In figure place be included in half of figure place in the error locator; And

The visit look-up table is to determine log (X ₀).

46. error correction system that is used for the solid-state disk drive of simulation disk drive, this error correction system is utilized nearly two mistakes of one 32 each sectors of code generator polynomial role of correcting in system, these 32 code generator polynomials are that two 14 polynomial expressions and 4 polynomial expression are long-pending, and wherein utilize these 4 polynomial expressions to generate to be used for the scope verification factor whether decision error appears at this sectors of data part.

47. the error correction system of claim 46, wherein first in two 14 polynomial expressions is polynomial expression (X ¹⁴+ X ¹⁰+ X ⁹+ X ⁶+ X ⁵+ X ⁴+ X ¹), wherein second in two 14 polynomial expressions is polynomial expression (X ¹⁴+ X ⁶+ X ⁵+ X ²+ 1), 4 polynomial expressions that reach wherein are polynomial expression (X ⁴+ 1).

48. the error correction system of claim 46, this error correction system comprises:

An ECC/ remainder generator sequentially receives the byte of sector and generates the ECC byte and generation verification remainder byte in read operation in write operation;

One group of remainder register that is loaded with verification remainder byte;

A counting circuit, the content of serial received remainder register group is to generate two syndromes.

49. an error correction system that is used for solid-state disk drive, this error correction system are utilized a long-pending generator polynomial of three polynomial expressions, this error correction system comprises:

An ECC/ remainder generator sequentially receives the byte of sector and generates the ECC byte and generation verification remainder byte in read operation in write operation;

One group of remainder register that is loaded with verification remainder byte;

A counting circuit, the content of serial received remainder register group also utilizes in these three polynomial expressions first to generate first syndrome; Second in these three polynomial expressions generates second syndrome; Reach the 3rd the formation range verification factor in three polynomial expressions.

50. the error correction system of claim 49, the wherein operation of this error correction system simulation disk drive.

51. the error correction system of claim 49, wherein this error correction system is utilized nearly two mistakes of one 32 each sectors of code generator polynomial role of correcting in system, these 32 code generator polynomials are that two 14 polynomial expressions and 4 polynomial expressions are long-pending, and wherein these 4 polynomial expressions are used for the formation range verification factor.

52. the error correction system of claim 51, wherein first in these two 14 polynomial expressions is polynomial expression (X ¹⁴+ X ¹⁰+ X ⁹+ X ⁶+ X ⁵+ X ⁴+ X ¹), wherein these two 14 polynomial second is polynomial expression (X ¹⁴+ X ⁶+ X ⁵+ X ²+ 1), reaching wherein, these 4 polynomial expressions are polynomial expression (X ⁴+ 1).

53. whether the error correction system of claim 49 wherein utilizes at least one location of mistake subvalue to come decision error to appear in this sectors of data part.

54. the error correction system of claim 49, wherein this remainder register group comprises four eight bit registers that load with verification remainder byte parallel, wherein these four eight bit registers connect into as a serial shift register job, and wherein after having generated two syndromes and the scope verification factor, serially these two syndromes and the scope verification factor are loaded in this serial shift register.

55. the error correction system of claim 49, wherein this error correction system adopts each code towards the position of handling a byte.

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