CN116978333A

CN116978333A - High-speed signal transmission system applied to display device

Info

Publication number: CN116978333A
Application number: CN202210553017.4A
Authority: CN
Inventors: 罗友龙; 赵自强; 陈泓霖; 何永祥
Original assignee: Raydium Semiconductor Corp
Current assignee: Raydium Semiconductor Corp
Priority date: 2022-04-22
Filing date: 2022-05-20
Publication date: 2023-10-31
Also published as: TWI810907B; TW202343399A

Abstract

The invention discloses a high-speed signal transmission system applied to a display device, which comprises a clock control circuit and a plurality of source drivers. The clock control circuit includes a driver for transmitting a data signal having an embedded clock. Each source driver includes an analog front end and a clock data recovery circuit. The analog front end is coupled to the driver and receives a data signal having an embedded clock. The analog front end includes an adaptive equalizer and the clock data recovery circuit is a binary clock data recovery circuit having a delay locked loop architecture.

Description

High-speed signal transmission system applied to display device

Technical Field

The present invention relates to a display device, and more particularly, to a high-speed signal transmission system for a display device.

Background

As shown in fig. 1, the clock controller TCON of the display panel may be coupled to the farthest driving IC among the plurality of driving ICs D1 to D6 more than 1 meter, so that the traces on the printed circuit board PCB become long to cause serious loss and distortion of the signal transmitted thereby.

At this time, as shown in fig. 2, the receiver RES may compensate the distorted signal in equal proportion by the adaptive equalizer AEQ to restore the signal. Since the signal loss of the far-end driving IC and the near-end driving IC are different, the far-end driving IC and the near-end driving IC located at different positions need to use different compensation settings to achieve signal optimization, and the schematic diagram is shown in fig. 3.

Although the use of a Clock and Data recovery (Clock and Data Recovery, CDR) system that provides both Clock and Data can effectively prevent the Clock and Data recovery circuit from unlocking during the adjustment of the equalizer, as shown in fig. 4, the Clock and Data recovery system needs to have Data channels (Data channels) CH 0-CH 2 and Clock channel (Clock channel) CH3 at the same time, resulting in increased hardware cost.

As shown in fig. 5, the conventional PLL-based clock data recovery circuit 11 includes a phase detector 111, a charge pump 112, a loop filter 113, and a Voltage-controlled oscillator (VCO) 114. During the optimization of the equalizer, the phase information DAT is still transmitted to the following clock data recovery circuit 11, so that the clock data recovery circuit 11 can reconstruct and correct the clock signal by using the phase information DAT. Therefore, the quality of the output signal of the equalizer directly affects the normal operation of the clock data recovery circuit 11. However, since the equalizer is optimized and the clock phase correction is performed simultaneously, the phase information DAT is transmitted to the clock data recovery circuit 11 before the equalizer has completed the optimization, which may possibly cause the clock data recovery circuit 11 to be unlocked.

Conventionally, a Phase-Locked Loop (PLL) architecture is typically used for the clock generator. Since the circuit is operated in the phase correction mode, the data signal only provides phase information and not a clock signal source, only the vco 114 can be used as a clock signal source in the correction loop. However, the disadvantage of using the voltage controlled oscillator 114 as a clock signal source is that: jitter in the clock signal is accumulated in the vco 114, resulting in a large increase in the sampling error rate.

From the above, it can be seen that: there are still a number of problems in the prior art, and further solutions are needed.

Disclosure of Invention

Accordingly, the present invention is directed to a high-speed signal transmission system for a display device, which is effective in solving the above-mentioned problems encountered in the prior art.

One aspect of the present invention is to improve the adaptability and the input jitter resistance of the panel for high-speed data signal transmission.

Another aspect of the present invention is to effectively improve the signal receiving capability of the driving IC by the design of the clock recovery circuit of the adaptive equalizer and delay lock.

A preferred embodiment according to the present invention is a high-speed signal transmission system. In this embodiment, the high-speed signal transmission system is applied to the display device. The high-speed signal transmission system comprises a clock control circuit and a plurality of source drivers. The clock control circuit includes a driver for transmitting a data signal having an embedded clock. Each source driver includes an analog front end and a clock data recovery circuit. The analog front end is coupled to the driver and receives a data signal having an embedded clock. The analog front end includes an adaptive equalizer and the clock data recovery circuit is a binary (Bang-Bang) clock data recovery circuit with a delay locked loop architecture.

In one embodiment, the embedded clock is encoded as a low frequency code.

In one embodiment, the optimization of the adaptive equalizer and the correction of the embedded clock are performed at different time periods.

In one embodiment, the optimal equalizer shift setting of the adaptive equalizer is automatically detected in each source driver to automatically compensate for signal differences generated by the source drivers at different positions.

In one embodiment, the source driver sequentially operates in a first mode, a second mode and a third mode.

In an embodiment, when the source driver is operated in the first mode, the first delay locked loop in the clock data recovery circuit is locked by using the low-frequency clock training, and after the phase locking is completed, the locking signal is changed from the low potential to the high potential.

In an embodiment, when the source driver is operated in the second mode, the lock signal is high, the analog front end receives the data signal with the embedded clock, extracts the embedded clock, inputs the data signal to the delay locked loop to keep the phase lock, and scans all the setting gears of the adaptive equalizer in the interval beyond the embedded clock to find the optimal setting value of the adaptive equalizer, so as to avoid unlocking before the adaptive equalizer is not optimized.

In one embodiment, when the source driver is operating in the third mode, the delay locked loop performs phase locking by using the interval of the embedded clock and performs binary (Bang-Bang) phase correction in the interval other than the embedded clock.

In one embodiment, the source driver further includes an on-chip open Eye (EOM) monitor circuit, an adaptive equalizer control circuit, and a comparator. The adaptive equalizer control circuit is coupled between the EOM monitoring circuit and the adaptive equalizer. The comparator is coupled between the adaptive equalizer and the clock data recovery circuit.

In one embodiment, the adaptive equalizer and comparator operate in a first mode, a second mode, and a third mode and the EOM monitoring circuit and adaptive equalizer control circuit operate in a second mode.

In one embodiment, the clock data recovery circuit includes a clock extractor, a multiplexer, a binary phase detector, a sampler, a voltage controlled delay line, a phase frequency detector, a first charge pump, a serial-to-parallel, a second charge pump, and a loop filter. The multiplexer is coupled between the clock extractor and the voltage-controlled delay line. The phase frequency detector is coupled to the second charge pump. The voltage-controlled delay line and the second charge pump are both coupled to the first charge pump and the loop filter, the sampler is coupled between the voltage-controlled delay line and the binary phase detector, the sequence-to-parallel is coupled to the sampler, the binary phase detector is coupled to the first charge pump, the voltage-controlled delay line, the second charge pump and the phase frequency detector form a first delay phase-locked loop, and the binary phase detector, the first charge pump, the sequence-to-parallel and the sampler form a second delay phase-locked loop.

In one embodiment, the multiplexer, the voltage controlled delay line, the phase frequency detector, the second charge pump and the loop filter operate in a first mode, a second mode and a third mode, the sampler and the sequence are operated in parallel in the second mode and the third mode, and the binary phase detector and the first charge pump operate in the third mode.

In one embodiment, the clock control circuit is disposed on the printed circuit board and the source drivers are coupled to the display panel.

Compared with the prior art, the high-speed signal transmission system applied to the display device of the invention effectively improves the capability of driving I C to receive signals through the design of the self-adaptive equalizer and the delay-locked clock recovery circuit, thereby greatly improving the adaptability and the input jitter resistance of the panel for high-speed data signal transmission and effectively solving various problems encountered in the prior art.

Drawings

Fig. 1 is a schematic diagram showing that the clock controller of the display panel is coupled to each of the drivers I C at different distances.

Fig. 2 is a schematic diagram of a receiver using an equalizer to compensate for distorted signals.

Fig. 3 is a schematic diagram of the remote and near-end drives I C that require different compensation settings to achieve signal optimization.

FIG. 4 is a schematic diagram of a clock data recovery system in which both data channels and clock channels are required.

FIG. 5 is a schematic diagram of a conventional equalizer that transmits phase information to a PLL-based clock recovery circuit before the conventional equalizer has been optimized, which may cause the clock recovery circuit to be unlocked.

Fig. 6 is a schematic diagram of a high-speed signal transmission system applied to a display device according to an embodiment of the invention.

Fig. 7 is a schematic diagram of a source driver in a high-speed signal transmission system according to another embodiment of the invention.

FIG. 8 is a timing diagram of data signals when the source driver is operating in different modes.

FIG. 9 is a timing diagram of signals when the source driver sequentially operates in the first mode, the second mode and the third mode.

Description of main reference numerals:

PCB: printed circuit board with improved heat dissipation

TCON: clock control circuit

RES: receiver with a receiver body

PL: display panel

D1-D6: driving IC

dat_p/N: data signal

AEQ: self-adaptive equalizer

AEQC: self-adaptive equalizer control circuit

IN: input to an adaptive equalizer

INB: input to an adaptive equalizer

OUT: output of adaptive equalizer

OUTB: output of adaptive equalizer

HDMI: high-definition multimedia interface (High Definition Multimedia Interface) system

TX: transmitting end device

RX: receiving end device

DAT0 to DAT2: data signal

CLK: clock signal

CH0 to CH2: data channel

CH3: clock channel

M: clock transmission unit

N: clock transmission unit

11: clock data recovery circuit

111: phase detector

112: charge pump

113: loop filter

114: voltage controlled oscillator

Q1: output of

Q2: output of

UP/DN: flag

I-clk: clock (clock)

Φ -clk: clock (clock)

6: high-speed signal transmission system

TCON: clock control circuit

SIC: source driver

TX: driver(s)

DATP, DATN: data signal with embedded clock

RX: analog front end

CDR: clock data recovery circuit

AEQ: self-adaptive equalizer

SAM: sampling device

MON: on-chip eye opening monitoring circuit

EQOP: self-adaptive equalizer control circuit

LF: loop filter

A1: self-adaptive equalizer control circuit

A2: self-adaptive equalizer

A3: on-chip eye opening monitoring circuit

A4: comparator with a comparator circuit

B1: clock extractor

B2: multiplexer

B3, BBPD: binary phase detector

B4: sampling device

B5: voltage controlled delay line

B6: phase frequency detector

B7: first charge pump

B8: sequence to parallel

B9: second charge pump

B10: loop filter

R: resistor

C: capacitance device

VCTRL: control voltage

Loop1: first delay phase-locked loop

Loop2: second delay phase-locked loop

CK0 to CK56: clock signal

MASK: mask cover

T1: first period of time

T2: a second period of time

T3: third period of time

DAT: data signal

VDD: operating voltage

LOCK: locking signal

MD1: first mode

MD2: second mode

MD3: third mode

CLKT: clock training

DAT1: display data with embedded clock

DAT2: display data with embedded clock

Detailed Description

A preferred embodiment according to the present invention is a high-speed signal transmission system. In this embodiment, the high-speed signal transmission system is applied to the display device, and is used for effectively improving the capability of the driving IC to receive signals through the design of the adaptive equalizer and the delay locked clock recovery circuit, so that the adaptability of the panel to transmit data signals at high speed and the capability of resisting input jitter can be greatly improved, but the invention is not limited thereto.

Referring to fig. 6, fig. 6 is a schematic diagram of a high-speed signal transmission system applied to a display device according to an embodiment of the invention. As shown in fig. 6, the high-speed signal transmission system 6 applied to the display device includes a clock control circuit TCON and a plurality of source drivers SIC. The clock control circuit TCON is disposed on a Printed Circuit Board (PCB) and the source drivers SIC are coupled to the display panel.

The clock control circuit TCON includes a driver TX for transmitting data signals DATP, DATN having an Embedded clock (Embedded clock). The embedded clock is encoded with low frequency, such as 001, 0011, 000111, …, but not limited thereto. Each source driver SIC includes an analog front end RX, a clock data recovery circuit CDR, an on-chip open eye monitor circuit MON, and an adaptive equalizer control circuit EQOP. The analog front end RX is coupled to the driver TX and receives data signals DATP, DATN with embedded clocks from the driver TX. The analog front end RX comprises an adaptive equalizer AEQ. The clock data recovery circuit CDR comprises a sampler SAM. The sampler SAM is coupled to the on-chip open eye monitoring circuit MON. The on-chip open eye monitor circuit MON is coupled to the adaptive equalizer control circuit EQOP. The adaptive equalizer control circuit EQOP is coupled to the analog front end RX. The clock data recovery circuit CDR is a binary (Bang-Bang) clock data recovery (Clock and Data Recovery, CDR) circuit with a delay locked loop (Delay Locked Loop, DLL) architecture.

In this embodiment, the optimal equalizer shift setting of the adaptive equalizer AEQ is automatically detected inside each source driver SIC to automatically compensate for the signal differences generated by the source drivers SIC disposed at different positions. It should be noted that, the optimization process of the adaptive equalizer AEQ and the correction process of the embedded clock are performed in different periods, so that the phase-locked loop can be effectively prevented from being unlocked when the adaptive equalizer AEQ is not optimized, which is obviously different from the optimization process of the equalizer and the correction process of the embedded clock in the prior art.

Referring to fig. 7, fig. 7 is a schematic diagram of a source driver in a high-speed signal transmission system according to another embodiment of the invention. As shown in fig. 7, the source driver si C includes an adaptive equalizer control circuit A1, an adaptive equalizer A2, an on-chip eye-opening monitoring circuit A3, a comparator A4 and a clock data recovery circuit CDR. The adaptive equalizer control circuit A1 is coupled between the on-chip open-eye monitor circuit A3 and the adaptive equalizer A2. The comparator A4 is coupled between the adaptive equalizer A2 and the clock data recovery circuit CDR.

In this embodiment, the clock data recovery circuit CDR includes a clock extractor B1, a multiplexer B2, a binary phase detector B3, a sampler B4, a Voltage controlled delay line (Voltage-Controlled Delay Line, VCDL) B5, a phase frequency detector (Phase Frequency Detector, PFD) B6, a first charge pump (First Charge Pump, CP 1) B7, a Series-To-Parallel (S2P) B8, a second charge pump (Second Charge Pump, CP 2) B9, and a Loop Filter (LF) B10.

The multiplexer B2 is coupled between the clock extractor B1 and the voltage-controlled delay line B5. The phase frequency detector B6 is coupled to the second charge pump B9. The voltage-controlled delay line B5 and the second charge pump B9 are coupled to the first charge pump B7 and the loop filter B10. The sampler B4 is coupled between the voltage-controlled delay line B5 and the binary phase detector B3. The sequence to parallel B8 is coupled to the sampler B4. The binary phase detector B3 is coupled to the first charge pump B7. The voltage-controlled delay line B5, the second charge pump B9 and the phase frequency detector B6 form a first delay locked Loop1 and the binary phase detector B3, the first charge pump B7, the serial-to-parallel B8 and the sampler B4 form a second delay locked Loop2.

In this embodiment, the adaptive equalizer A2 and the comparator A4 are operated in the first mode, the second mode and the third mode. The adaptive equalizer control circuit A1 and the on-chip eye-opening monitoring circuit A3 operate in a second mode. The multiplexer B2, the voltage-controlled delay line B5, the phase frequency detector B6, the second charge pump B9 and the loop filter B10 operate in the first mode, the second mode and the third mode. The sampler B4 and the sequence-to-parallel B8 operate in the second mode and the third mode. The binary phase detector B3 and the first charge pump B7 operate in a third mode.

Referring to fig. 8, fig. 8 is a timing diagram of data signals when the source driver operates in different modes. As shown in fig. 8, when the source driver operates in the MASK (MASK) mode in the first period T1 and the third period T3, the codes of the Embedded clocks (Embedded clocks) of the data signals DATP and DATN output by the driver TX in the clock control circuit TCON are the low frequency codes 0011, and the source driver operates in the binary phase detection (Bang PD) mode in the second period T2 between the first period T1 and the third period T3.

Referring to fig. 9, fig. 9 is a timing diagram of signals when the source driver sequentially operates in the first mode, the second mode and the third mode. As shown in fig. 9, the source driver SIC sequentially operates in a first mode MD1, a second mode MD2 and a third mode MD 3. In this embodiment, the first mode MD1 is a CLK (clock) training mode, the second mode MD2 is a MASK mode+adaptive equalizer, and the third mode MD3 is a MASK mode+bang-Bang PD (binary phase detection) mode.

When the source driver SIC is operated in the first mode (clock training mode) MD1, the first delay locked Loop1 in the clock data recovery circuit CDR shown in fig. 8 is phase-locked by using the low-frequency clock training CLKT. When the phase LOCK is completed, the LOCK signal LOCK is changed from low to high.

When the source driver SIC is operated in the second mode (mask mode+adaptive equalizer AEQ) MD2, the LOCK signal LOCK is high, the analog front end RX receives the data signals DATP and DATN with Embedded clocks (Embedded clocks) and extracts the Embedded clocks therefrom, then inputs the data signals DATP and DATN to the Delay Locked Loop (DLL) to keep the phase LOCK, and scans all the setting positions of the adaptive equalizer AEQ in the interval other than the Embedded clocks to find the optimal setting value of the adaptive equalizer AEQ, so as to avoid the problem of unlocking before the adaptive equalizer AEQ is not optimized.

When the source driver SIC is operated in the third mode (mask mode+binary phase detection mode) MD3, the Delay Locked Loop (DLL) performs phase locking by using the interval of the embedded clock and performs binary (Bang-Bang) phase correction in the interval other than the embedded clock, as shown in fig. 9.

Claims

1. A high-speed signal transmission system for a display device, comprising:

the clock control circuit comprises a driver for transmitting a data signal with an embedded clock; and

a plurality of source drivers, each source driver including an analog front end coupled to the driver and receiving the data signal with the embedded clock;

the analog front end comprises an adaptive equalizer and the clock data recovery circuit is a two-bit clock data recovery circuit with a delay locked loop architecture.

2. The high-speed signal transmission system according to claim 1, wherein the embedded clock is encoded as a low frequency code.

3. The system of claim 1, wherein the optimization of the adaptive equalizer and the calibration of the embedded clock are performed at different time periods.

4. The system of claim 1, wherein each source driver automatically detects an optimal equalizer shift setting of its adaptive equalizer to automatically compensate for signal differences generated by the source drivers at different locations.

5. The system of claim 1, wherein the source driver operates in a first mode, a second mode and a third mode sequentially.

6. The system of claim 5, wherein when the source driver is operating in the first mode, the first delay locked loop in the clock data recovery circuit is phase locked by using low frequency clock training, and the lock signal is changed from low to high after the phase locking is completed.

7. The system of claim 5, wherein when the source driver is operating in the second mode, the lock signal is high, the analog front end receives the data signal with the embedded clock, extracts the embedded clock, inputs the data signal to the delay locked loop to keep the phase lock, and scans all setting positions of the adaptive equalizer in a range other than the embedded clock to find an optimal setting value of the adaptive equalizer, so as to avoid unlocking before the adaptive equalizer is not optimized.

8. The system of claim 5, wherein when the source driver is operating in the third mode, the delay locked loop performs phase locking by using the interval of the embedded clock and performs two-bit phase correction in the interval other than the embedded clock.

9. The system of claim 1, wherein the source driver further comprises an on-chip open-eye monitor circuit, an adaptive equalizer control circuit and a comparator, the adaptive equalizer control circuit being coupled between the on-chip open-eye monitor circuit and the adaptive equalizer, the comparator being coupled between the adaptive equalizer and the clock data recovery circuit.

10. The system of any one of claims 5 or 9, wherein the adaptive equalizer and the comparator operate in the first mode, the second mode and the third mode and the on-chip eye-opening monitor circuit and the adaptive equalizer control circuit operate in the second mode.

11. The system of claim 1, wherein the clock data recovery circuit comprises a clock extractor, a multiplexer, a binary phase detector, a sampler, a voltage controlled delay line, a phase frequency detector, a first charge pump, a sequence-to-parallel, a second charge pump, and a loop filter, the multiplexer being coupled between the clock extractor and the voltage controlled delay line, the phase frequency detector being coupled to the second charge pump, the voltage controlled delay line and the second charge pump being both coupled to the first charge pump and the loop filter, the sampler being coupled between the voltage controlled delay line and the binary phase detector, the sequence-to-parallel being coupled to the sampler, the binary phase detector being coupled to the first charge pump, the voltage controlled delay line, the second charge pump, and the phase frequency detector forming a first delay locked loop, and the binary phase detector, the first charge pump, the sequence-to-parallel, and the sampler forming a second delay locked loop.

12. The system of any one of claims 5 or 11, wherein the multiplexer, the voltage controlled delay line, the phase frequency detector, the second charge pump, and the loop filter are operated in the first mode, the second mode, and the third mode, the sampler and the sequence are operated in parallel in the second mode and the third mode, and the two-bit phase detector and the first charge pump are operated in the third mode.

13. The system of claim 1, wherein the clock control circuit is disposed on a printed circuit board and the source drivers are coupled to the display panel.