CN116974330B - Dynamic frequency adjustment method and device - Google Patents
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- CN116974330B CN116974330B CN202311224740.9A CN202311224740A CN116974330B CN 116974330 B CN116974330 B CN 116974330B CN 202311224740 A CN202311224740 A CN 202311224740A CN 116974330 B CN116974330 B CN 116974330B
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 206010057249 Phagocytosis Diseases 0.000 claims abstract description 57
- 230000008782 phagocytosis Effects 0.000 claims abstract description 57
- 238000004364 calculation method Methods 0.000 claims abstract description 6
- 238000012544 monitoring process Methods 0.000 claims abstract description 6
- 230000008859 change Effects 0.000 claims description 18
- 230000000242 pagocytic effect Effects 0.000 claims description 11
- 230000000873 masking effect Effects 0.000 claims description 4
- 230000009194 climbing Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000013528 artificial neural network Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 210000001539 phagocyte Anatomy 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000006403 short-term memory Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention provides a dynamic frequency adjusting method and a device, which belong to phase-locked loop components in the chip field and solve the problem of overshoot protection of output frequency, and the device comprises a dynamic frequency adjusting unit positioned between a system control unit and a clock generator, wherein the calculation and control logic of the clock generator is realized by the dynamic frequency adjusting unit, the clock generator sends out the system clock frequency to a processor, and a performance monitoring unit in the processor controls the system clock frequency adjustment sent out by the clock generator through a dynamic frequency adjusting device; the clock generator comprises a phase-locked loop subsystem and a pulse phagocytosis unit which are respectively connected with the dynamic frequency adjusting unit, wherein the phase-locked loop subsystem sends out the system clock frequency through the pulse phagocytosis unit, the dynamic frequency adjusting unit sends out a feedback frequency division value to the phase-locked loop subsystem, and sends out a counter critical value to the pulse phagocytosis unit. The invention realizes the efficient dynamic frequency adjustment function with a simplified pure digital circuit structure and smaller hardware resource expenditure.
Description
Technical Field
The present invention relates to phase locked loop assemblies, and more particularly, to a dynamic frequency adjustment method and apparatus.
Background
Low power consumption computing is one of the most important challenges facing computer designers and operators today, and is exacerbated by the ever-increasing demand for faster, smaller, more energy efficient processors. To achieve the above objective, modern processor designs employ a general technique known as dynamic voltage frequency scaling (Dynamic Voltage Frequency Scaling, DVFS). DVFS refers to the dynamic variation of the power supply frequency and voltage of a processor according to the workload requirements of the processor in order to save or optimize the overall power consumption of the system without affecting the system functionality and performance. In general, the overall power consumption of a processor depends on the workload, which refers to the application executing on the processor. For heavy workloads such as gaming, video processing, etc., the processor may run at higher voltages and frequencies in order to achieve higher performance. On the other hand, for lighter workloads such as browsing web pages, word processing, etc., the processor may switch to a lower power supply and frequency to save system power consumption.
In principle, power consumption is proportional to the square of frequency and voltage, and there are some voltage-frequency interdependencies in the processor due to time sequence and other reasons, i.e. voltage reduction leads to frequency reduction, so it can be concluded that: processor power consumption is proportional to the approximate cube of the frequency. In general, dynamic power consumption accounts for a major part of total power consumption, and thus optimizing frequency is an important point in low power design.
Dynamic frequency adjustment is typically achieved by dynamically configuring the feedback divide value (feedback divide value) of the Phase-Locked Loop (Phase-Locked Loop) to adjust the clock frequency of the Phase-Locked Loop output. By varying the feedback divide ratio, the frequency of the Voltage Controlled Oscillator (VCO) can be varied while the phase locked loop is running. A basic phase-locked loop configuration is shown in FIG. 1, where R is the input divide value, Q is the output divide value, n andis a feedback frequency division value (wherein +.>Is a fixed value, n is an adjustable value; />Positive, n can be positive or negative, the sum of the two is positive), PD is a Phase Detector (Phase Detector), loop Filter low pass Filter, VCO is a Voltage controlled oscillator (Voltage-Controlled Oscillator), f in Is the reference clock frequency of the system input, f out Is the clock frequency of the phase locked loop output (i.e., the clock frequency corresponding to the actual application of the system). In conventional solutions, dynamic frequency adjustment uses two or more basic phase-locked loops. General purpose medicineThe dynamic frequency adjustment architecture for k phase-locked loops is shown in fig. 2. k phase locked loops (i=1, 2,., k) are driven by the same signal and their output frequencies are added (or subtracted) to provide an output clock frequency.
In many cases, a discrete step in the division ratio will result in an overshoot (over-shoot) of the output frequency. Gating the output clock or turning off the phase locked loop is considered a straightforward solution if overshoot cannot be tolerated by the phase locked loop clock generation circuit. However, the closing of the phase-locked loop output during frequency conversion constitutes a poor calculation delay added to the overall system calculation, compared to the case where the phase-locked loop can run continuously. For huge enterprises with strong research and development forces and technology accumulation, the deep customized design of the clock generation circuit is generally carried out, and the problem of frequency overshoot in the dynamic adjustment process is solved in the process. However, for enterprises that cannot customize the design circuit, the only option is to use the phase-locked loop IP provided by the provider as a clock generator, and for the best-at-present phase-locked loop IP provider, no clear general solution is available to cope with the problem of frequency overshoot protection in dynamic frequency adjustment faced in user integration; meanwhile, the dynamic frequency adjustment has certain requirements on real-time performance and system response speed (the meaning of dynamic adjustment is lost if the time period from the self oscillation of the phase-locked loop to locking is slower).
Reference to the literature
Sotiriadis P P. Diophantine Frequency Synthesis: A Forward Two-PLL Architecture Case-Study[C]//IEEJ Analog VLSI Workshop. 2007.
Disclosure of Invention
The invention provides a dynamic frequency adjusting method and a device, which solve the problem of overshoot protection of output frequency, thereby optimizing the response speed of a system as much as possible, and the technical scheme is as follows:
the dynamic frequency adjusting device comprises a dynamic frequency adjusting unit positioned between a system control unit and a clock generator, wherein the calculation and control logic of the clock generator is realized by the dynamic frequency adjusting unit, the clock generator sends system clock frequency to a processor, and a performance monitoring unit in the processor controls the system clock frequency sent by the clock generator through the dynamic frequency adjusting device; the clock generator comprises a phase-locked loop subsystem and a pulse phagocytosis unit which are respectively connected with the dynamic frequency adjusting unit, wherein the phase-locked loop subsystem sends out the system clock frequency through the pulse phagocytosis unit, the dynamic frequency adjusting unit sends out a feedback frequency division value to the phase-locked loop subsystem, and sends out a counter critical value to the pulse phagocytosis unit.
The dynamic frequency adjusting unit comprises a feedback frequency dividing value lookup table, a pulse phagocytosis critical table value, an adder and a D trigger, wherein the feedback frequency dividing value lookup table and the pulse phagocytosis critical table value are arranged in parallel, the feedback frequency dividing value lookup table is sequentially connected with the adder and the D trigger to output a current feedback frequency dividing value, and the pulse phagocytosis critical table value outputs a pulse phagocytosis enabling value and a counter critical value.
The feedback frequency division value lookup table provides updated feedback frequency division value step size for the adder, the D trigger provides current feedback frequency division value for the adder, and provides current feedback frequency division value for the phase-locked loop subsystem, and the adder provides updated feedback frequency division value for the D trigger according to the updated feedback frequency division value step size and the current feedback frequency division value, so that the dynamic frequency adjustment unit dynamically selects adjustment steps in the feedback frequency division value lookup table based on the received current feedback frequency division value.
The D trigger is also connected with a reference clock, and outputs the current feedback frequency division value according to the reference clock and a signal for updating the feedback frequency division value by combining with frequency adjustment enabling.
The pulse phagocytosis critical table value is used for determining the pulse to be phagocytosed according to the pulse phagocytosis request, the pulse phagocytosis critical value and the target frequency division ratio of the system control unit, realizing pulse phagocytosis enabling and determining the counter critical value of the pulse phagocytosis unit.
The feedback divider value may be updated by feedback divider value lookup table logic to change its value over a period of time, the pulse phagocytosis threshold table being configured to provide different thresholds to the pulse phagocytosis unit according to different target divider ratios, the feedback divider value lookup table and the pulse phagocytosis threshold table being freely configurable by a user through the system control unit.
The pulse phagocytic unit reduces power consumption by dividing the clock frequency, and comprises a counter and a comparator, wherein the comparator is used for receiving the counter critical value sent by the dynamic frequency adjusting unit, comparing the counter critical value with the count value of the counter by the comparator and outputting a signal to clock gating, and the phase-locked loop subsystem outputs the system clock frequency to the processor through clock gating.
A dynamic frequency adjusting method based on a dynamic frequency adjusting device is realized by the following two modes: (1) Changing the feedback frequency division value of the phase-locked loop subsystem in real time so as to change the output system clock frequency; (2) The pulse phagocytes are turned on and their counter thresholds are adjusted, masking the corresponding number of clock pulses to change the system clock frequency of the output.
Changing the feedback divide value of the phase-locked loop subsystem in real time to thereby change the system clock frequency of the output, comprising the steps of:
s1: the trunk is a system control unit passing through the system on chip, and sends out corresponding control instructions to the dynamic frequency adjustment unit and gives out corresponding control parameters according to the current application scene and power consumption state;
s2: and the dynamic frequency adjusting unit is used for operating and adjusting the clock generator according to the received control instruction information.
Opening the pulse phagocytic unit and adjusting its counter threshold, masking a corresponding number of clock pulses to change the system clock frequency of the output, comprising the steps of:
s11: the phase-locked loop subsystem is not turned off when performing dynamic frequency adjustment, and slowly ramping up the clock frequency to a higher target frequency using discrete variable size frequency steps when transitioning to a target clock frequency higher than the current clock frequency;
s12: the clock frequency is gradually increased by changing the feedback division ratio of the phase-locked loop subsystem, and the additional delay is minimized to be within the range allowed by the safety of the timing margin and the internal signal overshoot behavior constraint of the phase-locked loop subsystem by gradually climbing the frequency ramp.
In the low-power consumption design of the general processor subsystem, the dynamic frequency adjustment method and the device realize the high-efficiency dynamic frequency adjustment function by adopting a simple digital circuit structure and smaller hardware resource expenditure, flexibly adapt different clock generation components and logics in the system on chip (SoC) design, adapt to the mainstream phase-locked loop IP, and simultaneously, only a single phase-locked loop IP can be used instead of a plurality of phase-locked loops in the design of a system clock generation circuit, thereby reducing the expenditure of hardware design.
Drawings
Fig. 1 is a schematic diagram of the basic phase-locked loop structure;
FIG. 2 is a schematic diagram of a generic dynamic frequency adjustment architecture by k phase locked loops;
FIG. 3 is a schematic diagram of the dynamic frequency adjustment device;
fig. 4 is a schematic diagram of the structure of the dynamic frequency adjustment unit;
FIG. 5 is a schematic diagram of the dynamic frequency adjustment unit selecting an adjustment step according to a feedback divider value;
fig. 6 is a schematic diagram of the structure of the pulse phagocytic unit.
Detailed Description
As shown in fig. 3, the dynamic frequency adjustment device comprises a dynamic frequency adjustment unit located between a system control unit and a clock generator, wherein the calculation and control logic of the clock generator is realized by the dynamic frequency adjustment unit, the clock generator sends out the system clock frequency to a processor, and a performance monitoring unit in the processor controls the system clock frequency adjustment sent out by the clock generator through the dynamic frequency adjustment device.
The clock generator comprises a phase-locked loop subsystem and a pulse phagocytosis unit which are respectively connected with the dynamic frequency adjusting unit, wherein the phase-locked loop subsystem sends out the system clock frequency through the pulse phagocytosis unit, the dynamic frequency adjusting unit sends out a feedback frequency division value to the phase-locked loop subsystem, and sends out a counter critical value to the pulse phagocytosis unit.
The system clock frequency of the processor may be achieved in two ways: (1) Changing the feedback frequency division value of the phase-locked loop subsystem in real time so as to change the output system clock frequency; or (2) turn on the pulse phagocytic unit and adjust its counter threshold, masking the corresponding number of clock pulses to change the system clock frequency of the output.
As shown in fig. 4, in one embodiment of the dynamic frequency adjustment unit structure, the dynamic frequency adjustment unit structure includes a feedback frequency dividing value lookup table, a pulse phagocytosis threshold table value, an adder, and a D flip-flop, where the feedback frequency dividing value lookup table and the pulse phagocytosis threshold table value are arranged in parallel, the feedback frequency dividing value lookup table is connected to the D flip-flop through the adder, the D flip-flop provides the feedback frequency dividing value lookup table with a ratio of the feedback frequency dividing value to be adjusted based on the remaining feedback frequency dividing value, and calculates a difference between the target feedback frequency dividing value and the current feedback frequency dividing value, and the difference will look up a configurable stride size through the feedback frequency dividing value lookup table, which means that different differences will result in different steps so that the dynamic frequency adjustment unit shown in fig. 4 can operate efficiently. Wherein the ratio of the feedback division value adjusted based on the remaining need may be referred to as the current feedback division value.
Specifically, the feedback divider value lookup table provides an updated feedback divider value step size to the adder, the D flip-flop provides a current feedback divider value to the adder, and provides a current feedback divider value to the phase-locked loop subsystem, and the adder provides an updated feedback divider value to the D flip-flop based on the updated feedback divider value step size and the current feedback divider value. As shown in fig. 5, the dynamic frequency adjustment unit dynamically selects an adjustment step in the feedback divider value lookup table based on the received current feedback divider value. The D trigger is also connected with a reference clock, the reference clock is the clock of the system input phase-locked loop subsystem, the D trigger receives the reference clock and the signal for updating the feedback frequency division value, and the D trigger outputs the current feedback frequency division value by combining with the frequency adjustment enabling. The frequency adjustment enabling source is derived from a system control unit, and the dynamic frequency adjustment unit determines whether to adjust or not by comparing the target feedback frequency division value with the current feedback frequency division value.
The configurable parameters of the dynamic frequency adjustment unit comprise a target feedback frequency division value, an adjustment step length, a pulse phagocytosis critical value and a target frequency division ratio. Wherein:
(1) Target feedback frequency division value: indicating the final value to which the feedback divider value applied by the phase-locked loop subsystem is to be adjusted.
(2) Adjusting the step: an amplitude delta representing the delta change in the feedback divider value applied by the phase-locked loop subsystem.
(3) Adjusting step length: the duration (reference clock period) of a given frequency step representing the feedback division value during a frequency ramp up. Empirically, the time constant is about 6 PFD cycles (FREF/REFDIV), so 20-30 PFD cycles may be sufficient. The adjustment step size is configurable but is not dynamically updated by the internal logic of the dynamic frequency adjustment unit.
The pulse phagocytosis critical table value is used for determining the pulse to be phagocytosed according to the pulse phagocytosis request, the pulse phagocytosis critical value and the target frequency division ratio of the system control unit, realizing pulse phagocytosis enabling and determining the counter critical value of the pulse phagocytosis unit.
The Pulse phagocytosis requests an instruction of Pulse phagocytosis (Pulse switching) issued by a system control unit. Pulse phagocytosis is also a means of frequency regulation, and pulse phagocytosis requests originate from the system control unit, i.e. frequency regulation in the manner of pulse phagocytosis is required.
The pulse phagocytosis threshold is a period of clock pulse phagocytosed (eliminated) after reaching the set value, and the following counter threshold is similar.
The target division ratio refers to the desired value of the clock division given by the system control unit, i.e. how much the clock frequency is expected to drop before (e.g. one half, three quarters, four fifths, etc., where it cannot be lower than one half).
The pulse phagocytosis enabling refers to the clock gating starting and phagocytosing (eliminating) a clock pulse of one period when the count value of the current counter in fig. 6 is equal to the threshold value of the counter.
In the dynamic frequency adjustment unit, the feedback frequency division value can be updated by the feedback frequency division value lookup table logic to change the value thereof in a period of time, and the pulse phagocytosis threshold table is used for providing different threshold values for the pulse phagocytosis unit according to different target frequency division ratios. The feedback frequency division value lookup table and the pulse phagocytosis critical table can be freely configured by a user through the system control unit, so that different quantitative requirements on frequency adjustment control under different application scenes are met.
As shown in fig. 6, the pulse phagocytic unit may reduce power consumption by dividing the clock frequency, and includes a counter for receiving the counter threshold value transmitted from the dynamic frequency adjustment unit, and a comparator for comparing the counter threshold value with the count value of the counter and outputting a signal to the clock gating, and the phase locked loop subsystem outputs the system clock frequency to the processor through the clock gating.
If the count value of the current counter is equal to the critical value of the counter, pulse phagocytosis is given, clock gating is started, clock pulses of one period are phagocytosed (eliminated), and the counter value is reset (0); otherwise (at the start of the pulse phagocytic unit) the counter normally counts up.
The pulse phagocytosis unit is incremented every clock cycle of the source clock signal, and it can phagocytose one clock cycle (pulse) of the source clock signal every time the counter reaches a threshold overflow (flip). The target clock signal refers to a clock signal output by the pulse phagocytic unit, such as the processor system clock shown in fig. 6. The target clock signal may be considered to be the same as the source clock signal, but lacks a few cycles or pulses. The target clock signal has the expected target frequency, is in phase with the source clock signal (from the phase-locked loop subsystem), is quickly adjusted, does not need to change the configuration of the phase-locked loop subsystem, reduces the time loss for waiting for the phase-locked loop to lock again, and does not have the risk of frequency overshoot. In this case, the threshold of the pulse phagocytosis counter may be dynamically updated so that the clock frequency may be dynamically safely divided while the phase-locked loop subsystem is running.
The dynamic frequency adjustment method comprises the following two steps, wherein the first step is to change the feedback frequency division value of the phase-locked loop subsystem in real time so as to change the output system clock frequency, and the method comprises the following steps:
s1: the trunk is used for sending out corresponding control instructions to the dynamic frequency adjustment unit and giving out corresponding control parameters according to the current application scene and power consumption state by the system control unit of the system on chip;
s2: the dynamic frequency adjusting unit is used for further operating and adjusting the clock generator (comprising a phase-locked loop subsystem and a pulse phagocytizing unit) according to the received control instruction information. The optional control loop (dashed line portion in fig. 1) originates from the event driven performance monitoring unit (Performance Monitor Unit, PMU) of the processor, which is programmed to calculate specific events, such as pipeline stalls, utilization of memory subsystems, etc., over a given period of time. The large amount of data is updated continuously according to each task of the application program, the data set is composed of performance parameters of the application program running on the processor, the performance parameters comprise potential time features which possibly reflect potential trends and modes among the features in the data set, and the system clock frequency adjustment can be controlled through a corresponding performance monitoring unit event driven algorithm (such as Long short-term memory (LSTM)) of the artificial neural network.
The second is to turn on the pulse phagocytic unit and adjust its counter threshold, mask the corresponding number of clock pulses to change the system clock frequency of the output, comprising the steps of:
s1: the phase-locked loop subsystem does not shut down when performing dynamic frequency adjustment (transition to a higher target clock frequency), and slowly ramps the clock frequency up to a higher target frequency using discrete variable size frequency steps when transitioning to a target clock frequency higher than the current clock frequency;
s2: the clock frequency is gradually increased by changing the feedback division ratio of the phase-locked loop subsystem, and gradually climbs by the frequency ramp, thereby minimizing the additional delay to within the range allowed by the timing margin safety and the internal signal overshoot behavior constraints of the phase-locked loop subsystem.
The dynamic frequency adjustment method and the device provided by the invention have the following beneficial characteristics:
(1) The dynamic frequency adjusting unit adapting to various clock generating logics is realized through simple digital circuit logic, and the overshoot phenomenon possibly occurring in the frequency dynamic adjusting process is effectively solved.
(2) The frequency adjusting method is flexibly configured, and the response speed of the system adjustment is improved to the maximum extent.
(3) Using only a single phase-locked loop IP instead of multiple reduces the overhead of hardware design.
The dynamic frequency adjusting device realizes a general dynamic clock frequency adjusting subsystem in the low-power consumption design of the processor system-on-chip, can be adapted to a mainstream clock generator based on the phase-locked loop IP, and has simple realization and small hardware resource expense.
Claims (5)
1. A dynamic frequency adjustment device, characterized by: the system comprises a dynamic frequency adjusting unit positioned between a system control unit and a clock generator, wherein the calculation and control logic of the clock generator is realized by the dynamic frequency adjusting unit, the clock generator sends out the system clock frequency to a processor, and a performance monitoring unit in the processor controls the system clock frequency adjustment sent out by the clock generator through a dynamic frequency adjusting device; the clock generator comprises a phase-locked loop subsystem and a pulse phagocytosis unit which are respectively connected with the dynamic frequency adjusting unit, wherein the phase-locked loop subsystem sends out the system clock frequency through the pulse phagocytosis unit, the dynamic frequency adjusting unit sends out a feedback frequency division value to the phase-locked loop subsystem, and sends out a counter critical value to the pulse phagocytosis unit;
the dynamic frequency adjusting unit comprises a feedback frequency dividing value lookup table, a pulse phagocytosis critical table value, an adder and a D trigger, wherein the feedback frequency dividing value lookup table and the pulse phagocytosis critical table value are arranged in parallel, the feedback frequency dividing value lookup table is sequentially connected with the adder and the D trigger to output a current feedback frequency dividing value, and the pulse phagocytosis critical table value outputs a pulse phagocytosis enabling value and a counter critical value;
the feedback frequency dividing value lookup table provides updated feedback frequency dividing value step length for the adder, the D trigger provides current feedback frequency dividing value for the adder, and provides current feedback frequency dividing value for the phase-locked loop subsystem, the adder provides updated feedback frequency dividing value for the D trigger according to the updated feedback frequency dividing value step length and the current feedback frequency dividing value, and the dynamic frequency adjusting unit dynamically selects an adjusting step length in the feedback frequency dividing value lookup table based on the received current feedback frequency dividing value;
the pulse phagocytic unit reduces power consumption by dividing the clock frequency, and comprises a counter and a comparator, wherein the comparator is used for receiving the counter critical value sent by the dynamic frequency adjusting unit, comparing the counter critical value with the count value of the counter by the comparator and outputting a signal to clock gating, and the phase-locked loop subsystem outputs the system clock frequency to the processor through clock gating.
2. The dynamic frequency adjustment device according to claim 1, characterized in that: the D trigger is also connected with a reference clock, and outputs the current feedback frequency division value according to the reference clock and a signal for updating the feedback frequency division value by combining with frequency adjustment enabling.
3. The dynamic frequency adjustment device according to claim 1, characterized in that: the pulse phagocytosis critical table value is used for determining the pulse to be phagocytosed according to the pulse phagocytosis request, the pulse phagocytosis critical value and the target frequency division ratio of the system control unit, realizing pulse phagocytosis enabling and determining the counter critical value of the pulse phagocytosis unit.
4. The dynamic frequency adjustment device according to claim 1, characterized in that: the feedback frequency division value is updated by feedback frequency division value lookup table logic to change the value thereof in a period of time, and the pulse phagocytosis critical value table is used for providing different critical values for the pulse phagocytosis unit according to different target frequency division ratios, and the feedback frequency division value lookup table and the pulse phagocytosis critical table are freely configured by a user through the system control unit.
5. A dynamic frequency adjustment method based on the dynamic frequency adjustment device according to any one of claims 1 to 4, characterized in that: the system clock frequency of the processor is achieved in two ways: (1) Changing the feedback frequency division value of the phase-locked loop subsystem in real time so as to change the output system clock frequency; (2) Opening a pulse phagocytic unit and adjusting a counter critical value thereof, and shielding a corresponding number of clock pulses so as to change the output system clock frequency;
changing the feedback divide value of the phase-locked loop subsystem in real time to thereby change the system clock frequency of the output, comprising the steps of:
s1: the trunk is a system control unit passing through the system on chip, and sends out corresponding control instructions to the dynamic frequency adjustment unit and gives out corresponding control parameters according to the current application scene and power consumption state;
s2: the dynamic frequency adjusting unit is used for operating and adjusting the clock generator according to the received control instruction information;
opening the pulse phagocytic unit and adjusting its counter threshold, masking a corresponding number of clock pulses to change the system clock frequency of the output, comprising the steps of:
s11: the phase-locked loop subsystem is not turned off when performing dynamic frequency adjustment, and slowly ramping up the clock frequency to a higher target frequency using discrete variable size frequency steps when transitioning to a target clock frequency higher than the current clock frequency;
s12: the clock frequency is gradually increased by changing the feedback division ratio of the phase-locked loop subsystem, and the additional delay is minimized to be within the range allowed by the safety of the timing margin and the internal signal overshoot behavior constraint of the phase-locked loop subsystem by gradually climbing the frequency ramp.
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| CN111384948A (en) * | 2018-12-30 | 2020-07-07 | 炬芯（珠海）科技有限公司 | Frequency switching method, circuit and clock generating device for output signal of phase-locked loop |
| US10790838B1 (en) * | 2019-05-14 | 2020-09-29 | Intel Corporation | Method and apparatus to perform dynamic frequency scaling while a phase-locked loop operates in a closed loop |
| CN112713896A (en) * | 2021-01-29 | 2021-04-27 | 武汉大学 | Improved pulse swallowing frequency divider and frequency dividing method for fractional frequency division phase-locked loop |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111384948A (en) * | 2018-12-30 | 2020-07-07 | 炬芯（珠海）科技有限公司 | Frequency switching method, circuit and clock generating device for output signal of phase-locked loop |
| US10790838B1 (en) * | 2019-05-14 | 2020-09-29 | Intel Corporation | Method and apparatus to perform dynamic frequency scaling while a phase-locked loop operates in a closed loop |
| CN112713896A (en) * | 2021-01-29 | 2021-04-27 | 武汉大学 | Improved pulse swallowing frequency divider and frequency dividing method for fractional frequency division phase-locked loop |
Non-Patent Citations (1)
| Title |
|---|
| 高速低功耗传输电路的时钟系统设计;黄志正 等;微电子学与计算机;第25卷(第01期);第108-111页 * |
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