CN1169672C - Stepped etch process - Google Patents
Stepped etch process Download PDFInfo
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- CN1169672C CN1169672C CNB011118806A CN01111880A CN1169672C CN 1169672 C CN1169672 C CN 1169672C CN B011118806 A CNB011118806 A CN B011118806A CN 01111880 A CN01111880 A CN 01111880A CN 1169672 C CN1169672 C CN 1169672C
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- etch process
- protective layer
- substrate
- stepped
- etching
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Abstract
The present invention provides a step type etching method which provides a substrate. A first protective layer and a second protective layer in a pattern type are respectively formed on the corresponding top and bottom surfaces of the substrate. Then first etching technology is carried out to the substrate in order to etch part of the substrate and completely remove the first protective layer simultaneously. Finally, second etching technology is carried out to etch the substrate continuously until the predetermined thickness is realized in order to control the etched thickness of the substrate and the size of a chip.
Description
The present invention relates to a kind of stepped etch technology, relate in particular to a kind of can be widely used in ink-jet head of printer, MEMS (micro electro mechanical system) (Microelectromechanical System, MEMS) and the stepped etch technology on the related process such as semiconductor.
At present, silicon wafer has been widely used in the product of various integrated circuits, photoelectricity (opt electronics), microelectronic element (microelectronics), MEMS (micro electro mechanical system) or the like and has made, luxuriant is main flow, yet silicon wafer is not without at least one drawback when using yet.For example, silicon wafer is one to have the crystalline material of directivity, if when one surperficial silicon wafer for＜100〉lattice direction being carried out an anisotropic etching with a potassium hydroxide (KOH) etching solution, can be owing to the etch-rate difference of potassium hydroxide etch liquid to each lattice direction on the silicon wafer, and silicon wafer surface produce one with former＜100 lattice direction＜110 of face angle 54.74 degree the inclined-plane, and the inclined-plane of this lattice direction promptly can cause loss and waste on the space, and employed silicon wafer sizes is big more in technology, when thickness is thick more, this problem will be more remarkable.
See also Fig. 1 and Fig. 2, Fig. 1 and Fig. 2 are the structural representation of existing chip of ink-jet head, Fig. 1 is disclosed in US Pat.No.6,019,907 " Forming refill for monolithic inkjetprinthead ", as shown in Figure 1, the ink-jet head of printer of prior art is formed on the silicon base 10, it includes two guiding gutters 11,12, be used for carrying at least one ink (not shown), two nozzle chambers 14,15 are located at guiding gutter 11,12 surface is used for spraying this fluid, and two resistor 16,17 are located at respectively between nozzle chambers 14 and guiding gutter 11 and nozzle chambers 15 and the guiding gutter 12, are used to provide the energy of this ink ejection.Wherein, two guiding gutters 11,12 constitute a backfill groove 13, and the function of backfill groove 13 is when reducing the backfill of this ink ejection back, the fluid interference phenomenon that adjacent nozzles chamber 14 or 15 is produced.
See also Fig. 2, it is exposed in US Pat No.5,658,471 " Fabrication of thermalink-jet feed slots in a silicon substrate ", as shown in Figure 2, the ink-jet head of printer of prior art is formed on the silicon base 20, it includes a guiding gutter 21, be formed at the central authorities of silicon base 20, be used for carrying at least one ink (not shown), one dielectric layer 22 is formed on the silicon base 20, two heaters 23,24 are formed at the surface of dielectric layer 22, are used to provide the energy of this ink ejection, and dielectric layer 22 then is in order to isolated silicon base 20 and heater 23,24.Wherein,, but still have similar production method, and all face identical technology bottleneck, the different problem of etch-rate of each lattice direction on the promptly aforementioned silicon wafer though Fig. 1 and Fig. 2 adhere to different structures separately.
As shown in Figure 3, Fig. 3 is the existing schematic diagram of making the ink-jet head of printer chip.See also Fig. 3 A, prior art provides a width W
1, thickness T silicon base 30, and it is carried out a standard cleaning program.Then shown in Fig. 3 B, respectively form a protective layer 31, a patterned protective layer 32P of identical material in top, the bottom surface of silicon base 30, obtaining the picture on surface of two hole slots 33,34, and the distance of 33,34 of two hole slots is L
1, then be L apart from the distance at silicon base 30 edges
0Subsequently silicon base 30 is immersed in a potassium hydroxide (KOH) etching solution, carry out an etch process, till silicon base 30 is fully by eating thrown, have the overall structure of hole slot 33,34 to obtain one, shown in Fig. 3 C.Wherein, the material of formation protective layer 31,32P can be silicon dioxide (SiO
2) or silicon nitride (Si
3N
4).
Yet, with the disclosed process application of Fig. 3 when the described ink gun wafer of Fig. 1 and Fig. 2, can be because of the lattice direction inclined-plane that this etch process produced, and cause some restrictions on the structural design and the loss in space.In addition, because the needs of back segment processing technology, this chip of ink-jet head must be at the L shown in Fig. 3 C
0And L
1Place's gluing to be combining with a black casket (not shown), and then reaches the color separation ink supply and the effect of ink leak not.So in the chip size design, the space loss that the inclined-plane caused of lattice direction in the time of not only need considering anisotropic etching, when more needing its back segment processing technology, the area of gluing place palpus is taken into account (promptly must have enough big L
0And L
1), to reach this purpose, above-mentioned 2 is to cause the excessive reason of prior art chips area.
Therefore, the objective of the invention is to propose a kind of stepped etch process, the excessive problem of above-mentioned to solve (ink gun) chip area.
For achieving the above object; the present invention proposes a kind of stepped etch process; at first on the relative top of a substrate; basal surface forms a first patterned protection layer and one second protective layer respectively; then one first etch process is carried out in this substrate; with this substrate of while etching and this first protective layer; after this first protective layer is removed fully; continue this substrate of etching; until a desired depth; to control thickness and the chip size size of this substrate after etched; and then can keep under original ink-jet function, significantly reduce the size and the thickness of (ink gun) chip.
Advantage of the present invention is to control thickness and the chip size size of this substrate after etched, and another advantage of the present invention is the stepped etch technology that can be widely used on the related process such as ink-jet head of printer, MEMS (micro electro mechanical system) and semiconductor.
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described.In the accompanying drawing:
Fig. 1 and Fig. 2 are the structural representation of existing ink gun wafer;
Fig. 3 is the existing schematic diagram of making the printing ink head wafer;
Fig. 4 is a stepped etch process schematic representation of the present invention;
Fig. 5 is the schematic diagram of the second embodiment of the present invention;
Fig. 6 is the schematic diagram of the third embodiment of the present invention; And
Fig. 7 is the schematic diagram of the fourth embodiment of the present invention.
The drawing reference numeral explanation:
10,20,30,40,50,60,70 silicon base
11,12,21 guiding gutters, 13 backfill grooves
14,15 nozzle chambers, 16,17 resistors
22 dielectric layers, 23,24 heaters
W
1, W
2, W
3, W
4Width
T
1, T
2, T
3Thickness
L
0, L
1, L
2, L
3, L
4, L
5, L
6, L
7Distance
31,32P, 41,42P, 51,52P, 61,62P, 71,72P protective layer
33,34,43,44,53,54,63～65,73～78 hole slots
Fig. 4 to Fig. 7 is a stepped etch process schematic representation of the present invention, please consults Fig. 4 A earlier, the invention provides one with Fig. 3 A in silicon base 30 same widths W
1And thickness T
1A silicon base 40, and it is carried out a standard cleaning program.Then see also Fig. 4 B, respectively form a protective layer 41, a patterned protective layer 42P of unlike material again in top, the two sides, the end of silicon base 40, and obtain the picture on surface with measure-alike two hole slots 43,44 of the hole slot 33,34 of Fig. 3 B.Wherein, protective layer 41,42P have different etch-rates to same etching solution, and the silicon base among the present invention mainly does the usefulness of the chip of ink-jet head of printer, so hole slot 43,44 usefulness mainly as the guiding gutter in the chip of ink-jet head.In addition, silicon base of the present invention also can be replaced by the semi-conducting material that glass, pottery, metal or have a mono-crystalline structures.
Consult Fig. 4 C then, silicon base 40 is immersed in the potassium hydroxide etch liquid carry out an etch process.Since potassium hydroxide etch liquid can etching silicon substrate 40 and protective layer 42P, and the etched speed of silicon base 40 is big than the etched speed of protective layer 42P, so, when silicon base 40 is etched to T shown in Fig. 4 C
2During thickness, protective layer 42P also can be removed, and protective layer 41 is retained.See also Fig. 4 D at last, proceed an etch process, wait to be etched to silicon base 40 and taken out behind the food and clothing fully, get final product substrate thickness T
3(T
3＜T
1), and structure with two hole slots 43,44, and the distance of 43,44 of two hole slots is L
2, be L apart from the distance at silicon base 40 edges
3Wherein the material of protective layer 41,42P is made of metal, pottery or macromolecular material respectively, and if the material of protective layer 41,42P is made of commaterial, then the thickness of protective layer 42P needs less than protective layer 41; Otherwise, constituted by different materials as if protective layer 41,42P, then the etched speed of protective layer 42P must be greater than protective layer 41.At this, above-mentioned etch process also can be a wet etch process, dry etch process or mechanical type processing technology and replaces, and in the etch process among Fig. 4 C and Fig. 4 D, has at least one to get final product for anisotropic etching.
Than the prior art shown in Fig. 3 C, in identical protective layer geometric figure distance L
1Utilize resulting two hole slots of mode of the present invention 43,44 distance L down,
2Increase (L
2＞L
1), and the distance L at two hole slots 43,44 and silicon base 40 edges
3Big (L also becomes
3＞L
0).In addition, utilize the prepared chip of ink-jet head of mode of the present invention, also have a silicon base than the thinner thickness of prior art.
Yet the silicon base area of present embodiment still remains unchanged.
See also Fig. 5, Fig. 5 is the schematic diagram of the second embodiment of the present invention.Its provide one with Fig. 4 A same widths W
1Thickness T
1Silicon base 50, then respectively form a protective layer 51, a patterned protective layer 52P of unlike material in top, the two sides, the end of silicon base 50.On protective layer 52P, form two hole slots 53,54 subsequently, and with the distance of 53,54 of the two hole slots L from the hole slot 43,44 of Fig. 4
1Be reduced into L
4, and the width size of two hole slots 53,54 remains unchanged, and two hole slots 53,54 are L apart from the distance at silicon base 50 edges
5, geometry is shown in Fig. 5 B.In addition; patterned protective layer 52P is by a photoetching technology (photo-etching-process; PEP) finish, and disclosed step is similar among all the other technologies and Fig. 4, treats can obtain the structure of a geometry shown in Fig. 5 D after etching finishes.
Than disclosed first embodiment of Fig. 4 D, the final distance L that two hole slots of Fig. 5 D are 53,54
6Reduce (L significantly
6＜L
2).And if can in the optical mask pattern design, make the distance L of 53,54 of two hole slots
0And the distance L of 33,34 of resulting hole slots of prior art among Fig. 3 C
1Equate, then the width L that this moment, two hole slots, 53,54 outsides were had more
7Part can be done the sufficient room utilization, combines with gluing and with a black casket (not shown), and then reaches the color separation ink supply and the effect of ink leak not.In addition, the second embodiment of the present invention more can be reduced silicon base 50 width dimensions W
2(W
2＜W
1), to reach the purpose of dwindling chip size.
Now will utilize the size L on the photomask geometrical pattern of this design
4, L
3And post etch wafer width dimensions W
2The tabulation the present invention shown in " table 1 " that compares with existing etch process is applied to the physical dimension table of diplopore groove structure.
See also Fig. 6, Fig. 6 is the schematic diagram of the third embodiment of the present invention.See also Fig. 6 A, its also provide one with Fig. 5 same widths W
1Thickness T
1Silicon base 60, consult Fig. 6 B again, and Yu Qiding, two sides, the end form a protective layer 61, a patterned protective layer 62P of unlike material, go up in protective layer 62P subsequently and form three hole slots 63,64,65, and with the distance of 63,64,65 of each hole slots from L
1Be reduced into L
4, and the width size of each hole slot 63,64,65 remains unchanged, and both sides hole slot 63,65 is L apart from the distance at silicon base 60 edges
5, disclosed step is similar among all the other technologies and Fig. 4, treats can obtain the structure of a geometry shown in Fig. 6 C after etching finishes.
Now will utilize the size L on the photomask geometrical pattern of this design
4, L
5And chip width dimensions W after the etching
3Compared with prior art, tabulation the present invention shown in " table 2 " is applied to the physical dimension table of three hole slot structures.
See also Fig. 7, Fig. 7 is the schematic diagram of the fourth embodiment of the present invention, shown in Fig. 7 A, its provide one with Fig. 6 same widths W
1Thickness T
1Silicon base 70; consult Fig. 7 B again; and Yu Qiding, two sides, the end form a protective layer 71, a patterned protective layer 72P of unlike material, go up in protective layer 72P subsequently and form six hole slots 73,74,75,76,77,78, and with the L of the distance between each hole slot from Fig. 4
1Be reduced into L
4, and the width size of each hole slot remains unchanged, and hole slot 73,78 is L apart from the distance at silicon base 70 edges
5, geometry is shown in Fig. 7 B.Disclosed step is similar among all the other technologies and Fig. 4, treats can obtain the structure of a geometry shown in Fig. 7 C after etching finishes.
Now will utilize the size L on the photomask geometrical pattern of this design
4, L
5And chip width dimensions W after the etching
4Compare with existing etch process, tabulation the present invention shown in " table 3 " is applied to the physical dimension table of six hole slot structures.
The fifth embodiment of the present invention; earlier the silicon base wherein among any embodiment of front is carried out one first etch process; again the wherein protective layer (non-patterned protective layer) on the silicon base is carried out one second etch process; with removal earlier; again silicon base is carried out one the 3rd etch process at last; until a predetermined thickness, all the other technologies then embodiment with the front are similar with the etching silicon substrate.
The invention is characterized in: utilize the different etch-rates of two different protective layers, and produce the chip of a size reduction same etching solution.In addition, even two protective layers have identical etch-rate to same etching solution, also can remove the mode (promptly this protective layer being carried out an extra etch process) of one of them protective layer earlier, and reach purpose of the present invention.And when wafer thickness is thick more, use the resulting die size change of the present invention amount ratio high more, and get over for a long time when its hole slot number of geometrical pattern of etching photomask, the chip area minification is also high more.And cooperate following wafer to march toward under the technology of large scale and high density of texture, and utilize of the lifting of the disclosed stepped etch manufacture of the present invention to the production capacity and the output value, greatest help is provided surely.
Than prior art, the present invention can significantly reduce the chip of ink-jet head size and increase the number of nozzle (being hole slot), to also having the effect that improves production capacity in the integral body manufacturing.In addition,, also can be applicable to common device by this technology, as: on the different device such as filtration system, printing ink head system, micro sprue system and sensor.The disclosed stepped etch mode of the present invention can lower the crystallographic tilt corner effect that anisotropic etching causes; and the included step of technology is all similar with the used step of former etching program; do not need the technology of additional complexity, and can reach similar effect in shape yet via the geometrical pattern design of etching solution and protective layer in the structure that finally obtains.
Though the present invention discloses as above in conjunction with aforesaid preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art is in without departing from the spirit or scope of the invention; can make some and change and retouching, so protection scope of the present invention should be defined by the scope of accompanying Claim.
Unit: μ m
Unit: μ m
Claims (19)
1. stepped etch process, this stepped etch process is the etch process that is applied to a substrate, to control thickness and the chip size size of this substrate after etched, this stepped etch process comprises the following steps:
A top, the basal surface relative in this substrate form a first patterned protection layer and one second protective layer respectively;
At least one etch process is carried out in this substrate, with this substrate of while etching and this first patterned protection layer; And
After this first protective layer is removed fully, continue this substrate of etching until a predetermined thickness, to control the thickness and the chip size size of this substrate after etched.
2. stepped etch process as claimed in claim 1, wherein this substrate comprises that glass, pottery, metal or have the semi-conducting material of mono-crystalline structures.
3. stepped etch process as claimed in claim 1, wherein the material of this first, second protective layer is made of metal, pottery or macromolecular material respectively.
4. stepped etch process as claimed in claim 3, wherein the material of this first, second protective layer is made of commaterial, but the thickness of this second protective layer is greater than first protective layer.
5. stepped etch process as claimed in claim 3, wherein the material of this first, second protective layer is made of different materials, and the etched speed of this second protective layer is less than this first protective layer.
6. stepped etch process as claimed in claim 1, wherein this etch process is a wet etch process, dry etch process or mechanical type processing technology.
7. stepped etch process as claimed in claim 1, wherein this etch process is an anisotropic etching process.
8. stepped etch process, this stepped etch process is applied to the etch process of a substrate, and to control thickness and the chip size size of this substrate after etched, this stepped etch process comprises the following steps:
A top, the basal surface relative in this substrate form one first protective layer and one second protective layer respectively;
Carry out a lithography corrosion process, to form a pattern in this first protective layer; And
An etch process is carried out in this substrate, with this first protective layer of while etching and this substrate of part;
Wherein after this etch process is removed this first protective layer fully, still proceed this etch process one preset time,, and then control thickness and chip size size behind this substrate etching with this substrate to one predetermined thickness of etching.
9. stepped etch process as claimed in claim 8, wherein this substrate comprises that glass, pottery, metal or have the semi-conducting material of mono-crystalline structures.
10. stepped etch process as claimed in claim 8, wherein the material of this first, second protective layer is made of metal, pottery or macromolecular material respectively.
11. stepped etch process as claimed in claim 10, wherein the material of this first, second protective layer is made of commaterial, but the thickness of this second protective layer is greater than first protective layer.
12. stepped etch process as claimed in claim 10, wherein the material of this first, second protective layer is made of different materials, and the etched speed of this second protective layer is less than this first protective layer.
13. stepped etch process as claimed in claim 8, wherein this etch process comprises an anisotropic etching process.
14. stepped etch process as claimed in claim 8, wherein this etch process is a wet etch process, dry etch process or mechanical type processing technology.
15. a stepped etch process, this stepped etch process is applied to the etch process of a substrate, and to control thickness and the chip size size of this substrate after etched, this stepped etch process comprises the following steps:
A top, the basal surface relative in this substrate form one first protective layer and one second protective layer respectively;
Carry out a photoetching corrosion, to form a pattern in this first protective layer;
One first etch process is carried out in this substrate, with this substrate of etching;
Carry out one second etch process, to remove this first protective layer; And
Carry out one the 3rd etch process, until a predetermined thickness, and then control thickness and the chip size size of this substrate after etched with this substrate of etching.
16. stepped etch process as claimed in claim 15, wherein this substrate comprises that glass, pottery, metal or have the semi-conducting material of mono-crystalline structures.
17. stepped etch process as claimed in claim 15, wherein the material of this first, second protective layer is made of metal, pottery or macromolecular material respectively.
18. stepped etch process as claimed in claim 15, wherein this first, this second and the 3rd etch process comprises a wet etch process, dry etch process or mechanical type processing technology.
19. stepped etch process as claimed in claim 15 wherein in this first etch process and the 3rd etch process, has at least one to be an anisotropic etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011118806A CN1169672C (en) | 2001-03-23 | 2001-03-23 | Stepped etch process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011118806A CN1169672C (en) | 2001-03-23 | 2001-03-23 | Stepped etch process |
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| Publication Number | Publication Date |
|---|---|
| CN1376581A CN1376581A (en) | 2002-10-30 |
| CN1169672C true CN1169672C (en) | 2004-10-06 |
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|---|---|---|---|
| CNB011118806A Expired - Fee Related CN1169672C (en) | 2001-03-23 | 2001-03-23 | Stepped etch process |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050064714A1 (en) * | 2003-09-19 | 2005-03-24 | Applied Materials, Inc. | Method for controlling critical dimensions during an etch process |
| JP4274556B2 (en) * | 2004-07-16 | 2009-06-10 | キヤノン株式会社 | Method for manufacturing liquid ejection element |
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2001
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