CN116964942A

CN116964942A - Digital-to-analog conversion device and method for eliminating inter-symbol interference

Info

Publication number: CN116964942A
Application number: CN202180095191.2A
Authority: CN
Inventors: 金莫·科利
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-03-05
Filing date: 2021-03-05
Publication date: 2023-10-27
Also published as: WO2022184270A1

Abstract

Embodiments relate to digital-to-analog conversion and intersymbol interference cancellation during the conversion. A device may include at least two digital-to-analog converters connected in parallel with each other and configured to provide a scalable impedance for the device. For each of the at least two digital-to-analog converters, the apparatus may further comprise: a first circuit for providing at least one compensation current to compensate for error currents caused by parasitic capacitances of the respective digital-to-analog converters; a second circuit for detecting a change in data state between successive sampling periods of the respective digital to analog converter and triggering the first circuit to activate the at least one compensation current. An apparatus, a method and a computer program are disclosed.

Description

Digital-to-analog conversion device and method for eliminating inter-symbol interference

Technical Field

The present invention relates generally to the field of digital-to-analog conversion. In particular, some embodiments of the invention relate to inter-symbol interference cancellation in devices for digital-to-analog conversion.

Background

In order to support the latest 5G and conventional 2G standards, a Receive (RX) analog-to-digital converter (ADC) should be able to achieve ultra-wide bandwidth for medium resolution and ultra-high resolution for narrow bandwidth. A Continuous-time (CT) delta-sigma (ΔΣ) ADC with multi-bit quantization and feedback digital-to-analog converter (DAC) may be used to meet the requirements. The wide integrator time constant tuning range required for such multimode operation can be achieved by a readily scalable current steering non-return-to-zero (NRZ) DAC. DAC output scalability is required to find the best compromise between a sufficiently low impedance level for low analog noise and tolerable capacitor area and parasitic capacitance for stable high frequency performance for each mode of operation.

The minimization of the active integrator input capacitance of a CT delta sigma DAC is critical to efficient high frequency noise shaping of the ADC and loop stability of the active integrator. In order to ensure low sensitivity to clock jitter, a multi-bit thermometer-coded DAC consisting of, for example, tens of identical parallel DAC cells may be preferred. These DAC cells can become very large due to the low noise required and the good matching. Thus, the feedback DAC may dominate the parasitic capacitance, limiting the possible signal bandwidth of the CT ΔΣ ADC.

Disclosure of Invention

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

It is an object of the present invention to provide a device and method for compensating for undesired variations in the output caused by parasitic capacitance of a parallel resistive DAC, wherein the DAC is used to provide an impedance extension for the device, which further affects the parasitic capacitance. The requirement that a multi-bit CT delta-sigma ADC support all carrier-aggregation (CA) systems from 2G to 5G can be met by an optimized DAC architecture. The DAC architecture enables lower DAC output parasitic capacitance, high CT delta-sigma ADC bandwidth, and better noise shaping, can easily spread impedance levels, flexibly support all systems from 2G to 5G, and/or reduce ISI in all impedance levels. The embodiment of the invention can provide a sufficient amount of compensation current in time so as to reduce inter-symbol interference of equipment.

The above and other objects are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description and the drawings.

According to a first aspect, there is provided an apparatus for digital to analog conversion. The device may comprise at least two digital-to-analog converters connected in parallel with each other and arranged to provide a scalable impedance for the device. For each of the at least two digital-to-analog converters, the apparatus may further comprise: a first circuit for providing at least one compensation current to compensate for error currents caused by parasitic capacitances of respective ones of the at least two digital-to-analog converters; a second circuit for detecting a change in input data state between successive sampling periods of the respective digital to analog converter and triggering the first circuit to activate the at least one compensation current. This scheme can compensate for intersymbol interference between consecutive input samples. This is achieved by the second circuit activating a compensation current based on the detection of inter-symbol interference in the respective digital-to-analog converter. The second circuit controls the first circuit to feed a compensation current when needed so as to substantially cancel error currents associated with inter-symbol interference.

According to an implementation form of the first aspect, the second circuit may be further configured to detect that the input data remains unchanged between consecutive sampling periods of the respective digital-to-analog converter and to disable the first circuit from the at least one compensation current. This allows at least one compensation current to be fed only when needed in order to compensate for the error current and thus substantially eliminate inter-symbol interference.

According to an implementation form of the first aspect, the second circuit may be configured to activate the at least one compensation current in response to detecting the input data state change and to deactivate the at least one compensation current in response to detecting the input data state change to remain unchanged for the consecutive sampling periods. Thus, at least one compensation current is activated and deactivated by monitoring of the input data of the respective digital-to-analog converter performed by the second circuit. Timely control of the at least one compensation current is provided.

According to an implementation form of the first aspect, the at least two digital-to-analog converters may be coupled to a dynamic element matching circuit. When the DEM algorithm is used, the input data state changes are closely related to the signal, resulting in increased harmonic distortion. The scheme can compensate for the increased intersymbol interference due to the dynamic element matching circuit.

According to an implementation form of the first aspect, the value of the at least one compensation current may be controlled based on the length of the sampling period. This enables multiple sampling periods with the same impedance level to be supported so that a sufficient amount of current can be provided to compensate for the error current.

According to an implementation form of the first aspect, the value of the at least one compensation current may be controlled by determining a duty cycle of the at least one compensation current based on the length of the sampling period. This expands the possible current modifications. Optimal intersymbol interference cancellation with various clock frequencies and impedance levels may be provided. Further, the duty cycle may attenuate analog noise accumulated in the reference current generation chain.

According to an implementation form of the first aspect, the value of the at least one compensation current may be inversely proportional to the length of the sampling period. This enables control of the current values based on the sampling frequency of the respective digital-to-analog converter.

According to an implementation form of the first aspect, the value of the at least one compensation current may be controlled based on predefined current values associated with different levels of the extensible impedance. Thus, continuous calibration of the current may not be required to maintain high signal-to-noise and distortion ratios.

According to an implementation form of the first aspect, the value of the at least one compensation current is controlled by programmable current sources of the first and second circuits. Thus, a flexible and easily adjustable control of the value of the at least one compensation current is provided.

According to an implementation form of the first aspect, the first circuit may be configured to provide or sink the at least one compensation current at an intermediate power supply node shared by the at least two digital-to-analog converters. This enables compensation of the total intersymbol interference occurring in the device with a low complexity implementation. With the addition of the first and second circuits, the output parasitic capacitances and propagation delays of the at least two digital-to-analog converters may remain unchanged. The first and second circuits are not time critical because the circuits primarily cancel the low frequency error component at the shared node.

According to an implementation form of the first aspect, the at least two digital-to-analog converters may comprise a series resistance between a data switch of the at least two digital-to-analog converters and a reference voltage for expanding the expandable impedance, wherein a value of the at least one compensation current depends on a level of the impedance expandable by changing the value of the series resistance. This enables the device to be provided with a larger and/or smaller impedance by controlling the amount of series resistance and further compensates for different error currents due to quantization of the change in parasitic capacitance caused by the change in impedance.

According to an implementation form of the first aspect, the second circuit may be configured to trigger the first circuit to activate the at least one compensation current if the level of the expandable impedance is above a threshold value. This also enables at least one compensation current to be activated when intersymbol interference cancellation is required.

According to a second aspect, there is provided a method for compensating error currents caused by parasitic capacitances of at least two digital-to-analog converters connected in parallel with each other and arranged to provide a scalable impedance. Each of the at least two digital-to-analog converters may be coupled to the first circuit and the second circuit. The method may include: detecting, by the second circuit, a change in input data state of respective ones of the at least two digital-to-analog converters between successive sampling periods; the first circuit is triggered by the second circuit to activate at least one compensation current. This scheme can compensate for intersymbol interference between consecutive input samples. This is achieved by the second circuit activating a compensation current based on the detection of inter-symbol interference in the respective digital-to-analog converter. The second circuit controls the first circuit to feed a compensation current when needed so as to substantially eliminate voltage drops caused by error currents associated with intersymbol interference.

According to an implementation manner of the second aspect, the method may further include: detecting, by the second circuit, that the input data state remains unchanged between consecutive sampling periods; the first circuit is triggered by the second circuit to disable the at least one compensation current. This allows at least one compensation current to be fed only when needed in order to compensate for the error current and thus substantially eliminate inter-symbol interference.

According to one implementation of the second aspect, the first circuit may be triggered to activate the at least one compensation current in response to the second circuit detecting the input data state change and to deactivate the at least one compensation current in response to the second circuit detecting the input data state change remaining unchanged for the consecutive sampling periods. Thus, at least one compensation current is activated and deactivated by monitoring of the input data of the respective digital-to-analog converter performed by the second circuit. Timely control of the at least one compensation current is provided.

According to an implementation manner of the second aspect, the method may further comprise controlling a value of the at least one compensation current based on a length of the sampling period. This enables multiple sampling periods with the same impedance level to be supported so that a sufficient amount of current can be provided to compensate for the error current.

According to one implementation form of the second aspect, the method may comprise controlling the value of the at least one compensation current by determining a duty cycle of the at least one compensation current based on the length of the sampling period. This expands the possible current modifications. Optimal intersymbol interference cancellation with various clock frequencies and impedance levels may be provided. Further, the duty cycle may attenuate analog noise accumulated in the reference current generation chain.

According to an implementation form of the second aspect, the value of the at least one compensation current is inversely proportional to the length of the sampling period. This enables control of the current values based on the sampling frequency of the respective digital-to-analog converter.

According to an implementation form of the second aspect, the method may comprise controlling the value of the at least one compensation current based on predefined current values associated with different levels of the extensible impedance. Thus, continuous calibration of the current may not be required to maintain high signal-to-noise and distortion ratios.

According to an implementation form of the second aspect, the method may comprise controlling the value of the at least one compensation current by programmable current sources of the first and second circuits. Thus, a flexible and easily adjustable control of the value of the at least one compensation current is provided.

According to an implementation manner of the second aspect, the method may include triggering, by the second circuit, the first circuit to activate the at least one compensation current if a level of the expandable impedance is above a threshold value. This also enables at least one compensation current to be activated when intersymbol interference cancellation is required.

In a third aspect, a computer program is provided. The computer program may comprise instructions which, when executed by a computer, cause the computer to perform the method of the second aspect.

Accordingly, implementations of the present invention may provide an apparatus, method and computer program for digital to analog conversion. These and other aspects of the invention are apparent from and will be elucidated with reference to the exemplary embodiments described hereinafter.

Drawings

The accompanying drawings, which are included to provide a further understanding of the exemplary embodiments and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments and together with the description serve to explain the exemplary embodiments. In the drawings:

FIG. 1 shows an example of a device including a dynamic element matching circuit and a plurality of resistive digital-to-analog conversion units for providing an extensible impedance to the device;

FIG. 2 shows an example of a single digital-to-analog converter for providing a scalable impedance and error current caused by intersymbol interference;

fig. 3 shows an example of a device including a digital-to-analog converter for providing a scalable impedance for the device and coupled to first and second circuits for intersymbol interference cancellation;

FIG. 4 shows an example of two digital-to-analog converters coupled to a dynamic element matching circuit;

fig. 5 shows an example of a device comprising two parallel connected digital-to-analog converters, each coupled to a respective first and second circuit for inter-symbol interference cancellation;

fig. 6 shows a block diagram of a device including a plurality of parallel-connected digital-to-analog converters for providing a scalable impedance to the device and a plurality of inter-symbol interference cancellation circuits coupled in parallel with the digital-to-analog converters;

FIG. 7 illustrates an example of a digital-to-analog converter including an impedance extension setting and an example of a logic diagram of the digital-to-analog converter;

fig. 8 shows an example of an intersymbol interference cancellation circuit and an example of a logic diagram of the circuit;

fig. 9 shows an example of a method for compensating error currents caused by intersymbol interference of at least two digital-to-analog converters;

FIG. 10 shows an output spectrum plot of noise transient analog and analog waveforms for a digital-to-analog converter with and without data weighted average dynamic element matching;

FIG. 11 shows an output spectrum plot of noise transient analog and analog waveforms for a digital-to-analog converter with data weighted average dynamic element matching and with and without intersymbol interference cancellation;

fig. 12 illustrates an example of an apparatus for practicing one or more exemplary embodiments of the invention.

In the drawings, like reference numerals are used to designate like parts.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The detailed description provided below in connection with the appended drawings is intended as a description of embodiments and is not intended to represent the only forms in which an example may be constructed or utilized. The description sets forth the functions of the examples and the sequence of operations for constructing and operating the examples. However, the same or equivalent functions and sequences may be accomplished by different examples.

In a narrowband mode with 2G, for example, the signal-to-noise ratio and distortion (signal to noise and distortion, SNDR) need to be increased, which is also limited mainly by the DAC architecture. Minimizing analog noise results in a large DAC cell area. The distortion caused by the individual mismatches of the parallel DAC cells may be mitigated by dynamic element matching (dynamic element matching, DEM) algorithms or the like. A Data weighted-averaging (DWA) DEM algorithm may be used to improve CT delta-sigma ADC SNDR, particularly where the oversampling ratio (oversampling ratio, OSR) is high. The DEM algorithm increases the conversion between 1 and 0 of the individual DAC cells, which rate, unfortunately, depends on the signal. This phenomenon, known as inter-symbol-interference (ISI), causes harmonic distortion even with perfectly matched DAC cells. The amount of ISI depends on the DAC architecture and becomes more important as the DAC output extension range expands.

The DAC may be implemented in different architectures, including a current DAC or a current steering DAC. The current steering DAC may include a transistor-based current source in series with the data switch of the DAC. By virtue of the high output impedance, the current source can relax the data switch on-resistance requirements, thereby maintaining a smaller switch size and lower switch failure. In addition, the output current of the DAC can be widely spread. However, to achieve low output noise and good matching, the transistors of the current source become very large. Similarly, the entire bias chain that provides the reference bias current is critical to ensure low output noise. The large size of the current source forces the parallel DAC cell output wiring to become long, resulting in an increase in output capacitance.

Alternatively, a resistive DAC may be used. In one example of a resistive DAC, the current source transistor may be replaced with a resistor. The integrated resistor can have low noise and good matching, and even without calibration, has a small area/size. The impedance expansion may be direct or may be implemented as a low-noise low dropout regulator (low-dropout regulator, LDO) dedicated to low-noise DACs. However, in such an architecture, the data switching transistor of the DAC easily becomes very large, since a lower on-resistance than the current source is required. Thus, DAC output parasitic capacitance and output failure may increase.

With a resistive DAC, the data switch transistor has only half the supply voltage as the gate-source Voltage (VGS), thereby limiting the switch on-resistance. In another resistive DAC arrangement, the data switching transistor may have the entire supply voltage as VGS, enabling a significantly smaller switching device to achieve equal on-resistance. In another resistive DAC arrangement, instead of connecting the cell resistors between the reference voltages, the cell resistors may be connected between the DAC output and data switches that switch either the positive or negative reference voltages to the cell resistors. Furthermore, the cell resistance may provide isolation from data switch parasitic capacitance and switch failure, such that a minimum parasitic load may be provided for the CT delta-sigma integrator. The method of expanding the impedance level to be able to support the various receiver bandwidths required from 2G to 5G may be limited due to ensuring low DAC output parasitic capacitance.

In CT delta sigma ADC designs, it is desirable to achieve lower and lower impedance levels in order to achieve high SNDR over a wider bandwidth. This requirement increases the current steering DAC area, pushing the output parasitic capacitance to the picofarad range, resulting in excessive power consumption for high clock rate and wide bandwidth operation. On the other hand, the resistive DAC area actually decreases with the impedance level. However, with another resistive DAC arrangement, low area and parasitic capacitance can be achieved, ensuring energy-efficient wide bandwidth operation. On the other hand, narrow bandwidth performance may be affected by ISI-induced distortion. An option is provided for expanding the DAC impedance without affecting the low output parasitic capacitance of the alternative resistive DAC arrangement shown in fig. 1.

Fig. 1 shows an example of a device 100 including a dynamic element matching (dynamic element matching, DEM) circuit 104 and a plurality of resistive digital-to-analog converters 102 for providing a scalable impedance to the device 100, according to an embodiment of the invention. The digital to analog converter 102 may be configured according to another resistive DAC setting or the like. DEM circuitry 104 may be used, for example, for data-weighted-averaging (DWA) DEM.

The apparatus 100 may be used for thermometer coded 10-level differential output resistive digital-to-analog conversion. The device 100 may include nine substantially identical DACs 102 coupled in parallel with each other. The device 100 may also include a series resistance (R/9) between the shared nodes RDD, RSS of the parallel DACs 102. Each DAC may be coupled with a parallel cell resistor R.

By adding series resistors to the two DAC data switching power supplies AVDD, AVSS, the effective DAC impedance can be doubled, halving the internal DAC supply voltage from the original voltage, i.e., VRDD-vrss=1/2 (vadd-vacss). Since there are 9 identical differential DAC cells in parallel with the cell resistor R, the series resistance on the power supply line is equal to R/9 for halving the internal supply voltage and doubling the effective impedance level. Similarly, to again double the effective resistance, the series resistance can be extended from R/9 to R/3. Thus, DAC 102 may provide a scalable impedance to device 100 by adjusting the series resistance value.

The impedance extension method shown in fig. 1 has drawbacks. The device 100 performs well when the impedance is at a minimum level, i.e., when RDD is shorted to AVDD and RSS is shorted to AVSS. However, as the internal DAC power RDD and RSS decrease and the impedance expands, inter-symbol interference (inter-symbol interference, ISI) that causes harmonic distortion occurs.

It is important to address the ISI problem of an impedance-extended resistive DAC setting, otherwise the narrow-band SNDR requirement, e.g., in 2G mode, is not met. For example, the impedance level at the RDD and RSS nodes may be reduced by adding a shunt resistor between the RDD and RSS or using an active shunt regulator. Passive shunt resistors have limited impact while increasing power consumption. Active shunt regulation effectively eliminates the generation of distortion, but at the cost of significant increases in noise, area and power. Alternatively, a return-to-zero DAC may be used that is essentially free of ISI problems. For example, an NRZ DAC may be implemented by two time-interleaved RZ DACs: the first one runs in the first half of the sampling period and the second one runs in the second half of the sampling period. However, this results in double area and double parasitic capacitance, thereby increasing sensitivity to clock jitter and also reducing SNDR.

ISI mitigation may be achieved by modifying the algorithm of the DEM circuit by de-correlating the instantaneous number of DAC cell transitions with the signal. However, these modifications complicate the DEM algorithm, resulting in additional delays that are intolerable for CT ΔΣ ADCs that rely on short feedback delays.

Fig. 2 illustrates a mechanism for causing intersymbol interference in the resistive DAC arrangement of fig. 1 in accordance with an embodiment of the invention. In fig. 2, a single digital-to-analog converter 102x is used to provide the scalable impedance resulting from parasitic capacitance C _pp And C _pm Error current i caused _pp 、i _pm . These error currents can be considered as intersymbol interference when performing digital-to-analog conversion on multiple input samples. Note that the capacitance C _pp And C _pm The behavior of DAC 102x is illustrated and such capacitance is not visible in the physical structure of DAC 102 x. DAC 102x may include, for example, four switches operated by GPP, GNP, GPM and GNM node voltages for controlling the output voltage according to the signal to be converted. The switches may include, for example, PMOS and NMOS transistors, as shown in fig. 2.

DAC output state change occurs, so that GPP and GNP node voltages are changed from AVDD to AVSS, GPM and GNM node voltages are changed from AVSS to AVDD, resulting in output current i _P And i _M Is changed in polarity. During this transition, the parasitic capacitance C of the drain of the switching transistor _pp 、C _pm Series resistance R _scale And an output cell resistor R _unit Charge and discharge, resulting in an error current pulse i _pp And i _pm . The same error current will flow through the cell resistor R in series with the voltage supply _unit Resulting in a resistor R _unit Creating an additional pressure drop. This eventually results in a temporary reduction of the DAC output current. While DAC unit 102x is in continuousParasitic capacitance C when the same state is maintained during the sampling period, i.e. GPP, GNP, GPM and GNM node voltages remain the same _pp And C _pm No charging or discharging occurs. Therefore, the resistor R is not connected from the power supply unit _unit The error current is drawn. These DAC state changes are closely related to the signal, resulting in increased harmonic distortion, particularly when DEM algorithms (e.g., DWA-DEM) are used.

It is an object of the exemplary embodiments to provide improved ISI mitigation techniques and corresponding DAC device architectures. According to the present invention, DAC device architecture for performing ISI mitigation can support all systems from 2G to 5G and beyond by carrier aggregation. In addition, DAC output parasitic capacitance can be reduced, ensuring increased CT delta sigma ADC bandwidth and better noise shaping. Furthermore, flexible support can be provided for all systems from 2G to 5G by easily scalable impedance levels. ISI mitigation techniques may reduce ISI at all impedance levels, particularly when DEM algorithms are used.

Fig. 3 shows an example of a device 300 comprising a digital-to-analog converter 102x for providing a scalable impedance to the device 300. DAC 102x and its operation may correspond to DAC 102x shown in fig. 2. According to an embodiment of the invention, DAC 102x may be coupled to a first circuit 304 and a second circuit 302 for inter-symbol interference cancellation. The device 300, or any variation thereof described herein, may be implemented as part of an analog-to-digital converter (ADC) as a feedback DAC. Thus, the ADC may comprise the device 300. Further, the receiver (e.g., a mobile phone or other mobile device) may include an ADC.

ISI error can be eliminated by first detecting an input data state change that results in a signal due to parasitic capacitance C _pp And C _pm Error current i caused by charging and discharging of (a) _pp And i _pm . When an input data state change is detected, additional compensation current i can be provided to RDD and drawn from the RSS node _DD 、i _SS To eliminate the error current i _pp And i _pm Voltage drop caused. The input data state change may refer to any between the input data and the preconfigured value of the sampled dataWhat changes, e.g., any change in voltage or current values.

The second circuit 302 may be used for ISI detection. The second circuit 302 may be used to detect a change in the state of the input data between two consecutive sampling periods. The sampling period may refer to the time difference between two consecutive samples of the data input of DAC 102x. The sampling period may be equal to the inverse of the sampling frequency, which may include an average number of samples per second. In one embodiment, the control signal det_isi may be generated by comparing the DAC 102x data input with a previous data sample (e.g., with an XOR logic gate) to detect an input data state change. The setting of the second circuit is only an example and the skilled person knows other possible schemes for providing the control signal by comparing two data samples.

The first circuit 304 may be used for ISI correction. ISI correction may be performed by the first circuit 304 based on the control signal det_isi received from the second circuit 302. When the control signal det_isi is at a logic high level (or logic low level, depending on the configuration), the PMOS and NMOS current sources may be turned on, may be provided to RDD and sink (i) from the RSS node _SS ) Compensation current i _DD . If the data input remains unchanged from the previous sample period in the next sample period, the control signal det _ isi may go to a logic low level (or logic high level) disabling the additional current source and the compensation current i, respectively _DD 、i _SS . Different types of switches may be used as current sources, e.g. PMOS and NMOS transistors. In one embodiment, the second circuit may be configured to activate the compensation current if the impedance level of the device 300 is above a threshold. Therefore, even if there is a change in the state of the input data, the compensation current is not unnecessarily triggered when compensation is not required.

ISI error cancellation compensation current i may be characterized for each process corner with small temperature variation _DD 、i _SS So that the correct value can be stored in a small look-up table. Thus, continuous calibration is not required in order to maintain a high SNDR. The required compensation current is typically the output current i _P 、i _M Is a negligible effect on DAC output noise, as is 10% … …% of (a). Similarly, the silicon area and power consumption of the ISI cancellation circuit comprising the first and second circuits 302, 304 may be kept small compared to the main DAC 102 x.

By adding ISI cancellation circuitry, the main resistive DAC output parasitic capacitance and propagation delay remain unchanged. The ISI cancellation circuit is not time critical because it mainly cancels the RDD and low frequency error components at the RDD node. At high frequencies, decoupling capacitors have been able to effectively eliminate unwanted faults.

According to an embodiment, two substantially identical parallel connected resistive DAC cells may be provided for providing a scalable impedance. Each DAC may be coupled to a respective first and second circuit for ISI cancellation, as shown in fig. 5. The DAC 102 in fig. 5 may include, for example, two DACs 102x coupled to DEM, as shown in fig. 4, and thus described together below. In one embodiment, DEM 104 may be DWADEM. DEM 104, however, is optional and may be omitted from device 300. The two DACs 102, 102x may be coupled in parallel between the shared RDD and RSS nodes. The DACs 102, 102x may be further coupled to the outputs OUT of the two DACs 102x _P 、OUT _M A resistance R at. DEM 104 may be used to convert input data Q of a single DAC 102x ₁ And Q ₀ As input and respectively provide data Q to two DACs _P1 、Q _N1 And Q _P0 、Q _N0 。Q _N0 And Q _N1 May be Q _P0 And Q _P1 Is an inverted version of (a). For two rows of thermometer encoded data, dynamic element matching may include, for example, exchanging or not exchanging Q periodically or according to a pseudo-random sequence ₀ And Q ₁ And (5) inputting. For longer thermometer codes, various methods for implementing dynamic element matching algorithms may be used.

The lowest impedance of the scalable impedance may be achieved by switching the resistor R between the positive and negative reference voltages AVDD, AVSS. In one embodiment, the amplification impedance may be achieved by adding a series resistance R between the data switch of the DAC 102, 102x and the reference voltages AVDD, AVSS _scale To realize the method. Series resistor R _scale Variable resistors configured between the RDD and RSS nodes and the reference voltages AVDD, AVSS may be included, for example. Alternatively, the extensible impedance may be implemented with a fixed resistor. In the amplified impedance mode, when at least one of the second circuits 302 is based on the data input Q of the corresponding DAC coupled in parallel with the detection second circuit 302 ₀ 、Q ₁ Upon detecting a change in the input data state of at least one of the DACs 102, the resistor R may be connected in series by opening _scale Compensating source current and sink current i in parallel _DD 、i _SS To dynamically eliminate error currents caused by charge and discharge parasitic capacitances. In one embodiment, the compensation current i _DD 、i _SS Can use a programmable current source i _BB To control. Programmable current source i _BB May be coupled to a current mirror for mirroring the programming current fed to the lower transistor T1 to the upper transistor T2 such that substantially the same current is provided for the slave current source I _BB ISI is eliminated. In one embodiment, the current range of the compensation current may be controlled by controlling the compensation current i _DD 、i _SS Is further extended.

The operation of the device 300 in fig. 5 may correspond to the device 300 in fig. 3, but in fig. 5, each of the two second circuits 302 will have associated data (Q ₁ Or Q ₀ ) As input and based on input data Q ₁ Or Q ₀ A separate control signal det _ isi _0 or det _ isi _1 is output to control the compensation current activated by the first circuit 304 coupled to the respective DAC 102 x. The individually activated compensation currents may be provided and absorbed on the RDD and RSS nodes shared by each of the DACs 102, 102x and ISI cancellation circuits 302, 304 to compensate for the overall output error caused by ISI.

Fig. 6 shows a block diagram of a device 300 comprising a plurality of digital-to-analog converters 102 connected in parallel for providing a scalable impedance to the device 300 and a plurality of inter-symbol interference cancellation circuits 400 coupled in parallel with the digital-to-analog converters 102, according to an embodiment of the invention.

The apparatus 300 may include N (N.gtoreq.2) substantially identical parallel master DAC units 102. The control (ENA, ENB, ENC) and clock inputs (CLK) and outputs (OUTP, OUTM) and power supplies (AVDD, AVSS) of the parallel cells may be connected together. The data input (DAIN) and control signal ENC may be N-bit thermometer coded inputs such that each bit drives one DAC cell 102. The intermediate power supply nodes RDD and RSS of each parallel DAC cell 102 may also be connected together and these nodes may receive compensation currents from N substantially identical parallel ISI cancellation circuits 400.

Each ISI cancellation circuit 400 may be driven with an N-bit thermometer encoded data input (DAIN). Each ISI cancellation circuit 400 may also operate based on the same clock input (CLK) and power supply (AVDD, AVSS) as DAC 102. In addition, ISI cancellation circuit 400 may receive one or more control inputs (ENLIN, ENLRZ). Each of the ISI cancellation circuits 400 is operable to detect a change in data state and to activate a compensation current based on the data input of the corresponding DAC cell when needed. All N parallel compensation current source Outputs (ODD) may be connected to DAC 102 intermediate supply node RDD and all N parallel compensation current sink Outputs (OSS) may be connected to DAC 102 intermediate supply node RSS. ISI cancellation circuit 400 may use a digitally adjustable reference bias current I _BB The reference bias current may be derived from the bandgap reference voltage and similar integrated resistors used in the resistive DAC 102. The operation of the device 300 is further explained in connection with fig. 7 and 8, which show examples of the DAC 102 and ISI cancellation circuit 400 elements.

Fig. 7 shows an example of a digital-to-analog converter 102x including an impedance extension setting and an example of a logic diagram of the digital-to-analog converter 102x according to an embodiment of the present invention. The digital-to-analog converter 102x may be a single DAC of the plurality of DACs 102 shown in fig. 6. The exemplary DAC architecture and its control logic are exemplary settings, and many other possible settings for the same function may be used.

Main data switches MP1, MP2, MN1, MN2 and impedance expansion switches MP3, MP4, MN3, MN4 and cell resistor R of DAC 102 _unit Extension resistor R _scale Can be made lowNoise supplies AVDD and AVSS supply power. The main enable signal ENA may activate operation. With a logic low level, all data switches MP1, MP2, MN1, MN2 may be closed, causing DAC 102x to enter a high impedance state. When the control input is ena=enb=enc=1 in all parallel DAC cells 102 of the device 300, the lowest DAC output impedance can be achieved with RDD shorted to AVDD and RSS shorted to AVSS. When in all parallel DAC cells 102 of the device 300 the control input is enb=0, while the other control signals ENA, ENC remain unchanged, there is a signal from the spreading resistor R between AVDD and RDD and AVSS and RSS _scale Is a series resistance of (a). When R is _scale ＝R _unit When the DAC output impedance may be twice the minimum impedance. For example, the control signal ENA, ENB, ENC may be buffered via a double not gate prior to providing the control signal bena, benb, benc to the impedance expansion switches MP3, MP4, MN3, MN 4.

The control signal ENC may be a thermometer coded control word in which each bit line drives one DAC cell 102x. Thus, it is possible to turn off a certain amount of R _scale The resistor unit further amplifies the impedance, enabling finer granularity control of DAC output impedance and output current in a low complexity modular manner. However, this feature is optional and setting the final R may be used _scale Other ways of doing so. Alternatively, a fixed R may be used _scale The value is such that the switches MP4 and MN4 and the control signal or word ENC can be omitted.

The data input DAIN may be single ended and thermometer coded. For example, DAIN may be converted to differential outputs (bdata, xdata) by simple CMOS latches triggered by the falling edge of the clock. The gates between the differential latch outputs and the data switch gate (GPP, GNP, GPM, GNM) can provide the necessary buffering for fast transition times and disable the switches when the DAC 102x is powered down. For example, the data switch gate may be controlled based on the output of an and gate or an or gate input with differential outputs bdata, xdata, and buffer output bena, benb, benc. The latches and buffers shown may be implemented differently, so that the latches and buffers shown are not present in all embodiments of the apparatus 300.

Fig. 8 shows an example of an intersymbol interference cancellation circuit 400 and an example of a logic diagram of an ISI cancellation circuit according to an embodiment of the present invention.

Output switches TP1, TP2, TN1, TN2 and current source I of ISI cancellation circuit 400 _BB And current mirror transistors T1-T5 may be powered by low noise power supplies AVDD and AVSS. The main enable signal ENLIN may activate operation. Current source I _BB May be programmable and the output of the current source is divided equally to each of the ISI cancellation circuits of device 300.

The single-ended thermometer encoded DAIN signal may be the same data input signal as received by DAC 102 coupled to ISI cancellation circuit 400. The input DAIN may be compared in each parallel ISI cancellation circuit 400 of the device 300 with a previously sampled bit stored in the D flip-flop, e.g. by a CMOS XOR gate, resulting in a signal det_isi. The det_isi signal may be latched through a simple CMOS latch in the same manner as DAIN in DAC 102. The gates between the differential latch outputs bdata, xdata and the data switch gate (GPP, GNP, GPM, GNM) can provide the necessary buffering for fast transition times and disable the switches TP1, TP2, TP3, TP4 when the DAC 102 is powered down. When ISI cancellation circuit 400 detects a change in the state of the input data, signal det_isi may rise to a logic high level, on the falling edge of the clock, signals GPM and GNP may fall to VSS, signals GPP and GNM may rise to VDD, and thus implementation may include source current i _DD And sink current i _SS Is provided. When no input data state change is detected, the signal det_isi is at a logic low level and the compensation current may bypass the current source and sink outputs ODD, OSS.

The current mirror may be implemented with PMOS transistors T1, T2, T3, etc. The PMOS inputs of all of the parallel ISI cancellation circuits 400 of the device 300 may be connected together such that the cancellation current I is adjustable _BB May be divided equally among all N cells of ISI cancellation circuit 400. This current decay is useful because of the error current caused by the parasitic capacitance charge and discharge of the DAC compared to an accurately generated low noise current referenceIs small.

Several sampling periods with the same increased impedance level need to be supported. Thus, when the sampling period is doubled, the compensation current can be halved. Alternatively, the compensation current may be shortened to a current pulse by activating the control signal ENLRZ. For example, if the clock duty cycle is 50%, the compensation current is only valid for half the clock period. For longer sampling periods, the clock duty cycle may be set lower, e.g., as low as 25%, to achieve optimal ISI cancellation with various clock frequencies and impedance levels. Furthermore, the duty cycle may attenuate analog noise accumulated in the reference current generation chain.

Fig. 9 shows an example of a method 900 for compensating error currents caused by inter-symbol interference of at least two digital-to-analog converters according to an embodiment of the invention. For example, the method may be performed with the device 300.

At 902, the method may include detecting, by a second circuit, a change in an input data state of a corresponding digital-to-analog converter between consecutive sampling periods.

At 904, the method may include triggering, by a second circuit, the first circuit to activate at least one compensation current. At least one compensation current may be activated in response to detecting a change in the input data state of the corresponding digital-to-analog converter between successive sampling periods. In one embodiment, at least one compensation current may be deactivated in response to the second circuit detecting that the input data state remains unchanged between consecutive sampling periods.

Other features of the method are directly from the functions and parameters of the method and apparatus (e.g., apparatus 300) as described in the appended claims and throughout the specification and thus are not repeated here.

Fig. 10 shows output spectra of noise transient analog and analog waveforms of a digital-to-analog converter with and without data weighted average dynamic element matching, according to an embodiment of the invention. In the output spectra 1000, 1002 of the noise transient simulation of the parasitic capacitance extracted in the left image in fig. 10, DWADEM (solid line graph 1000) reduces the low frequency noise floor, but instead, significant third order harmonic distortion components appear. For comparison, dashed graph 1002 shows the spectrum without any DEM. Similarly, in the right image in fig. 10, the voltage 1008 on nodes RDD and RSS with DWADEM algorithm shows an error signal very similar to a full wave rectified version of the output signal. Voltage 1004 shows the output waveform of the DAC and voltage 1006 shows the voltages on the RDD and RSS nodes without DEM.

Fig. 11 shows output spectra of noise transient analog and analog waveforms for a digital-to-analog converter with data weighted average dynamic element matching and with and without intersymbol interference cancellation according to an embodiment of the present invention. The left image in fig. 11 shows the output spectrum of a noise transient simulation of parasitic capacitance extracted using DWA DEM algorithm without ISI cancellation (dashed line diagram 1102) and with ISI cancellation (solid line diagram 1100). The right image in fig. 11 shows an analog waveform using DWADEM algorithm with or without ISI cancellation, where voltage 1104 shows the DAC output waveform, voltage 1106 on the RDD and RSS nodes without ISI cancellation, and voltage 1108 on the RDD and RSS nodes with ISI cancellation. By introducing ISI cancellation, improvements in spectrum and voltage can be observed.

Fig. 12 illustrates an example of a device 1200 for implementing one or more exemplary embodiments of the invention. Device 1200 may include, for example, device 300.

The device 1200 may include at least one processor 1202. The at least one processor 1202 may include, for example, one or more of various processing devices, such as a coprocessor, a microprocessor, a controller, a digital signal processor (digital signal processor, DSP), processing circuitry including or not including a DSP, or various other processing devices including integrated circuits including application specific integrated circuits (application specific integrated circuit, ASIC), field programmable gate arrays (field programmable gate array, FPGA), microcontroller units (microcontroller unit, MCUs), hardware accelerators, special-purpose computer chips, or the like.

The device 1200 may also include at least one memory 1204. The at least one memory 1204 may be used to store, for example, computer program code 1206, such as operating system software and application software. The at least one memory 1204 may include one or more volatile storage devices, one or more non-volatile storage devices, and/or combinations thereof. For example, the at least one memory 1204 may be implemented as a magnetic storage device (e.g., hard disk drive, magnetic tape, etc.), an opto-magnetic storage device, or a semiconductor memory (e.g., mask ROM, PROM (programmable ROM), EPROM (erasable PROM), flash ROM, random access memory (random access memory, RAM), etc.).

Device 1200 may also include one or more communication interfaces 1208 that enable device 1200 to send and/or receive information to/from other devices. The communication interface 1208 may be used to provide at least one wireless connection, e.g., a 3GPP mobile broadband connection (e.g., 3G, 4G, 5G). However, the communication interface 804 may be used to provide one or more other types of connections, e.g., wireless local area network (wireless local area network, WLAN) connections, e.g., standardized by the IEEE 802.11 family or Wi-Fi alliance; a short-range wireless network connection, such as a bluetooth, near-field communication (NFC-field communication), or RFID connection; a wired connection, such as a local area network (local area network, LAN) connection, universal serial bus (universal serial bus, USB) connection, or an optical network connection; or a wired internet connection. The communication interface 804 may include or be configured to couple to at least one antenna to transmit and/or receive radio frequency signals. One or more of the various types of connections may also be implemented as separate communication interfaces that may be coupled to or used to couple to multiple antennas.

When the device 1200 is used to implement a certain function, certain and/or certain components of the device 1200 (e.g., the at least one processor 1202 and/or the memory 1204) may be used to implement the function. Further, when at least one processor 1202 is used to implement a function, the function may be implemented using, for example, program code 1206 included in memory 1204.

The functions described herein may be performed, at least in part, by one or more computer program product components (e.g., software components). According to an embodiment, the device 1200 includes a processor or processor circuit, e.g., a microcontroller, which is configured by program code when executed to perform the described embodiments of operations and functions. Alternatively, or in addition, the functions described herein may be performed, at least in part, by one or more hardware logic components. For example, but not limited to, exemplary types of hardware logic components that can be used include field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), application-specific standard product (ASSP), system-on-a-chip (SOC), complex programmable logic devices (complex programmable logic device, CPLD), and graphics processing units (graphics processing unit, GPU).

Device 1200 may include, for example, a computing device, e.g., a base station, network node, server device, client node, mobile phone, tablet, notebook, etc. While device 1200 is shown as a single device, it should be understood that the functionality of device 1200 may be distributed to multiple devices where applicable.

The apparatus 1200 includes means for performing at least one method described herein. In one example, the apparatus includes at least one processor 1202, at least one memory 1204 including program code 1206, which when executed by the at least one processor 1202, is to cause the device 1200 to perform the method.

The apparatus or system may be used to perform or cause to be performed any aspect of one or more methods described herein. Furthermore, the computer program may comprise a program code for performing one aspect of one or more methods described herein when the computer program is executed on a computer. Furthermore, the computer program product may comprise a computer readable storage medium storing program code comprising instructions for performing any aspect of one or more methods described herein. Furthermore, an apparatus may comprise means for performing any aspect of one or more methods described herein. According to an exemplary embodiment, the apparatus comprises at least one processor and at least one memory including program code for performing any aspect of one or more methods when executed by the at least one processor.

Any range or device value given herein may be extended or altered without losing the effect sought. Any embodiment may also be combined with another embodiment unless explicitly disabled.

Although the subject matter has been described in language specific to structural features and/or acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example of implementing the claims, and other equivalent features and acts are intended to be included within the scope of the claims.

It is to be understood that the advantages and benefits described above may relate to one embodiment or may relate to multiple embodiments. Embodiments are not limited to solving any or all of the problems, nor to embodiments having any or all of the advantages and benefits. It should also be understood that reference to "an" item may refer to one or more of those items. Further, reference to "at least one" item or "one or more" items may refer to one or more of those items.

The operations of the methods described herein may be performed in any suitable order, or simultaneously where appropriate. Furthermore, individual blocks may be deleted from any of the methods without departing from the scope of the subject matter described herein. Aspects of any of the embodiments described above may be combined with aspects of any of the other embodiments described to form further embodiments without affecting the desired effect.

The term "comprising" as used herein is intended to include the identified method, block diagram, or element, but such block diagram or element does not include an exclusive list, and the method or apparatus may include additional block diagrams or elements.

It should be understood that the above description is provided by way of example only and that various modifications may be made by one skilled in the art. The above specification, examples and data fully describe the structure and use of the exemplary embodiments. Although various embodiments have been described above in considerable detail or in connection with one or more individual embodiments, those skilled in the art can make numerous variations to the disclosed embodiments without departing from the scope of the invention.

Claims

1. An apparatus (300) for digital to analog conversion, comprising:

at least two digital-to-analog converters (102), wherein the digital-to-analog converters are connected in parallel with each other and are adapted to provide an extensible impedance to the device (300), wherein for each of the at least two digital-to-analog converters (102), the device (300) further comprises:

a first circuit (304), wherein the first circuit is adapted to provide at least one compensation current (i _DD 、i _SS ) To compensate for error currents caused by parasitic capacitances of respective digital-to-analog converters (102 x) of the at least two digital-to-analog converters (102);

A second circuit (302) for detecting a change in input data state between successive sampling periods of the respective digital-to-analog converter (102 x) and, in response to detecting the change in input data state, triggering the first circuit (304) to activate the at least one compensation current (i _DD 、i _SS )。

2. The apparatus (300) of claim 1, wherein the second circuit (302) is further configured to detect that the input data remains unchanged between consecutive sampling periods of the respective digital-to-analog converter (102 x) and to cause the first circuit (304) to disable the at least one compensation current (i) _DD 、i _SS )。

3. The device (300) of claim 1 or 2, wherein the second circuit (302) is configured to activate the at least one compensation current in response to detecting the input data state change and to deactivate the at least one compensation current in response to detecting the input data state change to remain unchanged for the consecutive sampling periods.

4. The device (300) of any of the preceding claims, wherein the at least two digital-to-analog converters (102) are coupled to a dynamic element matching circuit (104).

5. The apparatus (300) according to any one of the preceding claims, wherein the at least one compensation current (i _DD 、i _SS ) Is controlled based on the length of the sampling period.

6. The apparatus (300) of claim 5, wherein the at least one compensation current (i _DD 、i _SS ) Is obtained by determining said at least one compensation current (i _DD 、i _SS ) Is controlled by the duty cycle of (a).

7. The device (300) according to claim 5 or 6, wherein the at least one compensation current (i _DD 、i _SS ) Is inversely proportional to the length of the sampling period.

8. The apparatus (300) according to any one of the preceding claims, wherein the at least one compensation current (i _DD 、i _SS ) Is controlled based on predefined current values associated with different levels of the extensible impedance.

9. The device (300) according to any one of claims 5 to 8, wherein the at least one compensation current (i _DD 、i _SS ) Is a programmable current source (i) by said first and second circuits (302, 304) _BB ) Controlled.

10. The device (300) according to any one of the preceding claims, wherein the first circuit (304) is configured to provide or sink the at least one compensation current (i _DD 、i _SS )。

11. The device (300) according to any of the preceding claims, wherein the at least two digital-to-analog converters (102) comprise a series resistance (R) between a data switch (MP 1, MP2, MN1, MN 2) of the at least two digital-to-analog converters (102) and a reference voltage (AVDD, AVSS) _scale ) For expanding the expandable impedance, wherein the at least one compensation current (i _DD 、i _SS ) The value of (c) depends on the value of the voltage obtained by varying the series resistance (R _scale ) A level of said impedance that is scalable to said value of (c).

12. The device (300) according to any of the preceding claims, wherein the second circuit (302) is configured to trigger the first circuit (304) to activate the at least one compensation current (i _DD 、i _SS )。

13. A method (900) for compensating an error current caused by parasitic capacitances of at least two digital-to-analog converters (102), characterized in that the digital-to-analog converters are connected in parallel with each other and are adapted to provide a device (300) with a scalable impedance, wherein each of the at least two digital-to-analog converters (102) is coupled to a first circuit (304) and a second circuit (302), wherein the method (700) comprises:

-detecting (902), by said second circuit (302), a change in input data state of a respective digital-to-analog converter (102 x) between successive sampling periods;

-triggering (904) the first circuit (304) by the second circuit (302) to activate at least one compensation current (i _DD 、i _SS )。

14. The method (900) of claim 13, further comprising:

detecting, by the second circuit (302), that the input data state remains unchanged between consecutive sampling periods;

triggering the first circuit (304) by the second circuit (302) to disable the at least one compensation current (i) _DD 、i _SS )。

15. The method (900) of claim 13 or 14, wherein the first circuit (304) is triggered to activate the at least one compensation current in response to the second circuit (302) detecting the input data state change and to deactivate the at least one compensation current in response to the second circuit (302) detecting the input data state change remaining unchanged for the consecutive sampling periods.

16. The method (900) according to any one of claims 13 to 15, further comprising:

controlling the at least one compensation current (i _DD 、i _SS ) Is a value of (2).

17. The method (900) of claim 16, further comprising:

by determining the at least one compensation current (i) based on the length of the sampling period _DD 、i _SS ) To control the at least one compensation current (i _DD 、i _SS ) Is a function of the value of (a).

18. The method (900) according to claim 16 or 17, wherein the at least one compensation current (i _DD 、i _SS ) Is inversely proportional to the length of the sampling period.

19. The method (900) according to any one of claims 13 to 18, further comprising:

controlling the at least one compensation current (i) based on predefined current values associated with different levels of the extensible impedance _DD 、i _SS ) Is a value of (2).

20. The method (900) according to any one of claims 16 to 19, further comprising:

-a programmable current source (i) by said first and second circuit (302, 304) _BB ) Controlling the at least one compensation current (i _DD 、i _SS ) Is a function of the value of (a).

21. The method (900) according to any one of claims 13 to 20, further comprising:

if the level of the extensible impedance is above a threshold value, the first circuit (304) is triggered by the second circuit (302) to activate the at least one compensation current (i _DD 、i _SS )。

22. A computer program comprising instructions which, when executed by a computer, cause the computer to perform the method of any of claims 13 to 21.