CN116964421A - Temperature sensor integrated in transistor array - Google Patents

Abstract

A temperature sensor integrated in a transistor array, such as a metal-oxide-semiconductor field effect transistor (MOSFET) array, is provided. The integrated temperature sensor may include a doped well region formed in a substrate (e.g., a SiC substrate), a resistor gate formed over the doped well region, a first sensor terminal and a second sensor terminal conductively coupled to the doped well region on opposite sides of the resistor gate. The integrated temperature sensor includes a gate driver to apply a voltage to the resistor gate that affects the resistance of the doped well region under the resistor gate, and a temperature analysis circuit to determine the resistance of a conductive path through the doped well region and determine a temperature associated with the transistor array.

Description

Temperature sensor integrated in transistor array

Related patent application

The present application claims priority from commonly owned U.S. provisional patent application 63/217,352 filed on 7/1/2021, the entire contents of which are hereby incorporated by reference for all purposes.

Technical Field

The present disclosure relates to temperature sensors, and more particularly to temperature sensors integrated in transistor arrays (e.g., metal-oxide-semiconductor field effect transistor (MOSFET) arrays) and methods for using such integrated temperature sensors.

Background

Many Integrated Circuit (IC) chips include MOSFET arrays. MOSFETs are metal-oxide-semiconductor field effect transistors, which are insulated gate field effect transistors in which the voltage of the gate controls the operation of the device. Fig. 1A and 1B show a top view and a cross-sectional side view, respectively, of an exemplary power MOSFET 100 constructed on silicon carbide (SiC) and thus referred to as a SiC MOSFET. Power MOSFET 100 includes a pair of n + source regions 102a and 102b (e.g., nitrogen doped implants) formed in a corresponding pair of p-wells 104a and 104b (e.g., aluminum implants) formed in an n-type SiC epitaxial layer 110. A p-well junction 112a, 112b may be formed in each respective p-well 104a, 104b to provide a conductive contact for a respective pair of source contacts or terminals 114a, 114b (e.g., aluminum lines). The p-well junctions 112a and 112b may include higher concentration p-doped regions within the p-wells 104a and 104b, respectively.

A gate oxide 120 is formed over the source regions 102a and 102b, and a gate 122 (e.g., formed of n-doped polysilicon or metal) is formed over the gate oxide 120. An n+ drain 130 (e.g., comprising sintered gold or sintered nickel silicide) is formed on the back side of SiC epitaxial layer 110. In operation, in the on state of power MOSFET 100, a flow EF of electrons is generated from source regions 102a, 102b through junction gate field effect transistor (JFET) channel 140 between p-wells 104 and 108 and down to back drain 130.

The temperature of the MOSFET varies as a function of the MOSFET operation and related components. For example, a MOSFET may experience a range of temperature changes during operation. Furthermore, MOSFET temperatures may increase beyond the normal operating range due to device failure or other deleterious conditions, such as device degradation, failure of the gate driver chip driving the MOSFET gate, or electrical shorts or other faults associated with the MOSFET load. These conditions may be particularly pronounced in certain types of MOSFETs, such as power MOSFETs designed to handle significant power or voltage levels (e.g., voltages above 500V for applications such as, but not limited to, electric vehicles or green energy systems), due to high potential power dissipation in such devices.

Thus, the condition of the MOSFET can be checked by monitoring the MOSFET temperature over time. Conventional temperature sensing of the MOSFET is typically performed off-chip using external circuitry. Recently, integrated temperature sensors, i.e. temperature sensors formed integrally with MOSFET arrays, have been developed. However, such integrated temperature sensors typically have low sensitivity and may not be available in certain switching states of the MOSFET array, and also have process and integration limitations.

Disclosure of Invention

The present invention provides a temperature sensor integrated in a Field Effect Transistor (FET) array (e.g., a power MOSFET array). The integrated temperature sensor may include a resistor including a doped well region (e.g., a p-well region); and circuitry for measuring the resistance of the doped well region and calculating a temperature associated with the transistor array based on the measured resistance. Thus, the resistor may be referred to herein as a temperature sensing resistor. The resistance of the doped well region may be adjusted by applying a selected voltage to a control gate formed over the doped well region (and separated from the doped well region by a gate oxide), for example to increase the sensitivity of the temperature sensor or to reduce the dependence of the measured resistance (and hence the calculated temperature) on the on/off state of the FET array.

In some examples, a terminal of the temperature sensing resistor may be electrically coupled to a source contact of at least one FET in the array.

In some examples, the control gate of the resistor is electrically coupled to the control gate of at least one FET in the array. In other examples, the control gates of the resistors have separate terminals that are different from the control gates of the FETs in the array.

An integrated temperature sensor may be used to monitor a temperature associated with one or more FETs, for example, to detect abnormal temperatures that may be indicative of problems with the monitored FETs or related components. For example, an integrated temperature sensor may be used to monitor one or more high power MOSFETs, such as MOSFETs that use voltages above 500V in applications related to, for example, electric vehicles or green energy systems, but is not limited thereto. In some examples, multiple instances of the temperature sensing resistor are integrated across an FET array or other area of the integrated circuit die and connected in parallel such that an average temperature of the FET array or associated die area can be calculated.

One aspect provides a temperature sensor integrated in a transistor array. The integrated temperature sensor includes a resistor including a doped well region formed in a substrate (e.g., a SiC substrate); a resistor gate formed over the doped well region and separated from the doped well region by a gate oxide; and first and second sensor terminals conductively coupled to the doped well region on opposite sides of the resistor gate. The integrated temperature sensor further includes a gate driver to apply a voltage to the resistor gate that affects the resistance of the doped well region beneath the resistor gate. The integrated temperature sensor further includes a temperature analysis circuit to determine a resistance correlation value corresponding to a resistance of the conductive path through the doped well region, analyze a temperature associated with the transistor array based at least on the determined resistance correlation value corresponding to the resistance of the conductive path through the doped well region, and output a temperature-related signal based on the analyzed temperature.

In some examples, the doped well region includes a p-well region.

In some examples, the resistor gate is conductively coupled to a control gate of at least one transistor cell in the transistor array.

In some examples, the second sensor terminal is conductively coupled to a transistor source terminal of at least one transistor cell in the transistor array.

Another aspect provides a transistor array including a plurality of transistors including a plurality of transistor doped well regions formed in a substrate, and a temperature sensor. The temperature sensor includes a resistor including a sensor doped well region formed in a substrate; a resistor gate formed over the second doped well region and separated from the doped well region by a gate oxide; and first and second sensor terminals conductively coupled to the second doped well region on opposite sides of the resistor gate. The temperature sensor further includes a gate driver to apply a voltage to the resistor gate that affects the resistance of the second doped well region; and a temperature analysis circuit to determine a resistance correlation value corresponding to a resistance of the conductive path through the doped well region, analyze a temperature associated with the transistor array based at least on the determined resistance correlation value corresponding to the resistance of the conductive path through the doped well region, and output a temperature-related signal based on the analyzed temperature.

In some examples, the plurality of transistors includes a plurality of metal-oxide-semiconductor field effect transistors.

In some examples, the plurality of transistors includes a plurality of transistor gates, and wherein the resistor gate and the plurality of transistor gates are formed in a common gate layer. In some examples, the common gate layer includes a common metal layer.

In some examples, the second sensor terminal is electrically connected to a transistor source contact of at least one transistor of the plurality of transistors.

In some examples, the second sensor terminal and the transistor source contact are defined by a common conductive structure.

In some examples, the resistor gate is connected to a transistor gate of at least one of the plurality of transistors.

In some examples, the resistor gate and the transistor gate are defined by a common conductive structure.

In some examples, the second doped well region of the temperature sensor has a different dopant concentration than the first doped well region of the plurality of transistors.

In some examples, the second doped well region of the temperature sensor has a lower dopant concentration than the first doped well region of the plurality of transistors.

Another aspect provides a method for determining a temperature associated with a transistor array using a temperature sensor integrated in the transistor array and including (a) a doped well region formed in a substrate, and (b) a resistor gate formed over the sensor doped well region and separated from the doped well region by a gate oxide. The method includes applying a voltage to the resistor gate that affects the resistance of the doped well region; generating a current along a conductive path through the doped well region; determining a resistance-related value corresponding to a resistance of a conductive path through the doped well region; analyzing a temperature associated with the transistor array based at least on the determined resistance related value corresponding to the resistance of the conductive path through the doped well region; and outputting a temperature-related signal based on the analyzed temperature.

In some examples, a voltage applied to the resistor gate increases the resistance of the doped well region.

In some examples, the resistance of the doped well region is determined by a temperature analysis circuit connected to the first sensor terminal.

In some examples, the resistor gate is connected to a transistor control gate of at least one of the plurality of transistors, and the voltage applied to the resistor gate is defined by a control gate voltage applied to the transistor control gate.

In some examples, determining the conductive path through the doped well region includes supplying a current to the first sensor terminal, determining a voltage drop between the first sensor terminal and the second sensor terminal, and determining a resistance of the conductive path based on the supplied current and the measured voltage drop.

In some examples, the second sensor terminal is connected to a transistor source contact of at least one transistor of the plurality of transistors, a transistor source voltage is applied to the second sensor terminal, and determining a voltage drop between the first sensor terminal and the second sensor terminal includes measuring a second terminal voltage at the first sensor terminal and the second sensor terminal and determining a difference between the second terminal voltage and the transistor source voltage.

In some examples, determining the conductive path through the doped well region includes applying a first terminal voltage to a first sensor terminal, measuring a current through the conductive path, and determining a resistance of the conductive path based on the first terminal voltage and the measured current.

Drawings

Exemplary aspects of the disclosure are described below in conjunction with the following drawings, in which:

FIGS. 1A and 1B illustrate an exemplary SiC power MOSFET;

FIGS. 2A-2C illustrate an exemplary integrated temperature sensor including an exemplary temperature sensing resistor with a controllable gate;

FIG. 3 illustrates an exemplary FET array including an exemplary integrated temperature sensor including the temperature sensing resistor shown in FIGS. 2A-2C, wherein the temperature sensing resistor includes a control gate that is controllable independently of the FET gates in the array;

FIG. 4A illustrates another example FET array including an example integrated temperature sensor including an example temperature sensing resistor sharing a pair of control gates with adjacent FET cells;

FIG. 4B illustrates a cross-sectional side view of the integrated temperature sensor shown in FIG. 4A;

FIG. 5A shows a circuit diagram of a portion of an exemplary FET array including a temperature sensing resistor and a nearby FET, wherein the temperature sensing resistor control gate is controllable independently of the FET gates in the array, such as in accordance with the exemplary FET array shown in FIG. 3;

FIG. 5B provides a circuit diagram of a portion of an exemplary FET array including a temperature sensing resistor and a nearby FET, with the temperature sensing resistor control gate coupled to one or more FET gates in the array, for example, according to the exemplary FET array shown in FIG. 4A;

FIGS. 6A and 6B illustrate cross-sectional views of exemplary temperature sensing resistors integrated in FET arrays, showing various dimensions related to the p-well resistance of the temperature sensing resistors;

FIG. 7 shows an exemplary graph illustrating the relationship between p-well temperature and p-well resistance for a temperature sensing resistor with and without a controllable gate;

FIG. 8 shows a graph illustrating an exemplary relationship between p-well sheet resistance of a temperature sensing resistor and implant dose of a doped p-well region;

fig. 9A and 9B show graphs illustrating exemplary relationships between p-well sheet resistance and resistor gate voltage applied to the temperature sensing resistor for an exemplary temperature sensing resistor with a p-well region of lower dopant concentration (fig. 9A) and an exemplary temperature sensing resistor with a p-well region of higher dopant concentration (fig. 9B); and is also provided with

Fig. 10-12 illustrate exemplary methods of using a temperature sensor to determine a resistance-related value corresponding to a conductive path of an integrated temperature-sensing resistor, analyzing a temperature based on the determined resistance-related value, and outputting a temperature-related signal based on the analyzed temperature.

It will be appreciated that the reference numerals of any illustrated element appearing in a plurality of different figures have the same meaning in the plurality of figures, and that any illustrated element mentioned or discussed herein in the context of any particular figure is also applicable to every other figure (if any), where the same illustrated element is shown.

Detailed Description

The present invention provides a temperature sensor integrated in a Field Effect Transistor (FET) array (e.g., a power MOSFET array). The integrated temperature sensor may include a temperature sensing resistor including a doped well region (e.g., a p-well region); and circuitry for measuring the resistance of the doped well region and calculating a temperature associated with the transistor array based on the measured resistance. The resistance of the doped well region may be adjusted by applying a selected voltage to a control gate formed over the doped well region, for example to increase the sensitivity of the temperature sensor or to reduce the dependence of the measured resistance (and hence the calculated temperature) on the on/off state of the FET array.

Fig. 2A-2C illustrate an example integrated circuit structure 200 including an integrated temperature sensor 201. In particular, fig. 2A shows a top view of the integrated temperature sensor 201, fig. 2B shows a first cross-sectional side view of the integrated temperature sensor 201 taken along line 2B-2B shown in fig. 2A, and fig. 2C shows a second cross-sectional side view of the integrated temperature sensor 201 taken along line 2C-2C shown in fig. 2A. As discussed below, for example, with reference to fig. 3, an integrated temperature sensor 201 may be formed integrally with a transistor array (e.g., a power MOSFET array or other FET array) and analyze the temperature associated with the transistor array. For convenience, the integrated temperature sensor 201 is also referred to as the temperature sensor 201.

As shown in fig. 2A-2C, an exemplary temperature sensor 201 includes a controllable temperature sensing resistor 202, a gate resistor gate driver 250, and a temperature analysis circuit 260. Fig. 2A to 2C illustrate the physical structure of the temperature sensing resistor 202. In contrast, a gate resistor gate driver 250 and a temperature analysis circuit 260 are schematically shown; the gate resistor the gate driver 250 and the temperature analysis circuit 260 may each be embodied by any suitable physical structure.

As shown in fig. 2A-2C, the temperature sensing resistor 202 includes a sensor doped well region 204 (or doped well region 204 for convenience) formed in a substrate 206 and a resistor gate 210 formed over the doped well region 204 and separated from the doped well region 204 by a resistor gate oxide 212. Doped well region 204 may also be referred to as a resistor body. First doped well junction 214 and second doped well junction 216 are formed in doped well region 204 (laterally) on opposite sides of resistor gate 21O. The first sensor terminal 220 and the second sensor terminal 222 are formed in contact with the doped well region 204. In particular, the first sensor terminal 220 is formed in contact with the first doped well junction 214, which provides a conductive contact between the first sensor terminal 220 and the doped well region 204, and the second sensor terminal 222 is formed in contact with the second doped well junction 216, which provides a conductive contact between the second sensor terminal 222 and the doped well region 204. A resistor gate terminal 226 (shown schematically except in fig. 2C) is formed in contact with the resistor gate 210.

In one example, the substrate 206 includes an n-type SiC epitaxial region, and the doped well region 204 includes a doped p-well region (e.g., defined by an aluminum implant) formed in the n-type SiC epitaxial substrate 206. The first doped well junction 214 and the second doped well junction 216 may include highly doped p+ regions (e.g., having a higher dopant concentration than the p-well region 204). The first sensor terminal 220, the second sensor terminal 222, and the resistor gate terminal 226 may each be formed of aluminum or other metals. The resistor gate 210 may be formed of n-doped polysilicon, or alternatively of a metal (e.g., aluminum), and the resistor gate oxide 212 may include SiO containing nitrogen dopants ₂ 。

The integrated circuit structure 200 may also include an n+ drain region 230 formed on the back side of the substrate 206, for example comprising sintered gold or sintered nickel silicide. In some examples, the integrated temperature sensor 201 operates without triggering vertical current flow from the temperature sensing resistor 202 through the substrate 206 to the drain region 230, for example by selecting an operating voltage low enough to avoid triggering such vertical current flow.

In some examples (e.g., as shown in fig. 3 and 4), the second sensor terminal 222 is electrically coupled to a variable voltage FET source contact of at least one nearby FET, while in other examples, the second sensor terminal 222 is coupled to ground.

Further, in some examples (e.g., as shown in fig. 2A, 2C, and 3), the resistor gate terminal 226 may be independently controlled from each FET gate in the associated FET array, while in other examples (e.g., as shown in fig. 4, discussed below), the resistor gate terminal 226 is electrically coupled to at least one FET gate in the associated FET array.

Such as fig. 2A and 2C (and the figures discussed below3) As shown, the resistor gate driver 250 is connected to the resistor gate terminal 226 to couple the resistor gate voltage V via the resistor gate terminal 226 _GR Applied to the resistor gate 210, which affects the resistance of the underlying doped well region 204. The resistor gate driver 250 is independent of the FET gate voltage V applied to the FET gates in the associated FET array _GFET To control the resistor gate voltage V _GR . (in other examples, such as the example shown in FIG. 4, the resistor gate voltage V _GR And a FET gate voltage V applied to adjacent FET gates in the FET array _GFET Associated with).

In some examples, for example, as shown in fig. 2A (and fig. 3 discussed below), the temperature analysis circuit 260 may include circuitry to select the resistor gate voltage V _GR And by transmitting a designation V _GR Control signal Control of (2) _VGR To control the circuitry of the resistor gate driver 250, which control signal is to be applied by the resistor gate driver 250 to the resistor gate terminal 226.

The temperature analysis circuit 260 may also include circuitry to:

(a) Determining at least one resistance-related value corresponding to a conductive path CP (see fig. 2B) through the doped well region 204;

(b) Analyzing a temperature associated with the temperature sensing resistor 202 (e.g., corresponding to a temperature of a transistor array or region of a transistor array in which the temperature sensing resistor 202 is integrated) based at least on the determined resistance correlation value corresponding to a resistance of the conductive path CP through the doped well region 204; and is also provided with

(c) Outputting a temperature-dependent signal S based on the analyzed temperature _temp 。

As used herein, a resistance-related value corresponding to the conductive path CP (through the doped well region 204) may refer to (a) a value (R _CP ) Or (b) as R _CP A value of a parameter that varies as a function of (e.g., a voltage (in volts) associated with the conductive path CP (e.g., a voltage V at the first sensor terminal 220) _T1 With voltage V at second sensor terminal 222 _T2 The difference between them, i.e.,voltage drop between the first sensor terminal 220 and the second sensor terminal 222) or current (amps) associated with the conductive path CP). Resistance of conductive path CP (R _CP ) Including (b) the resistance of the doped well region 204 itself (R _p-well ) And (b) a respective contact resistance (R) between doped well region 204 and each of first and second sensor terminals 220 and 222 _contact ) Wherein the resistive components are arranged in series (i.e., added). In some examples, the doped well region resistance (R _p-well ) Comparable contact resistance (R _contact ) Much larger (e.g., several orders of magnitude larger) such that the contact resistance constitutes the conductive path resistance R _CP Is a negligible component of (c).

The resistance related value corresponding to conductive path CP may be measured or determined in any suitable manner using temperature analysis circuit 260. For example, the temperature analysis circuit 260 may include circuitry to determine any one of the following exemplary resistance related values using any one of the following processes:

example (1): resistance related value = voltage V at first sensor terminal 220 _T1 . An exemplary process for determining the voltage at the first sensor terminal 220 includes: (a) A predetermined current I is caused, for example, by supplying a current to the first sensor terminal 220 _CP (e.g., 100 microamps) along the conductive path CP, and (b) measuring the voltage V at the first sensor terminal 220 _T1 . In the event that the voltage at the second sensor terminal 222 is known, such as in the event that the second sensor terminal 222 is grounded or otherwise held constant, the voltage V _T1 May correspond to the resistance of the conductive path CP.

Example (2): resistance related value = voltage drop V between first sensor terminal 220 and second sensor terminal 222 _T1 -V _T2 . For determining voltage drop V _T1 -V _T2 Comprises: (a) A predetermined current I is caused, for example, by supplying a current to the first sensor terminal 220 _CP (e.g., 100 microamps) along the conductive path CP; (b) Measuring the voltage V at the first sensor terminal 220 _T1 And electricity at the second sensor terminal 222Pressure V _T2 The method comprises the steps of carrying out a first treatment on the surface of the (c) calculating the voltage drop V _T1 -V _T2 。

Example (3): resistance related value = current I through conductive path CP _CP . For determining the current I if the voltage at the second sensor terminal 222 is known (e.g., if the second sensor terminal 222 is grounded or otherwise constant and known) _CP Comprises: (a) A predetermined voltage V is applied at the first sensor terminal 220 _T1 And (b) measuring the current I at the first sensor terminal 220 _CP . For determining the current I in case the voltage at the second sensor terminal 222 is variable or unknown (e.g. in case the second sensor terminal 222 is coupled to a variable voltage FET source contact) _CP Comprises: (a) A predetermined voltage V is applied at the first sensor terminal 222 _T1 (b) measuring the voltage V at the second sensor terminal 220 _T2 And (c) measuring the current I at the first sensor terminal 220 _CP . In either case, the current I _CP The amount of (a) may correspond to the resistance of the conductive path CP. In some examples, temperature analysis circuit 260 selects V _T1 Is (via Control signal Control) _VGR Signaling resistor gate driver 250) that is low enough not to trigger vertical current flow through the p-n diode defined by integrated circuit structure 200. For example, in the exemplary IC structure 200 built on the SiC substrate 206 where the p-n diode is activated (turned on) by a voltage above 2V, the temperature analysis circuit 260 may select V of 1V _T1 。

Example (4): resistance related value=resistance R _CP I.e. the resistance across the conductive path CP. For determining resistance R _CP Comprises: (a) Determining the voltage V according to the procedure described above for embodiment (1) _T1 The method comprises the steps of carrying out a first treatment on the surface of the (b) voltage V-based _T1 And current I _CP Calculating resistance R _CP . For determining resistance R _CP Comprises: (a) Determining the voltage drop V according to the procedure described above for embodiment (2) _T1 -V _T2 The method comprises the steps of carrying out a first treatment on the surface of the And (b) based on voltage drop V _T1 -V _T2 And current I _CP To calculate the resistance R _CP . For determining resistance R _CP The third exemplary process of (1) includes: (a) Determining the current I according to the procedure described above for embodiment (3) _CP The method comprises the steps of carrying out a first treatment on the surface of the (b) based on current I _CP And voltage V _T1 (wherein V _T2 Constant and known) or voltage drop V _T1 -V _T2 (wherein V _T2 Variable or unknown) to calculate the resistance R _CP 。

As described above, the resistance R _CP Depending on the temperature of resistor 202 and in particular the temperature of doped well region 204 through which conductive path CP passes. Thus, each of the resistance related values discussed above is also temperature dependent. In some examples, temperature analysis circuit 260 includes circuitry to analyze a resistor temperature associated with resistor 202 based on one or more of such temperature-dependent resistance-related values (e.g., any one or more of the exemplary resistance-related values discussed above in embodiments (1) - (4)). The resistor temperature may correspond to or represent a specified temperature of interest, such as an operating temperature of one or more FETs in the vicinity of the temperature sensing resistor 202, or a temperature at a particular location or region of an associated chip or electronic device. For example, it may be determined (e.g., measured by modeling or testing) that the temperature of interest is sufficiently similar to the temperature of the temperature-sensing resistor 202 to treat the temperature of the temperature-sensing resistor 202 as an effective indicator for analyzing the temperature of interest, such as determining whether the temperature of interest has exceeded a defined unsafe or dangerous temperature threshold.

As used herein, analyzing the temperature may include (a) actually calculating a resistor temperature value or (b) analyzing at least one temperature-dependent resistance-related value (e.g., any one or more of the exemplary resistance-related values discussed above in embodiments (1) - (4)) as an indicator of the resistor temperature, for example, by comparing the at least one temperature-dependent resistance-related value to a respective threshold value corresponding to a defined temperature state (e.g., defining an overheat state).

As described above, the temperature analysis circuit 260 may control the resistor gate voltage V _GR (by controlled engagement to the gate terminal)Resistor gate driver 250 of sub 226) to improve the performance of temperature sensor 201. For example, the temperature analysis circuit 260 may apply and control V for any one or more of the following purposes _GR ：

(1) The temperature analysis circuit 260 can selectively control the gate voltage V _GR To increase the absolute resistance of the doped well region 204 and thus the absolute resistance of the conductive path CP through the doped region (referred to herein as the conductive path resistance or R _CP ). For example, in comparison to prior art temperature sensing resistors that do not include a control gate, the use of a gate voltage V _GR To increase the resistance R of the conductive path _CP Allows for a given sense voltage (V _T1 ) Using lower sense current (I _CP ) To measure R _CP . Additionally, the resistance R of the conductive path is increased by providing a resistor gate 210 _CP (by applying a gate voltage V _GR ) The temperature sensing resistor 202 may be formed with a doped well region 204 that is reduced in size in at least one direction (e.g., y-direction length), thereby reducing the layout area required for the temperature sensing resistor 202, for example, as compared to prior art temperature sensing resistors that do not include a control gate. In some examples, the gate voltage V is applied in the on state of the FET _GR But not in the off state of the FET. Control gate voltage V is discussed in more detail below with reference to table 1 _GR To increase the R of the doped well region 204 _CP Is characterized by (3).

(2) Due to the gate voltage V _GR Can be independent of FET gate voltage V _GFET Is controlled so that the temperature analysis circuit 260 can selectively control the gate voltage V according to FET states (e.g., on and off states) _GR To reduce the p-well resistance (R _CP ) Dependency on the current FET state. In particular, the gate voltage V may be controlled based on FET state _GR To reduce the effect of drain bias on the temperature sensing resistor 202 by using depletion from the resistor gate 210. Control gate voltage V _GR To reduce R _CP The characteristics of the dependency on FET state will be discussed in more detail below with reference to table 2.

(3) The temperature analysis circuit 260 can control the gate voltage V _GR To affect the Temperature Coefficient of Resistance (TCR) of the temperature sensing resistor 202. For example, the temperature analysis circuit 260 may increase V _GR This increases the p-well resistance (R _CP ) This in turn increases the TCR of resistor 202.

Determining a resistance-related value corresponding to the conductive path CP of a temperature sensing resistor (e.g., temperature sensing resistor 202) using a temperature sensor (e.g., temperature sensor 201), analyzing a temperature based on the determined resistance-related value, and outputting a temperature-related signal S based on the analyzed temperature _temp An exemplary method of (a) is discussed below with reference to fig. 10-12.

Fig. 3 is a top view of a portion of a MOSFET array 300 including the exemplary temperature sensor 201 of fig. 2A-2C integrated in the MOSFET array 300 according to one example. As with fig. 2A-2C, a gate resistor gate driver 250 and a temperature analysis circuit 260 are schematically shown in fig. 3.

As shown in fig. 3, the MOSFET array 300 includes an array of FET cells 302 defined by a plurality of FET gates 310 formed over a respective FET doped well region 304 formed in a substrate 206 (e.g., an n-type SiC epitaxial substrate), with FET source contacts 306 formed on each doped well region 304 between an adjacent pair of FET gates 310. JFET channels 316 are defined between each pair of adjacent FET doped well regions 304. FET gate 310 may be formed of polysilicon or metal (e.g., aluminum) and may be formed through FET gate oxide 312 (e.g., siO including nitrogen dopants) ₂ ) Separated from the underlying FET doped well region 304. The FET source contact 306 may be formed of aluminum or other metal. Gate voltage V _GFET Can be selectively applied to the FET gate 310 by a corresponding gate driver (not shown), and the source voltage V _SFET May be selectively applied to FET source contact 306 by a corresponding source driver (not shown).

The temperature sensing resistor 202 of the temperature sensor 201 is integrated in the MOSFET array 300. In particular, the various structures of the temperature sensing resistor 202 are formed in the same layer and/or simultaneously with the various structures of the FET cell 302. For example, the doped well region 204 of the temperature sensing resistor 202 is formed in the same substrate 206 as the FET doped well region 304 (e.g., p-channel) of the FET cell 302, and may be formed simultaneously with the doped well region 304, i.e., using the same dopant and doping process. As another example, the resistor gate 210 and the resistor gate oxide 212 may be formed in the same layer (and thus of the same material) in the FET gate 310 and the FET gate oxide 312, respectively.

In some examples, because doped well region 204 is physically different from FET doped well region 304 (shown in fig. 3) of FETs 302 in array 300, doped well region 204 of temperature sensing resistor 202 may be formed to have a lower dopant concentration than FET doped well region 304. This may provide improved performance of the temperature sensor 201, for example as discussed below with reference to fig. 8 and 9A-9B.

As another example, the first and second sensor terminals 220, 222 of the temperature sensing resistor 202 and the resistor gate terminal 226 may be formed in the same layer (and thus from the same material, e.g., aluminum) as the FET source contact 306. Further, in the example shown in fig. 3, the second sensor terminal 222 is formed as a physical extension of the particular FET source contact 306, indicated at 306a, such that the second sensor terminal voltage V _T2 Voltage V to FET source contact 306a _SFET And (5) linking. In contrast, the resistor gate voltage V applied to the resistor gate 210 _GR May be independent of the gate voltage V applied to each FET gate 310 _GFET Because the resistor gate 210 is physically different from the FET gate 310. In particular, the temperature analysis circuit 260 controls the driver 250 (using the Control signal Control V _GR ) To provide a predetermined resistor gate voltage V _GR Applied to the resistor gate 210. (in other examples, for example, as shown in fig. 4A-4B discussed below, resistor gate voltage V _GR And gate voltage V adjacent to FET gate _GFET Associated with).

Fig. 4A is a top view of a portion of a MOSFET array 400 including an exemplary temperature sensor 401 integrated in the MOSFET array 400 according to another example. The temperature sensor 401 includes a temperature sensing resistor 402 and a temperature analysis circuit 460, which Receiving voltage Signal from FET gate driver 450 _VGFET . The temperature analysis circuit 460 and FET gate driver 450 are schematically shown in fig. 4A.

Fig. 4B is a cross-sectional view of the temperature sensing resistor 402 taken along the serpentine cut line 4B-4B shown in fig. 4A.

As shown in fig. 4A and 4B, the temperature sensing resistor 402 includes: (a) Resistor gates 410a/410b formed over the sensor doped well region 404 (or doped well region 404 for convenience) and separated from the doped well region 404 by gate oxide 412; (b) A first sensor terminal 220 connected to doped well region 404 through first doped well junction 214; and (c) a second sensor terminal 222 connected to doped well region 404 through a second doped well junction 216.

The resistor gate 410 includes (a) a first resistor gate region 410a defined by a physical extension of the first FET gate 310a and (b) a second resistor gate region 410b defined by a physical extension of the second FET gate 310 b. Thus, the resistor gate voltage V _GR And a gate voltage V applied (by FET gate driver 450) to FET gates 310a and 310b _GFET And (5) linking. Furthermore, as with the temperature sensing resistor 202 discussed above, the second sensor terminal 222 is formed as a physical extension of the particular FET source contact 306, indicated at 306a, such that the second sensor terminal voltage V _T2 Voltage V to FET source contact 306a _SFET And (5) linking.

Thus, the temperature sensor 401 is substantially similar to the temperature sensor 201 discussed above with reference to fig. 2A-2C and 3, with the key difference being that the resistor gate 410 of the controllable temperature sensing resistor 402 is defined by a pair of respective extensions adjacent to the FET gates 310a and 310b (defined along the conductive path CP as discussed below) _a And CP _b Two parallel resistors of (a) such that the resistor gate voltage V _GR Gate voltage V to FET gates 310a and 310b _GFET In connection with which the resistor gate voltage V _GR The temperature sensor 201, which may be controlled independently of the FET gates 310 in the FET array 300, is different.

As shown in fig. 4A, the doped well region 404 includes (a) a first doped well region 404A aligned under a first resistor gate region 410a, a second doped well region 404b aligned under a second resistor gate region 410b, a first doped well junction 214 located under a first sensor terminal 220, and a second doped well junction 216 located under a second sensor terminal 222. As discussed above, the first doped well junction 214 provides a conductive contact between the first sensor terminal 220 and the doped well region 404, and the second doped well junction 216 provides a conductive contact between the second sensor terminal 222 and the doped well region 404.

As shown, doped well region 404 is physically separated from adjacent FET doped well region 304. In some examples, doped well region 404 may be formed with the same dopant concentration as FET doped well region 304; for example, doped well region 404 and FET doped well region 304 may be doped simultaneously. In other examples, doped well region 304 may be formed with a different dopant concentration (e.g., a higher or lower dopant concentration) than FET doped well region 404, such as by forming doped well region 404 in a separate step from FET doped well region 304. For example, in some examples, doped well region 404 may be formed with a lower dopant concentration than FET doped well region 304 to provide a higher sheet resistance of doped well region 404, which may provide improved temperature detection.

In the illustrated example, the first doped well region 404A and the second doped well region 404b are separated from each other by an undoped region 420 of the substrate 206, thereby defining an annular doped well region 404 from the top view shown in fig. 4A. In another example (not shown), doped well region 404 may be formed to have a rectangular shape from a top view, i.e., wherein undoped region 420 shown in fig. 4A is included in doped well region 404.

As shown in fig. 4A, the annular doped well region 404 defines a conductive path that includes (a) a first conductive path component CP that passes through the first doped well region 404A _a And (b) a second conductive path component CP through the second doped well region 404b _b Wherein the first conductive path component CP _a And a second conductive path component CP _b Defining an electrically parallel path. FIG. 4B is a cross-sectionThe view shows a first conductive path component CP through first doped well region 404a and connected to first and second sensor terminals 220 and 220 by doped well junctions 214 and 216, respectively _a 。

And wherein the temperature analysis circuit 260 is independent of the FET gate voltage V _GFET Controlling resistor gate voltage V _GR Unlike the exemplary temperature sensor 201 discussed above with respect to fig. 2A-2C (and fig. 3), the resistor gate voltage V of the temperature sensing resistor _GR By FET gate voltage V _GFET Control (equal to the FET gate voltage).

However, although not independent of FET gate voltage V _GFET Controlled, but resistor gate voltage V _GR Which is applied during the FET on state increases the absolute resistance of doped well region 404 and thus increases the conductive path CP extending through doped well regions 404a and 404b, respectively _a And CP _b Corresponding resistance R of (2) _CP . For example, in comparison to prior art temperature sensing resistors that do not include a control gate, the use of a gate voltage V _GR To increase the resistance R of the conductive path _CP Allows for a given sense voltage (V _T1 ) Using lower sense current (I _CP ) To measure R _CP . Additionally, the resistance R of the conductive path is increased by providing a resistor gate 410 _CP The temperature sensing resistor 402 may be formed with a doped well region 404 of reduced size in at least one direction (e.g., y-direction length), thereby reducing the layout area required for the temperature sensing resistor 402, for example, as compared to prior art temperature sensing resistors that do not include a control gate. An exemplary scenario illustrating this feature is discussed below with reference to table 1.

Fig. 5A and 5B show circuit diagrams corresponding to portions of two exemplary MOSFET arrays. First, fig. 5A provides a circuit diagram of a portion of an exemplary MOSFET array including a temperature sensing resistor and a nearby FET, wherein the resistor gate of the temperature sensing resistor may be controlled independently of the FET gates in the array, such as provided in the exemplary MOSFET array 300 shown in fig. 3. Thus, it can be independent of the FET gate voltage V _GFET To control the resistor gate electricityPressure V _GR . The doped well region of the temperature sensing resistor may be different from the FET doped well region, for example, as shown in the exemplary MOSFET array 300 shown in fig. 3. Thus, the dimensions (e.g., width and length) of the resistor doped well regions may be different from the corresponding dimensions of the FET doped well regions in the array.

As shown in fig. 5A, the voltage V at the second sensor terminal T2 _T2 Equal to FET source voltage V _SFET Because the second sensor terminal is formed as a physical extension of the FET source line. To perform an exemplary temperature measurement, a first sensor terminal V may be provided _T1 Where the current I is applied _CP The resulting voltage V can be measured _T1 To determine V _T1 And V is equal to _T2 Voltage drop between, where V _T2 Is of a known value, shown as ground, and may be based on current I _CP And voltage drop V _T1 -V _T2 To calculate the resistance R _CP And can then be based on the calculated resistance R _CP To determine the temperature.

Next, fig. 5B provides a circuit diagram of a portion of an exemplary MOSFET array including a temperature sensing resistor and a nearby FET according to another example. The exemplary configuration shown in fig. 5B is similar to the configuration shown in fig. 5A, except that the resistor gate of the temperature sensing resistor in fig. 5B is bonded to the FET gate in the array, for example as provided in the exemplary MOSFET array 400 shown in fig. 4A. Thus, the resistor gate voltage V _GR Equal to FET gate voltage V _GFET . The resistor doped well region may be located between a pair of FETp channels (in the x-axis direction shown in fig. 4A) on opposite sides of the resistor doped well region, and thus the width of the resistor doped well region (in the x-axis direction) may be defined or limited by the distance between the pair of FET doped well regions (e.g., p-channels).

As with the exemplary configuration shown in fig. 5A, the voltage V at the second sensor terminal T2 _T2 Equal to FET source voltage V _SFET . Also similar to the example configuration of fig. 5A, example temperature measurements may be performed by: at the first sensor terminal V _T1 Where the current I is applied _CP The method comprises the steps of carrying out a first treatment on the surface of the Measuring the resulting voltage V _T1 To determine the electricityPressure drop V _T1 -V _T2 Wherein V is _T2 Is a known value, shown as ground; based on current I _CP And voltage drop V _T1 -V _T2 To calculate R _CP The method comprises the steps of carrying out a first treatment on the surface of the Based on the calculated resistance R _CP To determine the temperature.

Fig. 6A and 6B illustrate cross-sectional views of exemplary temperature sensing resistors (e.g., exemplary resistors 302 or 402 discussed above) integrated in an FET array. Resistance of doped p-well region (R) representing resistance of temperature sensing resistor _cP ) Is determined by the following equation:

R _CP ＝R _{sheet_p-well} *L _p-well /(W _p-well *(T _p-well -d1-d2))+R _contact (1)

wherein the method comprises the steps of

R _{sheet_p-well} Represents p-well sheet resistance (controlled by doping concentration);

d1 denotes the gate voltage V from the resistor _GR Is referred to as a depletion region (i.e., a region that "depletes" free charge);

d2 represents the slave drain voltage V _D A depletion region at the beginning;

L _p-well 、W _p-well and T _p-well Representing the length, width and thickness of the doped p-well as shown in fig. 6A-6B; and is also provided with

R _contact Representing the sum of (a) the contact resistance between the doped p-well region and the first sensor terminal T1 and (b) the contact resistance between the doped p-well region and the second sensor terminal T2. R is R _contact Can form R _CP Is a negligible component of (c).

According to equation (1), resistance R _cP Depending on depletion regions d1 and d2; in particular, R _CP As d1 or d2 increases. Depletion region d1 is defined by resistor gate voltage V _GR Controlled, the resistor gate voltage can be independent of the FET gate voltage V _GFET Control or association with the FET gate voltage depends on the specific integration of the temperature sensing resistor in the FET array. Depletion regions d1 and V _GR Is proportional to the square root of (c). Depletion region d2 is defined by drain voltage V _D Control of the drain voltage in the on-state of the FETApplied in the state and off state, but not in the standby (i.e., power off) state of the FET.

As discussed above, the resistor gate voltage V may be selectively controlled _GR To improve operation of an integrated temperature sensor including a resistor with a controllable gate as disclosed herein (e.g., temperature sensors 201 and 401 discussed above). For example, as discussed above, the resistor gate voltage V may be _GR Applied to the resistor gate to increase the absolute p-well resistance R _CP This may improve resistance sensing (e.g., by for a given sense voltage V _T1 Allowing reduced current I _CP )。

Table 1 shows the operation of an exemplary temperature sensing resistor 202 (see fig. 2A-2C and 3) including a resistor gate 210 or an exemplary temperature sensing resistor 402 (see fig. 4A-4B) including a resistor gate 410, as compared to a conventional temperature sensing resistor without a control gate. In particular, table 1 shows the p-well resistance (R _{no_gate} ) In contrast, the gate voltage V is used in the ON state of the FET (FET-ON state) _GR Biasing resistor gate 210 or 410 (referred to as V _{GR_FET_ON} ) How to increase the measured resistance (R _{CP_FET_ON} )。R _{CP_FET_ON} May allow (a) a reduced sense current for a given sense voltage applied to the first sensor terminal 220 (of the temperature sensing resistor 202) or the first sensor terminal 220 (of the temperature sensing resistor 402), and/or (B) a reduced length of the resistor p-well (in the y-axis direction shown in fig. 2A-4B), thus reducing the required area of the respective temperature sensing resistor 202 or 402 in the related IC structure as compared to the prior art.

_GR TABLE 1 use of V to increase the temperature of a conventional temperature sensing resistor including a control gate compared to a conventional temperature sensing resistor without a control gate _CP R of temperature sensing resistor。

Fig. 7 shows an exemplary graph 700 illustrating the relationship between p-well temperature and p-well resistance of a temperature sensing resistor with and without a controllable gate. The first curve 702 indicates an example temperature-resistance curve of a conventional temperature sensing resistor that does not include a control gate. For example, referring to Table 1, curve 702 indicates the resistance R indicated in the top row of Table 1 for temperature _{no_gate} Is a function of (a) and (b). The second curve 704 indicates an exemplary temperature-resistance curve of a temperature-sensing resistor including a control gate (e.g., the temperature-sensing resistor 202 including the resistor gate 210 or the temperature-sensing resistor 402 including the resistor gate 410) according to examples of the present disclosure. For example, referring to Table 1, curve 704 indicates the resistance R indicated in the bottom row of temperature versus Table 1 _{CP_FET_ON} Is a function of (a) and (b). As shown, for any given temperature, the resistance R provided by a temperature sensing resistor (e.g., temperature sensing resistor 202 or 402) comprising a resistor gate _{CP_FET_ON} Higher than the resistance R _{no_gate} . This may improve the performance of a corresponding temperature sensor (e.g., the exemplary temperature sensor 201 or 401 discussed above) that includes such a temperature sensing resistor. Note that as the addition of the resistor gates 210, 410 increases the TCR of the temperature sensing resistors 202, 402, respectively, the second curve 704 exhibits a higher slope than the first curve 702.

Furthermore, as discussed above, for the case where the gate voltage V _GR Can be independent of the corresponding FET gate voltage V _GFET To control an exemplary temperature sensing resistor 202, resistor gate voltage V _GR Can be selectively controlled to reduce R as a function of the current FET state (e.g., on or off) _CP Dependency on the current FET state. For example, the temperature analysis circuit 260 may apply a first predetermined resistor gate voltage V in the ON state of the FET (FET-ON state) _{GR_FET_ON} And applying a second, different predetermined resistor gate voltage V in the OFF state of the FET (FET-OFF "state) _{GR_FET_OFF} Wherein V is _{GR_FET_ON} And V is equal to _{GR_FET_OFF} The difference between them reduces or minimizes the difference between the resistor 202 and the resistorMeasured p-well resistance (R _{CP_FET_ON} ) And the p-well resistance (R) measured under FET-OFF _{CP_FET_OFF} ) Difference between them.

Table 2 illustrates the operation of the exemplary temperature sensing resistor 202, where the gate voltage V _GR Can be independent of FET gate voltage V _GFET To control. In particular, table 2 shows a case in which the temperature analysis circuit 260 applies a positive resistor gate voltage V in the FET-ON state _GR (V _{GR_FET_ON} > 0), but no voltage (V) _{GR_FET_OFF} =0).

_GR TABLE 2 reduction using V in a temperature sense resistor including a control gate independent of the FET control gate Dependence of measured resistance on FET state。

As shown in table 2, in the FET-OFF state, the FET drain voltage (V _D ) At the same time V _GR And V _GFET Maintained at ground potential (i.e., V _{GR_FET_OFF} ＝V _GFET =0v), and the resulting resistor p-well resistance (R _{CP_FFT_OFF} ) Greater than the resistor p-well resistance (R) in the FET-Standby (i.e., power-down) state _{CP_FET_Standby} )。

As further shown in Table 2, in the FET-ON state, the FET gate voltage (V _GFET ) This switches the FET to its conductive state. In addition, the resistor gate voltage V will be specified _GR Applied to the resistor gate 210 (i.e., V _{GR_FET_ON} > 0) which causes the resulting resistor p-well resistance R _{CP_FET_ON} And without applying a resistor gate voltage (i.e., V _{GR_FET_ON} =0) and closer to the FET-OFF state p-well resistance R than conventional temperature sensing resistors that do not include a resistor gate _{CP_FET_OFF} . In particular, V applied _{GR_FET_ON} A net depletion region (d1+d2) in the FET-ON state that approximates the net depletion region (d1+d2) in the FET-OFF state can be provided,thereby reducing the difference in absolute resistance between the different states of FET operation.

In some examples, V _{GR_FET_OFF} Zero, V _{GR_FET_ON} Is a non-zero voltage, for example, in the range of 2V-10V. In other examples, V _{GR_OFF} And V _{GR_ON} Is a different non-zero voltage. For example, V can be _{GR_FET_OFF} Set to a first non-zero voltage to set V _{GR_FET_ON} Set equal to V _{GR_FET_OFF} A second voltage of the differential voltage in the range of 2V-10V is added.

In some examples, V _{GR_FET_ON} The value of (2) may be selected such that R _{CP_FET_ON} And R is R _{CP_FET_OFF} The difference is less than 15%, or less than 10%, or less than 5%, depending on the particular example. In some examples, V providing such results may be determined through a calibration process performed during wafer testing _{GR_FET_ON} Is selected from the group consisting of a plurality of values.

Further, for a set of temperature sensing resistors 202, for example, on the same wafer across multiple wafers, the gate voltage V of each temperature sensing resistor 202 _GR May be tuned to reduce the p-well resistance (R) across various temperature sensing resistors 202 _CP ) Is a manufacturing related variation of (a). For example, process-related variations in P-well ion implantation (e.g., variations in P-well patterning or variations in thermal activation of implants across wafers or between wafer lots) may result in R between different temperature sensing resistors 202 _CP Is a variation of (c). In some examples, the temperature analysis circuit 260 connected to each respective temperature-sensing resistor 202 may determine a baseline V for the respective temperature-sensing resistor 202 _GR A value that reduces R across different temperature sensing resistors 202 _CP Is a variation of (c). The temperature analysis circuit 260 connected to each respective temperature sensing resistor 202 may compare the determined baseline V _GR The values are applied as a constant baseline voltage to the respective temperature sensing resistors 202. Different baselines V applied to different temperature sensing resistors 202 _GR The value may reduce R across different temperature sensing resistors 202 _CP To improve the accuracy of the temperature analysis performed using each temperature sensing resistor 202 Sex.

FIG. 8 shows a graph illustrating the temperature at 25℃and at V _RG P-well sheet resistance of temperature sensing resistor with =0v (R in equation (1) above _{sheet_p-well} ) A graph of an exemplary relationship with the implanted dopant concentration of the doped p-well region.

Further, fig. 9A and 9B show diagrams illustrating p-well sheet resistance (R _{sheet_p-well} ) And resistor gate voltage V _GR Graphs 900a and 900b of exemplary relationships therebetween. First, FIG. 9A illustrates R of an exemplary temperature sensing resistor 202 _{sheet_p-well} And V is equal to _GR Is illustrated (where doped p-well region 204 is formed with a lower p-well dopant concentration (1 e 13/cm) ² ) As well as a corresponding curve 904a showing the change in rate (percent change) of the curve 902 a. Second, FIG. 9B illustrates R of the exemplary temperature sensing resistor 202 _{sheet_p-well} And V is equal to _GR Is illustrated for curve 902b (where doped p-well region 204 is formed with a higher p-well implant dopant concentration (5 e13/cm ² ) And a corresponding curve 904b showing the change in rate (percent change) of the curve 902 b. As shown by comparing graphs 900a and 900b, for a given resistor gate voltage V _GR Lower p-well implant dopant concentrations provide much higher p-well sheet resistance and resistivity.

Thus, based on the above, a low or reduced dopant concentration of the temperature sensing resistor doped p-well region may be used to provide improved temperature analysis. For example, for the exemplary temperature sensing resistor 202, because the doped p-well region 204 is physically different from the FET doped p-well region 304 (shown in fig. 3) of the FETs 302 in the array 300, the doped p-well region 204 of the temperature sensing resistor 202 may be formed to have a lower dopant concentration than the FET p-well region 304.

Fig. 10-12 illustrate the use of a temperature sensor (e.g., temperature sensor 201 or 401) to determine a resistance correlation value corresponding to a conductive path CP of an integrated temperature sensing resistor (e.g., temperature sensing resistor 202 integrated in FET array 200 or temperature sensing resistor 402 integrated in FET array 400), to analyze a temperature based on the determined resistance correlation value, and to analyze a temperature based on the analyzed temperatureOutput a temperature-related signal S _temp Is described.

Fig. 10 illustrates an exemplary method 1000 for analyzing a temperature associated with an FET array using a temperature sensor including a temperature sensing resistor (e.g., temperature sensor 201 including temperature sensing resistor 202 or temperature sensor 401 including temperature sensing resistor 402). At 1002, voltage V _GR Applied to the resistor gate, which affects (e.g., increases) the resistance of the doped well region under the resistor gate, thereby affecting (e.g., increasing) the conductive path resistance R _CP . At V _GR Can be independent of V _GFET In the controlled exemplary temperature sensor 201, the voltage V _GR May be selected and applied by the temperature analysis circuit 260. At V _GR Is joined to V _GFET In the exemplary temperature sensor 401 of (1), voltage V _GR And V is equal to _GFET And (3) combined application.

At 1004, a temperature analysis circuit (e.g., temperature analysis circuit 260 of temperature sensor 202 or temperature analysis circuit 460 of temperature sensor 402) determines at least one Resistance Related Value (RRV) associated with conductive path CP. As discussed above with respect to fig. 2A-2C, the resistance-related value may include the resistance R of the conductive path CP _CP Or with the resistance R of the conductive path _CP The associated parameter values. In some examples, the temperature analysis circuit is based on a current I across a conductive path CP through the temperature sensing resistor doped well region _CP And voltage drop V _T1 -V _T2 To determine at least one RRV, as discussed below with reference to fig. 11-12.

At 1006, a temperature analysis circuit determines or otherwise analyzes a temperature associated with the FET array based on the determined resistance related value. The characteristics of analyzing temperature based on the resistance correlation values are discussed above with respect to fig. 2A-2C.

At 1008, the temperature analysis circuit may output a temperature related signal S based on the analyzed temperature _temp . For example, the temperature analysis circuit may send a signal S indicative of temperature data _temp To a display device, processor or storage device (or to a contact or transmitter to transmit such a signal S) _temp For receipt by a display device (to display temperature data), a processor (e.g., to further analyze temperature data), or a storage device (to store temperature data).

As another example, the temperature analysis circuit may determine a temperature-based condition or event based on the analyzed temperature (e.g., by detecting that the temperature exceeds or falls below a predetermined threshold), and will signal S indicative of the temperature-based condition or event _temp To a display device, processor or storage device (or to a contact or transmitter to transmit such a signal S) _temp For display means (to display alarms or other information associated with temperature-based conditions or events), a processor (e.g. to further analyze S _temp Data) or storage means (for storing S _temp Data) received).

Fig. 11 illustrates another exemplary method 1100 for analyzing a temperature associated with an FET array using a temperature sensor including a temperature sensing resistor (e.g., temperature sensor 201 including temperature sensing resistor 202 or temperature sensor 401 including temperature sensing resistor 402). At 1102, a resistor gate voltage V is applied _GR This affects (e.g., increases) the resistance of the resistor doped well region under the resistor gate, thereby affecting (e.g., increasing) the conductive path resistance R _CP . At V _GR Can be independent of V _GFET In the controlled exemplary temperature sensor 201, the voltage V _GR May be selected and applied by the temperature analysis circuit 260. At V _GR Is joined to V _GFET In the exemplary temperature sensor 401 of (1), voltage V _GR And V is equal to _GFET And (3) combined application.

At 1104, a temperature analysis circuit of a respective temperature sensor (e.g., temperature analysis circuit 260 of temperature sensor 202 or temperature analysis circuit 460 of temperature sensor 402) applies a predetermined current I along a conductive path CP through the temperature sensing resistor doped well region _CP . In one example, a predetermined current I is applied at the first sensor terminal T1 _CP 。

At 1106, the temperature analysis circuit measures a first sensor endVoltage V at sub T1 _T1 And measures (or accesses) the voltage V at the second sensor terminal T2 _T2 . At 1108, the temperature analysis circuit calculates a voltage drop V across the resistor doped well region _T1 -V _T2 . Voltage V at second sensor terminal T2 _T2 May be a predetermined voltage and thus the value need not be measured.

At 1110, the temperature analysis circuit is based on the voltage drop V _T1 -V _T2 And a predetermined current I _CP To determine the resistance R of the conductive path _CP 。

At 1112, the temperature analysis circuit is based on the determined conductive path resistance R _CP To determine or otherwise analyze the temperature associated with the FET array.

At 1114, the temperature analysis circuit may output a temperature related signal S based on the analyzed temperature _temp For example similar to step 1008 discussed above with respect to fig. 10.

Fig. 12 illustrates another exemplary method 1200 for analyzing a temperature associated with an FET array using a temperature sensor including a temperature sensing resistor (e.g., temperature sensor 201 including temperature sensing resistor 202 or temperature sensor 401 including temperature sensing resistor 402). At 1202, a resistor gate voltage V is applied _GR This affects (e.g., increases) the resistance of the temperature sensing resistor doped well region, thereby affecting (e.g., increasing) the conductive path resistance R _CP . At V _GR Can be independent of V _GFET In the controlled exemplary temperature sensor 201, the voltage V _GR May be selected and applied by the temperature analysis circuit 260. At V _GR Is joined to V _GFET In the exemplary temperature sensor 401 of (1), voltage V _GR And V is equal to _GFET And (3) combined application.

At 1204, a temperature analysis circuit of the respective temperature sensor (e.g., temperature analysis circuit 260 of temperature sensor 202 or temperature analysis circuit 460 of temperature sensor 402) applies a predetermined voltage V at first sensor terminal T1 _T1 。

At 1206, the temperature analysis circuit uses, for example, a circuit connected to the first sensor terminal T1Appropriate circuitry (e.g., included in a temperature analysis circuit) to measure the current I along the conductive path CP _CP . At 1208, the temperature analysis circuit measures or otherwise determines the voltage V at the second sensor terminal T2 _T2 And calculates the voltage drop V across the resistor doped well region _T1 -V _T2 。

At 1210, the temperature analysis circuit is based on the voltage drop V _T1 -V _T2 And current I _CP To determine or otherwise calculate the resistance R of the conductive path _CP . At 1212, the temperature analysis circuit is based on the determined conductive path resistance R _CP To determine or otherwise analyze the temperature associated with the FET array. Finally, at 1214, the temperature analysis circuit may output a temperature-related signal S based on the analyzed temperature _temp For example similar to step 1008 discussed above with respect to fig. 10.

Claims (21)

1. A temperature sensor integrated in a transistor array, the temperature sensor comprising:

a temperature sensing resistor, the temperature sensing resistor comprising:

a doped well region formed in the substrate;

a resistor gate formed over the doped well region and separated from the doped well region by a gate oxide;

a first sensor terminal conductively coupled to the doped well region on a first side of the resistor gate; and

A second sensor terminal conductively coupled to the doped well region on a second side of the resistor gate;

a gate driver to apply a voltage to the resistor gate, the voltage affecting a resistance of the doped well region under the resistor gate; and

a temperature analysis circuit to:

determining a resistance-related value corresponding to a resistance of a conductive path through the doped well region;

analyzing a temperature associated with the transistor array based at least on the determined resistance related value; and

a temperature-dependent signal is output based on the analyzed temperature.

2. The temperature sensor of claim 1, wherein the doped well region comprises a P-well region.

3. The temperature sensor of any one of claims 1-2, wherein the resistor gate is conductively coupled to a control gate of at least one transistor cell in the transistor array.

4. A temperature sensor according to any one of claims 1 to 3, wherein the second sensor terminal is conductively coupled to a transistor source terminal of at least one transistor cell in the transistor array.

5. A transistor array, the transistor array comprising:

a plurality of transistors including a plurality of transistor doped well regions formed in a substrate; and

a temperature sensor comprising any one of the temperature sensors of claims 1-4, wherein the temperature analysis circuit is to analyze a temperature associated with the transistor array further based on a determined resistance related value corresponding to the resistance of the conductive path through the doped well region.

6. The transistor array of claim 5, wherein the plurality of transistors comprises a plurality of metal-oxide-semiconductor field effect transistors (MOSFETs).

7. The transistor array of any of claims 5-6, wherein the plurality of transistors comprises a plurality of transistor gates, and wherein the resistor gate and the plurality of transistor gates are formed in a common gate layer.

8. The transistor array of claim 7, wherein the common gate layer comprises a common metal layer.

9. The transistor array of any of claims 5 to 8, wherein the second sensor terminal is electrically connected to a transistor source contact of at least one transistor of the plurality of transistors.

10. The transistor array of claim 9, wherein the second sensor terminal is defined by an extension of the transistor source contact.

11. The transistor array of any of claims 5 to 11, wherein the resistor gate is connected to a transistor gate of at least one transistor of the plurality of transistors.

12. The transistor array of claim 11, wherein the resistor gate is defined by an extension of the transistor gate.

13. The transistor array of any of claims 5 to 12, wherein the sensor doped well region of the temperature sensor has a different dopant concentration than the transistor doped well regions of the plurality of transistors.

14. The transistor array of claim 13, wherein the sensor doped well region of the temperature sensor has a lower dopant concentration than the transistor doped well regions of the plurality of transistors.

15. A method for determining a temperature associated with a transistor array using a temperature sensor integrated in the transistor array and comprising (a) a doped well region formed in a substrate, and (b) a resistor gate formed over the doped well region and separated from the doped well region by a gate oxide, the method comprising:

Applying a voltage to the resistor gate that affects the resistance of the doped well region;

generating a current along a conductive path through the doped well region;

determining a resistance-related value corresponding to a resistance of the conductive path through the doped well region;

analyzing a temperature associated with the transistor array based at least on the determined resistance related value corresponding to the resistance of the conductive path through the doped well region; and

a temperature-dependent signal is output based on the analyzed temperature.

16. The method of claim 15, comprising applying the voltage to the resistor gate to increase the resistance of the doped well region.

17. The method of any of claims 15 to 16, comprising determining the resistance of the doped well region by a temperature analysis circuit connected to the first sensor terminal.

18. The method of any one of claims 15 to 17, wherein:

the resistor gate is connected to a transistor control gate of at least one transistor of the transistor array; and is also provided with

The voltage applied to the resistor gate is defined by a control gate voltage applied to the transistor control gate.

19. The method of any of claims 15-18, wherein determining the conductive path through the doped well region comprises:

supplying current to the first sensor terminal;

determining a voltage drop between the first sensor terminal and the second sensor terminal; and

the resistance of the conductive path is determined based on the supplied current and the measured voltage drop.

20. The method according to claim 19, wherein:

the second sensor terminal is connected to a transistor source contact of at least one transistor of the transistor array;

a transistor source voltage is applied to the second sensor terminal; and is also provided with

Determining a voltage drop between the first sensor terminal and the second sensor terminal includes measuring a first terminal voltage at the first sensor terminal and determining a difference between the first terminal voltage and the transistor source voltage.

21. The method of any of claims 15 to 20, wherein determining the resistance-related value comprises:

applying a first terminal voltage to a first sensor terminal electrically connected to the doped well region;

measuring a current through the conductive path; and

The resistance of the conductive path is determined based on the first terminal voltage and the measured current.