CN116961646A - Low-noise phase-locked loop with temperature compensation - Google Patents

Low-noise phase-locked loop with temperature compensation Download PDF

Info

Publication number
CN116961646A
CN116961646A CN202311204723.9A CN202311204723A CN116961646A CN 116961646 A CN116961646 A CN 116961646A CN 202311204723 A CN202311204723 A CN 202311204723A CN 116961646 A CN116961646 A CN 116961646A
Authority
CN
China
Prior art keywords
voltage
charge pump
locked loop
controlled oscillator
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202311204723.9A
Other languages
Chinese (zh)
Other versions
CN116961646B (en
Inventor
胡华栋
章豪顺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Lianxintong Semiconductor Co ltd
Original Assignee
Hangzhou Lianxintong Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Lianxintong Semiconductor Co ltd filed Critical Hangzhou Lianxintong Semiconductor Co ltd
Priority to CN202311204723.9A priority Critical patent/CN116961646B/en
Publication of CN116961646A publication Critical patent/CN116961646A/en
Application granted granted Critical
Publication of CN116961646B publication Critical patent/CN116961646B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Abstract

The present disclosure provides a low noise phase locked loop with temperature compensation, comprising: a basic phase-locked loop with a voltage-controlled oscillator and a current-type digital-to-analog converter with temperature compensation characteristics; the temperature compensation current type digital-to-analog converter is connected with a voltage-controlled oscillator in the basic phase-locked loop; the temperature compensation current type digital-to-analog converter is used for adjusting the bit number corresponding to the reference current flowing into the voltage-controlled oscillator according to the bit control of the preset register, dividing the frequency of the voltage-controlled oscillator into a plurality of different frequency bands according to the bit number, and simultaneously, having the temperature compensation characteristic, so that the current can automatically change along with the temperature under the wide-range temperature change after the bit number is set, and the frequency of the voltage-controlled oscillator is ensured not to change along with the temperature. The output frequency range of the phase-locked loop can be maintained while reducing the noise of the phase-locked loop.

Description

Low-noise phase-locked loop with temperature compensation
Technical Field
The present disclosure relates to the field of electronics, and in particular, to a low noise phase locked loop with temperature compensation.
Background
The phase-locked loop is an important module in the digital-analog hybrid circuit, and can utilize the voltage generated by phase synchronization to tune the voltage-controlled oscillator to generate a negative feedback control system with target frequency, and output a clock signal with low jitter. It has become an indispensable module in special chips such as communication system, digital circuit, hard disk drive circuit and CPU.
In the phase-locked loop, a voltage-controlled oscillator gives out a signal, one part of the signal is used as output, the other part of the signal is compared with a local oscillation signal generated by the phase-locked loop integrated circuit through frequency division, in order to keep the frequency unchanged, the phase difference is required not to change, and if the phase difference changes, the voltage at the voltage output end of the phase-locked loop integrated circuit changes, so that the voltage-controlled oscillator is controlled until the phase difference is recovered, and the purpose of phase locking is achieved. At present, in order to reduce noise of the phase-locked loop, the frequency gain (KVCO) of the voltage-controlled oscillator needs to be reduced, but the narrowing of the control voltage of the voltage-controlled oscillator due to the reduction of the power supply voltage and the addition of the low frequency gain lead to the problem that the output frequency of the phase-locked loop is narrowed, and meanwhile, in the more advanced process, the output frequency of the voltage-controlled oscillator is greatly changed along with the change of temperature, and a larger KVCO is required, which contradicts the requirement of reducing the KVCO, so that the reduction of the KVCO is limited, and the reduction of the noise is limited.
Disclosure of Invention
Embodiments of the present disclosure provide at least a phase-locked loop with low noise and temperature compensation, which can reduce noise of the phase-locked loop and maintain an output frequency range of the phase-locked loop.
The embodiment of the disclosure provides a low-noise phase-locked loop with temperature compensation, comprising: a basic phase-locked loop with a voltage-controlled oscillator and a temperature compensated current-type digital-to-analog converter;
the temperature compensation current type digital-to-analog converter is connected with the voltage-controlled oscillator in the basic phase-locked loop;
the temperature compensation current type digital-to-analog converter is used for adjusting the bit number corresponding to the reference current flowing into the voltage-controlled oscillator according to the bit control of a preset register, and dividing the frequency of the voltage-controlled oscillator into a plurality of different frequency bands according to the bit number, so that the phase-locked loop has a large output frequency range, but the KVCO of each frequency band is reduced, and the phase-locked loop noise is reduced.
In a possible implementation manner, the temperature compensation current type digital-to-analog converter includes: the device comprises a first resistor, a second resistor, a bit control module, a voltage locking module and a positive temperature coefficient current source;
the bit control module is connected in parallel with two ends of the second resistor;
one end of the second resistor is connected with an external voltage source, and the other end of the second resistor is connected to the voltage-controlled oscillator through the voltage locking module;
one end of the first resistor is connected with the positive temperature coefficient current source through the voltage locking module, and the other end of the first resistor is connected to the external voltage source;
the positive temperature coefficient current source is grounded.
In a possible implementation manner, the bit control module comprises a plurality of bit control paths, and the bit control paths comprise a third resistor and a switch;
the bit control path is connected in parallel with two ends of the second resistor;
in each of the bit control paths, the third resistor is connected in series with the switch.
In a possible implementation, the switch is connected to the preset register;
and controlling the switch to be turned on and off through the preset register, so as to adjust the bit number corresponding to the reference current flowing into the voltage-controlled oscillator.
In one possible implementation manner, the voltage locking module includes a first PMOS transistor and a second PMOS transistor;
the grid electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the source electrode of the first PMOS tube is connected with the first resistor, and the drain electrode of the first PMOS tube is connected with the positive temperature coefficient current source;
the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the second PMOS tube is connected with the second resistor, and the drain electrode of the second PMOS tube is connected with the voltage-controlled oscillator.
In a possible implementation manner, the basic phase-locked loop includes: the circuit comprises a phase frequency detector, a charge pump, a low-pass filter, the voltage-controlled oscillator and a frequency divider;
the phase frequency detector, the charge pump, the low-pass filter and the voltage-controlled oscillator are sequentially connected;
the frequency divider is connected between the output end of the voltage-controlled oscillator and the input end of the phase frequency detector.
In a possible implementation manner, the low-pass filter includes: the circuit comprises an operational amplifier, a filter resistor, a first filter capacitor and a second filter capacitor;
the filter resistor is connected with the first filter capacitor in series;
the first filter capacitor is connected with the positive input end of the operational amplifier, and the filter resistor is connected with the charge pump;
one end of the second filter capacitor is connected with the negative input end of the operational amplifier, and the other end of the second filter capacitor is connected with the output end of the operational amplifier;
and the negative input end and the positive input end of the operational amplifier are connected with the charge pump, and the output end of the operational amplifier is connected with the voltage-controlled oscillator.
In one possible embodiment, the charge pump includes a first charge pump path and a second charge pump path;
one end of the first charge pump passage is connected with the phase frequency detector, and the other end of the first charge pump passage is connected with the negative input end of the operational amplifier;
one end of the second charge pump passage is connected with the phase frequency detector, and the other end of the second charge pump passage is connected with the positive input end of the operational amplifier.
In a possible implementation manner, the first charge pump path and the second charge pump path are formed by a first charge pump switch, a second charge pump switch, a third charge pump switch and a fourth charge pump switch;
the first charge pump switch is connected in series with the second charge pump switch;
the third charge pump switch is connected in series with the fourth charge pump switch;
the first charge pump switch is connected with the third charge pump switch, and the second charge pump switch is connected with the fourth charge pump switch.
In a possible implementation, the voltage controlled oscillator is a cross-coupled even-stage ring oscillator.
The embodiment of the disclosure provides a low-noise phase-locked loop with temperature compensation, which comprises: a basic phase-locked loop with a voltage-controlled oscillator and a temperature compensated current-type digital-to-analog converter; the temperature compensation current type digital-to-analog converter is connected with the voltage-controlled oscillator in the basic phase-locked loop; the temperature compensation current type digital-to-analog converter is used for adjusting the bit number corresponding to the reference current flowing into the voltage-controlled oscillator according to the bit control of a preset register, and dividing the frequency of the voltage-controlled oscillator into a plurality of different frequency bands according to the bit number. The output frequency range of the phase-locked loop can be maintained while reducing the noise of the phase-locked loop.
The foregoing objects, features and advantages of the disclosure will be more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the embodiments are briefly described below, which are incorporated in and constitute a part of the specification, these drawings showing embodiments consistent with the present disclosure and together with the description serve to illustrate the technical solutions of the present disclosure. It is to be understood that the following drawings illustrate only certain embodiments of the present disclosure and are therefore not to be considered limiting of its scope, for the person of ordinary skill in the art may admit to other equally relevant drawings without inventive effort.
FIG. 1 illustrates a schematic diagram of a low noise phase locked loop with temperature compensation provided by embodiments of the present disclosure;
FIG. 2 shows a schematic diagram of a temperature compensated current mode digital to analog converter provided by an embodiment of the present disclosure;
FIG. 3 illustrates a schematic diagram of another low noise phase locked loop with temperature compensation provided by embodiments of the present disclosure;
FIG. 4 illustrates a schematic diagram of a charge pump provided by an embodiment of the present disclosure;
fig. 5 shows a schematic diagram of a voltage controlled oscillator provided by an embodiment of the present disclosure.
Illustration of:
100-low noise phase locked loop with temperature compensation; 110-a basic phase-locked loop; 120-temperature compensated current mode digital to analog converter; 111-a phase frequency detector; 112-a charge pump; 113-a low pass filter; 114-a voltage controlled oscillator; 115-divider; 1131-an operational amplifier; 1132-a filter resistor; 1133-a first filter capacitor; 1134-a second filter capacitor; 121-a first resistor; 122-a second resistor; a 123-bit control module; 124-a voltage locking module; 125-positive temperature coefficient current source; 1231-third resistance; 1232-switch; 1241-a first PMOS tube; 1242-a second PMOS tube; 1121-a first charge pump switch; 1122-a second charge pump switch; 1123-a third charge pump switch; 1124-fourth charge pump switch.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. The components of the embodiments of the present disclosure, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the disclosure, as claimed, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of this disclosure without making any inventive effort, are intended to be within the scope of this disclosure.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The term "and/or" is used herein to describe only one relationship, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
It is found that in the phase-locked loop, the voltage-controlled oscillator gives out a signal, one part is used as output, the other part is compared with the local oscillation signal generated by the phase-locked loop integrated circuit through frequency division, in order to keep the frequency unchanged, the phase difference is required not to change, if the phase difference changes, the voltage at the voltage output end of the phase-locked loop integrated circuit changes, the voltage-controlled oscillator is controlled until the phase difference recovers, and the phase locking purpose is achieved. At present, in order to reduce noise of the phase-locked loop, the frequency gain (KVCO) of the voltage-controlled oscillator needs to be reduced, but the narrowing of the control voltage of the voltage-controlled oscillator due to the reduction of the power supply voltage and the addition of the low frequency gain lead to the problem that the output frequency of the phase-locked loop is narrowed, and meanwhile, in the more advanced process, the output frequency of the voltage-controlled oscillator is greatly changed along with the change of temperature, and a larger KVCO is required, which contradicts the requirement of reducing the KVCO, so that the reduction of the KVCO is limited, and the reduction of the noise is limited.
Based on the above study, the present disclosure provides a low noise phase locked loop with temperature compensation, comprising: a basic phase-locked loop with a voltage-controlled oscillator and a temperature compensated current-type digital-to-analog converter; the temperature compensation current type digital-to-analog converter is connected with the voltage-controlled oscillator in the basic phase-locked loop; the temperature compensation current type digital-to-analog converter is used for adjusting the bit number corresponding to the reference current flowing into the voltage-controlled oscillator according to the bit control of a preset register, and dividing the frequency of the voltage-controlled oscillator into a plurality of different frequency bands according to the bit number, so that the phase-locked loop has a large output frequency range, but the KVCO of each frequency band is reduced, and the phase-locked loop noise is reduced. Meanwhile, the voltage-controlled oscillator has the temperature compensation characteristic, so that after the bit number is set, the current can automatically change along with the temperature under the condition of large-range temperature change, the frequency of the voltage-controlled oscillator is ensured not to change along with the temperature, and the control voltage of the voltage-controlled oscillator is kept unchanged under the condition of large-range temperature change, and the KVCO can also be reduced. The output frequency range of the phase-locked loop can be maintained while reducing the noise of the phase-locked loop.
To facilitate understanding of the present embodiment, a low noise phase locked loop with temperature compensation disclosed in the embodiments of the present disclosure will be described in detail. Referring to fig. 1, a schematic diagram of a low noise phase locked loop 100 with temperature compensation is provided in an embodiment of the disclosure.
Specifically, the low noise phase locked loop with temperature compensation 100 includes: a base phase locked loop 110 and a temperature compensated current mode digital to analog converter 120; the basic phase-locked loop 110 includes: a phase frequency detector 111, a charge pump 112, a low pass filter 113, a voltage controlled oscillator 114, and a frequency divider 115.
Here, the temperature compensated current mode digital to analog converter 120 is connected to the voltage controlled oscillator 114 in the basic phase locked loop 110; the phase frequency detector 111, the charge pump 112, the low-pass filter 113 and the voltage-controlled oscillator 114 are connected in sequence; a frequency divider 115 is connected between the output of the voltage controlled oscillator 114 and the input of the phase frequency detector 111.
In a specific implementation, the input of the phase frequency detector 111 is a reference signal and the output signal of the voltage-controlled oscillator 114 fed back by the frequency divider 115, and the input reference signal and the signal fed back by the frequency divider 115 are compared in frequency and phase, so as to generate output control signals UP, UPB, DN, and DNB representing the difference between the two signals, and the output control signals are sent to the charge pump 112. The charge pump 112 receives the control signal and charges and discharges the low-pass filter 113. The low-pass filter 113 filters out high-frequency components in the input signal, and the remaining dc component is supplied to the voltage-controlled oscillator 114. The voltage controlled oscillator 114 outputs a periodic signal whose frequency is controlled by the input voltage. The frequency divider 115 serves as a feedback loop to send the signal output from the voltage controlled oscillator 114 back to the phase frequency detector 111.
Here, the frequency of the output signal of the voltage-controlled oscillator 114 is generally greater than the frequency of the reference signal, so a frequency divider 115 is added thereto to reduce the frequency.
Further, the temperature compensation current type dac 120 is configured to adjust the number of bits corresponding to the reference current flowing into the vco 114 according to the bit control of the preset register, and divide the frequency of the vco 114 into a plurality of different frequency bands according to the number of bits.
Here, the register controls the bits of the temperature compensation current mode digital-to-analog converter 120, so that the temperature compensation current mode digital-to-analog converter 120 controls the reference current flowing into the voltage-controlled oscillator 114 according to the bits, divides the frequency of the voltage-controlled oscillator 114 into a plurality of frequency bands of a plurality of different frequency ranges according to different numbers of bits, and further solves the problem of narrowing the output frequency by operating the voltage-controlled oscillator 114 in different frequency bands.
In a specific implementation, the vco 114 is a core part of the pll, and the temperature change may cause the parameters of the MOS transistor to change, so that the frequency of the clock signal output by the vco 114 may change along with the temperature change, especially in a more advanced process, the influence of the temperature on the frequency is greater and greater, and generally decreases along with the temperature rise, in the pll with low frequency gain, the control voltage of the pll is reduced or increased to saturation under the temperature change, so that the pll is unlocked during the temperature change.
In the embodiment of the present application, in order to solve the problem that the control voltage of the phase-locked loop is reduced or increased to saturation under the temperature change, thereby causing the phase-locked loop to lose lock during the temperature change, the structure of the temperature compensation current mode digital-to-analog converter 120 provided in the embodiment of the present application may be shown in fig. 2, which is a schematic diagram of the temperature compensation current mode digital-to-analog converter 120 provided in the embodiment of the present disclosure.
Specifically, the temperature compensated current type digital-to-analog converter 120 includes: a first resistor 121, a second resistor 122, a bit control module 123, a voltage lock module 124, and a positive temperature coefficient current source 125. The bit control module 123 includes a plurality of bit control paths, and each bit control path includes a third resistor 1231 and a switch 1232; the voltage locking module 124 includes a first PMOS transistor 1241 and a second PMOS transistor 1242.
Here, the bit control module 123 is connected in parallel to both ends of the second resistor 122; one end of the second resistor 122 is connected to an external voltage source, and the other end is connected to the voltage-controlled oscillator 114 through the voltage locking module 124; one end of the first resistor 121 is connected to the positive temperature coefficient current source 125 through the voltage locking module 124, and the other end is connected to the external voltage source; the positive temperature coefficient current source 125 is grounded.
Further, the bit control path is connected in parallel to two ends of the second resistor 122; in each of the bit control paths, the third resistor 1231 is connected in series with the switch 1232. The switch 1232 is connected to the preset register; the switch 1232 is controlled to be turned on or off by the preset register, so as to adjust the number of bits corresponding to the reference current flowing into the voltage-controlled oscillator 114.
Here, a plurality of bit control paths are sequentially connected in parallel to both ends of the second resistor 122.
In a specific implementation, the temperature compensation current type digital-to-analog converter 120 uses feedback locking voltages of the first PMOS transistor 1241 and the second PMOS transistor 1242, and uses a register to control on/off of the switch 1232 in the bit control path, so as to adjust the number of the third resistors 1231 connected in parallel to two ends of the second resistor 122, so as to realize binary bit control.
Further, the register controls the number of resistance switches, thereby controlling the current flowing into the voltage-controlled oscillator 114, and the number of bits of the current also causes the output frequency of the voltage-controlled oscillator 114 to form a plurality of frequency bands.
The first resistor 121, the second resistor 122 and the positive temperature coefficient current source 125 have temperature compensation characteristics, so that the output frequency is greatly reduced in (-40-125) within a wide temperature range.
Here, the temperature compensation current type digital-to-analog converter 120 has a temperature compensation characteristic through the first resistor 121, the second resistor 122, and the positive temperature coefficient current source 125, so that the current flowing into the voltage controlled oscillator 114 varies with the temperature, and the variation trend of the current flowing into the voltage controlled oscillator 114 with the temperature varies is opposite to the variation trend of the frequency of the voltage controlled oscillator 114 with the temperature.
Specifically, the current flowing into the voltage controlled oscillator 114 can be expressed as:
wherein, the liquid crystal display device comprises a liquid crystal display device,representing the reference current flowing into the voltage controlled oscillator 114; i1 represents the current flowing in the low-pass filter, iptat represents the current corresponding to the ptc current source 125; />Representing the corresponding voltage at the source of the second PMOS transistor 1242; r1 represents the resistance value of the first resistor 121; r2 represents the resistance value of the second resistor 122.
Here, the reference current flowing into the voltage-controlled oscillator 114 is derived from the temperature, and the slope of the current with temperature can be obtained; the derived variables are the current corresponding to the positive temperature coefficient current source 125 and the slopes of the resistance values of the first resistor 121 and the second resistor 122 along with the temperature change.
In a specific implementation, different types of resistors can be selected according to the slope of the frequency of the voltage-controlled oscillator 114 along with the temperature, and the characteristics of the resistance values of the first resistor 121 and the second resistor 122 along with the temperature change are selected, so that the ratio of the resistance values of the first resistor 121 and the second resistor 122 is selected, the slope of the resistance values of the first resistor 121 and the second resistor 122 along with the temperature change is changed, and the current flowing into the voltage-controlled oscillator is changed to achieve the effect of compensating the trend of the frequency of the voltage-controlled oscillator 114 along with the temperature change.
It should be noted that, the current corresponding to the ptc current source 125 may be directly mirrored from a predetermined bandgap reference circuit (bandgap) through a current mirror, so as to change the slope of the current with temperature.
The embodiment of the disclosure provides a low-noise phase-locked loop with temperature compensation, which comprises: a basic phase-locked loop with a voltage-controlled oscillator and a temperature compensated current-type digital-to-analog converter; the temperature compensation current type digital-to-analog converter is connected with a voltage-controlled oscillator in the basic phase-locked loop; the temperature compensation current type digital-to-analog converter is used for adjusting the bit number corresponding to the reference current flowing into the voltage-controlled oscillator according to the bit control of the preset register, and dividing the frequency of the voltage-controlled oscillator into a plurality of different frequency bands according to the bit number. The output frequency range of the phase-locked loop can be maintained while reducing the noise of the phase-locked loop.
As one possible implementation, referring to fig. 3, another low noise phase locked loop 100 with temperature compensation is provided in an embodiment of the disclosure.
Specifically, the low noise phase locked loop with temperature compensation 100 includes: a base phase locked loop 110 and a temperature compensated current mode digital to analog converter 120; the basic phase-locked loop 110 includes: a phase frequency detector 111, a charge pump 112, a low pass filter 113, a voltage controlled oscillator 114, and a frequency divider 115. The low-pass filter 113 includes: an operational amplifier 1131, a filter resistor 1132, a first filter capacitor 1133, and a second filter capacitor 1134.
Here, the filter resistor 1132 is connected in series with the first filter capacitor 1133; the first filter capacitor 1133 is connected with the positive input end of the operational amplifier 1131, and the filter resistor 1132 is connected with the charge pump 112; one end of the second filter capacitor 1134 is connected with the negative input end of the operational amplifier 1131, and the other end of the second filter capacitor 1134 is connected with the output end of the operational amplifier 1131; the operational amplifier 1131 has a negative input terminal and a positive input terminal connected to the charge pump 112, and an output terminal connected to the voltage-controlled oscillator 114.
In a specific implementation, an active filter is used to control the variation current flowing into the voltage range of the voltage-controlled oscillator 114, so as to affect the variation range of a single frequency band of the voltage-controlled oscillator 114, and the variable current is combined with the temperature compensation current type digital-to-analog converter 120 to achieve low frequency gain, so that the noise effect of the phase-locked loop is reduced.
Here, the frequency variation range of the voltage controlled oscillator 114 can be controlled by setting the capacitance area of the current ratio reducing low pass filter including 113 filter, preventing noise from being substituted into the voltage controlled oscillator 114.
Further, referring to fig. 4, a schematic diagram of a charge pump 112 according to an embodiment of the present disclosure is shown based on the low noise phase locked loop 100 with temperature compensation as shown in fig. 1 and 2 for adapting to the differential input of the two current flows of the active filter.
Specifically, the charge pump 112 includes a first charge pump path and a second charge pump path, each of which is composed of a first charge pump switch 1121, a second charge pump switch 1122, a third charge pump switch 1123, and a fourth charge pump switch 1124.
Here, one end of the first charge pump path is connected to the phase frequency detector 111, and the other end is connected to the negative input end of the operational amplifier 1131; one end of the second charge pump path is connected to the phase frequency detector 111, and the other end is connected to the positive input of the operational amplifier 1131.
Further, the first charge pump switch 1121 is connected in series with the second charge pump switch 1122; the third charge pump switch 1123 is connected in series with the fourth charge pump switch 1124; the first charge pump switch 1121 is connected to the third charge pump switch 1123, and the second charge pump switch 1122 is connected to the fourth charge pump switch 1124.
In an implementation, for the first charge pump path, the first charge pump switch 1121 and the third charge pump switch 1123 are connected to the phase frequency detector 111 for receiving DN, DNB control signals; the second charge pump switch 1122 and the fourth charge pump switch 1124 are connected to the phase frequency detector 111, and are used for receiving UP and UPB control signals, and one end of the third charge pump switch 1123 connected to the fourth charge pump switch 1124 is connected to the negative input end of the operational amplifier 1131; one end of the first charge pump switch 1121 connected to the second charge pump switch 1122 is connected to the reference voltage Vref.
Further, for the second charge pump path, the first charge pump switch 1121 and the third charge pump switch 1123 are connected to the phase frequency detector 111, for receiving UP and UPB control signals; the second charge pump switch 1122 and the fourth charge pump switch 1124 are connected to the phase frequency detector 111, and are used for receiving DN and DNB control signals, and one end of the third charge pump switch 1123 connected to the fourth charge pump switch 1124 is connected to the reference voltage Vref; one end of the first charge pump switch 1121 connected to the second charge pump switch 1122 is connected to the positive input of the operational amplifier 1131.
As another possible implementation, the voltage controlled oscillator 114 may be a cross-coupled even-stage ring oscillator. Specific structure may be seen in fig. 5, which is a schematic diagram of a voltage-controlled oscillator 114 according to an embodiment of the disclosure.
The embodiment of the disclosure provides a low noise phase-locked loop with temperature compensation, comprising: a basic phase-locked loop with a voltage-controlled oscillator and a temperature compensated current-type digital-to-analog converter; the temperature compensation current type digital-to-analog converter is connected with a voltage-controlled oscillator in the basic phase-locked loop; the temperature compensation current type digital-to-analog converter is used for adjusting the bit number corresponding to the reference current flowing into the voltage-controlled oscillator according to the bit control of the preset register, and dividing the frequency of the voltage-controlled oscillator into a plurality of different frequency bands according to the bit number. The output frequency range of the phase-locked loop can be maintained while reducing the noise of the phase-locked loop.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system may be implemented in other ways. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
Finally, it should be noted that: the foregoing examples are merely specific embodiments of the present disclosure, and are not intended to limit the scope of the disclosure, but the present disclosure is not limited thereto, and those skilled in the art will appreciate that while the foregoing examples are described in detail, it is not limited to the disclosure: any person skilled in the art, within the technical scope of the disclosure of the present disclosure, may modify or easily conceive changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features thereof; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the disclosure, and are intended to be included within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A low noise phase locked loop with temperature compensation comprising: a basic phase-locked loop with a voltage-controlled oscillator and a temperature compensated current-type digital-to-analog converter;
the temperature compensation current type digital-to-analog converter is connected with the voltage-controlled oscillator in the basic phase-locked loop;
the temperature compensation current type digital-to-analog converter is used for adjusting the bit number corresponding to the reference current flowing into the voltage-controlled oscillator according to the bit control of a preset register, and dividing the frequency of the voltage-controlled oscillator into a plurality of different frequency bands according to the bit number.
2. The low noise phase locked loop with temperature compensation of claim 1, wherein the temperature compensated current mode digital to analog converter comprises: the device comprises a first resistor, a second resistor, a bit control module, a voltage locking module and a positive temperature coefficient current source;
the bit control module is connected in parallel with two ends of the second resistor;
one end of the second resistor is connected with an external voltage source, and the other end of the second resistor is connected to the voltage-controlled oscillator through the voltage locking module;
one end of the first resistor is connected with the positive temperature coefficient current source through the voltage locking module, and the other end of the first resistor is connected to the external voltage source;
the positive temperature coefficient current source is grounded.
3. The low noise phase locked loop with temperature compensation of claim 2, wherein:
the bit control module comprises a plurality of bit control paths, and the bit control paths comprise a third resistor and a switch;
the bit control path is connected in parallel with two ends of the second resistor;
in each of the bit control paths, the third resistor is connected in series with the switch.
4. A low noise phase locked loop with temperature compensation according to claim 3, characterized in that:
the switch is connected to the preset register;
and controlling the switch to be turned on and off through the preset register, so as to adjust the bit number corresponding to the reference current flowing into the voltage-controlled oscillator.
5. The low noise phase locked loop with temperature compensation of claim 2, wherein:
the voltage locking module comprises a first PMOS tube and a second PMOS tube;
the grid electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, the source electrode of the first PMOS tube is connected with the first resistor, and the drain electrode of the first PMOS tube is connected with the positive temperature coefficient current source;
the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the second PMOS tube is connected with the second resistor, and the drain electrode of the second PMOS tube is connected with the voltage-controlled oscillator.
6. The low noise phase locked loop with temperature compensation of claim 1, wherein the base phase locked loop comprises: the circuit comprises a phase frequency detector, a charge pump, a low-pass filter, the voltage-controlled oscillator and a frequency divider;
the phase frequency detector, the charge pump, the low-pass filter and the voltage-controlled oscillator are sequentially connected;
the frequency divider is connected between the output end of the voltage-controlled oscillator and the input end of the phase frequency detector.
7. The low noise phase locked loop with temperature compensation of claim 6, wherein the low pass filter comprises: the circuit comprises an operational amplifier, a filter resistor, a first filter capacitor and a second filter capacitor;
the filter resistor is connected with the first filter capacitor in series;
the first filter capacitor is connected with the positive input end of the operational amplifier, and the filter resistor is connected with the charge pump;
one end of the second filter capacitor is connected with the negative input end of the operational amplifier, and the other end of the second filter capacitor is connected with the output end of the operational amplifier;
and the negative input end and the positive input end of the operational amplifier are connected with the charge pump, and the output end of the operational amplifier is connected with the voltage-controlled oscillator.
8. The low noise phase locked loop with temperature compensation of claim 7, wherein:
the charge pump comprises a first charge pump path and a second charge pump path;
one end of the first charge pump passage is connected with the phase frequency detector, and the other end of the first charge pump passage is connected with the negative input end of the operational amplifier;
one end of the second charge pump passage is connected with the phase frequency detector, and the other end of the second charge pump passage is connected with the positive input end of the operational amplifier.
9. The low noise phase locked loop with temperature compensation of claim 8, wherein:
the first charge pump path and the second charge pump path are formed by a first charge pump switch, a second charge pump switch, a third charge pump switch and a fourth charge pump switch;
the first charge pump switch is connected in series with the second charge pump switch;
the third charge pump switch is connected in series with the fourth charge pump switch;
the first charge pump switch is connected with the third charge pump switch, and the second charge pump switch is connected with the fourth charge pump switch.
10. The low noise phase locked loop with temperature compensation of claim 1, wherein:
the voltage controlled oscillator is a cross-coupled even-stage ring oscillator.
CN202311204723.9A 2023-09-19 2023-09-19 Low-noise phase-locked loop with temperature compensation Active CN116961646B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311204723.9A CN116961646B (en) 2023-09-19 2023-09-19 Low-noise phase-locked loop with temperature compensation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311204723.9A CN116961646B (en) 2023-09-19 2023-09-19 Low-noise phase-locked loop with temperature compensation

Publications (2)

Publication Number Publication Date
CN116961646A true CN116961646A (en) 2023-10-27
CN116961646B CN116961646B (en) 2023-12-15

Family

ID=88447678

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311204723.9A Active CN116961646B (en) 2023-09-19 2023-09-19 Low-noise phase-locked loop with temperature compensation

Country Status (1)

Country Link
CN (1) CN116961646B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040189417A1 (en) * 2003-03-28 2004-09-30 Ken Fujita Oscillator circuit with temperature compensation function
US20100085092A1 (en) * 2008-10-07 2010-04-08 Shin Jong Shin Phase-Locked Loop Integrated Circuits Having Dual Feedback Control
CN201444630U (en) * 2009-07-29 2010-04-28 浪潮电子信息产业股份有限公司 Phase-locked loop circuit with adjustable frequency range
CN102299706A (en) * 2010-06-28 2011-12-28 开曼晨星半导体公司 VCO frequency temperature compensation system for PLLS
US20120013375A1 (en) * 2010-07-15 2012-01-19 Oki Semiconductor Co., Ltd. Frequency synthesizer device and modulation frequency displacement adjustment method
US20210175850A1 (en) * 2019-12-10 2021-06-10 Nxp Usa, Inc. Freqency synthesizer with phase noise temperature compensation, communication unit and method therefor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040189417A1 (en) * 2003-03-28 2004-09-30 Ken Fujita Oscillator circuit with temperature compensation function
US20100085092A1 (en) * 2008-10-07 2010-04-08 Shin Jong Shin Phase-Locked Loop Integrated Circuits Having Dual Feedback Control
CN201444630U (en) * 2009-07-29 2010-04-28 浪潮电子信息产业股份有限公司 Phase-locked loop circuit with adjustable frequency range
CN102299706A (en) * 2010-06-28 2011-12-28 开曼晨星半导体公司 VCO frequency temperature compensation system for PLLS
US20110316595A1 (en) * 2010-06-28 2011-12-29 Mstar Semiconductor, Inc. vco frequency temperature compensation system for plls
US20120013375A1 (en) * 2010-07-15 2012-01-19 Oki Semiconductor Co., Ltd. Frequency synthesizer device and modulation frequency displacement adjustment method
US20210175850A1 (en) * 2019-12-10 2021-06-10 Nxp Usa, Inc. Freqency synthesizer with phase noise temperature compensation, communication unit and method therefor

Also Published As

Publication number Publication date
CN116961646B (en) 2023-12-15

Similar Documents

Publication Publication Date Title
US7554413B2 (en) Voltage controlled oscillator with compensation for power supply variation in phase-locked loop
US7876136B2 (en) Phase-locked-loop circuit having a pre-calibration function and method of pre-calibrating the same
EP1454415B1 (en) Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit
US7312663B2 (en) Phase-locked loop having a bandwidth related to its input frequency
US5748048A (en) Voltage controlled oscillator (VCO) frequency gain compensation circuit
US7268630B2 (en) Phase-locked loop using continuously auto-tuned inductor-capacitor voltage controlled oscillator
US7633347B2 (en) Apparatus and method for operating a phase-locked loop circuit
US7907022B2 (en) Phase-locked loop and method for operating the same
US10623008B2 (en) Reconfigurable fractional-N frequency generation for a phase-locked loop
US7750701B2 (en) Phase-locked loop circuits and methods implementing multiplexer circuit for fine tuning control of digitally controlled oscillators
US20080122546A1 (en) Variable frequency oscillator and communication circuit with it
US20050057313A1 (en) Differential charge pump phase lock loop (PLL) synthesizer with adjustable tuning voltage range
US20080088379A1 (en) Current device and method for phase-locked loop
US5952892A (en) Low-gain, low-jitter voltage controlled oscillator circuit
CN110572150B (en) Clock generation circuit and clock generation method
EP1897221B1 (en) Phase-locked loop systems using adaptive low-pass filters in switched bandwidth feedback loops
WO2006022054A1 (en) Pll frequency synthesizer
CN110999087A (en) Phase-locked loop circuit
US7148758B1 (en) Integrated circuit with digitally controlled phase-locked loop
EP2713518B1 (en) Voltage translation circuit and a voltage-controlled oscillator including the latter
US20060267693A1 (en) VCO digital range selection
CN109586714B (en) Calibrating a voltage controlled oscillator to trim its gain using a phase locked loop and a frequency locked loop
CN116961646B (en) Low-noise phase-locked loop with temperature compensation
US10715158B1 (en) Phase-locked loop (PLL) with calibration circuit
CN109075794B (en) PLL system and operation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant