CN116961413B

CN116961413B - Charge pump circuit

Info

Publication number: CN116961413B
Application number: CN202311202762.5A
Authority: CN
Inventors: 卫梦昭
Original assignee: Hangzhou Shenlian Microelectronics Technology Co ltd
Current assignee: Hangzhou Shenlian Microelectronics Technology Co ltd
Priority date: 2023-09-18
Filing date: 2023-09-18
Publication date: 2024-03-15
Anticipated expiration: 2043-09-18
Also published as: CN116961413A

Abstract

Embodiments of the present disclosure provide a charge pump circuit, comprising: a frequency modulation circuit, an amplitude modulation circuit, a modulation mode switching circuit, a booster circuit, and a feedback control circuit. The frequency modulation circuit generates a clock signal according to the first voltage and the first feedback voltage. The amplitude modulation circuit generates a pumping voltage according to the first voltage and the second feedback voltage. The modulation mode switching circuit controls a frequency lower limit value of the clock signal, and supplies a compensation current to the feedback control circuit when the frequency of the clock signal is equal to the frequency lower limit value. The boost circuit boosts the first voltage according to the clock signal and the pumping voltage to generate an output voltage. The feedback control circuit generates first and second feedback voltages based on the output voltage. When the frequency of the clock signal is higher than the lower frequency limit value, the charge pump circuit achieves a voltage stabilizing state by adjusting the frequency of the clock signal. When the frequency of the clock signal is equal to the lower limit value of the frequency, the charge pump circuit reaches a voltage stabilizing state by adjusting the amplitude of the pumping voltage.

Description

Charge pump circuit

Technical Field

Embodiments of the present disclosure relate to the field of circuit technology, and in particular, to a charge pump circuit.

Background

A charge pump is a circuit capable of providing a voltage higher than a power supply voltage to a system. Compared with an inductive booster circuit, the charge pump occupies smaller area due to the characteristic that the charge pump only needs capacitance, thereby being more economical. However, existing charge pump circuits may have audio noise such that some noise sensitive systems are affected.

Disclosure of Invention

Embodiments described herein provide a charge pump circuit.

According to a first aspect of the present disclosure, a charge pump circuit is provided. The charge pump circuit includes: a frequency modulation circuit, an amplitude modulation circuit, a modulation mode switching circuit, a boost circuit, and a feedback control circuit. Wherein the frequency modulation circuit is configured to: a clock signal is generated based on a first voltage from the first voltage terminal and a first feedback voltage from the feedback control circuit. The amplitude modulation circuit is configured to: a pumping voltage is generated based on the first voltage and a second feedback voltage from the feedback control circuit. The modulation mode switching circuit is configured to: and controlling a frequency lower limit value of the clock signal, and providing a compensation current to the feedback control circuit in case the frequency of the clock signal is equal to the frequency lower limit value. The boost circuit is configured to: the first voltage is boosted according to the clock signal and the pumping voltage to generate an output voltage. The feedback control circuit is configured to: a first feedback voltage and a second feedback voltage are generated from the output voltage. Wherein, in the case that the frequency of the clock signal is higher than the frequency lower limit value, the charge pump circuit reaches the voltage stabilizing state by adjusting the frequency of the clock signal. In the case where the frequency of the clock signal is equal to the frequency lower limit value, the charge pump circuit reaches the voltage-stabilizing state by adjusting the amplitude of the pump-up voltage.

In some embodiments of the present disclosure, the second feedback voltage is lower than the first feedback voltage.

In some embodiments of the present disclosure, in the case where the frequency of the clock signal is higher than the frequency lower limit value, the frequency of the clock signal is proportional to the first voltage difference between the first voltage and the first feedback voltage.

In some embodiments of the present disclosure, a frequency modulation circuit includes: a first error amplifier, and a voltage controlled oscillator. The first input end of the first error amplifier is coupled to the first voltage end. The second input of the first error amplifier is provided with a first feedback voltage. The output end of the first error amplifier is coupled with the input end of the voltage-controlled oscillator. The first error amplifier is configured to: the first voltage difference is amplified to generate a first error voltage. The voltage controlled oscillator is configured to: a clock signal is generated from the first error voltage and provided to the boost circuit. Wherein the frequency of the clock signal is proportional to the first error voltage.

In some embodiments of the present disclosure, a modulation mode switching circuit includes: a first transistor, a second transistor, and a third transistor. The control electrode of the first transistor is coupled with the control electrode of the second transistor, the second electrode of the second transistor and the second electrode of the third transistor. The first pole of the first transistor is coupled to the first pole of the second transistor and the first voltage terminal. The second pole of the first transistor is provided with a second feedback voltage. The control electrode of the third transistor is coupled to the bias voltage terminal. The first pole of the third transistor is coupled to the output terminal of the first error amplifier.

In some embodiments of the present disclosure, the magnitude of the pumping voltage is proportional to a second voltage difference between the first voltage and the second feedback voltage where the frequency of the clock signal is equal to the frequency lower limit value. In the case where the frequency of the clock signal is higher than the frequency lower limit value, the pump-up voltage is equal to the first voltage.

In some embodiments of the present disclosure, an amplitude modulation circuit includes: a second error amplifier, a third error amplifier, and a fourth transistor. The first input end of the second error amplifier is coupled to the first voltage end. The second input of the second error amplifier is provided with a second feedback voltage. The output end of the second error amplifier is coupled with the first input end of the third error amplifier. The second input end of the third error amplifier is coupled with the second pole of the fourth transistor and the boost circuit. The output end of the third error amplifier is coupled with the control electrode of the fourth transistor. The first electrode of the fourth transistor is coupled to the first voltage terminal.

In some embodiments of the present disclosure, a boost circuit includes: a first diode, a second diode, a first capacitor, and an inverter. The anode of the first diode is coupled to the first voltage terminal. The cathode of the first diode is coupled to the anode of the second diode and the first end of the first capacitor. The cathode of the second diode is coupled to the output end of the charge pump circuit. The second end of the first capacitor is coupled with the output end of the inverter. The input of the inverter is provided with a clock signal. The power supply terminal of the inverter is supplied with a pumping voltage.

In some embodiments of the present disclosure, the feedback control circuit includes: a first current source, a first resistor, and a second resistor. Wherein the first current source is configured to generate a first current and provide the first current to the first resistor and the second resistor. The first end of the first resistor is coupled to the output end of the charge pump circuit. The second end of the first resistor is coupled to the first end of the second resistor. The second end of the second resistor is coupled to the first current source. Wherein the voltage at the second end of the first resistor is equal to the first feedback voltage. The voltage at the second end of the second resistor is equal to the second feedback voltage.

According to a second aspect of the present disclosure, a charge pump circuit is provided. The charge pump circuit includes: the first error amplifier, the second error amplifier, the third error amplifier, the voltage-controlled oscillator, the first transistor, the second transistor, the third transistor, the fourth transistor, the first diode, the second diode, the first capacitor, the inverter, the first current source, the first resistor, and the second resistor. The first input end of the first error amplifier is coupled to the first voltage end. The second input terminal of the first error amplifier is coupled to the second terminal of the first resistor. The output end of the first error amplifier is coupled with the input end of the voltage-controlled oscillator. The first error voltage is output from the output terminal of the first error amplifier. The voltage controlled oscillator is configured to: a clock signal is generated from the first error voltage. Wherein the frequency of the clock signal is proportional to the first error voltage. The control electrode of the first transistor is coupled to the control electrode and the second electrode of the second transistor and the second electrode of the third transistor. The first pole of the first transistor is coupled to the first pole of the second transistor and the first voltage terminal. The second pole of the first transistor is coupled to the second end of the second resistor. The control electrode of the third transistor is coupled to the bias voltage terminal. The first pole of the third transistor is coupled to the output terminal of the first error amplifier. The first input terminal of the second error amplifier is coupled to the first voltage terminal. The second input terminal of the second error amplifier is coupled to the second terminal of the second resistor. The output end of the second error amplifier is coupled with the first input end of the third error amplifier. The second input terminal of the third error amplifier is coupled to the second pole of the fourth transistor and the power terminal of the inverter. The output end of the third error amplifier is coupled with the control electrode of the fourth transistor. The first electrode of the fourth transistor is coupled to the first voltage terminal. The anode of the first diode is coupled to the first voltage terminal. The cathode of the first diode is coupled to the anode of the second diode and the first end of the first capacitor. The cathode of the second diode is coupled to the output end of the charge pump circuit. The second end of the first capacitor is coupled with the output end of the inverter. The input end of the inverter is coupled with the output end of the voltage-controlled oscillator. The first current source is configured to generate a first current and provide the first current to the first resistor and the second resistor. The first end of the first resistor is coupled to the output end of the charge pump circuit. The second end of the first resistor is coupled to the first end of the second resistor. The second end of the second resistor is coupled to the first current source.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:

FIG. 1 is an exemplary circuit diagram of an open loop controlled charge pump circuit;

FIG. 2 is an exemplary circuit diagram of a closed loop controlled charge pump circuit;

FIG. 3 is a schematic block diagram of a charge pump circuit according to an embodiment of the present disclosure;

FIG. 4 is an exemplary circuit diagram of a charge pump circuit according to an embodiment of the present disclosure;

FIG. 5 is a graph of switching frequency versus output current for the charge pump circuit shown in FIGS. 2 and 3;

fig. 6 is a comparison of the output voltages of the charge pump circuits shown in fig. 2 and 3.

In the drawings, the last two digits are identical to the elements. It is noted that the elements in the drawings are schematic and are not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.

In all embodiments of the present disclosure, since the source and drain of a Metal Oxide Semiconductor (MOS) transistor are symmetrical and the on-current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control pole and the remaining two terminals of the MOS transistor are referred to as the first pole and the second pole, respectively. In addition, for convenience of unified expression, in the context, the base of a bipolar transistor (BJT) is referred to as a control electrode, the emitter of the BJT is referred to as a first electrode, and the collector of the BJT is referred to as a second electrode. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

The current output capability of a typical charge pump is determined by its switching frequency (switching frequency), the pump up voltage magnitude (pumping voltage amplitude), and the boost capacitance value (flying capacitance). Maximum output current iout_max=f_sw×c_fly×vsup of the charge pump. Where f_sw represents the switching frequency, c_fly represents the boost capacitance value, and Vsup represents the pump-up voltage amplitude. The output voltage ripple (voltagram) of a typical charge pump is mainly determined by the load current (load current), the switching frequency, and the load capacitance (loading capacitance). Output voltage ripple v_ripple=i_load/(f_sw×c_load). Where f_sw represents the switching frequency, i_load represents the load current, and c_load represents the load capacitance value.

An open loop controlled charge pump typically has a fixed switching frequency, pump up voltage amplitude, and boost capacitance, and therefore has a fixed equivalent output impedance and therefore produces a voltage drop at the output that is proportional to the load current. Fig. 1 shows an exemplary circuit diagram of an open loop controlled charge pump circuit 100. In fig. 1, V1 represents a power supply voltage, and V1 is also a start reference of the charge pump circuit 100. C_fly is the boost capacitor. The charge from the power supply voltage V1 is stored when the first diode D1 is forward-turned on, and is output when the second diode D2 is forward-turned on to obtain an output voltage VCP higher than V1. For ease of calculation, assuming that the forward turn-on voltage of the diode is 0V, the output voltage VCP in steady state is equal to v1+vsup. Where Vsup is the supply voltage of inverter NG. And the maximum current that the charge pump circuit 100 can output is calculated as:

Iout_max = f_sw×C_fly×Vsup （1）

Where iout_max represents the maximum output current of the charge pump circuit 100, f_sw represents the frequency of the clock signal CLK (i.e., the switching frequency of the charge pump circuit 100), c_fly represents the capacitance value of the boost capacitor, and Vsup represents the power supply voltage (i.e., the pump-up voltage amplitude) of the inverter NG.

The output impedance of the charge pump circuit 100 is:

Zout = 1/(f_sw×C_fly) （2）

where Zout represents the output impedance of the charge pump circuit 100, f_sw represents the frequency of the clock signal CLK (i.e., the switching frequency of the charge pump circuit 100), and c_fly represents the capacitance value of the boost capacitor.

Therefore, when the output of the charge pump circuit 100 has a load current, the output voltage VCP will drop to:

VCP = V1 + Vsup – Iout×Zout （3）

where V1 represents the power supply voltage of the charge pump circuit 100, iout represents the output current of the charge pump circuit 100, vsup represents the pump up voltage amplitude, and Zout represents the output impedance of the charge pump circuit 100.

If the load current of the charge pump circuit 100 is higher than the maximum output current iout_max, VCP < V1.

The closed-loop control or voltage-stabilizing charge pump (Regulated Charge Pump) can adjust the current output capacity of the charge pump according to the requirement by feeding back the switching frequency, the pumping voltage amplitude or the boosting capacitance value (usually, independently adjusting the switching frequency or the pumping voltage amplitude) in real time, so that the output current and the load current are balanced to achieve the purpose of voltage stabilization. The output voltage ripple at this time is a fixed value and is determined only by the boost capacitance value, the pump-up voltage amplitude, and the load capacitance value.

Among the various control and modulation techniques, frequency modulation techniques generally provide the widest range of adjustment. This is because the switching frequency of the charge pump can be changed by adjusting the output frequency of the Voltage Controlled Oscillator (VCO). However, under light load conditions, the switching frequency of the charge pump may be tuned to the audio range (below 20 KHz). Since the output voltage ripple of the regulated charge pump cannot be reduced by adjusting the switching frequency, if the load capacitance is small, such a regulated charge pump based on frequency modulation only can generate audio noise, so that some systems sensitive to noise are affected.

Fig. 2 shows an exemplary circuit diagram of a closed-loop controlled charge pump circuit 200. The charge pump circuit 200 includes the charge pump circuit 100 shown in fig. 1. The output impedance of the charge pump circuit 200 is modulated by adjusting the output frequency of the voltage controlled oscillator VCO (the frequency of the clock signal CLK). Any variation in the output voltage VCP of the charge pump circuit 200 is sensed through the resistor R1 and sent to the inverting input of the error amplifier A1 to form negative feedback. The current source I1 provides a constant first current I1 for the resistor R1. Due to the negative feedback, if the required output current increases, the output frequency of the VCO will increase to decrease the output impedance of the charge pump circuit 200, thereby achieving the purpose of increasing the output current. In steady state, the output voltage VCP is:

VCP = V1+ I1×R1 （4）

As the load current decreases, the switching frequency continues to decrease without a lower limit until the output current of the charge pump circuit 200 and the load current are balanced. The switching frequency of the charge pump circuit 200 may drop below 20 KHz, thereby affecting some systems that are sensitive to audio noise. The output voltage ripple is:

V_ripple = I_load/(f_sw×C_load)

= Iout/(f_sw×C_load)

= (f_sw×C_fly×Vsup)/(f_sw×C_load)

=C_fly×Vsup/C_load （5）

where V1 represents the supply voltage of the charge pump circuit 100, i_load represents the load current of the charge pump circuit 100, iout represents the output current of the charge pump circuit 100, f_sw represents the frequency of the clock signal CLK (i.e., the switching frequency of the charge pump circuit 100), c_fly represents the capacitance value of the boost capacitor, and c_load represents the load capacitance value.

As can be seen from equation (5) above, in steady state, the output voltage ripple amplitude is independent of the switching frequency and is a fixed value since both Vsup (equal to V1) and c_load are fixed values.

The present disclosure proposes to apply frequency modulation and pump up voltage amplitude modulation (Amplitude Modulation, AM) together to a voltage regulated charge pump, with the assistance of a smooth modulation switching approach to mitigate the effects of the above-mentioned problems. In heavy load conditions, the charge pump employs frequency modulation, while in light load conditions, the charge pump employs amplitude modulation. This ensures that the switching frequency of the charge pump is always higher than the target frequency (e.g., 20 KHz) and that the output voltage ripple is reduced as the pump up voltage amplitude is reduced in the amplitude modulation mode.

Fig. 3 shows a schematic block diagram of a charge pump circuit 300 according to an embodiment of the present disclosure. The charge pump circuit 300 includes: a frequency modulation circuit 320, an amplitude modulation circuit 330, a modulation mode switching circuit 340, a boost circuit 310, and a feedback control circuit 350. The load capacitor C load is also shown in fig. 3. One end of the load capacitor c_load is coupled to the output terminal of the charge pump circuit 300, and the other end of the load capacitor c_load is coupled to the first voltage terminal V1.

The frequency modulation circuit 320 is coupled to the feedback control circuit 350 via the first node N1. The frequency modulation circuit 320 is further coupled to the modulation mode switching circuit 340, the boost circuit 310, and the first voltage terminal V1. The frequency modulation circuit 320 is configured to: the clock signal CLK is generated based on the first voltage V1 from the first voltage terminal V1 and the first feedback voltage Vfb1 from the feedback control circuit 350.

The amplitude modulation circuit 330 is coupled to the feedback control circuit 350 and the modulation mode switching circuit 340 via a second node N2. The amplitude modulation circuit 330 is further coupled to the voltage boost circuit 310 and the first voltage terminal V1. The amplitude modulation circuit 330 is configured to: the pumping voltage Vsup is generated according to the first voltage V1 and the second feedback voltage Vfb2 from the feedback control circuit 350.

The modulation mode switching circuit 340 is coupled to the frequency modulation circuit 320. The modulation mode switching circuit 340 is coupled to the amplitude modulation circuit 330 and the feedback control circuit 350 via the second node N2. The modulation mode switching circuit 340 is configured to: the lower limit value of the frequency of the clock signal CLK is controlled and the compensation current I2' is provided to the feedback control circuit 350 in case the frequency of the clock signal CLK is equal to the lower limit value of the frequency.

The boost circuit 310 is coupled to the frequency modulation circuit 320, the amplitude modulation circuit 330 and the first voltage terminal V1. The output terminal of the boost circuit 310 is coupled to the output terminal of the charge pump circuit 300. The boost circuit 310 is configured to: the first voltage V1 is boosted according to the clock signal CLK and the pumping voltage Vsup to generate the output voltage VCP. The output voltage VCP is output from the output terminal of the charge pump circuit 300. In some embodiments of the present disclosure, the circuit structure of the boost circuit 310 may be the same as the circuit structure of the charge pump circuit 100 in fig. 1.

The feedback control circuit 350 is coupled to the output terminal of the boost circuit 310, the frequency modulation circuit 320, the amplitude modulation circuit 330, and the modulation mode switching circuit 340. The feedback control circuit 350 is configured to: the first feedback voltage Vfb1 and the second feedback voltage Vfb2 are generated according to the output voltage VCP. In some embodiments of the present disclosure, the first feedback voltage Vfb1 and the second feedback voltage Vfb2 are respectively proportional to the output voltage VCP.

In the case where the frequency of the clock signal CLK is higher than the frequency lower limit value, the frequency modulation circuit 320, the booster circuit 310, and the feedback control circuit 350 form a feedback loop, and the charge pump circuit 300 reaches the voltage-stabilized state by adjusting the frequency of the clock signal CLK. At this time, the charge pump circuit 300 is in the frequency modulation mode.

In the frequency modulation mode, in the case where the load current of the charge pump circuit 300 becomes large, the output voltage VCP of the charge pump circuit 300 has a decreasing tendency, and the first feedback voltage Vfb1 follows the decrease. The falling trend of the first feedback voltage Vfb1 is fed back to the frequency modulation circuit 320, so that the frequency modulation circuit 320 speeds up the frequency of the clock signal CLK. In the case where the frequency of the clock signal CLK increases, the output voltage VCP generated by the booster circuit 310 increases, thereby suppressing the falling tendency to reach the voltage-stabilized state. When the load current of the charge pump circuit 300 decreases, the output voltage VCP of the charge pump circuit 300 tends to rise, and the first feedback voltage Vfb1 follows the rise. The rising trend of the first feedback voltage Vfb1 is fed back to the frequency modulation circuit 320, so that the frequency modulation circuit 320 slows down the frequency of the clock signal CLK. In the case where the frequency of the clock signal CLK decreases, the output voltage VCP generated by the booster circuit 310 decreases, thereby suppressing the rising trend to reach the voltage-stabilized state. Since the modulation mode switching circuit 340 controls the lower limit value of the frequency of the clock signal CLK, the frequency of the clock signal CLK does not drop infinitely. When the frequency of the clock signal CLK falls to the frequency lower limit value, the frequency of the clock signal CLK is maintained to the frequency lower limit value.

Fig. 5 shows a plot of switching frequency versus output current for the charge pump circuits shown in fig. 2 and 3. In fig. 5, a solid line shows a relationship between the switching frequency f_sw and the output current Iout of the charge pump circuit shown in fig. 3, and the frequency of the clock signal CLK is maintained at the frequency lower limit value f_min after the frequency of the clock signal CLK is reduced to the frequency lower limit value f_min as the output current Iout is reduced. The dashed line shows the relationship between the switching frequency and the output current of the charge pump circuit shown in fig. 2, and the frequency of the clock signal CLK may eventually decrease to 0 as the output current Iout decreases.

In the case where the frequency of the clock signal CLK is equal to the frequency lower limit value, the amplitude modulation circuit 330, the booster circuit 310, and the feedback control circuit 350 form a feedback loop, and the charge pump circuit 300 reaches the regulated state by adjusting the amplitude of the pumping voltage Vsup. At this time, the charge pump circuit 300 is in the amplitude modulation mode.

In the amplitude modulation mode, in the case where the load current of the charge pump circuit 300 becomes large, the output voltage VCP of the charge pump circuit 300 has a decreasing tendency, and the second feedback voltage Vfb2 follows the decrease. The falling trend of the second feedback voltage Vfb2 is fed back to the amplitude modulation circuit 330, so that the amplitude modulation circuit 330 increases the amplitude of the pumping-up voltage Vsup. In the case where the magnitude of the pump-up voltage Vsup increases, the output voltage VCP generated by the booster circuit 310 increases, thereby suppressing the falling tendency to reach the regulated state. When the load current of the charge pump circuit 300 becomes smaller, the output voltage VCP of the charge pump circuit 300 tends to rise, and the second feedback voltage Vfb2 follows the rise. The rising trend of the second feedback voltage Vfb2 is fed back to the amplitude modulation circuit 330, so that the amplitude modulation circuit 330 reduces the amplitude of the pumping-up voltage Vsup. In the case where the magnitude of the pump-up voltage Vsup decreases, the output voltage VCP generated by the booster circuit 310 decreases, thereby suppressing the rising trend to reach the regulated state.

In the case where the frequency of the clock signal CLK is equal to the frequency lower limit value, the modulation mode switching circuit 340 supplies the compensation current I2' to the feedback control circuit 350, so that the steady-state output voltage VCP in the amplitude modulation mode can be made equal to the steady-state output voltage VCP in the frequency modulation mode. In this way, the charge pump circuit 300 can smoothly switch between the frequency modulation mode and the amplitude modulation mode.

By setting the lower frequency limit to be higher than the audio range (e.g., higher than 20 KHz), the effect of audio noise on a system using the charge pump circuit 300 can be mitigated. Further, according to equation (5), the output voltage ripple v_ripple is proportional to the pumping voltage Vsup. Since the pumping voltage Vsup in the amplitude modulation mode may be lower than the first voltage V1 (power supply voltage), the output voltage ripple v_ripple in the amplitude modulation mode is smaller than that of the charge pump circuit 300 shown in fig. 2. Fig. 6 shows a comparison of the output voltage VCP of the charge pump circuit 300 shown in fig. 2 and 3. In fig. 6, a solid line represents the output voltage VCP of the charge pump circuit 300 shown in fig. 3, and a broken line represents the output voltage VCP of the charge pump circuit 300 shown in fig. 2. It can be seen that the ripple of the output voltage VCP of the charge pump circuit 300 is significantly smaller than the ripple of the output voltage VCP of the charge pump circuit 300.

In some embodiments of the present disclosure, the second feedback voltage Vfb2 is lower than the first feedback voltage Vfb1. In this case, the compensation current I2' is a forward current flowing to the feedback control circuit 350.

In some embodiments of the present disclosure, in the case where the frequency of the clock signal CLK is higher than the frequency lower limit value, the frequency of the clock signal CLK is proportional to the first voltage difference between the first voltage V1 and the first feedback voltage Vfb1. The larger the first voltage difference, the larger the frequency of the clock signal CLK. The smaller the first voltage difference, the smaller the frequency of the clock signal CLK.

In some embodiments of the present disclosure, in case that the frequency of the clock signal CLK is equal to the frequency lower limit value, the magnitude of the pumping voltage Vsup is proportional to the second voltage difference between the first voltage V1 and the second feedback voltage Vfb2. The larger the second voltage difference, the larger the magnitude of the pumping voltage Vsup. The smaller the second voltage difference, the smaller the magnitude of the pumping voltage Vsup. In the case where the frequency of the clock signal CLK is higher than the frequency lower limit value, the pumping voltage Vsup is equal to the first voltage V1.

Fig. 4 shows an exemplary circuit diagram of a charge pump circuit 400 according to an embodiment of the present disclosure. In the example of fig. 4, the feedback control circuit 450 includes: a first current source I1, a first resistor R1, and a second resistor R2. One end of the first current source I1 is coupled to the second end of the second resistor R2 via the second node N2. The other end of the first current source I1 is coupled to the second voltage terminal V2. The first current source I1 is configured to generate a first current I1 and to provide the first current I1 to the first resistor R1 and the second resistor R2. The first current I1 may flow from the first end of the first resistor R1 to the second end (the second node N2) of the second resistor R2. A first terminal of the first resistor R1 is coupled to an output terminal of the charge pump circuit 400. The second end (first node N1) of the first resistor R1 is coupled to the first end of the second resistor R2. The second end of the second resistor R2 is coupled to the first current source I1. Wherein the voltage at the second end of the first resistor R1 is equal to the first feedback voltage Vfb1. The voltage of the second terminal of the second resistor R2 is equal to the second feedback voltage Vfb2.

The frequency modulation circuit 420 includes: a first error amplifier A1, and a voltage controlled oscillator VCO. The first input terminal of the first error amplifier A1 is coupled to the first voltage terminal V1. The second input terminal of the first error amplifier A1 is coupled to the first node N1, thereby being supplied with the first feedback voltage Vfb1. The output of the first error amplifier A1 is coupled to the input of the voltage controlled oscillator VCO. The first error amplifier A1 is configured to: the first voltage difference is amplified to generate a first error voltage Vx. The voltage controlled oscillator VCO is configured to: the clock signal CLK is generated from the first error voltage Vx and supplied to the booster circuit 310. Wherein the frequency of the clock signal CLK is proportional to the first error voltage Vx.

The modulation mode switching circuit 440 includes: a first transistor M1, a second transistor M2, and a third transistor M3. The control electrode of the first transistor M1 is coupled to the control electrode and the second electrode of the second transistor M2 and the second electrode of the third transistor M3. A first pole of the first transistor M1 is coupled to a first pole of the second transistor M2 and the first voltage terminal V1. The second diode of the first transistor M1 is coupled to the second node N2, thereby being provided with the second feedback voltage Vfb2. The control electrode of the third transistor M3 is coupled to the bias voltage terminal Vb. A first pole of the third transistor M3 is coupled to the output of the first error amplifier A1.

The amplitude modulation circuit 430 includes: a second error amplifier A2, a third error amplifier A3, and a fourth transistor M4. The first input terminal of the second error amplifier A2 is coupled to the first voltage terminal V1. The second input terminal of the second error amplifier A2 is coupled to the second node N2, thereby being provided with a second feedback voltage Vfb2. The output terminal of the second error amplifier A2 is coupled to the first input terminal of the third error amplifier A3. The second input terminal of the third error amplifier A3 is coupled to the second pole of the fourth transistor M4 and the boost circuit 310. The voltage at the second pole of the fourth transistor M4 is equal to the pumping voltage Vsup. The output terminal of the third error amplifier A3 is coupled to the gate of the fourth transistor M4. The first pole of the fourth transistor M4 is coupled to the first voltage terminal V1.

The circuit configuration of the booster circuit 310 may be the same as that of the charge pump circuit 100 in fig. 1. Specifically, referring to fig. 1, the boost circuit 310 may include: a first diode D1, a second diode D2, a first capacitor c_fly, and an inverter NG. The anode of the first diode D1 is coupled to the first voltage terminal V1. The cathode of the first diode D1 is coupled to the anode of the second diode D2 and the first end of the first capacitor c_fly. The cathode of the second diode D2 is coupled to the output terminal of the charge pump circuit 400. The second terminal of the first capacitor c_fly is coupled to the output terminal of the inverter NG. The input of the inverter NG is supplied with the clock signal CLK. The power supply terminal of the inverter NG is supplied with the pumping voltage Vsup.

In the example of fig. 4, a high voltage signal is input from a first voltage terminal V1, and a second voltage terminal V2 is grounded. The first transistor M1, the second transistor M2, and the fourth transistor M4 are PMOS transistors. The third transistor M3 is an NMOS transistor. The first input of the first error amplifier A1 is a non-inverting input. The second input of the first error amplifier A1 is an inverting input. The first input of the second error amplifier A2 is a non-inverting input. The second input of the second error amplifier A2 is an inverting input. The first input of the third error amplifier A3 is an inverting input. The second input of the third error amplifier A3 is a non-inverting input. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 4 based on the above inventive concepts are also within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different settings from the example shown in fig. 4.

The operation of the charge pump circuit 400 according to the embodiment of the present disclosure is described below.

In the example of fig. 4, the first error amplifier A1, the voltage controlled oscillator VCO, the boost circuit 310, the first resistor R1, the second resistor R2 and the first current source I1 together constitute a frequency modulated feedback loop. The second error amplifier A2, the third error amplifier A3, the fourth transistor M4, the boost circuit 310, the first resistor R1, the second resistor R2, and the first current source I1 together form an amplitude modulation feedback loop.

In the heavy load, the output voltage VCP may first drop below the target voltage, so that the first feedback voltage Vfb1 and the second feedback voltage Vfb2 drop simultaneously. When the first feedback voltage Vfb1 drops below the first voltage V1, the first error voltage Vx output by the error amplifier A1 increases, causing the third transistor M3 to turn off and the frequency of the clock signal CLK output by the voltage controlled oscillator VCO to increase, thereby decreasing the output impedance of the boost circuit 310, providing more output current to increase and restore VCP to the target voltage. In steady state, the first feedback voltage Vfb1 is equal to the first voltage V1. Meanwhile, since the second feedback voltage Vfb2 is always lower than the first feedback voltage Vfb1, it is also always lower than the first voltage V1. The second error amplifier A2 output is saturated (the second error voltage Vy output by the second error amplifier A2 reaches a maximum value) so that the second error voltage Vy is equal to the first voltage V1. The third error amplifier A3 and the fourth transistor M4 constitute a unit follower such that vsup=v1. Under this condition, the charge pump circuit 400 is in the frequency modulation mode, and the output voltage VCP is represented as:

VCP_FM = V1 + I1×R1 （6）

wherein vcp_fm represents the output voltage VCP in the frequency modulation mode, V1 represents the voltage value of the first voltage V1, I1 represents the current value of the first current I1, and R1 represents the resistance value of the first resistor R1.

When the load current decreases, the output voltage VCP has a rising trend such that the second feedback voltage Vfb2 and the first feedback voltage Vfb1 follow the rising. Since the first feedback voltage Vfb1 is always higher than the second feedback voltage Vfb2, the first feedback voltage Vfb1 will first exceed the first voltage V1, so that the first error voltage Vx output by the first error amplifier A1 is reduced to reduce the frequency of the clock signal CLK. However, due to the presence of the third transistor M3, the maximum current that the first error amplifier A1 can output is limited to the second current I2. The second current I2 is equal to the current flowing through the second transistor M2 and the third transistor M3. At this time, the first error voltage Vx cannot be further reduced due to the third transistor M3, so that the frequency of the clock signal CLK output by the voltage-controlled oscillator VCO reaches the lowest frequency (frequency lower limit value), and thus the charge pump circuit 400 has a lowest switching frequency, denoted as f_min. At this point the frequency modulation feedback loop is destroyed and the amplitude modulation feedback loop begins to operate. Since the charge pump circuit 400 cannot make the switching frequency lower than f_min, the output impedance cannot be further reduced. If the output current provided by the charge pump circuit 400 is still higher than the load current, the output voltage VCP still tends to rise. As the second feedback voltage Vfb2 increases, the second error voltage Vy and the pumping voltage Vsup decrease to limit the amount of charge provided to the output terminal of the charge pump circuit 400 by the first voltage V1 in each switching period, so as to achieve the purpose of reducing the output current. At this time, the charge pump circuit 400 is in the amplitude modulation mode, and the output current Iout can be expressed as:

Iout = C_fly×Vsup×f_min （7）

Where c_fly represents the boost capacitance value, vsup represents the pump-up voltage amplitude, and f_min represents the frequency lower limit of the switching frequency.

Since the first transistor M1 and the second transistor M2 constitute a current mirror, in the amplitude modulation mode, the output current I2' of the first transistor M1 is equal to the second current I2. Thus, the output voltage in amplitude modulation mode is expressed as:

VCP_AM = V1 + (I1-I2)×(R1+R2) （8）

wherein vcp_am represents the output voltage VCP in the amplitude modulation mode, V1 represents the voltage value of the first voltage V1, I1 represents the current value of the first current I1, I2 represents the current value of the second current I2, R1 represents the resistance value of the first resistor R1, and R2 represents the resistance value of the second resistor R2.

By adjusting the numerical proportions of I2, I3, R1 and R2, VCP_AM can be modulated to be equal to VCP_FM. Thus, the output voltage VCP may remain relatively stationary over the full load range.

At this time, in the amplitude modulation mode, the output voltage ripple size is:

V_ripple_AM = C_fly×Vsup/C_load （9）

where Vsup represents the pump-up voltage, c_fly represents the capacitance value of the boost capacitor, and c_load represents the load capacitance value.

Since Vsup may be lower than V1 in the amplitude modulation mode, the output voltage ripple of the charge pump circuit 400 may also be reduced under light load conditions. By setting the amplitude of the bias voltage Vb of the bias voltage terminal Vb, the lower limit value of the first error voltage Vx can be controlled, thereby setting the frequency lower limit value f_min. The lower frequency limit f _ min may be set to a frequency well above 20 KHz so that noise due to output voltage ripple will not occur within the acoustic frequency band.

The operation of the charge pump circuit 400 can be briefly summarized as: when the output voltage VCP is higher than the target voltage, maintaining the voltage-stabilized state by reducing the output current; when the output voltage VCP is lower than the target voltage, the regulated state is maintained by increasing the output current. When it is necessary to reduce the output current, if the switching frequency (the frequency of the clock signal CLK) is higher than the frequency lower limit value, the regulated state is reached by reducing the switching frequency (at this time, the pumping voltage Vsup is equal to the first voltage V1). If the switching frequency (the frequency of the clock signal CLK) is equal to the frequency lower limit value, the regulated state is reached by decreasing the pumping voltage Vsup. When the output current needs to be increased, if the pumping voltage Vsup is smaller than the first voltage V1, the regulated state is reached by increasing the pumping voltage Vsup (at this time, the frequency of the clock signal CLK is equal to the frequency lower limit value). If the pumping voltage Vup is equal to the first voltage V1, the regulated state is achieved by increasing the switching frequency.

In summary, the charge pump circuit according to the embodiment of the present disclosure attenuates noise in the audio range by setting the lower limit value of the switching frequency. In heavy load situations the switching frequency is higher than the lower limit value, the charge pump circuit adopts frequency modulation, and in light load situations the switching frequency is equal to the lower limit value, the charge pump circuit adopts amplitude modulation. The charge pump circuit according to the embodiments of the present disclosure can smoothly switch the frequency modulation mode and the amplitude modulation mode. Further, the output voltage ripple is reduced due to the reduced pump voltage amplitude in the amplitude modulation mode, which is beneficial to maintaining the stability of the output voltage of the charge pump circuit.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A charge pump circuit, the charge pump circuit comprising: a frequency modulation circuit, an amplitude modulation circuit, a modulation mode switching circuit, a booster circuit, and a feedback control circuit,

wherein the frequency modulation circuit is configured to: generating a clock signal according to a first voltage from a first voltage terminal and a first feedback voltage from the feedback control circuit;

the amplitude modulation circuit is configured to: generating a pumping voltage according to the first voltage and a second feedback voltage from the feedback control circuit;

the modulation mode switching circuit is configured to: controlling a frequency lower limit value of the clock signal, and providing a compensation current to the feedback control circuit if the frequency of the clock signal is equal to the frequency lower limit value;

the boost circuit is configured to: boosting the first voltage according to the clock signal and the pump-up voltage to generate an output voltage;

the feedback control circuit is configured to: generating the first feedback voltage and the second feedback voltage according to the output voltage;

wherein the charge pump circuit reaches a voltage-stabilizing state by adjusting the frequency of the clock signal in a case where the frequency of the clock signal is higher than the frequency lower limit value; in the case where the frequency of the clock signal is equal to the frequency lower limit value, the charge pump circuit reaches a stable voltage state by adjusting the magnitude of the pump-up voltage.

2. The charge pump circuit of claim 1, wherein the second feedback voltage is lower than the first feedback voltage.

3. The charge pump circuit of claim 1, wherein the frequency of the clock signal is proportional to a first voltage difference between the first voltage and the first feedback voltage if the frequency of the clock signal is above the frequency lower limit.

4. A charge pump circuit according to claim 3, wherein the frequency modulation circuit comprises: a first error amplifier, and a voltage controlled oscillator,

wherein a first input terminal of the first error amplifier is coupled to the first voltage terminal, a second input terminal of the first error amplifier is provided with the first feedback voltage, an output terminal of the first error amplifier is coupled to an input terminal of the voltage controlled oscillator, and the first error amplifier is configured to: amplifying the first voltage difference to generate a first error voltage;

the voltage controlled oscillator is configured to: the clock signal is generated according to the first error voltage and provided to the boost circuit, wherein the frequency of the clock signal is proportional to the first error voltage.

5. The charge pump circuit of claim 4, wherein the modulation mode switching circuit comprises: a first transistor, a second transistor, and a third transistor,

wherein the control electrode of the first transistor is coupled to the control electrode and the second electrode of the second transistor and the second electrode of the third transistor, the first electrode of the first transistor is coupled to the first electrode and the first voltage terminal of the second transistor, and the second electrode of the first transistor is provided with the second feedback voltage;

the control electrode of the third transistor is coupled to the bias voltage end, and the first electrode of the third transistor is coupled to the output end of the first error amplifier.

6. The charge pump circuit of claim 1, wherein the magnitude of the pump up voltage is proportional to a second voltage difference between the first voltage and the second feedback voltage, where the frequency of the clock signal is equal to the frequency lower limit; in the case where the frequency of the clock signal is higher than the frequency lower limit value, the pump-up voltage is equal to the first voltage.

7. The charge pump circuit of claim 6, wherein the amplitude modulation circuit comprises: a second error amplifier, a third error amplifier, and a fourth transistor,

The first input end of the second error amplifier is coupled with the first voltage end, the second input end of the second error amplifier is provided with the second feedback voltage, and the output end of the second error amplifier is coupled with the first input end of the third error amplifier;

the second input end of the third error amplifier is coupled with the second pole of the fourth transistor and the boost circuit, and the output end of the third error amplifier is coupled with the control pole of the fourth transistor;

the first pole of the fourth transistor is coupled to the first voltage terminal.

8. The charge pump circuit of claim 1, wherein the boost circuit comprises: a first diode, a second diode, a first capacitor, and an inverter,

wherein an anode of the first diode is coupled to the first voltage terminal, and a cathode of the first diode is coupled to an anode of the second diode and a first terminal of the first capacitor;

the cathode of the second diode is coupled with the output end of the charge pump circuit;

a second end of the first capacitor is coupled with an output end of the inverter;

the input terminal of the inverter is supplied with the clock signal, and the power supply terminal of the inverter is supplied with the pumping voltage.

9. The charge pump circuit of claim 1, wherein the feedback control circuit comprises: a first current source, a first resistor, and a second resistor,

wherein the first current source is configured to generate a first current and provide the first current to the first resistor and the second resistor;

a first end of the first resistor is coupled with the output end of the charge pump circuit, and a second end of the first resistor is coupled with a first end of the second resistor;

a second end of the second resistor is coupled to the first current source;

wherein the voltage at the second end of the first resistor is equal to the first feedback voltage and the voltage at the second end of the second resistor is equal to the second feedback voltage.

10. A charge pump circuit, the charge pump circuit comprising: a first error amplifier, a second error amplifier, a third error amplifier, a voltage-controlled oscillator, a first transistor, a second transistor, a third transistor, a fourth transistor, a first diode, a second diode, a first capacitor, an inverter, a first current source, a first resistor, and a second resistor,

The first input end of the first error amplifier is coupled with a first voltage end, the second input end of the first error amplifier is coupled with the second end of the first resistor, the output end of the first error amplifier is coupled with the input end of the voltage-controlled oscillator, and a first error voltage is output from the output end of the first error amplifier;

the voltage controlled oscillator is configured to: generating a clock signal from the first error voltage, wherein a frequency of the clock signal is proportional to the first error voltage;

the control electrode of the first transistor is coupled with the control electrode and the second electrode of the second transistor and the second electrode of the third transistor, the first electrode of the first transistor is coupled with the first electrode of the second transistor and the first voltage end, and the second electrode of the first transistor is coupled with the second end of the second resistor;

a control electrode of the third transistor is coupled with a bias voltage end, and a first electrode of the third transistor is coupled with an output end of the first error amplifier;

the first input end of the second error amplifier is coupled with the first voltage end, the second input end of the second error amplifier is coupled with the second end of the second resistor, and the output end of the second error amplifier is coupled with the first input end of the third error amplifier;

The second input end of the third error amplifier is coupled with the second pole of the fourth transistor and the power supply end of the inverter, and the output end of the third error amplifier is coupled with the control pole of the fourth transistor;

a first pole of the fourth transistor is coupled to the first voltage terminal;

the anode of the first diode is coupled with the first voltage end, and the cathode of the first diode is coupled with the anode of the second diode and the first end of the first capacitor;

the input end of the inverter is coupled with the output end of the voltage-controlled oscillator;

the first current source is configured to generate a first current and provide the first current to the first resistor and the second resistor;

a first end of the first resistor is coupled to the output end of the charge pump circuit, and a second end of the first resistor is coupled to a first end of the second resistor;

a second end of the second resistor is coupled to the first current source.