CN116959987A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN116959987A CN116959987A CN202210409910.XA CN202210409910A CN116959987A CN 116959987 A CN116959987 A CN 116959987A CN 202210409910 A CN202210409910 A CN 202210409910A CN 116959987 A CN116959987 A CN 116959987A
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims abstract description 111
- 238000010438 heat treatment Methods 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 7
- 230000000903 blocking effect Effects 0.000 claims abstract description 7
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 7
- 239000010936 titanium Substances 0.000 claims abstract description 7
- 238000005240 physical vapour deposition Methods 0.000 claims description 15
- 238000000231 atomic layer deposition Methods 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- 239000002070 nanowire Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002135 nanosheet Substances 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- -1 aluminum Chemical class 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate, wherein a plurality of channel layers which are vertically stacked and spaced mutually are formed on the substrate, a dielectric layer and a first barrier layer are sequentially formed on the channel layer, the dielectric layer coats the channel layer, and the first barrier layer coats the dielectric layer; forming a second barrier layer containing silicon, wherein the second barrier layer coats the first barrier layer, and the material of the second barrier layer also comprises one or more of titanium, tantalum or nitrogen; and performing heat treatment to combine the silicon in the second barrier layer with the first barrier layer to play a role of blocking. The characteristic that the second barrier layer is not easy to crystallize and agglomerate can prevent the second barrier layer from closing the channel between the adjacent channel layers in the heat treatment process, thereby solving the problem that residues exist in the interval between the channel layers.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a semiconductor device and a method for fabricating the same.
Background
With the development of technology nodes, GAA (gate all around) structures are beginning to be used for MOS transistors. The nanowire/gate-all-around transistor (Nano sheet/wire-GAA FET) is a key device capable of effectively replacing a FinFET (Fin Field-Effect Transistor, fin Field effect transistor) after a node of 3nm, and capable of remarkably suppressing short channel effect and improving current driving performance of the device.
In the conventional GAA HKMG (high K metal gate) process, a PCA (post high-K capping and annealing) process is required after a-Si deposition to improve reliability. Fig. 1 is a schematic structural view of a semiconductor device, as shown in fig. 1, the semiconductor device includes a substrate 10, on which a plurality of channel layers 20 are formed, which are vertically stacked and spaced apart, the channel layers 20 are sequentially coated with a dielectric layer 21, a barrier layer 22, and an a-Si layer (not shown), and then PCA processing is performed. However, the PCA process can lead to the following problems: 1. since A-Si is crystallized and agglomerated at a high temperature of PCA, si after crystallization and agglomeration is difficult to remove. 2. The spacing between the channel layers 20 is relatively close, and a-Si may remain between the layers after wet etching to remove a-Si, such as a-Si 23 in fig. 1. The A-Si which cannot be removed can lead the corresponding position in the subsequent process to be incapable of being filled with the metal grid, and other structural layers can be damaged if etching is enhanced.
Accordingly, it is necessary to provide a method for fabricating a semiconductor device to solve the problem of residues in the space between the channel layers.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for solving the problem that residues exist in the interval between channel layers.
In order to solve the technical problems, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate, wherein a plurality of channel layers which are vertically stacked and spaced mutually are formed on the substrate, a dielectric layer and a first barrier layer are sequentially formed on the channel layer, the dielectric layer covers the channel layer, and the first barrier layer covers the dielectric layer;
forming a second barrier layer containing silicon, wherein the second barrier layer coats the first barrier layer, and the material of the second barrier layer also comprises one or more of titanium, tantalum or nitrogen; the method comprises the steps of,
and performing heat treatment to combine the silicon in the second barrier layer with the first barrier layer to play a role of blocking.
Optionally, the material of the first barrier layer includes titanium nitride, and the material of the second barrier layer includes titanium silicon nitride.
Optionally, after the heat treatment, the manufacturing method further includes: the second barrier layer is thinned to a desired thickness.
Optionally, before the heat treatment, the manufacturing method further includes: forming a sacrificial layer which covers the substrate and the second barrier layer, and the interval between adjacent channel layers is not filled by the sacrificial layer;
after the heat treatment, the manufacturing method further comprises: and removing the sacrificial layer.
Optionally, the material of the sacrificial layer includes silicon.
Optionally, the sacrificial layer is formed by physical vapor deposition.
Optionally, removing the sacrificial layer by wet etching, wherein the etchant of the wet etching comprises NH 4 OH。
Optionally, the heat treatment comprises a PCA treatment.
Optionally, an atomic layer deposition method is adopted to form the second barrier layer, and an atomic layer etching method is adopted to thin the second barrier layer.
Correspondingly, the invention also provides a semiconductor device which is manufactured by adopting the manufacturing method of the semiconductor device.
The invention provides a semiconductor device and a manufacturing method thereof, wherein a substrate is provided firstly, a plurality of channel layers which are vertically stacked and spaced mutually are formed on the substrate, a dielectric layer and a first barrier layer are sequentially formed on the channel layer, the dielectric layer coats the channel layer, the first barrier layer coats the dielectric layer, then a second barrier layer containing silicon is formed, the second barrier layer coats the first barrier layer, the material of the second barrier layer also comprises one or more of titanium, tantalum or nitrogen, and then heat treatment is carried out, so that silicon in the second barrier layer and the first barrier layer are combined to play a role of blocking. The invention adopts the second barrier layer to replace A-Si in the prior art, the function of the second barrier layer in the semiconductor device is the same as that of the A-Si in the semiconductor device, and the characteristic that the second barrier layer is not easy to crystallize and agglomerate can prevent the second barrier layer from closing the channel between adjacent channel layers in the heat treatment process, thereby solving the problem that residues exist in the interval between the channel layers.
Furthermore, due to the characteristic that the second barrier layer is not easy to crystallize and agglomerate, the generation of residues can be avoided when the second barrier layer is thinned in the follow-up process.
Further, before the heat treatment, a sacrificial layer is formed, and the sacrificial layer covers the substrate and the second barrier layer, so that the second barrier layer can be prevented from being damaged by the subsequent heat treatment. And the sacrificial layer is formed by adopting a physical vapor deposition method, and because the physical vapor deposition method has poor filling capability, gaps between adjacent channel layers are not filled by the sacrificial layer, the sacrificial layer is easier to clean later, so that the residue of the sacrificial layer is avoided. In addition, the vacuum environment provided by the physical vapor deposition method can further protect the second barrier layer from cracking during heat treatment.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation on the scope of the invention.
Fig. 1 is a schematic structure of a semiconductor device.
Fig. 2 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.
Fig. 3 to fig. 4 are schematic structural diagrams illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 5 to 6 are schematic structural diagrams illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
In the context of figure 1 of the drawings,
10-substrate, 20-channel layer, 21-dielectric layer, 22-barrier layer, 23-a-Si;
in the figures 3 to 6 of the drawings,
100-substrate, 200-channel layer, 210-dielectric layer, 220-first barrier layer, 230-second barrier layer, 240-sacrificial layer.
Detailed Description
In the semiconductor device shown in fig. 1, PCA is performed after a-Si deposition, and silicon in a-Si and the barrier layer 22 (preferably, the material of the barrier layer 22 is titanium nitride) combine to play a role in blocking metals such as aluminum, and improve the stability of the film layer of the dielectric layer 21. However, since a-Si is crystallized and agglomerated at a high temperature of PCA, residues are generated in the space between channel layers.
In view of the above, the present invention provides a semiconductor device and a method for fabricating the same.
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or at least two of the feature, either explicitly or implicitly, unless the context clearly dictates otherwise.
Fig. 2 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.
As shown in fig. 2, the method for manufacturing the semiconductor device includes the following steps:
s1: providing a substrate, wherein a plurality of channel layers which are vertically stacked and spaced mutually are formed on the substrate, a dielectric layer and a first barrier layer are sequentially formed on the channel layer, the dielectric layer covers the channel layer, and the first barrier layer covers the dielectric layer;
s2: forming a second barrier layer containing silicon, wherein the second barrier layer coats the first barrier layer, and the material of the second barrier layer also comprises one or more of titanium, tantalum or nitrogen;
s3: and performing heat treatment to combine the silicon in the second barrier layer with the first barrier layer to play a role of blocking.
Fig. 3 to fig. 4 are schematic structural views of steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, and fig. 5 to fig. 6 are schematic structural views of steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. Next, a method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to fig. 2 and fig. 3 to 6.
[ embodiment one ]
In step S1, referring to fig. 3, a substrate 100 is provided, a plurality of vertically stacked channel layers 200 are formed on the substrate 100, a dielectric layer 210 and a first barrier layer 220 are sequentially formed on the channel layers, the dielectric layer 210 wraps the channel layer 200, and the first barrier layer 220 wraps the dielectric layer 210.
The material of the substrate 100 may be silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like, or may be silicon on insulator, germanium on insulator; or may be other materials such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 10 is preferably silicon.
The channel layer 200 may be a nanowire, a nanosheet, or any other shape. The thicknesses of the plurality of channel layers 200 may be the same or different, and the intervals between adjacent channel layers 200 may be the same or different.
The dielectric layer 210 is preferably an HK dielectric layer, and an Interface Layer (IL) may be further formed before the HK dielectric layer is formed, the interface layer covering the channel layer, and the HK dielectric layer covering the interface layer. The material of the Interface Layer (IL) may comprise a material such as silicon nitride, or other suitable material, such as silicon oxynitride. The interfacial layer may be fabricated by chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), or combinations thereof. The HK dielectric layer may be made of tantalum oxide (Ta 2 O 5 ) Strontium titanium oxide (SrTiO) 3 ) Hafnium oxide (HfO) 2 ) Hafnium silicon oxide (HfSiO), zirconium oxide (ZrO 2 ) And the like, hafnium oxide is preferable. The HK dielectric layer may be formed by one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof. In some embodiments, it may be preferable to use ALD, in which a film is grown on a surface by exposing the surface to alternating gaseous species (commonly referred to as precursors). The ALD process has the advantage of forming HK dielectric layers with high uniformity and high accuracy on the substrate surface. The material of the first barrier layer 220 is preferably TiN, but is not limited thereto. The first barrier layer 220 is preferably formed using an Atomic Layer Deposition (ALD), but is not limited thereto.
In one embodiment of the present invention, after the dielectric layer 210 is formed, a heat treatment, preferably a PDA (post High-K deposition anneal post High-K deposition anneal) treatment is performed.
In another embodiment of the present invention, after forming the first barrier layer 220, a heat treatment, preferably a post-metal annealing (PMA) treatment, is performed.
In another embodiment of the present invention, after the dielectric layer 210 is formed, a heat treatment, preferably a PDA treatment, is performed, and after the first barrier layer 220 is formed, a heat treatment, preferably a PMA treatment, is performed.
The PMA process introduces ammonia (NH 3) under the protection of nitrogen (N2), argon (Ar), or helium (He) to improve the interface state characteristics of the first barrier layer 220. Preferably, the PMA treatment comprises a Soak (penetration) stage and a Spike (rapid rise) stage, the temperature of the Soak stage is between 500 ℃ and 700 ℃, and the temperature of the Spike stage is between 700 ℃ and 1000 ℃, but is not limited thereto.
In step S2, referring to fig. 4, a second barrier layer 230 containing silicon is formed, the second barrier layer 230 encapsulates the first barrier layer 220, and the material of the second barrier layer 230 further includes one or more of titanium, tantalum or nitrogen.
The material of the second barrier layer 230 may further include one or more of titanium, tantalum or nitrogen in addition to silicon, and the material is characterized by being not easy to crystallize and agglomerate after the heat treatment. In this embodiment, the material of the second barrier layer 23 preferably includes, but is not limited to, titanium silicon nitride (TiSiN).
In step S3, please continue to refer to fig. 4, a heat treatment is performed to combine the silicon in the second barrier layer 230 with the first barrier layer 220 to perform a blocking function.
In this example, the heat treatment is PCA (post high-K capping and annealing) and the high-K capping and annealing is performed. The PCA treatment was performed under nitrogen (N) 2 ) Argon (Ar), oxygen (O) 2 ) Or under an atmosphere of a protective gas such as helium (He). Preferably, the PCA treatment includes a Soak (penetration) stage having a temperature between 500 ℃ and 700 ℃ and a Spike (rapid rise) stage having a temperature between 700 ℃ and 1000 ℃, but is not limited thereto.
The second barrier layer 230 is subjected to the heat treatment, and the silicon therein combines with the first barrier layer 220 to perform a barrier function, for example, a barrier function to metal in a subsequently formed metal gate, mainly a barrier function to aluminum. And, the stability of the dielectric layer 210 film layer can be improved and the reliability of the semiconductor device can be improved through the heat treatment. In the present invention, the second barrier layer 230 is used to replace a-Si in the prior art, the function of the second barrier layer 230 in the semiconductor device is the same as that of the a-Si in the semiconductor device, and the characteristic that the second barrier layer 230 is not easy to crystallize and agglomerate can prevent the second barrier layer 230 from closing the channel between adjacent channel layers 20 during the heat treatment process, thereby solving the problem that residues exist in the interval between the channel layers 20 in the prior art, and preventing the electrical property of the semiconductor device from being difficult to reach the standard or from being excessively fluctuated.
In addition, the material of the second barrier layer 230 is titanium nitride, the material of the first barrier layer 220 is titanium nitride, and in the semiconductor device, titanium nitride may replace a part of titanium nitride, so that the thickness of titanium nitride is reduced, thereby reducing the budget of the heat treatment, where the heat treatment refers to the heat treatment performed after the first barrier layer 220 is formed.
In this embodiment, in order to avoid the second barrier layer 230 from being damaged during the heat treatment, in step S2, the thickness of the second barrier layer 230 is formed to be greater than the actual required thickness.
Therefore, in this embodiment, after the heat treatment, the manufacturing method further includes: the second barrier layer 230 is thinned to a desired thickness. The second barrier layer 230 may be uniformly thinned to a desired thickness using an Atomic Layer Etching (ALE), but is not limited thereto. Because the second barrier layer 230 is not easy to crystallize and agglomerate, the occurrence of residues can be avoided when the second barrier layer 230 is thinned.
[ example two ]
In comparison with the first embodiment, the thickness of the second barrier layer does not need to be thinned.
In this embodiment, after executing step S2, before executing step S3, the manufacturing method further includes: a sacrificial layer is formed covering the substrate and the second barrier layer, and gaps between adjacent channel layers are not filled by the sacrificial layer. After executing step S3, the manufacturing method further includes: and removing the sacrificial layer.
Specifically, referring to fig. 5, a sacrificial layer 240 is formed, the sacrificial layer 240 covers the substrate 100 and the second barrier layer 230, and the gap between the adjacent channel layers 200 is not filled with the sacrificial layer 240.
In this embodiment, the material of the sacrificial layer 240 is preferably silicon, but is not limited thereto. The sacrificial layer 240 may be formed using physical vapor deposition (Physical Vapor Deposition, PVD), although other methods known to those skilled in the art may be used to form the sacrificial layer 240.
The sacrificial layer 240 covers the second barrier layer 230, and protects the second barrier layer 230, so as to prevent damage to the second barrier layer 230 caused by subsequent heat treatment. Therefore, in this embodiment, the thickness of the second barrier layer 230 is not excessively thick, and only the thickness of the second barrier layer 230 needs to be brought to a desired thickness after the heat treatment, and a thinning step is not required.
Because of the poor filling capability of the physical vapor deposition method, the sacrificial layer 240 may not fill the space between adjacent channel layers 200 while covering the second barrier layer 230, or may slightly fill the space between adjacent channel layers 200, so that the sacrificial layer 240 may be more easily removed later. And the second barrier layer 230 may be further protected from cracking during a subsequent heat treatment due to the vacuum environment provided by the physical vapor deposition method.
The step of removing the sacrificial layer is shown in fig. 6, and the sacrificial layer 240 is removed.
The sacrificial layer 240 is preferably removed by a wet etching process, and the etchant of the wet etching process includes NH 4 OH solution, but is not limited thereto. Since the sacrificial layer 240 has poor filling ability, and does not fill the space between the channel layers 200, the wet etching process easily cleans the sacrificial layer 240 and does not remain in the space between the channel layers 200.
Correspondingly, the invention also provides a semiconductor device which is manufactured by adopting the manufacturing method of the semiconductor device.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. A method of fabricating a semiconductor device, comprising the steps of:
providing a substrate, wherein a plurality of channel layers which are vertically stacked and spaced mutually are formed on the substrate, a dielectric layer and a first barrier layer are sequentially formed on the channel layer, the dielectric layer covers the channel layer, and the first barrier layer covers the dielectric layer;
forming a second barrier layer containing silicon, wherein the second barrier layer coats the first barrier layer, and the material of the second barrier layer also comprises one or more of titanium, tantalum or nitrogen; the method comprises the steps of,
and performing heat treatment to combine the silicon in the second barrier layer with the first barrier layer to play a role of blocking.
2. The method of claim 1, wherein the material of the first barrier layer comprises titanium nitride and the material of the second barrier layer comprises titanium silicon nitride.
3. The method for manufacturing a semiconductor device according to claim 2, wherein after the heat treatment is performed, the method further comprises: the second barrier layer is thinned to a desired thickness.
4. The method for manufacturing a semiconductor device according to claim 2, wherein before the heat treatment is performed, the method further comprises: forming a sacrificial layer which covers the substrate and the second barrier layer, and the interval between adjacent channel layers is not filled by the sacrificial layer;
after the heat treatment, the manufacturing method further comprises: and removing the sacrificial layer.
5. The method of manufacturing a semiconductor device according to claim 4, wherein the material of the sacrificial layer comprises silicon.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the sacrificial layer is formed by physical vapor deposition.
7. The method of manufacturing a semiconductor device according to claim 5, wherein the sacrificial layer is removed by wet etching, and an etchant of the wet etching includes NH 4 OH。
8. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment comprises a PCA treatment.
9. The method of manufacturing a semiconductor device according to claim 3, wherein the second barrier layer is formed by an atomic layer deposition method, and the second barrier layer is thinned by an atomic layer etching method.
10. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to any one of claims 1 to 9.
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