CN116954715A - Transplanting method and device of processor platform, electronic equipment and medium - Google Patents
Transplanting method and device of processor platform, electronic equipment and medium Download PDFInfo
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Abstract
The invention relates to the technical field of embedded software, discloses a method and a device for transplanting a processor platform, electronic equipment and a medium, and provides a method for transplanting the processor platform, which is applied to a MicroBlaze platform and comprises the following steps: obtaining module information of a target hard core processor based on embedded engineering on a ZYNQ platform, and further determining a function to be added to a soft core processor; identifying a function type of the function to be added in the target hard core processor; if the function to be added is the main function of the target hard core processor, performing first function configuration on the soft core processor by adopting a first configuration strategy to obtain the target soft core processor; converting the first running code of the embedded engineering into a second running code; if the target soft core processor can normally operate according to the second operation code, the success of the embedded engineering transplanting is determined, and the purpose of transplanting the embedded engineering from the ZYNQ platform to the MicroBlaze platform is achieved.
Description
Technical Field
The invention relates to the technical field of embedded software, in particular to a method and a device for transplanting a processor platform, electronic equipment and a medium.
Background
A field programmable gate array (Field Programmable Gate Array, FPGA) is a programmable logic device that can be programmed to implement different digital circuit functions. Wherein the FPGA comprises a soft core processor (System on a Programmable Chip, SOPC) and a hard core processor. A soft core processor refers to a configurable processor implemented inside an FPGA chip. A hard core processor refers to a processor of fixed function implemented inside an FPGA chip.
In the related art, due to different application scenarios of the hard core processor and the soft core processor, the processor architecture of the hard core processor platform and the processor architecture of the soft core processor platform are different, and the configuration flow is different, so that the case that the hard core processor platform is successfully applied cannot be re-engraved on the soft core processor platform, and the research and development design period of the FPGA is long.
In view of this, the present invention provides a method for transplanting a processor platform, so as to improve the functions that can be implemented by a soft core processor platform, and further shorten the development and design cycle of FPGA.
Disclosure of Invention
In view of the above, the present invention provides a method, an apparatus, an electronic device, and a medium for transplanting a processor platform, so as to solve the problem of longer development and design period of FPGA.
In a first aspect, the present invention provides a method for transplanting a processor platform, applied to a MicroBlaze platform, the method comprising:
obtaining module information of a target hard core processor based on embedded engineering on a ZYNQ platform, wherein the ZYNQ platform is a processor platform of the target hard core processor;
determining a function to be added to the soft core processor based on a comparison result between a first target function corresponding to the module information and a second target function to be executed by the soft core processor;
identifying a function type of the function to be added in the target hard core processor;
if the function to be added is the main function of the target hard core processor, performing first function configuration on the soft core processor by adopting a first configuration strategy to control the soft core processor to realize the function to be added, so as to obtain the target soft core processor;
converting the first operation code of the embedded engineering into a second operation code, wherein the second operation code is used for controlling the operation of the target soft core processor;
and if the target soft core processor can normally operate according to the second operation code, determining that the embedded engineering transplanting is successful.
In this mode, can carry out the pertinence configuration to MicroBlaze platform based on the functional difference between MicroBlaze platform and the ZYNQ platform to realize transplanting the embedded engineering from the ZYNQ platform to the purpose of MicroBlaze platform, and then be favorable to promoting the development performance of MicroBlaze platform, thereby help shortening the research and development design cycle length of FPGA.
In an alternative embodiment, a first configuration policy is used to perform a first function configuration on the soft core processor, so as to control the soft core processor to implement a function to be added, so as to obtain a target soft core processor, including:
creating and configuring a first intellectual property core, wherein the first intellectual property core is the intellectual property core corresponding to the main body function in the second target function and comprises a first data transmission interface corresponding to the first intellectual property core;
adding a target functional module, wherein the target functional module is a functional module corresponding to the function to be added;
configuring a target function module according to configuration parameters of the function to be added in the embedded engineering;
and responding to the completion of the configuration of the first intellectual property core and the target functional module to obtain the target soft core processor.
In this manner, the main structure of the soft core processor can be configured in a targeted manner based on the difference between the first target function and the second target function, so that the main structure of the obtained target soft core processor can realize the main function which can be executed by the target hard core processor, and further realize targeted re-etching, thereby helping to ensure the transplanting effectiveness of the embedded engineering.
In an alternative embodiment, the method further comprises:
and adding a bus controller to be respectively connected with a bus interface of the soft core processor, the first data transmission interface and the target functional module.
In an alternative embodiment, if the function to be added further includes a peripheral function of the target hard core processor, before obtaining the target soft core processor, the method further includes:
and performing second function configuration on the soft core processor by adopting a second configuration strategy so as to control the soft core processor to realize peripheral functions.
In the mode, different configuration strategies can be adopted for aiming at different functions to carry out targeted configuration on the soft core processor, so that repeated development can be effectively avoided, and the time and labor consumption of project development can be greatly reduced.
In an alternative embodiment, the second functional configuration of the soft-core processor using the second configuration policy includes:
determining a second intellectual property core corresponding to the peripheral function in the MicroBlaze platform;
acquiring a target constraint strategy for controlling the second intellectual property core;
the second intellectual property core is configured based on the target constraint policy to perform a second functional configuration on the soft core processor.
In an alternative embodiment, the target constraint policy includes a target physical constraint policy and/or a target timing constraint policy; configuring the second intellectual property core based on the target constraint policy to perform a second functional configuration of the soft core processor, comprising:
Determining a physical pin pair corresponding to the second intellectual property core in the soft core processor according to the target physical constraint strategy, wherein the physical pin pair comprises an input pin and an output pin;
binding an input port of the second intellectual property core with an input pin, and binding an output port of the second intellectual property core with an output pin;
and/or configuring the operation time sequence of the second intellectual property core according to the target time sequence constraint strategy.
In this way, the problem that the MicroBlaze platform has no integrated peripheral function can be solved.
In an alternative embodiment, the method further comprises:
if the number of the peripheral functions is a plurality of, adding a third intellectual property core, wherein the third intellectual property core is used for merging interrupt requests of a plurality of second intellectual property cores.
In an alternative embodiment, before obtaining the target soft-core processor, the method further comprises:
autonomous write logic of the target hard core processor is migrated to the soft core processor.
In a second aspect, the present invention provides a migration apparatus for a processor platform, for use with a MicroBlaze platform, the apparatus comprising:
the first determining module is used for obtaining module information of the target hard core processor through embedded engineering on the ZYNQ platform, wherein the ZYNQ platform is a processor platform of the target hard core processor;
The second determining module is used for determining a function to be added to the soft core processor based on a comparison result between the first target function corresponding to the module information and a second target function to be executed by the soft core processor;
the identification module is used for identifying the function type of the function to be added in the target hard core processor;
the first configuration module is used for carrying out first function configuration on the soft core processor by adopting a first configuration strategy if the function to be added is the main function of the target hard core processor so as to control the soft core processor to realize the function to be added and obtain the target soft core processor;
the conversion module is used for converting the first operation code of the embedded engineering into a second operation code, and the second operation code is used for controlling the operation of the target soft core processor;
and the detection module is used for determining that the embedded engineering transplanting is successful if the target soft core processor can normally operate according to the second operation code.
In a third aspect, the present invention provides an electronic device, comprising: the processor executes the computer instructions, thereby executing the migration method of the processor platform according to the first aspect or any implementation manner corresponding to the first aspect.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the migration method of the processor platform of the first aspect or any one of its corresponding embodiments.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow diagram of a migration method for a processor platform according to an embodiment of the present invention;
FIG. 2 is a flow chart of a migration method of another processor platform according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the main structure of an FPGA according to an embodiment of the present invention;
FIG. 4 is a flow chart of a migration method of a further processor platform according to an embodiment of the present invention;
FIG. 5 is a block diagram of a migration apparatus of a processor platform according to an embodiment of the present invention;
Fig. 6 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the related art, due to different application scenarios of the hard core processor and the soft core processor, the processor architecture of the hard core processor platform and the processor architecture of the soft core processor platform are different, and the configuration flow is different, so that the case that the hard core processor platform is successfully applied cannot be re-engraved on the soft core processor platform, and the research and development design period of the FPGA is long.
In view of this, an embodiment of the present invention provides a method for transplanting a processor platform, applied to a MicroBlaze platform, where the method includes: obtaining module information of a target hard core processor based on embedded engineering on a ZYNQ platform, wherein the ZYNQ platform is a processor platform of the target hard core processor; determining a function to be added to the soft core processor based on a comparison result between a first target function corresponding to the module information and a second target function to be executed by the soft core processor; identifying a function type of the function to be added in the target hard core processor; if the function to be added is the main function of the target hard core processor, performing first function configuration on the soft core processor by adopting a first configuration strategy to control the soft core processor to realize the function to be added, so as to obtain the target soft core processor; converting the first operation code of the embedded engineering into a second operation code, wherein the second operation code is used for controlling the operation of the target soft core processor; and if the target soft core processor can normally operate according to the second operation code, determining that the embedded engineering transplanting is successful. The transplanting method of the processor platform can be used for carrying out targeted configuration on the MicroBlaze platform based on the functional difference between the MicroBlaze platform and the ZYNQ platform so as to realize the purpose of transplanting embedded engineering from the ZYNQ platform to the MicroBlaze platform, thereby being beneficial to improving the development performance of the MicroBlaze platform and being beneficial to shortening the research and development design cycle of the FPGA.
In accordance with an embodiment of the present invention, there is provided a migration method embodiment of a processor platform, it should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.
In this embodiment, a method for transplanting a processor platform is provided, which may be used for the MicroBlaze platform described above, and fig. 1 is a flowchart of a method for transplanting a processor platform according to an embodiment of the present invention, as shown in fig. 1, where the flowchart includes the following steps:
step S101, obtaining module information of a target hard core processor based on embedded engineering on a ZYNQ platform.
In the embodiment of the invention, the ZYNQ platform is a processor platform of a target hard core processor. In order to ensure the transplanting effectiveness of the processor platform, according to the embedded engineering on the ZYNQ platform, a first target function executable by the target hard core processor is analyzed, and then a functional module corresponding to the first target function is determined, so that module information of the target hard core processor is obtained. For example, the target hard core processor may be any of the ARM family of processors. The target hard core processor may be a single core processor or a multi-core processor, and is not limited in the present invention.
Step S102, determining a function to be added to the soft-core processor based on a comparison result between the first target function corresponding to the module information and the second target function to be executed by the soft-core processor.
In the embodiment of the invention, the first target function corresponding to the module information is compared with the second target function to be executed by the soft core processor, so that the difference between the first target function and the second target function is clear, and a comparison result is obtained. Since there is a functional difference between the target hard core processor and the soft core processor, the function to be added to the soft core processor can be determined by comparing the results.
Step S103, identifying the function type of the function to be added in the target hard core processor.
In an embodiment of the present invention, the first target function includes a plurality of sub-functions. In order to facilitate targeted migration, the multiple sub-functions are pre-function-type-classified. The function type includes a main body function or a peripheral function. Namely, the functions realized by the main body module of the target hard core processor are divided into main body functions; the functionality implemented by the second intellectual property core of the target hardcore processor is divided into peripheral functions. In order to determine the function type of the function to be added, the function type is identified so as to carry out targeted configuration on the MicroBlaze platform later. For example: the type of function in the target hardcore processor to be added may be identified by a configuration file. The configuration file comprises a first list and a second list, wherein the first list comprises a plurality of first sub-functions belonging to the main body function, and the second list comprises a plurality of second sub-functions belonging to the peripheral function. And respectively matching the function to be added with the plurality of first sub-functions or the plurality of second sub-functions to obtain a matching result. If the plurality of first sub-functions include the function to be added, determining that the function type of the function to be added is a main function. If the plurality of second sub-functions comprise functions to be added, determining that the function type of the functions to be added is a peripheral function. Wherein the list is merely a cluster expression for illustrating the plurality of first sub-functions or the plurality of second sub-functions, and is not limited in the present invention.
Step S104, if the function to be added is the main function of the target hard core processor, performing a first function configuration on the soft core processor by adopting a first configuration strategy to control the soft core processor to realize the function to be added, thereby obtaining the target soft core processor.
In the embodiment of the present invention, the first configuration policy may be understood as a policy for performing targeted configuration on the main body of the soft core processor. When the function to be added is identified as the main function of the target hard core processor, the second target function of how the processor needs to be regulated is characterized, so that a first configuration strategy is adopted to perform first function configuration on the soft core processor so as to control the soft core processor to realize the function to be added, and the target soft core processor is obtained.
Step S105, converting the first running code of the embedded project into the second running code.
In the embodiment of the invention, the first running code of the embedded engineering is a code for controlling the running of the target hard core processor, and the code cannot be directly transplanted to the MicroBlaze platform to control the running of the soft core processor. Thus, to enable the target soft-core processor to copy the first target function executable by the target hard-core processor, the first execution code is further converted into the second execution code to control the target soft-core processor to execute via the second execution code.
And step S106, if the target soft core processor can normally operate according to the second operation code, determining that the embedded engineering transplanting is successful.
In the embodiment of the invention, if the target soft core processor can normally operate according to the second operation code, the target soft core processor obtained after the characterization configuration can realize the first target function of the target hard core processor in the operation process, so that the embedded engineering can be determined to be successfully transplanted to the MicroBlaze platform from the ZYNQ platform, and the target soft core processor developed by the MicroBlaze platform can realize the first target function executable by the target hard core processor.
The transplanting method of the processor platform can be used for carrying out targeted configuration on the MicroBlaze platform based on the functional difference between the MicroBlaze platform and the ZYNQ platform so as to achieve the purpose of transplanting embedded engineering from the ZYNQ platform to the MicroBlaze platform, and further is beneficial to improving the development performance of the MicroBlaze platform, thereby being beneficial to shortening the research and development design cycle of the FPGA.
In some alternative implementation scenarios, the process of converting the first running code of the embedded project into the second running code may be as follows:
And modifying the function corresponding relation in the embedded engineering code to accurately map the function corresponding relation to the address space of each module of the MicroBlaze platform. For example: and replacing the drive file of the ZYNQ platform with the drive file of the MicroBlaze platform. Taking a UART module as an example, the file name of a drive library of the ZYNQ platform is "uartps", and the drive library is required to be changed into "xuartite" so as to form a drive file applicable to the MicroBlaze platform, so that the UART module can find out the corresponding drive file in the process of executing read-write operation.
The method also comprises the step of replacing the macro definition name of the device of the ZYNQ platform by the macro definition name of the device of the MicroBlaze platform, and mainly naming of each peripheral module. Taking a UART module as an example, the prefix of the device name of the ZYNQ platform is 'XPAR_PS7_UART_', and the device name of the ZYNQ platform needs to be changed into 'XPAR_AXI_UART_' so as to be applicable to the MicroBlaze platform, thereby ensuring that the UART module can find out a corresponding register when performing read-write operation.
In addition, the re-writing is directly removed for interrupt module related code. Because the soft core interrupt controller 'AXI Interrupt Controller' IP core of the MicroBlaze platform and the hard core interrupt controller ScuGic of the ZYNQ platform are huge in difference, the interrupt exception numbers of the processors for asynchronous events are different, and the hardware logic of the interrupts is greatly different. The handling of interrupt events is particularly critical to the proper functioning of the processor, and therefore, the associated code is preferably redeveloped according to the interrupt controller (Interrupt Controller, INTC) of the MicroBlaze platform interrupt driven library.
In this embodiment, a method for transplanting a processor platform is provided, which may be used for the MicroBlaze platform described above, and fig. 2 is a flowchart of a method for transplanting a processor platform according to an embodiment of the present invention, as shown in fig. 2, where the flowchart includes the following steps:
step S201, obtaining module information of a target hard core processor based on embedded engineering on a ZYNQ platform. Please refer to step S101 in the embodiment shown in fig. 1 in detail, which is not described herein.
Step S202, determining a function to be added to the soft-core processor based on a comparison result between the first target function corresponding to the module information and the second target function to be executed by the soft-core processor. Please refer to step S102 in the embodiment shown in fig. 1 in detail, which is not described herein.
In step S203, the function type of the function to be added in the target hard core processor is identified. Please refer to step S103 in the embodiment shown in fig. 1 in detail, which is not described herein.
In step S204, if the function to be added is the main function of the target hard core processor, the soft core processor is configured with the first function by adopting the first configuration policy to control the soft core processor to realize the function to be added, so as to obtain the target soft core processor.
Specifically, the step S204 includes:
step S2041, creating and configuring a first intellectual property core, includes configuring a first data transmission interface corresponding to the first intellectual property core.
In an embodiment of the present invention, the first intellectual property core is an intellectual property core (Intellectual Property core, IP core) corresponding to the subject function in the second target function. In order to ensure that a target soft core processor developed by the MicroBlaze platform can work normally, a first intellectual property core is preferably created and configured.
In creating and configuring the first intellectual property core, the creation may be based on the intellectual property core provided by the default subject template. In the configuration process, in order to ensure that the data can be effectively transmitted, the method further comprises configuring a first data transmission interface corresponding to the first intellectual property core. The first data transmission interface may be a data interface supporting data transmission of a specified bus type. For example: if the specified bus type is a bus supported by the AXI (Advanced eXtensible Interface) protocol, the first data transfer interface may be an enabled peripheral AXI data interface.
In some examples, in the configuring, configuring further comprises configuring the following parameters: processor bit width (e.g., 32 bits), debug enabled (Debug) module, determination of bus type (e.g., select an AXI protocol supported bus as the bus for data transfer), enable local store bus instruction interface, and data interface.
In step S2042, a target function module is added.
In the embodiment of the invention, the target function module is a function module corresponding to the main body function to be added. In order to ensure that the main body function executable by the target soft core processor obtained later can cover the main body function executable by the target hard core processor, a target function module is added in the process of configuring the main body structure of the soft core processor, so that the main body function of the target hard core processor can be realized in the running process of the target soft core processor obtained later.
For example: the target hard core processor is controlled by a clock module in the running process, and the clock module is one of functional modules corresponding to the main body functions of the target hard core processor. Therefore, for the main function of the copy target hard core processor, the added target functional module may be a clock generation module instead of a clock module integrated at the ZYNQ platform Processing System (PS) end. Specifically, the target functional module may be a clock IP core (clock Wizard), and may combine with a clock source provided by a crystal oscillator clock of the board card to add a clock function to a main function of the soft core processor.
Step S2043, configuring the target function module according to the configuration parameters of the function to be added in the embedded engineering.
In the embodiment of the invention, in order to ensure that the working state of the target functional module in the soft core processor can be consistent with the working state in the target soft core processor, the target functional module is configured according to the configuration parameters of the function to be added in the embedded engineering so as to control the target functional module by adopting the same control strategy.
In some alternative implementation scenarios, if the target functional module is a clock generation module, the configuration parameters may include: frequency reset duty cycle, configuration mode, configuration interface, etc. In the process of configuring the target functional module, the configuration can be performed manually, or the external input clock can be accessed through the connecting wire of the mini type A version connector (SubMiniature version A, SMA).
And step S2044, responding to the completion of the configuration of the first intellectual property core and the target functional module, and obtaining the target soft core processor.
In the embodiment of the invention, when the configuration of the first intellectual property core and the target functional module is completed, the configuration of the soft core processor is characterized to be completed, and then the target soft core processor is obtained.
By adopting the mode, the main body structure of the soft core processor can be configured in a targeted manner based on the difference between the first target function and the second target function, so that the main body structure of the obtained target soft core processor can realize the main body function which can be executed by the target hard core processor, and further, the targeted re-etching is realized, and the transplanting effectiveness of the embedded engineering is guaranteed.
Step S205, converting the first running code of the embedded project into the second running code. Please refer to step S105 in the embodiment shown in fig. 1 in detail, which is not described herein.
Step S206, if the target soft core processor can normally operate according to the second operation code, the success of the embedded engineering transplanting is determined. Please refer to step S106 in the embodiment shown in fig. 1 in detail, which is not described herein.
According to the transplanting method of the processor platform, the main body structure of the soft core processor can be configured in a targeted mode based on the difference between the first target function and the second target function, so that the main body function which can be achieved by the obtained target soft core processor can cover the main body function which can be achieved by the target hard core processor, and further when the target soft core processor can normally operate according to the second operation code, the success of embedded engineering transplanting can be determined, the obtained target soft core processor can carry out targeted re-etching on the function which can be achieved by the target hard core processor, and therefore development performance of the MicroBlaze platform can be improved, and the development and design period of the FPGA can be shortened.
In some optional embodiments, the step S204 further includes: and adding a bus controller to be respectively connected with a bus interface of the soft core processor, the first data transmission interface and the target functional module. In the MicroBlaze platform, in order to ensure that data can be effectively transmitted between each other, therefore, the bus controller is highly dependent, and the embedded engineering of the ZYNQ platform may not include bus control, so that the bus controller is added to ensure that the generated or received data can be effectively transmitted in the running process of the target soft core processor. The bus controller may be understood as a data transmission hub where the soft core processor performs data transmission with other intellectual property cores or functional modules. The bus controller can be a newly added intellectual property core or can be obtained through added peripheral post-software. For example: if an intellectual property core is added, the bus controller may be an AXI Interconnect (an intellectual property core for connecting a plurality of AXI buses); if obtained by adding peripheral IP core back software, the bus controller may be axismartconnect (a layered intellectual property block in an integrated design suite).
In some alternative implementation scenarios, a schematic diagram of the main structure of the FPGA of the main structure of the configured target soft-core processor may be shown in fig. 3. Taking the bus type designated as the bus supported by AXI protocol (hereinafter referred to as AXI bus as an example), in the main structure of FPGA, the following submodules are included: the system comprises a target soft core processor, a clock generation module, a bus controller (AXI Interconnect), an interrupt controller (AXI Interrupt Controller), a connection module (Concat), a Timer module (AXI Timer), a User-defined module (User Logic), a universal serial interface (AXI Uartlite), a universal input/Output interface (AXI General Purpose Input/Output, AXI GPIO), a flash serial interface (Quad Serial Peripheral Interface, quad SPI), a memory interface (such as DDR4 SDRAM (Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory) (a memory capable of supporting high bandwidth)), an Ethernet interface (such as AXI Ethernet Lite) and an integrated circuit bus interface (such as AXI IIC (Inter-Integrated Circuit) interface). The data interaction manner of each sub-module may be as shown in fig. 3, and is not limited in the present invention. Wherein a single arrow indicates that data can only flow in one direction. Double-headed arrows indicate that data may be transferred bi-directionally.
In this embodiment, a method for transplanting a processor platform is provided, which may be used for the MicroBlaze platform described above, and fig. 4 is a flowchart of a method for transplanting a processor platform according to an embodiment of the present invention, as shown in fig. 4, where the flowchart includes the following steps:
step S401, obtaining module information of the target hard core processor based on embedded engineering on the ZYNQ platform. Please refer to the above description of related steps for details, which are not repeated herein.
Step S402, determining a function to be added to the soft-core processor based on a comparison result between the first target function corresponding to the module information and the second target function to be executed by the soft-core processor. Please refer to the above description of related steps for details, which are not repeated herein.
In step S403, the function type of the function to be added in the target hard core processor is identified. Please refer to the above description of related steps for details, which are not repeated herein.
In step S404, if the function to be added is the main function of the target hard core processor, the soft core processor is configured with the first function by adopting the first configuration policy, so as to control the soft core processor to realize the function to be added. Please refer to the above description of related steps for details, which are not repeated herein.
Step S405, if the function to be added further includes a peripheral function of the target hard core processor, performing a second function configuration on the soft core processor by using a second configuration policy, so as to control the soft core processor to implement the peripheral function, thereby obtaining the target soft core processor.
In the embodiment of the invention, if the function to be added comprises not only the main body function but also the peripheral function, the soft core processor is subjected to second function configuration by adopting a second configuration strategy so as to control the soft core processor to realize the peripheral function. The second configuration policy may be understood as a policy for targeted configuration of the non-body functions. And when the main body function and the peripheral function included in the functions to be added are configured and completed, obtaining the target soft core processor.
In some alternative embodiments, the step S405 includes:
and step S4051, determining a second intellectual property core corresponding to the peripheral function in the MicroBlaze platform.
In this manner, a second intellectual property core corresponding to the peripheral function is determined from the intellectual property soft cores mated with the MicroBlaze platform.
In an example, the peripheral module of ZYNQ may be replaced by a generic IP core (second intellectual property core) provided by the vendor of some programmable logic complete solution. For example: a module input/output (Module Input Output, MIO) module of ZYNQ is replaced with an AXI GPIO core, a EMIO (Endless Moments Input Outpu) module (an extensible MIO), a universal asynchronous receiver/Transmitter (UART) module of ZYNQ is replaced with an AXI Uartlite core, an I2C module of ZYNQ is replaced with an AXI IIC core, a Quad SPI Flash module of ZYNQ is replaced with an AXI Quad SPI core, a CAN module of ZYNQ is replaced with an AXI controller area network (Controller Area Network, CAN) core, a USB2 Device module of ZYNQ is replaced with an AXI USB2 Device core; an AXI Ethernet Lite core is used for replacing an Ethernet module of ZYNQ, and if the Ethernet is required to carry out high-speed transmission, other IP cores such as 10G Ethernet Subsystem and the like can be selected according to a specific board card; the method comprises the steps that a 32-bit Timer integrated in a ZYNQ processor is replaced by a Timer IP core (AXI Timer) mounted on a bus in a MicroBlaze platform, and the clock frequency of accessing the module is required to be adjusted according to source engineering; the DDR controller is used for replacing the DDR resource of the PS end on the ZYNQ, and one of DDR3SDRAM, DDR4 SDRAM, memory Ineterface Generator and the like can be selected according to the specific board card type. The above examples are only for illustration, and the second intellectual property core to be added may be determined according to actual requirements, and is not limited in the present invention.
In another example, if the peripheral module corresponding to the peripheral function is an interrupt controller, AXI Interrupt Controller may be used instead of the hard core interrupt controller ScuGic of the Zynq platform.
Step S4052, a target constraint policy controlling the second intellectual property core is acquired.
In this manner, the control strategies of the different peripheral modules during operation are different. And in order to ensure that the constraint control mode of the second intellectual property core can be the same as the operation control logic of the corresponding peripheral module in the target hard core processor, acquiring a target constraint strategy for controlling the second intellectual property core.
Step S4053 configures the second intellectual property core based on the target constraint policy to perform a second functional configuration on the soft core processor.
By adopting the mode to configure the second intellectual property core, the second intellectual property module can be configured in a targeted manner, so that the subsequently obtained target soft core processor not only has the first intellectual property core capable of realizing the main body function of the target hard core processor, but also has the second intellectual property core capable of realizing the peripheral function of the target hard core processor.
In an implementation scenario, if the second intellectual property core is an interrupt controller, when the second intellectual property core is configured based on the target constraint policy, it may be selected whether the interrupt type is level triggered or edge triggered, whether the interrupt polarity is high or low, whether the rising edge or the falling edge, and thus enable the related registers.
Specifically, the target constraint policy includes a target physical constraint policy and/or a target timing constraint policy, and the step S4053 includes:
step a1, determining a physical pin pair corresponding to a second intellectual property core in a soft core processor according to a target physical constraint strategy, wherein the physical pin pair comprises an input pin and an output pin;
step a2, binding an input port of the second intellectual property core with an input pin, and binding an output port of the second intellectual property core with an output pin;
and/or, step a3, configuring the operation time sequence of the second intellectual property core according to the target time sequence constraint strategy.
Specifically, since the peripheral modules of the hard core processors of the ZYNQ series are connected to the corresponding pins in advance, the hard core processors can be used only by simple hooking. However, if the soft core processor needs to add the peripheral function, the soft core processor needs to be added manually and binds the corresponding pins. Thus, the target physical constraint policy may be understood as a layout constraint that configures the second intellectual property core on the soft-core processor. For example: if an input/output port (second intellectual property core) is added in the transplanting process, the input/output port is bound to a corresponding position on a board card of the FPGA. Taking the second intellectual property core as a UART module as an example, according to the corresponding target physical constraint strategy, the output end (RX) of the UART module is bound to the corresponding output pin on the board card, and the input end (TX) of the UART module is bound to the corresponding input pin on the board card.
Because the peripheral modules of the ZYNQ-series hard core processor do not need to carry out time sequence constraint additionally, but in the MicroBlaze platform, the clock attribute of the second intellectual property core needs to be defined, and therefore, if the clock attribute of the second intellectual property core needs to be defined, the operation time sequence of the second intellectual property core is configured according to a target time sequence constraint strategy. The target timing constraint strategy may include, but is not limited to, a period, a duty cycle, a phase, etc. of the input clock, to which a constraint command is to be added. In an example, additional constraint clock attributes are also required if a timing violation occurs, such as setup time, hold time, clock domain, etc.
Step S406, converting the first operation code of the embedded engineering into a second operation code. Please refer to the above description of related steps for details, which are not repeated herein.
Step S407, if the target soft core processor can normally operate according to the second operation code, determining that the embedded engineering transplanting is successful. Please refer to the above description of related steps for details, which are not repeated herein.
According to the transplanting method of the processor platform, different configuration strategies can be adopted for aiming at different functions to conduct targeted configuration on the soft core processor, repeated development can be effectively avoided, and project development time and labor consumption can be greatly reduced.
In other alternative embodiments, if the number of peripheral functions is plural, a third intellectual property core is added, and the third intellectual property core is configured to combine interrupt requests of the plural second intellectual property cores. For example: the third intellectual property core may be a Concat core, which may be used as a bridge for interrupt request merging.
In yet other alternative embodiments, the method further comprises, prior to obtaining the target soft-core processor: autonomous write logic of the target hard core processor is migrated to the soft core processor. That is, in the present invention, the autonomous write logic may include logic of the following devices: a first-in first-out memory (First Input First Output, FIFO), a random access memory (Random Access Memory, RAM), a register transfer level (Real Time Logistics, RLT) code written by the user at his own discretion, and the like.
In some alternative implementation scenarios, the implementation of transplanting the ZYNQ platform to the MicroBlaze platform may be as follows:
firstly, on a MicroBlaze platform, newly building an engineering, creating and configuring a first intellectual property core according to the intellectual property core provided by a default main body template, and configuring the following parameters: the processor bit width of 32 bits is selected, a Debug module is enabled, the bus type is selected as a bus supported by an AXI protocol, an AXI data interface is enabled, and a local storage bus instruction interface and a data interface are enabled. And adding a bus controller, selecting AXI Interconnect, or automatically connecting software after adding a peripheral IP core. And adding a target functional module (closing Wizard core), and setting corresponding parameters to eliminate the main structure difference between the main structure of the target hard core processor and the main structure of the target hard core processor, so as to realize the coverage of the main functions executable by the target hard core processor.
And secondly, if the target hard core processor is provided with the peripheral module, adding a second intellectual property core according to the peripheral function corresponding to the peripheral module, and carrying out targeted configuration on the second intellectual property core by combining with a corresponding target constraint strategy. For example: using AXI GPIO core to replace MIO and EMIO modules of ZYNQ, wherein the bit width is equal to the sum of the bit widths set by MIO+EMIO; the AXI Uartlite core is used for replacing a UART module of the ZYNQ, and the settings of the baud rate, the bit width, the verification and the like are consistent with the embedded engineering on the ZYNQ platform; using AXI IIC core to replace the I2C module of ZYNQ, and configuring general selection default; the AXIQUad SPI core is used for replacing a Quad SPI Flash module of ZYNQ, and the mode is preferably QUAD; an AXI Ethernet Lite core is used for replacing an Ethernet module of ZYNQ, and a full duplex communication mode is preferred; replacing a 32-bit Timer integrated in the ZYNQ processor by using a Timer IP core (AXI Timer) mounted on a bus in a MicroBlaze platform; and replacing the DDR resource of the PS end on the ZYNQ by using a DDR controller, and selecting DDR4 SDRAM according to the type of the board card.
The soft core interrupt controller AXI Interrupt Controller core of the MicroBlaze platform is used for replacing the hard core interrupt controller ScuGic of the Zynq platform, the level trigger of the preferred interrupt type is configured, the level type is high, the related register is enabled, the Concat core is added as a bridge due to the fact that a plurality of peripheral interrupt requests are generated, the input end is connected with interrupt signals of all the peripheral devices, and the output end is connected with a processor.
And the modules such as RTL codes and general IP cores which are independently written by users are directly transplanted without modification.
And after each functional module (comprising a first intellectual property core, a target functional module and a second intellectual property core) is connected correctly, performing electric consistency check, generating and outputting a target soft core processor, generating a corresponding bit stream file, and exporting a MicroBlaze platform.
And finally, transplanting the software part codes in the embedded engineering to a MicroBlaze platform, and modifying the function corresponding relation in the software part codes, wherein the method comprises the steps of replacing a drive file of a ZYNQ platform with a drive file of the MicroBlaze platform, deleting sentences related to a ZYNQ drive library in original #include sentences, and adding sentences of the drive library corresponding to each functional module in the MicroBlaze platform.
And replacing the macro definition name of the device of the ZYNQ platform with the macro definition name of the device of the MicroBlaze platform. The device names of macro definition parts in the UART module, the I2C module, the SPI module, the Ethernet module and the DDR module code are all required to be modified into names which are suitable for the definition of header files in a MicroBlaze platform board level support package (Board Support Package, BSP) package of a MicroBlaze platform.
For the redevelopment part. The interrupt control logic re-develops the relevant code according to the interrupt driver library "INTC" replacing the original ScuGic part. The relevant code parts of the MIO and EMIO modules need to be deleted and re-developed by using the GPIO driver library.
Compiling after modification, downloading the modified modules to an FPGA evaluation board for operation, and if the modified modules can normally operate, indicating that the embedded engineering is successfully transplanted, and if the modified modules can not normally operate, checking and modifying the modified modules.
The transplanting method of the processor platform can solve the problem that codes from the ZYNQ platform to the MicroBlaze platform are difficult to transplant, so that excellent codes of the ZYNQ platform can run on the MicroBlaze platform with wider application range, further repeated development is avoided, and the time and labor consumption of project development can be greatly reduced.
The embodiment also provides a device for transplanting a processor platform, which is used for implementing the above embodiment and the preferred implementation, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The embodiment provides a transplanting device of a processor platform, which is applied to a MicroBlaze platform, as shown in fig. 5, and includes:
The first determining module 501 is configured to obtain module information of a target hard core processor through embedded engineering on a ZYNQ platform, where the ZYNQ platform is a processor platform of the target hard core processor;
a second determining module 502, configured to determine a function to be added to the soft-core processor based on a comparison result between the first target function corresponding to the module information and a second target function to be executed by the soft-core processor;
an identifying module 503, configured to identify a function type of the function to be added in the target hardcore processor;
the first configuration module 504 is configured to perform a first function configuration on the soft core processor by using a first configuration policy if the function to be added is a main function of the target hard core processor, so as to control the soft core processor to implement the function to be added, thereby obtaining the target soft core processor;
the conversion module 505 is configured to convert the first running code of the embedded engineering into a second running code, where the second running code is used to control the target soft core processor to run;
and the detection module 506 is configured to determine that the embedded engineering migration is successful if the target soft core processor can operate normally according to the second operation code.
In some alternative embodiments, the first configuration module 504 includes: the first configuration unit is used for creating and configuring a first intellectual property core, wherein the first intellectual property core is the intellectual property core corresponding to the main body function in the second target function and comprises a first data transmission interface corresponding to the first intellectual property core; the first adding unit is used for adding a target functional module, wherein the target functional module is a functional module corresponding to a function to be added; the second configuration unit is used for configuring the target function module according to the configuration parameters of the function to be added in the embedded engineering; and the first execution unit is used for responding to the completion of the configuration of the first intellectual property core and the target functional module to obtain the target soft core processor.
In some alternative embodiments, the apparatus further comprises: and the adding module is used for adding the bus controller to be respectively connected with the bus interface of the soft core processor, the first data transmission interface and the target functional module.
In some alternative embodiments, if the function to be added further includes a peripheral function of the target hard core processor, before obtaining the target soft core processor, the apparatus further includes: and the second configuration module is used for carrying out second function configuration on the soft core processor by adopting a second configuration strategy so as to control the soft core processor to realize the peripheral function.
In some alternative embodiments, the second configuration module includes: the second execution unit is used for determining a second intellectual property core corresponding to the peripheral function in the MicroBlaze platform; an acquisition unit configured to acquire a target constraint policy for controlling the second intellectual property core; and a third configuration unit, configured to configure the second intellectual property core based on the target constraint policy to perform a second functional configuration on the soft core processor.
In some alternative embodiments, the target constraint policy includes a target physical constraint policy and/or a target timing constraint policy; a third configuration unit including: the first processing unit is used for determining a physical pin pair corresponding to the second intellectual property core in the soft core processor according to the target physical constraint strategy, wherein the physical pin pair comprises an input pin and an output pin; the second processing unit is used for binding the input port and the input pin of the second intellectual property core and binding the output port and the output pin of the second intellectual property core; and/or a fourth configuration unit, configured to configure the operation timing of the second intellectual property core according to the target timing constraint policy.
In some alternative embodiments, the apparatus further comprises: and the fourth configuration module is used for adding a third intellectual property core if the number of the peripheral functions is multiple, and the third intellectual property core is used for merging interrupt requests of the multiple second intellectual property cores.
In some alternative embodiments, before obtaining the target soft-core processor, the apparatus further comprises: and a fifth configuration module for transplanting autonomous writing logic of the target hard core processor to the soft core processor.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The portable device of the processor platform in this embodiment is presented in the form of functional units, where the units refer to ASIC (Application Specific Integrated Circuit ) circuits, processors and memories executing one or more software or fixed programs, and/or other devices that can provide the above-described functionality.
The embodiment of the invention also provides an electronic device, which is provided with the transplanting device of the processor platform shown in the figure 5.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an electronic device according to an alternative embodiment of the present invention, as shown in fig. 6, the electronic device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the electronic device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple electronic devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 6.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the electronic device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The electronic device further comprises input means 30 and output means 40. The processor 10, memory 20, input device 30, and output device 40 may be connected by a bus or other means, for example in fig. 6.
The input device 30 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic device, such as a touch screen, keypad, mouse, trackpad, touchpad, pointer stick, one or more mouse buttons, trackball, joystick, and the like. The output means 40 may include a display device, auxiliary lighting means (e.g., LEDs), tactile feedback means (e.g., vibration motors), and the like. Such display devices include, but are not limited to, liquid crystal displays, light emitting diodes, displays and plasma displays. In some alternative implementations, the display device may be a touch screen.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (11)
1. A method of transplanting a processor platform, applied to a MicroBlaze platform, the method comprising:
obtaining module information of a target hard core processor based on embedded engineering on a ZYNQ platform, wherein the ZYNQ platform is a processor platform of the target hard core processor;
determining a function to be added to the soft-core processor based on a comparison result between a first target function corresponding to the module information and a second target function to be executed by the soft-core processor;
identifying a function type of the function to be added in the target hard core processor;
if the function to be added is the main function of the target hard core processor, performing first function configuration on the soft core processor by adopting a first configuration strategy to control the soft core processor to realize the function to be added, so as to obtain the target soft core processor;
converting the first operation code of the embedded engineering into a second operation code, wherein the second operation code is used for controlling the operation of the target soft core processor;
And if the target soft core processor can normally operate according to the second operation code, determining that the embedded engineering transplanting is successful.
2. The method of claim 1, wherein the performing a first function configuration on the soft-core processor using a first configuration policy to control the soft-core processor to implement the function to be added, to obtain a target soft-core processor, includes:
creating and configuring a first intellectual property core, wherein the first intellectual property core is the intellectual property core corresponding to the main body function in the second target function and comprises a first data transmission interface corresponding to the first intellectual property core;
adding a target functional module, wherein the target functional module is a functional module corresponding to the function to be added;
configuring the target function module according to configuration parameters of the function to be added in the embedded engineering;
and responding to the completion of the configuration of the first intellectual property core and the target function module to obtain a target soft core processor.
3. The method according to claim 2, wherein the method further comprises:
and adding a bus controller to be respectively connected with the bus interface of the soft core processor, the first data transmission interface and the target functional module.
4. The method of claim 1, wherein if the function to be added further comprises a peripheral function of the target hard core processor, the method further comprises, prior to the obtaining the target soft core processor:
and performing second function configuration on the soft core processor by adopting a second configuration strategy so as to control the soft core processor to realize the peripheral function.
5. The method of claim 4, wherein said configuring the soft-core processor with the second configuration policy comprises:
determining a second intellectual property core corresponding to the peripheral function in the MicroBlaze platform;
obtaining a target constraint strategy for controlling the second intellectual property core;
and configuring the second intellectual property core based on the target constraint strategy to perform second function configuration on the soft core processor.
6. The method according to claim 5, wherein the target constraint policy comprises a target physical constraint policy and/or a target timing constraint policy; the configuring the second intellectual property core based on the target constraint policy to perform a second functional configuration on the soft core processor includes:
Determining a physical pin pair corresponding to the second intellectual property core in the soft core processor according to the target physical constraint strategy, wherein the physical pin pair comprises an input pin and an output pin;
binding an input port of the second intellectual property core with the input pin, and binding an output port of the second intellectual property core with the output pin;
and/or configuring the operation time sequence of the second intellectual property core according to the target time sequence constraint strategy.
7. The method of claim 6, wherein the method further comprises:
if the number of the peripheral functions is multiple, adding a third intellectual property core, wherein the third intellectual property core is used for merging interrupt requests of the multiple second intellectual property cores.
8. The method of claim 1, wherein prior to said deriving a target soft-core processor, the method further comprises:
and transplanting autonomous programming logic of the target hard core processor to the soft core processor.
9. A migration apparatus for a processor platform, the apparatus comprising:
the first determining module is used for obtaining module information of a target hard core processor through embedded engineering on a ZYNQ platform, wherein the ZYNQ platform is a processor platform of the target hard core processor;
The second determining module is used for determining a function to be added to the soft core processor based on a comparison result between the first target function corresponding to the module information and a second target function to be executed by the soft core processor;
the identification module is used for identifying the function type of the function to be added in the target hard core processor;
the first configuration module is used for carrying out first function configuration on the soft core processor by adopting a first configuration strategy if the function to be added is the main function of the target hard core processor so as to control the soft core processor to realize the function to be added and obtain the target soft core processor;
the conversion module is used for converting the first operation code of the embedded engineering into a second operation code, and the second operation code is used for controlling the target soft core processor to operate;
and the detection module is used for determining that the embedded engineering transplanting is successful if the target soft core processor can normally operate according to the second operation code.
10. An electronic device, comprising:
a memory and a processor, the memory and the processor being communicatively coupled to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the migration method of the processor platform of any one of claims 1 to 8.
11. A computer readable storage medium having stored thereon computer instructions for causing a computer to perform the migration of the processor platform of any one of claims 1 to 8.
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