CN116953459A - Aging test method for silicon carbide device - Google Patents
Aging test method for silicon carbide device Download PDFInfo
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- CN116953459A CN116953459A CN202211424491.3A CN202211424491A CN116953459A CN 116953459 A CN116953459 A CN 116953459A CN 202211424491 A CN202211424491 A CN 202211424491A CN 116953459 A CN116953459 A CN 116953459A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 327
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 327
- 230000032683 aging Effects 0.000 title claims abstract description 69
- 238000010998 test method Methods 0.000 title claims abstract description 42
- 238000012360 testing method Methods 0.000 claims abstract description 220
- 230000001360 synchronised effect Effects 0.000 claims abstract description 190
- 239000003990 capacitor Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 23
- 238000007599 discharging Methods 0.000 claims description 4
- 230000035882 stress Effects 0.000 description 27
- 238000010586 diagram Methods 0.000 description 18
- 230000007774 longterm Effects 0.000 description 9
- 238000004088 simulation Methods 0.000 description 9
- 238000004364 calculation method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004422 calculation algorithm Methods 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a silicon carbide device aging test method, which comprises the following steps: the test platform comprises a front-stage synchronous Boost bridge arm circuit and a rear-stage synchronous Buck bridge arm circuit which are connected in series; the direct-current power supply is input into the front-stage synchronous Boost bridge arm circuit through a diode and is connected with the output end of the rear-stage synchronous Buck bridge arm circuit; the direct current power supply is arranged according to the test working condition, and the test platform realizes the circulating flow of energy in the test platform through a power inductor in the circuit; setting the switching frequency, drain-source voltage and drain current of the tested silicon carbide device by setting the working mode of the test platform, so as to accelerate the aging of the silicon carbide device under different test working conditions and obtain an aging test result; the silicon carbide device is placed in the bridge arm structure circuit by the test platform, so that the influence of crosstalk on the reliability of gate oxide under the condition of continuous operation of the silicon carbide device is fully considered, and the accuracy of the aging test result of the silicon carbide device is improved.
Description
Technical Field
The invention relates to a silicon carbide device aging test method.
Background
Compared with the traditional Si material, the SiC material is used as a third generation wide bandgap semiconductor material, has higher critical electric field intensity, higher saturated electron drift rate and higher heat conductivity, and the power device or module produced by adopting the SiC material has higher blocking voltage, faster switching speed and better heat conduction performance, and the application of the SiC power device can promote the design of a modern power converter to trend toward the development of high frequency, high efficiency and high power density.
However, high-end power electronic converters are required to have high reliability due to the diversified application scenarios, and the reliability of silicon carbide power devices is a most common failure cause. While silicon carbide power devices have greater advantages, they present greater challenges with respect to reliability and stability, silicon carbide MOSFETs (i.e., silicon carbide devices) have a high defect density at the gate oxide and oxide-semiconductor interface, and thus, long-term reliability issues remain a challenge. On the other hand, in designing a silicon carbide MOSFET, there is a trade-off relationship between the reliability of its gate oxide and the on-resistance of the device, for which accurate evaluation of the long-term reliability of its gate oxide is essential in order to improve the performance of the silicon carbide MOSFET.
The gate oxide reliability test of silicon carbide MOSFETs can be categorized into a dc gate bias temperature instability stress test and an ac gate bias temperature instability stress test. The DC grid bias temperature instability stress test is to apply static bias stress to a silicon carbide MOSFET, and the traditional test method is to repeatedly apply bias and temperature stress to the grid in order of measurement-stress-measurement (MSM) and then read, but since the accuracy of the method is largely related to the reading time, the Indeluxe corporation adopts pretreatment pulse to improve the grid bias temperature instability stress and carry out secondary reading, and the method is not easy to be influenced by reading delay and device conditions.
Meanwhile, aiming at the evaluation test of the reliability of the external gate oxide layer of the silicon carbide MOSFET, the Infray test develops two test methods of a Martensil stress test and a gate voltage stepping stress test, and the Martensil stress test can realize that stresses close to running conditions are applied to thousands of devices at the same time, so that the test efficiency is high, but the test is required to be verified in a very complex mode, and the stress level of a selected gate is also harsh. The gate voltage step stress test is performed by gradually increasing the gate stress bias voltage, which can qualitatively evaluate the reliability of the gate oxide layer of the silicon carbide MOSFET, and is more accurate and effective, but has a smaller test number.
The dc gate bias temperature instability stress test is performed under static bias stress conditions, however, in actual operation of the silicon carbide MOSFET, under certain AC gate bias stress conditions, the degree of parameter drift may exceed the typical value after standard dc gate stress is applied, for which an evaluation test of AC gate bias temperature instability (AC BTI) of the silicon carbide MOSFET is necessary. According to the test method, the drain electrode and the source electrode of the silicon carbide MOSFET are generally short-circuited, no load current is ensured when the silicon carbide MOSFET is conducted, an alternating-current high-frequency dynamic voltage stress is applied to the grid electrode for testing, data are read out according to a certain measurement sequence, under the test, the working condition of the silicon carbide MOSFET in the operation of the converter is simulated as much as possible, the switching frequency of the grid electrode, the upper limit and the lower limit of the bias voltage and the influence factors of signal overshoot and undershoot are mainly considered, and the alternating-current grid bias voltage temperature unstable stress test is used for effectively evaluating the reliability problem of a grid electrode oxide layer of the silicon carbide MOSFET in the actual operation.
According to the testing method, the silicon carbide MOSFET is in an isolated state and is subjected to aging test by adopting a static testing method or a dynamic testing method, the silicon carbide MOSFET is not arranged in a bridge arm type structural circuit, however, in practical application, the silicon carbide MOSFET is often arranged in the bridge arm type structural circuit, so that crosstalk also has a certain influence on the grid oxide reliability of the silicon carbide MOSFET, meanwhile, due to the fact that the silicon carbide MOSFET has higher switching speed, the crosstalk problem in the bridge arm type structural circuit is more prominent, the serious crosstalk problem prevents the improvement of the switching speed, the potential influence of grid compressive stress on the reliability and the risk of bridge arm penetration caused by misleading are considered, the crosstalk problem influences the further improvement of the efficiency, the power density and the service life of the power electronic converter, the further reduction of cost is limited, and the working reliability of the converter is even reduced.
Disclosure of Invention
The invention aims to solve the technical problem of providing a burn-in test method for a silicon carbide device, which enables a grid electrode of the silicon carbide device to work in a continuous switch mode, and simultaneously enables the working condition of the silicon carbide device to be closer to the actual working condition of the silicon carbide device applied to a power electronic converter and to be set freely when the accelerated burn-in test is carried out on the silicon carbide device. According to the aging test method for the silicon carbide devices, a plurality of silicon carbide devices can be tested simultaneously during each test, and the test efficiency of the silicon carbide devices is improved; according to the aging test method for the silicon carbide device, the silicon carbide device is placed in the bridge arm type structural circuit, the influence of crosstalk on the gate oxide reliability of the silicon carbide device is fully considered, and the accuracy of the aging test result of the silicon carbide device is improved.
In a first aspect, the present invention provides a method for burn-in testing a silicon carbide device, comprising: the test platform takes a synchronous cascading Boost-Buck as a topological bridge arm type structure circuit and comprises a front-stage synchronous Boost bridge arm circuit and a rear-stage synchronous Buck bridge arm circuit, and the front-stage synchronous Boost bridge arm circuit and the rear-stage synchronous Buck bridge arm circuit are cascaded;
the direct current power supply is input into the front-stage synchronous Boost bridge arm circuit through a diode and is connected with the output end of the rear-stage synchronous Buck bridge arm circuit; the direct current power supply is arranged according to a test working condition, and the test platform realizes the circulating flow of energy in the test platform through the power inductance of the front-stage synchronous Boost bridge arm circuit and the power inductance of the rear-stage synchronous Buck bridge arm circuit;
by setting the working mode of the test platform and setting the switching frequency, drain-source voltage and drain current of the tested silicon carbide device, the aging of the silicon carbide device is accelerated under different test working conditions, and an aging test result is obtained.
Further, the silicon carbide devices are placed in a front-stage synchronous Boost bridge arm circuit and a rear-stage synchronous Buck bridge arm circuit, the front-stage synchronous Boost bridge arm circuit is used for placing two silicon carbide devices in an upper bridge arm and a lower bridge arm respectively, and the rear-stage synchronous Buck bridge arm circuit is used for placing two silicon carbide devices in the upper bridge arm and the lower bridge arm respectively.
Further, the test platform comprises a direct current power supply and a diode BD;
the front-stage synchronous Boost bridge arm circuit comprises: capacitor C 1 Power inductance L 1 Silicon carbide device Q of lower bridge arm 1 First driving unit, upper bridge arm silicon carbide device Q 2 A second driving unit;
the back-stage synchronous Buck bridge arm circuit comprises: capacitor C 2 Power inductance L 2 Upper bridge arm silicon carbide device Q 3 Third drive unit, lower bridge arm silicon carbide device Q 4 A fourth driving unit;
the positive electrodes of the direct current power supply are respectively connected with the capacitor C through the diode BD 1 One end of (a) and a power inductance L 1 One end of (a) and a power inductor L 2 Is provided; the negative electrode of the direct current power supply is respectively connected with the capacitor C 1 Another end of (a) lower bridge arm silicon carbide device Q 1 Source, capacitance C of (2) 2 One end of (a) and a lower arm silicon carbide device Q 4 A source of (a); the power inductance L 1 Is connected to the upper bridge arm silicon carbide device Q 2 Is a lower bridge arm silicon carbide device Q 1 The upper bridge arm silicon carbide device Q 2 The drains of the capacitors are respectively connected with the capacitor C 2 Another end of (a) and an upper arm silicon carbide device Q 3 The drain electrode of the power inductance L 2 Is respectively connected with the silicon carbide device Q of the upper bridge arm at the other end part 3 Is a lower bridge arm silicon carbide device Q 4 A drain electrode of (2); the first driving unit is used for driving the lower bridge arm silicon carbide device Q 1 The second driving unit is used for driving the upper bridge arm silicon carbide device Q 2 The third driving unit is used for driving the upper bridge arm silicon carbide device Q 3 The fourth driving unit is used for driving the lower bridge arm silicon carbide device Q 4 。
Further, the working modes of the test platform sequentially comprise an A working mode, a B working mode, a D working mode and a C working mode; the A working mode is at time t 1 -t 2 The method comprises the steps of carrying out a first treatment on the surface of the The B working mode is at time t 3 -t 4 The method comprises the steps of carrying out a first treatment on the surface of the The D working mode is at time t 4 -t 5 The method comprises the steps of carrying out a first treatment on the surface of the The C working mode is at time t 5 -t 6 ；
The working mode A is as follows:
lower bridge arm silicon carbide device Q of front-stage synchronous Boost bridge arm circuit 1 Upper bridge arm silicon carbide device Q of back-stage synchronous Buck bridge arm circuit 3 The current of the front-stage synchronous Boost bridge arm circuit flows through the power inductor L in turn 1 Lower bridge arm silicon carbide device Q 1 Current of the back-stage synchronous Buck bridge arm circuit sequentially flows through the upper bridge arm silicon carbide device Q 3 And power inductance L 2 Capacitance C 1 And capacitor C 2 All discharge, power inductance L 1 And L 2 Charging is carried out;
the working mode B is as follows:
Lower bridge arm silicon carbide device Q of front-stage synchronous Boost bridge arm circuit 1 Upper bridge arm silicon carbide device Q of rear synchronous Buck bridge arm circuit maintaining on state 3 Turn off its lower bridge arm silicon carbide device Q 4 Conducting to carry out current follow current, keeping the current flow in the front-stage synchronous Boost bridge arm circuit unchanged, and enabling the current in the rear-stage synchronous Buck bridge arm circuit to sequentially flow through the lower bridge arm silicon carbide device Q 4 And power inductance L 2 Capacitance C at this time 2 The current state is kept unchanged, the energy is neither charged nor discharged, and the energy is converted into a power inductance L 2 Providing a power inductance L 2 Discharging, and energy of front-stage synchronous Boost bridge arm circuit is represented by capacitor C 1 Providing, power inductance L 1 Charging;
the D working mode is as follows:
the front-stage synchronous Boost bridge arm circuit enters into a follow current state, and the upper bridge arm silicon carbide device Q thereof 2 Follow current is carried out, and silicon carbide device Q of lower bridge arm 1 Turn-off, current flows through the power inductor L 1 And upper bridge arm silicon carbide device Q 2 The method comprises the steps of carrying out a first treatment on the surface of the The later synchronous Buck bridge arm circuit keeps the follow current state in the B working mode; wherein the energy of the front-stage synchronous Boost bridge arm circuit is represented by a power inductance L 1 Providing, power inductance L 1 Discharging, and the energy of the later-stage synchronous Buck bridge arm circuit is converted into a power inductance L 2 Providing;
the working mode C is as follows:
the state of the front-stage synchronous Boost bridge arm circuit enters into a follow current state, and the follow current state is formed by an upper bridge arm silicon carbide device Q of the front-stage synchronous Boost bridge arm circuit 2 The current of the front-stage synchronous Boost bridge arm circuit flows through the power inductor L in turn 1 And upper bridge arm silicon carbide device Q 2 The energy of which is represented by power inductance L 1 Providing, power inductance L 1 Is in a discharge state; upper bridge arm silicon carbide device Q of rear synchronous Buck bridge arm circuit 3 On, energy is transferred by capacitor C 2 Providing a power inductance L 2 In a charged state.
Further, by setting the working mode of the test platform and setting the switching frequency, drain-source voltage and drain current of the tested silicon carbide device, the aging of the silicon carbide device is accelerated under different test working conditions, and the obtained aging test result is further specifically: the duty ratio of a back-stage synchronous Buck bridge arm circuit is determined, the duty ratio is fixed, the voltage class of a test working condition is determined according to the input voltage of a direct current power supply, and the target of the preset test working condition is realized by adjusting the duty ratio of a silicon carbide device in a front-stage synchronous Boost bridge arm circuit;
first, the duty ratio D of the post-stage synchronous Buck bridge arm circuit is determined 2 Determining the input voltage of the direct current power supply according to the relation between the test working condition voltage and the duty ratio of the post-stage synchronous Buck bridge arm circuitE.g. formula (5)
In the formula (5), V in Is the input voltage of the direct current power supply, V 2 The output voltage of the front-stage synchronous Boost bridge arm circuit is calculated according to the power inductance L of the front-stage synchronous Boost bridge arm circuit and the rear-stage synchronous Buck bridge arm circuit in each switching period 1 And L 2 The volt-second characteristic of the silicon carbide device is shown as (6), and the silicon carbide device Q of the lower bridge arm is obtained 1 Duty cycle of (2);
d in (6) 1 Silicon carbide device Q for lower bridge arm in front-stage synchronous Boost bridge arm circuit 1 Duty cycle of D 2 Silicon carbide device Q for upper bridge arm in back-stage synchronous Buck bridge arm circuit 3 Duty cycle, I D Drain currents for four silicon carbide devices;
simplifying and solving the formula (6) according to the time relation of each working mode, wherein,in each switching period, the phase difference between the driving waveform of the front-stage synchronous Boost bridge arm circuit and the driving waveform of the rear-stage synchronous Buck bridge arm circuit is formed; calculating to obtain the duty ratio of a front-stage synchronous Boost bridge arm circuit, as shown in a formula (7);
according to the time relation of the working modes, determining the value range of the phase difference between the driving waveform of the front-stage synchronous Boost bridge arm circuit and the driving waveform of the rear-stage synchronous Buck bridge arm circuit, wherein the value range is shown as a formula (8);
As can be seen from (7), the upper arm silicon carbide device Q of the later synchronous Buck arm circuit 3 When the duty ratio of the (B) is determined, the voltage class of the test working condition is determined, and the lower bridge arm silicon carbide device Q of the front-stage synchronous Boost bridge arm circuit 1 The duty ratio of the front-stage synchronous Boost bridge arm circuit is determined through the setting target of the input test working condition, so that the continuous switch test is performed on the silicon carbide device under the set test working condition, and the aging test result is obtained.
One or more technical solutions provided in the embodiments of the present invention at least have the following technical effects or advantages:
1. the influence of crosstalk on the reliability of the silicon carbide device is fully considered: the aging test method for the silicon carbide device has the advantages that the aging test method for the silicon carbide device has a bridge arm type structure, the silicon carbide device can be subjected to grid voltage bias with a certain frequency in the normal operation process of the converter, including positive bias and negative bias, and can also be subjected to crosstalk stress caused by higher switching speed, so that the aging test method for the silicon carbide device can be used for evaluating the long-term reliability problem of the silicon carbide device, the silicon carbide device is placed in a bridge arm type structure circuit, the influence of crosstalk on the grid oxygen reliability of the silicon carbide device is considered, and the accuracy degree of the aging test result for the silicon carbide device is improved.
2. Energy feedback: the aging test method for the silicon carbide device can realize the function of energy feedback. The simulation waveform can show that the power supply only provides excitation energy when the test platform is started, and then in the normal operation of the test platform, the energy is not provided by the power supply, but the energy always realizes circulating flow in the test platform through the power inductor, so that the power output of the power supply in the test process is reduced, the function can effectively reduce the energy consumption of the test platform, and the test cost of the silicon carbide device is greatly reduced.
3. Dynamic continuous switch test condition: the aging test method of the silicon carbide device can realize the test of the silicon carbide device under the continuous switch test working condition, apply the grid voltage stress with a certain frequency to the tested silicon carbide device, accelerate the aging degree of the device, be effectively used for evaluating the long-term reliability of the device when the dynamic stress is applied to the silicon carbide device, and be more similar to the actual application condition of the silicon carbide device compared with the test method of applying the static stress, and the test result is also more similar to the actual application condition of the silicon carbide device.
4. Freely setting working conditions: the aging test method for the silicon carbide device can be set according to the required test working conditions, the working conditions are not unique, the practical application working conditions of the silicon carbide device can be simulated to a greater extent, and in each working period, the aging test method for the silicon carbide device performs actions of different modes, and the modes are more various, so that the test result is more reliable and accurate, and the grid alternating current bias temperature instability (AC BTI) of the silicon carbide device can be effectively evaluated.
5. Multiple silicon carbide devices were tested simultaneously: according to the aging test method for the silicon carbide devices, simulation waveforms show that the working conditions of the four silicon carbide devices are almost the same, so that high-temperature grid bias (HTGB) tests can be simultaneously carried out on the four silicon carbide devices, and meanwhile, the long-term reliability of the silicon carbide devices is evaluated, so that the test efficiency is effectively improved, and the test progress of the silicon carbide devices is accelerated.
6. The power supply voltage level is lower, safe and reliable: according to the synchronous Boost type energy feedback aging test method for the silicon carbide device, provided by the invention, the test purpose of setting the silicon carbide device can be achieved under the condition that the input power supply voltage is lower than the test working condition voltage, the external power supply voltage of the test platform is lower, the safety requirements on insulation and the like are relatively loose, and the aging test of the silicon carbide MOSFET is easy to realize.
7. Robustness is high: according to the aging test method of the silicon carbide MOSFET, the lower bridge arm silicon carbide device Q in the front synchronous Boost bridge arm circuit is adjusted according to the target test working condition of the silicon carbide device 1 Duty cycle and phase of (a). Power based on front-stage synchronous Boost bridge arm circuit and rear-stage synchronous Buck bridge arm circuit in each switching period Inductance L 1 And L 2 Calculation of volt-second characteristics of silicon carbide device Q 1 Duty ratio D of (2) 1 The method comprises the steps of carrying out a first treatment on the surface of the Silicon carbide device Q 1 And Q 3 Drive signal phase of (2)In a wider range->The stable operation and energy circulation flow of the platform can be ensured, so that the control algorithm is relatively easy to realize, and the robustness of the platform is high.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
The invention will be further described with reference to examples of embodiments with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a test platform circuit for a silicon carbide device burn-in test method of the present invention;
FIG. 2 is a waveform diagram illustrating the operation of a silicon carbide device burn-in test method according to the present invention;
fig. 3a to 3d are schematic views of the principle of the working mode of the present invention;
FIG. 4 is a schematic diagram of the time relationship of the working modes of the present invention;
FIG. 5 is a driving waveform diagram of each silicon carbide device at the first test of the present invention;
FIG. 6 is a graph showing a current waveform of the power inductor in the first test of the present invention;
FIG. 7 is a voltage waveform diagram of a capacitor in a post-stage synchronous Buck bridge arm circuit during a first test according to the present invention;
FIG. 8 is a waveform diagram of drain-source voltage and drain current of a pre-synchronization type Boost bridge arm circuit silicon carbide device of the present invention during a first test;
FIG. 9 is a waveform diagram of drain-source voltage and drain current of a silicon carbide device of a back-end synchronous Buck bridge arm circuit during a first test of the present invention;
FIG. 10 is a waveform diagram of the power supply current at the first test of the present invention;
FIG. 11 is a driving waveform diagram of each SiC device according to the second test of the present invention;
FIG. 12 is a graph showing the current waveform of the power inductor during the second test of the present invention;
FIG. 13 is a waveform diagram of drain-source voltage and drain current of a pre-synchronization type Boost bridge arm circuit silicon carbide device during a second test of the present invention;
FIG. 14 is a waveform diagram of drain-source voltage and drain current of a post-synchronization type Boost bridge arm circuit silicon carbide device during a second test of the present invention;
FIG. 15 is a driving waveform diagram of each SiC device according to the third test of the present invention;
FIG. 16 is a diagram showing the current waveform of the power inductor in the third test of the present invention;
FIG. 17 is a waveform diagram of drain voltage and drain current of a pre-synchronization type Boost bridge arm circuit silicon carbide device during a third test of the present invention;
FIG. 18 is a waveform diagram of the drain voltage and drain current of a silicon carbide device of a back-end synchronous Buck bridge arm circuit in a third test of the present application;
FIG. 19 is a driving waveform diagram of each SiC device during a fourth test according to the present application;
FIG. 20 is a current waveform of the power inductor during the fourth test of the present application;
FIG. 21 is a waveform diagram of drain voltage and drain current of a pre-stage synchronous Boost bridge arm circuit silicon carbide device during a fourth test of the present application;
fig. 22 is a waveform diagram of the drain voltage and drain current of the silicon carbide device of the back-end synchronous Buck leg circuit in the fourth test of the present application.
Detailed Description
The technical scheme in the embodiment of the application has the following overall thought:
1. according to the aging test method for the silicon carbide device, the synchronous cascading Boost-Buck is used as a bridge arm type structure circuit of a topology, the front stage is a synchronous Boost bridge arm topology, the rear stage is a synchronous Buck bridge arm topology, the synchronous Boost bridge arm topology is cascaded to form the test platform of the aging test method, the silicon carbide device is placed in the bridge arm type structure circuit, the test platform can realize the accelerated aging test of the silicon carbide device, the energy can also circulate in the test platform, the power output of a power supply in the test process is reduced, and dynamic voltage stress can be applied to the silicon carbide device in a continuous switching mode.
2. The test platform of the aging test method for the silicon carbide device has a mixed Boost working mode and Buck working mode, and has 4 working modes in actual operation, wherein the specific working mode is an ABDC mode.
3. The aging test method for the silicon carbide devices can realize the simultaneous test of 4 silicon carbide devices, and in the accelerated aging test, the working condition of each silicon carbide device is the same, so that the accelerated aging test can be carried out on the 4 silicon carbide devices simultaneously under the same set working condition, the long-term reliability of the test is tested, and the test efficiency is greatly improved. Meanwhile, the test platform adopts a full silicon carbide device, and due to the topological characteristic, the crosstalk problem can exist at a higher switching speed, so that the aging test method of the silicon carbide device is beneficial to evaluating the influence of the crosstalk problem of the silicon carbide device on the long-term reliability of the silicon carbide device in operation.
4. According to the aging test method for the silicon carbide device, disclosed by the invention, the input voltage is boosted to the working condition demand voltage through Boost conversion, and the driving signal of the silicon carbide device is reasonably designed through the prior art, so that the current flowing through the silicon carbide device reaches the working condition demand current, and therefore, the grid alternating current bias temperature instability (AC BTI) of the silicon carbide device in practical application is effectively evaluated.
As shown in FIG. 1, the test platform of the invention takes a synchronous cascading Boost-Buck as a topological bridge arm type structure circuit, and comprises a front-stage synchronous Boost bridge arm circuit and a rear-stage synchronous Buck bridge arm circuit, wherein the front-stage synchronous Boost bridge arm circuit and the rear-stage synchronous Buck bridge arm circuit are cascaded;
the test platform comprises a direct current power supply and a diode BD;
the front-stage synchronous Boost bridge arm circuit comprises: capacitor C 1 Power inductance L 1 Silicon carbide device Q of lower bridge arm 1 First driving unit, upper bridge arm silicon carbide device Q 2 A second driving unit;
the back-stage synchronous Buck bridge arm circuit comprises: capacitor C 2 Power inductance L 2 Upper bridge arm silicon carbide device Q 3 Third drive unit, lower bridge arm silicon carbide device Q 4 A fourth driving unit;
the positive electrodes of the direct current power supply are respectively connected with the capacitor C through the diode BD 1 One end of (a) and a power inductance L 1 One end of (a) and a power inductor L 2 Is provided; the negative electrode of the direct current power supply is respectively connected with the capacitor C 1 Another end of (a) lower bridge arm silicon carbide device Q 1 Source, capacitance C of (2) 2 One end of (a) and a lower arm silicon carbide device Q 4 A source of (a); the power inductance L 1 Is connected to the upper bridge arm silicon carbide device Q 2 Is a lower bridge arm silicon carbide device Q 1 The upper bridge arm silicon carbide device Q 2 The drains of the capacitors are respectively connected with the capacitor C 2 Another end of (a) and an upper arm silicon carbide device Q 3 The drain electrode of the power inductance L 2 Is respectively connected with the silicon carbide device Q of the upper bridge arm at the other end part 3 Is a lower bridge arm silicon carbide device Q 4 A drain electrode of (2); the first driving unit is used for driving the lower bridge arm silicon carbide device Q 1 The second driving unit is used for driving the upper bridge arm silicon carbide device Q 2 The third driving unit is used for driving the upper bridge arm silicon carbide device Q 3 The fourth driving unit is used for driving the lower bridge arm silicon carbide device Q 4 . Wherein the resistance R Q1 Resistance R Q2 Resistance R Q3 Resistance R Q4 Respectively lower bridge arm silicon carbide device Q 1 Upper bridge arm silicon carbide device Q 2 Carbonization of upper armSilicon device Q 3 Silicon carbide device Q of lower bridge arm 4 On-resistance of itself, resistance R L1 Is a power inductance L 1 Is a self-impedance of (a); resistor R L2 Is a power inductance L 2 Is a self-impedance of the (c). The first driving unit consists of a driving signal, an RC circuit and a silicon carbide device Q of a lower bridge arm 1 Is connected to drive the lower bridge arm silicon carbide device Q 1 Is provided; the second driving unit consists of a driving signal, an RC circuit and an upper bridge arm silicon carbide device Q 2 Is connected to drive the upper bridge arm silicon carbide device Q 2 Is provided; the third driving unit consists of a driving signal, an RC circuit and an upper bridge arm silicon carbide device Q 3 Is connected to drive the upper bridge arm silicon carbide device Q 3 Is provided; the fourth driving unit consists of a driving signal, an RC circuit and a silicon carbide device Q of a lower bridge arm 4 Is connected to drive the lower bridge arm silicon carbide device Q 4 Is provided; the first drive unit, the second drive unit, the third drive unit and the fourth drive unit are all arranged by adopting the prior art, and comprise: a driving signal, a driving resistor and a control capacitor; the driving resistor is arranged according to a driving signal, the capacitor is used for adjusting the switching speed, and the driving signal is sent out by the existing driving circuit.
The silicon carbide MOSFET is placed in the bridge arm structure circuit by the test platform, so that the influence of crosstalk on the reliability of gate oxide under the condition of continuous operation of the silicon carbide MOSFET is fully considered, and the accuracy of the aging test result of the silicon carbide device is improved.
The test platform can realize the aging test of the silicon carbide device under the continuous switch test, can effectively evaluate the long-term reliability of the device when the dynamic stress is applied to the silicon carbide device, and is more similar to the actual application condition of the silicon carbide device compared with the test method for applying the static stress.
The test platform not only considers the influence of the grid voltage bias with a certain frequency on the aging degree of the silicon carbide device in the normal operation process of the converter, but also fully considers the influence of crosstalk on the grid oxygen reliability of the silicon carbide device by placing the silicon carbide device in a bridge arm type structure circuit, so that the aging test result of the silicon carbide device is closer to the actual application condition of the silicon carbide device, and the test result is more accurate.
DC power supply (V) in ) The power supply is input into a front-stage synchronous Boost topology through a diode and is connected with the output end of a rear-stage synchronous Buck topology so as to prevent power supply damage, input voltage is set according to a test working condition (the test working condition is the switching frequency, drain-source voltage and drain current of a silicon carbide device), and a test platform realizes the circulating flow of energy in the test platform through a power inductor of the synchronous Boost and a power inductor of the synchronous Buck, so that the power output of the power supply in the test process is reduced; the working mode of the test platform considers the impedance and the inductance impedance of each silicon carbide device and has four working modes: ABDC mode, the working principle of which will be analyzed in detail and verification will be given below.
1. Principle of operation
As shown in FIG. 2, the working modes of the aging test method of the silicon carbide device are sequentially A mode, B mode, D mode and C mode, which are mixed Boost working mode and Buck working mode to realize the circulating flow of energy in the test platform, and the working waveforms of the aging test method are shown in FIG. 2
(1) A working mode (t) 1 -t 2 ) Not including t 2 Time of day
The working mode of the aging test method of the silicon carbide device in the mode A is shown in figure 3a, and the lower bridge arm silicon carbide device Q of the bridge arm in the front synchronous Boost is shown in the specification 1 And upper bridge arm silicon carbide device Q of rear synchronous type Buck bridge arm 3 On, the current of the front stage topology flows through the power inductor L in turn 1 Lower bridge arm silicon carbide device Q 1 Current of the subsequent stage topology sequentially flows through the upper bridge arm silicon carbide device Q 3 And power inductance L 2 Capacitance C of synchronous Boost 1 And synchronous Buck capacitor C 2 All discharge to provide energy, power inductance L 1 And L 2 Charging is performed. In this stage, lower arm silicon carbide device Q 1 And upper bridge arm silicon carbideDevice Q 3 The voltage across (a) has a small voltage due to the presence of on-resistance, and the upper arm silicon carbide device Q 2 Lower bridge arm silicon carbide device Q 4 The voltage at two ends of the test platform is approximately equal to the output voltage of the front-stage synchronous Boost, and the state equation of the test platform at the stage is shown as the formula (1)
R in formula (1) Q1 Lower bridge arm silicon carbide device Q 1 On-resistance of R Q3 Is an upper bridge arm silicon carbide device Q 3 On-resistance of R L1 Is a power inductance L 1 R, R L2 Is a power inductance L 2 Impedance of V in For input voltage, V 2 Is the output voltage of a front-stage synchronous Boost bridge arm circuit, I L1 Is a power inductance L 1 Is a steady state current of I L2 Is a power inductance L 2 Is set in the above-described state.
(2) B working mode (t) 2 -t 3 ) Not including t 3 Time of day
As shown in FIG. 3B, the second working mode of the aging test platform, namely the mode B, is the lower bridge arm silicon carbide device Q of the bridge arm in the front-stage synchronous Boost bridge arm circuit 1 Still keep the on state, the upper bridge arm silicon carbide device Q of the bridge arm in the synchronous Buck bridge arm circuit of the rear stage 3 Turn off its lower bridge arm silicon carbide device Q 4 Conducting to carry out current follow current, keeping the current flow in the front-stage synchronous Boost bridge arm circuit unchanged, and enabling the current in the rear-stage synchronous Buck bridge arm circuit to sequentially flow through the lower bridge arm silicon carbide device Q 4 And power inductance L 2 At the moment, the capacitor of the later-stage synchronous Buck bridge arm circuit keeps unchanged the current state, and is neither charged nor discharged, and the energy is converted into a power inductance L 2 Providing a power inductance L 2 The energy of the pre-stage synchronous Boost bridge arm circuit is still provided by the pre-stage capacitor, however, the power inductance L 1 And (5) charging. In this stage, the front-stage synchronous Boost bridge arm circuit bridge arm and the rear stage are the sameLower bridge arm silicon carbide device Q of step-type Buck bridge arm circuit bridge arm 1 And Q 4 Is approximately zero, however its respective upper leg silicon carbide device Q 2 And Q 3 The output voltage of the pre-stage synchronous Boost bridge arm circuit is approximately equal to that of the test platform in the mode, and the state equation of the test platform in the mode is shown in a formula (2).
Wherein R is Q1 Lower bridge arm silicon carbide device Q 1 On-resistance of R Q4 Lower bridge arm silicon carbide device Q 4 On-resistance of R L1 Is a power inductance L 1 R, R L2 Is a power inductance L 2 Impedance of V in For input voltage, V 2 Is the output voltage of a front-stage synchronous Boost bridge arm circuit, I L1 Is a power inductance L 1 Is a steady state current of I L2 Is a power inductance L 2 Is set in the above-described state.
(3) D mode of operation (t) 3 -t 4 ) Not including t 4 Time of day
As shown in FIG. 3c, the third working mode of the aging test platform, D mode, is that the pre-stage synchronous Boost bridge arm circuit enters into a follow current state, and the upper bridge arm silicon carbide device Q thereof 2 Follow current is carried out, and silicon carbide device Q of lower bridge arm 1 Turn-off, current flows through the power inductor L 1 And upper bridge arm silicon carbide device Q 2 The method comprises the steps of carrying out a first treatment on the surface of the The later synchronous Buck bridge arm circuit keeps the follow current state in the front B mode. The energy of the front-stage synchronous Boost bridge arm circuit is provided by a power inductor, the inductor discharges, and the energy of the rear-stage synchronous Buck bridge arm circuit is also provided by the power inductor. Under the mode, an upper bridge arm silicon carbide device Q in a front-stage synchronous Boost bridge arm circuit bridge arm 2 And a lower bridge arm silicon carbide device Q in a later stage synchronous Buck bridge arm circuit bridge arm 4 The drain-source voltage is approximately zero due to the conduction state, and the lower bridge arm silicon carbide device Q in the front-stage synchronous Boost bridge arm circuit 1 And synchronous Buck bridge arm of back-endSilicon carbide device Q of upper bridge arm in road 3 The output voltage of the pre-stage synchronous Boost bridge arm circuit is approximated, and the state equation of the test platform in the stage is shown in the formula (3).
R in formula (3) Q2 Is an upper bridge arm silicon carbide device Q 2 On-resistance of R Q4 Lower bridge arm silicon carbide device Q 4 On-resistance of R L1 Is a power inductance L 1 R, R L2 Is a power inductance L 2 Impedance of V in For input voltage, V 2 Is the output voltage of a front-stage synchronous Boost bridge arm circuit, I L1 Is a power inductance L 1 Is a steady state current of I L2 Is a power inductance L 2 Is set in the above-described state.
(4) C working modality (t) 4 -t 5 )
FIG. 3d shows a final operation mode of the burn-in platform, C mode, in which the state of the pre-stage synchronous Boost bridge arm circuit enters a freewheel state, which is formed by the upper bridge arm silicon carbide device Q in the pre-stage synchronous Boost bridge arm circuit bridge arm 2 The current of the front-stage synchronous Boost bridge arm circuit flows through the power inductor L in turn 1 And upper bridge arm silicon carbide device Q 2 The energy of which is represented by power inductance L 1 Providing, power inductance L 1 Is in a discharge state; upper bridge arm silicon carbide device Q in rear synchronous Buck bridge arm circuit bridge arm 3 Conduction and energy is generated by capacitor C of later-stage synchronous Buck bridge arm circuit 2 Providing a power inductance L 2 In a charged state. In this stage, the upper arm silicon carbide device in the front-stage synchronous Boost arm circuit arm and the upper arm silicon carbide device Q in the rear-stage synchronous Buck arm circuit arm 2 And Q 3 The respective lower bridge arm silicon carbide devices Q are in a conducting state and the voltages at the two ends are approximately zero 1 And Q 4 The voltage at two ends is approximately the output voltage of the front-stage synchronous Boost bridge arm circuit, and the test platform is in the stageThe state equation of (2) is shown in the formula (4).
R in formula (4) Q2 Upper bridge arm silicon carbide device Q 2 On-resistance of R Q3 Upper bridge arm silicon carbide device Q 3 On-resistance of R L1 Is a power inductance L 1 R, R L2 Is a power inductance L 2 Impedance of V in For input voltage, V 2 Is the output voltage of a front-stage synchronous Boost bridge arm circuit, I L1 Is a power inductance L 1 Is a steady state current of I L2 Is a power inductance L 2 Is set in the above-described state.
2. Design of test condition setting parameters
(1) Expected target of test working condition
The aging test method of the silicon carbide device can set the switching frequency, the drain-source voltage and the drain current of the tested silicon carbide device, can accelerate the aging of the silicon carbide device under different test working conditions, is suitable for the test working conditions of the silicon carbide device in actual operation, and enables the test result to be closer to the actual working conditions.
(2) Test condition parameter design
The aging test method of the silicon carbide device needs to determine the duty ratio of the back-stage synchronous Buck bridge arm circuit, is fixed, can further determine the voltage class of the test working condition according to the input voltage, and achieves the target of the expected test working condition by adjusting the duty ratio of the silicon carbide device in the front-stage synchronous Boost bridge arm circuit, and the parameter design set for the test working condition is described in detail below.
First, the duty ratio D of the post-stage synchronous Buck bridge arm circuit needs to be determined 2 And determining the input voltage according to the relation between the test working condition voltage and the duty ratio of the post-stage synchronous Buck bridge arm circuit, wherein the input voltage is shown in a formula (5).
According to the power inductance L of the front-stage synchronous Boost bridge arm circuit and the rear-stage synchronous Buck bridge arm circuit in each switching period 1 And L 2 The volt-second characteristic of the silicon carbide device Q of the lower bridge arm can be obtained as shown in the formula (6) 1 Duty cycle of the piece.
D in (6) 1 Silicon carbide device Q for front-stage synchronous Boost type middle and lower bridge arm 1 Duty cycle of D 2 Silicon carbide device Q for rear-stage synchronous Buck type upper arm 3 Duty cycle, I D Is the drain current of four silicon carbide devices.
As shown in fig. 4, equation (6) is simplified to solve for the time relationship of the operation modes. dA is the time of each A working mode in each switching period;in each switching period, the phase difference between the driving waveform of the front-stage synchronous Boost bridge arm circuit and the driving waveform of the rear-stage synchronous Buck bridge arm circuit is formed; dD is the silicon carbide device Q of the lower bridge arm 1 And upper bridge arm silicon carbide device Q 3 The phase relation of the driving signals of the front-stage synchronous Boost bridge arm circuit can be obtained, and the duty ratio of the front-stage synchronous Boost bridge arm circuit can be obtained by solving the equation, as shown in the formula (7).
And according to the time relation of the working modes of the topology, the value range of the phase difference between the driving waveform of the front-stage synchronous Boost bridge arm circuit and the driving waveform of the rear-stage synchronous Buck bridge arm circuit can be determined, as shown in a formula (8).
As can be seen from (7), the upper arm silicon carbide device Q of the later synchronous Buck arm circuit 3 When the duty ratio of the (B) is determined, the voltage class of the test working condition can be determined, and the lower bridge arm silicon carbide device Q of the front-stage synchronous Boost bridge arm circuit 1 The duty ratio of the pre-stage synchronous Boost bridge arm circuit is determined by inputting a test working condition setting target, so that continuous switch test under the set test working condition is carried out on the silicon carbide device, and an aging test result is obtained; the aging test result can be obtained by testing the required corresponding voltage or current through an external corresponding voltage test probe, a current test probe or other test equipment.
3. Simulation verification
(1) Test condition setting
The principle of the aging test method for the silicon carbide device is simulated by adopting placs simulation software, the input voltage is 400V, and specific topological parameters are shown in table 1.
Table 1 simulation topology parameters
The test conditions are set according to actual conditions, and the test conditions set by simulation in the invention are shown in table 2.
Table 2 test operating parameters
From the above test conditions, the duty ratio of the front-stage synchronous Boost bridge arm circuit and the driving waveform phase difference of the power devices of the front-stage synchronous Boost bridge arm circuit and the rear-stage synchronous Buck bridge arm circuit can be set, and the calculation results are shown in table 3.
Table 3 calculation parameters
(2) Simulation results
Aiming at the simulation of the aging test method of the silicon carbide device, four simulation tests under different test conditions are carried out, and the test conditions of four silicon carbide devices under different test conditions are respectively concerned.
(a) First test
The test conditions are set to 800V drain-source voltage, 20A drain current and 100kHz switching frequency, and the grid driving waveform of each silicon carbide device is shown in FIG. 5, so that the aging test platform of the invention works in the state of ABDC mode and V gs Representing the driving voltage.
As shown in fig. 6, the power inductance L 1 And power inductance L 2 Is stabilized at 20A.
As shown in fig. 7, the capacitor C of the synchronous Buck bridge arm circuit of the subsequent stage 2 The voltage is also the output voltage of the front-stage synchronous Boost bridge arm circuit, and the voltage value of the voltage is approximately 800V of the test working condition voltage according to the waveform.
As shown in fig. 8, the waveforms of the drain-source voltage and the drain-source current of the silicon carbide device in the front-stage synchronous Boost bridge arm circuit are shown in fig. 9, and the waveforms of the drain-source voltage and the drain-source current of the silicon carbide device in the rear-stage synchronous Buck bridge arm circuit are shown in the waveforms, in the aging test method of the silicon carbide device, the test working condition of each silicon carbide device is almost the same, and the drain-source voltage and the drain-source current of each silicon carbide device accord with the set values of the expected test working condition, namely 800V and 20A.
As shown in fig. 10, the power supply current waveform is shown, the power supply current is 0, and after the power supply gives out instantaneous excitation only when the test platform is started, the energy circulates in the test platform, and the power supply is not used for supplying energy to the test platform, so that the function of energy feedback is realized.
(b) Second test
As shown in fig. 11, in the second test, the test conditions were set to a drain-source voltage of 800V, a drain current of 30A, and a switching frequency of 100kHz, which is the gate driving waveform of each silicon carbide device.
As shown in fig. 12, it can be seen from the driving waveform that when driving according to the calculated duty ratio of the front-stage synchronous Boost bridge arm circuit, the working mode is an ABDC mode, which accords with the working principle of the aging test method of the silicon carbide device of the present invention, fig. 12 is a current waveform of the power inductor, the current of which is set value 30A, and which accords with the test working condition.
As shown in fig. 13, the test condition of the silicon carbide device in the front-stage synchronous Boost bridge arm circuit and the test condition of the silicon carbide device in the rear-stage synchronous Buck bridge arm circuit are shown in fig. 14, it can be seen that each silicon carbide device is under the set test working conditions, namely 800V, 30A and 100kHz, so that the accelerated aging test can be performed on each silicon carbide device under the test working conditions.
(c) Third test
The set test conditions of the third test are as follows: drain-source voltage 800V, drain current 40A, switching frequency 100kHz, wherein the gate drive waveform for each silicon carbide device is shown in fig. 15. Through driving waveforms, the aging test platform can be seen to normally operate according to the ABDC mode, and the duty ratio is a theoretical calculated value.
As shown in fig. 16, the current waveform of the power inductor, the current 40A of the test condition, is consistent with the theoretical calculation value.
As shown in fig. 17, the drain voltage and drain current of the silicon carbide device in the front-stage synchronous Boost bridge arm circuit are shown, while the drain voltage and drain current of the silicon carbide device in the rear-stage synchronous Buck bridge arm circuit are shown in fig. 18, and it can be seen that the drain voltage is 800V, the drain current is 40A, and the switching frequency is 100kHz under the set test condition.
(d) Fourth test
In the fourth test, the test conditions were set to 800V drain-source voltage, 50A drain current, and 100kHz switching frequency, and the driving waveforms of each silicon carbide device, as shown in fig. 19, it can be seen that the burn-in test platform was operated in the ABDC mode, in accordance with the theoretical analysis described above.
As shown in fig. 19, the phase relationship and the duty ratio are in accordance with the theoretical calculation value, and the current of the power inductor is also in accordance with the calculation value 50A, and the current waveform of the power inductor is shown in fig. 20.
As shown in fig. 21, the drain voltage and drain current of the silicon carbide device in the front-stage synchronous Boost bridge arm circuit are shown in fig. 22, and each silicon carbide device is under the same test condition, and the test condition accords with the set test condition, so that the accelerated aging test of the silicon carbide device can be performed by using the aging test method of the silicon carbide device.
In the simulation circuit, the silicon carbide MOSFET is arranged in the bridge arm type structure circuit, the problem of long-term reliability of the silicon carbide device under the operation of applying dynamic continuous switching is considered, and the influence of crosstalk on the gate oxide reliability of the silicon carbide device is fully considered, so that the test result of the silicon carbide aging test method is closer to the actual application condition of the silicon carbide device, and the accuracy degree of the aging test result is improved.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the invention, and that equivalent modifications and variations of the invention in light of the spirit of the invention will be covered by the claims of the present invention.
Claims (5)
1. A silicon carbide device aging test method is characterized in that: comprising the following steps: the test platform takes a synchronous cascading Boost-Buck as a topological bridge arm type structure circuit and comprises a front-stage synchronous Boost bridge arm circuit and a rear-stage synchronous Buck bridge arm circuit, and the front-stage synchronous Boost bridge arm circuit and the rear-stage synchronous Buck bridge arm circuit are cascaded;
the direct current power supply is input into the front-stage synchronous Boost bridge arm circuit through a diode and is connected with the output end of the rear-stage synchronous Buck bridge arm circuit; the direct current power supply is arranged according to a test working condition, and the test platform realizes the circulating flow of energy in the test platform through the power inductance of the front-stage synchronous Boost bridge arm circuit and the power inductance of the rear-stage synchronous Buck bridge arm circuit;
by setting the working mode of the test platform and setting the switching frequency, drain-source voltage and drain current of the tested silicon carbide device, the aging of the silicon carbide device is accelerated under different test working conditions, and an aging test result is obtained.
2. The method for burn-in testing a silicon carbide device according to claim 1, wherein: the method comprises the steps that silicon carbide devices are placed in a front-stage synchronous Boost bridge arm circuit and a rear-stage synchronous Buck bridge arm circuit, the front-stage synchronous Boost bridge arm circuit is used for placing two silicon carbide devices in an upper bridge arm and a lower bridge arm respectively, and the rear-stage synchronous Buck bridge arm circuit is used for placing two silicon carbide devices in the upper bridge arm and the lower bridge arm respectively.
3. The method for burn-in testing a silicon carbide device according to claim 1, wherein: the test platform comprises a direct current power supply and a diode BD;
the front-stage synchronous Boost bridge arm circuit comprises: capacitor C 1 Power inductance L 1 Silicon carbide device Q of lower bridge arm 1 First driving unit, upper bridge arm silicon carbide device Q 2 A second driving unit;
the back-stage synchronous Buck bridge arm circuit comprises: capacitor C 2 Power inductance L 2 Upper bridge arm silicon carbide device Q 3 Third drive unit, lower bridge arm silicon carbide device Q 4 A fourth driving unit;
the positive electrodes of the direct current power supply are respectively connected with the capacitor C through the diode BD 1 One end of (2)Part, power inductance L 1 One end of (a) and a power inductor L 2 Is provided; the negative electrode of the direct current power supply is respectively connected with the capacitor C 1 Another end of (a) lower bridge arm silicon carbide device Q 1 Source, capacitance C of (2) 2 One end of (a) and a lower arm silicon carbide device Q 4 A source of (a); the power inductance L 1 Is connected to the upper bridge arm silicon carbide device Q 2 Is a lower bridge arm silicon carbide device Q 1 The upper bridge arm silicon carbide device Q 2 The drains of the capacitors are respectively connected with the capacitor C 2 Another end of (a) and an upper arm silicon carbide device Q 3 The drain electrode of the power inductance L 2 Is respectively connected with the silicon carbide device Q of the upper bridge arm at the other end part 3 Is a lower bridge arm silicon carbide device Q 4 A drain electrode of (2); the first driving unit is used for driving the lower bridge arm silicon carbide device Q 1 The second driving unit is used for driving the upper bridge arm silicon carbide device Q 2 The third driving unit is used for driving the upper bridge arm silicon carbide device Q 3 The fourth driving unit is used for driving the lower bridge arm silicon carbide device Q 4 。
4. The method for burn-in testing a silicon carbide device according to claim 2, wherein: the working modes of the test platform sequentially comprise an A working mode, a B working mode, a D working mode and a C working mode; the A working mode is at time t 1 -t 2 The method comprises the steps of carrying out a first treatment on the surface of the The B working mode is at time t 3 -t 4 The method comprises the steps of carrying out a first treatment on the surface of the The D working mode is at time t 4 -t 5 The method comprises the steps of carrying out a first treatment on the surface of the The C working mode is at time t 5 -t 6 ；
The working mode A is as follows:
lower bridge arm silicon carbide device Q of front-stage synchronous Boost bridge arm circuit 1 Upper bridge arm silicon carbide device Q of back-stage synchronous Buck bridge arm circuit 3 The current of the front-stage synchronous Boost bridge arm circuit flows through the power inductor L in turn 1 Lower bridge arm silicon carbide device Q 1 The current of the later synchronous Buck bridge arm circuit sequentially flows through Bridge arm silicon carbide device Q 3 And power inductance L 2 Capacitance C 1 And capacitor C 2 All discharge, power inductance L 1 And L 2 Charging is carried out;
the working mode B is as follows:
lower bridge arm silicon carbide device Q of front-stage synchronous Boost bridge arm circuit 1 Upper bridge arm silicon carbide device Q of rear synchronous Buck bridge arm circuit maintaining on state 3 Turn off its lower bridge arm silicon carbide device Q 4 Conducting to carry out current follow current, keeping the current flow in the front-stage synchronous Boost bridge arm circuit unchanged, and enabling the current in the rear-stage synchronous Buck bridge arm circuit to sequentially flow through the lower bridge arm silicon carbide device Q 4 And power inductance L 2 Capacitance C at this time 2 The current state is kept unchanged, the energy is neither charged nor discharged, and the energy is converted into a power inductance L 2 Providing a power inductance L 2 Discharging, and energy of front-stage synchronous Boost bridge arm circuit is represented by capacitor C 1 Providing, power inductance L 1 Charging;
the D working mode is as follows:
the front-stage synchronous Boost bridge arm circuit enters into a follow current state, and the upper bridge arm silicon carbide device Q thereof 2 Follow current is carried out, and silicon carbide device Q of lower bridge arm 1 Turn-off, current flows through the power inductor L 1 And upper bridge arm silicon carbide device Q 2 The method comprises the steps of carrying out a first treatment on the surface of the The later synchronous Buck bridge arm circuit keeps the follow current state in the B working mode; wherein the energy of the front-stage synchronous Boost bridge arm circuit is represented by a power inductance L 1 Providing, power inductance L 1 Discharging, and the energy of the later-stage synchronous Buck bridge arm circuit is converted into a power inductance L 2 Providing;
the working mode C is as follows:
the state of the front-stage synchronous Boost bridge arm circuit enters into a follow current state, and the follow current state is formed by an upper bridge arm silicon carbide device Q of the front-stage synchronous Boost bridge arm circuit 2 The current of the front-stage synchronous Boost bridge arm circuit flows through the power inductor L in turn 1 And upper bridge arm silicon carbide device Q 2 The energy of which is represented by power inductance L 1 Providing, power inductance L 1 For puttingAn electrical state; upper bridge arm silicon carbide device Q of rear synchronous Buck bridge arm circuit 3 On, energy is transferred by capacitor C 2 Providing a power inductance L 2 In a charged state.
5. The method for burn-in testing a silicon carbide device according to claim 1, wherein: the aging of the silicon carbide device is accelerated under different test working conditions by setting the working mode of the test platform and setting the switching frequency, the drain-source voltage and the drain current of the tested silicon carbide device, and the obtained aging test result is further specifically as follows: the duty ratio of a back-stage synchronous Buck bridge arm circuit is determined, the duty ratio is fixed, the voltage class of a test working condition is determined according to the input voltage of a direct current power supply, and the target of the preset test working condition is realized by adjusting the duty ratio of a silicon carbide device in a front-stage synchronous Boost bridge arm circuit;
First, the duty ratio D of the post-stage synchronous Buck bridge arm circuit is determined 2 And determining the input voltage of the direct current power supply according to the relation between the test working condition voltage and the duty ratio of the post-stage synchronous Buck bridge arm circuit, as shown in formula (5)
In the formula (5), V in Is the input voltage of the direct current power supply, V 2 The output voltage of the front-stage synchronous Boost bridge arm circuit is calculated according to the power inductance L of the front-stage synchronous Boost bridge arm circuit and the rear-stage synchronous Buck bridge arm circuit in each switching period 1 And L 2 The volt-second characteristic of the silicon carbide device is shown as (6), and the silicon carbide device Q of the lower bridge arm is obtained 1 Duty cycle of (2);
d in (6) 1 Silicon carbide device Q for lower bridge arm in front-stage synchronous Boost bridge arm circuit 1 Duty cycle of D 2 Silicon carbide device Q for upper bridge arm in back-stage synchronous Buck bridge arm circuit 3 Duty cycle, I D Drain currents for four silicon carbide devices;
simplifying and solving the formula (6) according to the time relation of each working mode, wherein,in each switching period, the phase difference between the driving waveform of the front-stage synchronous Boost bridge arm circuit and the driving waveform of the rear-stage synchronous Buck bridge arm circuit is formed; calculating to obtain the duty ratio of a front-stage synchronous Boost bridge arm circuit, as shown in a formula (7);
according to the time relation of the working modes, determining the value range of the phase difference between the driving waveform of the front-stage synchronous Boost bridge arm circuit and the driving waveform of the rear-stage synchronous Buck bridge arm circuit, wherein the value range is shown as a formula (8);
As can be seen from (7), the upper arm silicon carbide device Q of the later synchronous Buck arm circuit 3 When the duty ratio of the (B) is determined, the voltage class of the test working condition is determined, and the lower bridge arm silicon carbide device Q of the front-stage synchronous Boost bridge arm circuit 1 The duty ratio of the front-stage synchronous Boost bridge arm circuit is determined through the setting target of the input test working condition, so that the continuous switch test is performed on the silicon carbide device under the set test working condition, and the aging test result is obtained.
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| CN117148092A (en) * | 2023-11-01 | 2023-12-01 | 深圳基本半导体有限公司 | Test method and device for accelerating bipolar degradation of SiC MOSFET |
| CN117148092B (en) * | 2023-11-01 | 2024-03-12 | 深圳基本半导体有限公司 | Test method and device for accelerating bipolar degradation of SiC MOSFET |
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