CN116953313A - Probe card and packaging method of transducer of probe card - Google Patents
Probe card and packaging method of transducer of probe card Download PDFInfo
- Publication number
- CN116953313A CN116953313A CN202310893632.4A CN202310893632A CN116953313A CN 116953313 A CN116953313 A CN 116953313A CN 202310893632 A CN202310893632 A CN 202310893632A CN 116953313 A CN116953313 A CN 116953313A
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- metal
- converter
- layer
- probes
- probe card
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- 239000000523 sample Substances 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 134
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000000149 penetrating effect Effects 0.000 claims abstract description 3
- 238000001259 photo etching Methods 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000004140 cleaning Methods 0.000 claims description 12
- 238000009713 electroplating Methods 0.000 claims description 12
- 210000001503 joint Anatomy 0.000 claims description 11
- 238000004528 spin coating Methods 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 4
- 230000007797 corrosion Effects 0.000 claims description 4
- 238000003491 array Methods 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 2
- 238000012360 testing method Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The application discloses a probe card and a packaging method of a converter of the probe card, wherein the probe card comprises a PCB (printed circuit board), a converter and a plurality of probes, one side surface of the PCB is provided with a bonding pad array, the converter is provided with a first surface butted with the bonding pad array and a second surface butted with the plurality of probes, the converter comprises a substrate, a plurality of metal pins penetrating through the substrate and a rewiring layer formed on the second surface, the plurality of metal pins are arranged in one-to-one correspondence with the bonding pad array, a plurality of metal connecting pieces are arranged on the rewiring layer, one end part of each metal connecting piece is respectively in one-to-one butting connection with the plurality of metal pins, and the other end part of each metal connecting piece is respectively in one-to-one butting connection with the plurality of probes. According to the application, the rewiring layer on the substrate is redistributed by a packaging method according to the positions of a plurality of probes butted with the chip to be tested, and the rewiring layer is matched with the metal connectors butted with a plurality of metal pins and the probe array, so that the probe card has high suitability, and the packaging method is simple to operate and has faster timeliness.
Description
Technical Field
The present application relates to the field of semiconductor manufacturing technology, and in particular, to a probe card and a method for packaging a transducer of the probe card.
Background
The probe card is an interface between the connection ATE (Automatic Test Equipment) test machine and the semiconductor wafer, and is a necessary device for realizing the test of the wafer CP (Chip probing). In the CP test process, the ATE test machine cannot directly measure the wafer, and after the probe (probe) in the probe card contacts with the pad or bump (bump) on the wafer, electrical connection with the chip (chip) in the wafer is established, so as to achieve the purpose of electrical performance test.
The probe card comprises a PCB and a plurality of probes, wherein the PCB is an intermediate component for connecting the PCB and the probes. In the prior art, metal contacts on a PCB of a probe card are generally arranged in a pad array mode, a plurality of probes are required to be matched with the arrangement of chips to be tested, the adapter plate plays a role in middle transition, but the probe card cannot be suitable for chips in different packaging modes.
Disclosure of Invention
In order to solve the problem that the probe card in the prior art cannot adapt to chips in different packaging forms, the application aims to provide a probe card and a packaging method of a converter of the probe card.
In order to achieve the above purpose, the application adopts the following technical scheme: the utility model provides a probe card, includes PCB board, converter and a plurality of probe, one side surface of PCB board be formed with the pad array, the converter have with the first surface of pad array butt joint and with a plurality of probe butt joint's second surface, the converter include the base plate, run through a plurality of metal pins of base plate and the rewiring layer of formation on the second surface of converter, a plurality of metal pins and the pad array on the PCB board arrange, the rewiring layer on have a plurality of metal and connect the guide, a tip of metal connect the guide respectively with a plurality of metal pins on the converter arrange and electric conduction one by one, another tip of metal connect the guide respectively with a plurality of probes arrange and conduction one by one.
In the above technical solution, it is further preferable that the transducer is a ceramic transducer.
In the above technical solution, it is further preferable that the land array of the PCB board is a BGA land array.
In the above technical solution, it is further preferable that the arrangement positions of the plurality of probes are in one-to-one correspondence with the positions of the soldering pins of the chip to be tested.
The application also provides a packaging method of the converter of the probe card, wherein the converter is provided with a first surface butted with the PCB pad array and a second surface butted with a plurality of probes, and a plurality of metal connectors respectively connected with a plurality of metal pins and a plurality of probes on the converter are formed on the second surface of the converter through a rewiring process, and the leading-out ends of the metal connectors are in one-to-one correspondence with the distribution positions of the plurality of probes.
In the above technical solution, it is further preferable that the method includes the steps of:
s1, cleaning the surface of the converter, manufacturing a first seed layer on the second surface, and photoetching by using a first mask;
s2, electroplating the first metal, and forming a first metal layer after photoresist removal and corrosion;
s3, spin-coating a first photoresist layer on the surface of the first metal layer, and carrying out photoetching by using a second mask plate to form a plurality of first through holes connected with the first metal layer, wherein the first through holes deviate from the positions of metal pins of the converter, and a first dielectric layer is formed after the first photoresist layer is solidified;
s4, carrying out organic cleaning on the converter, and manufacturing a second seed layer on the surface of the first dielectric layer;
s5, photoetching on the second seed layer by using a third mask plate to form windows at the positions corresponding to the plurality of first through holes;
s6, electroplating first metal to form a first metal lead which is electrically connected with the first metal layer in the first through hole;
s7, grinding the converter.
In the above technical solution, it is further preferable that after step S7, the method further includes the following steps:
s8, carrying out organic cleaning on the converter, and continuously manufacturing a third seed layer on the second surface;
s9, photoetching by using a fourth mask plate to form a plurality of windows corresponding to the plurality of first metal leads respectively;
s10, electroplating second metal, removing photoresist and corroding to form a second metal layer which is electrically connected with the plurality of first metal leads;
s11, continuously spin-coating a second photoresist on the second metal layer, forming a plurality of second through holes communicated with the second metal layer by utilizing a fifth mask plate for photoetching, and curing the second photoresist to form a second dielectric layer;
s12, carrying out organic cleaning on the converter again, and manufacturing a third seed layer on the surface of the second dielectric layer;
s13, photoetching by using a sixth mask plate, and forming a plurality of windows at the second through holes respectively;
s14, electroplating second metal to form a plurality of second metal leads which are electrically connected with the second metal layer in the second through holes;
s15, grinding the converter.
Compared with the prior art, the application has the following beneficial effects:
according to the probe card, the metal pins on the converter are rewiring and reassigning through the packaging method according to the positions of the plurality of probes butted with the chip to be tested, so that the plurality of metal connectors butted with the metal pins are matched with the probe array, the suitability of the probe card is high, and the packaging method is simple to operate.
Drawings
Fig. 1 to 14 are schematic structural views of steps of a packaging method according to an embodiment of the present application.
Wherein: 10. a converter; 101. a first surface; 102. a second surface; 1. a substrate; 2. a metal pin; 3. rewiring layers; 4. a metal connector; 41. a first metal layer; 42. a first metal lead; 43. a second metal layer; 44. a second metal lead; 5. a first dielectric layer; 51. a first through hole; 6. a second dielectric layer; 61. and a second through hole.
Detailed Description
In order to describe the technical content, constructional features, objects and effects of the application in detail, the technical solutions of the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments of the present application. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a detailed description of various exemplary embodiments or implementations of the application. However, various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, the specific shapes, configurations, and characteristics of the exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.
Hereinafter, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the present application, unless explicitly specified and limited otherwise, the term "connected" is to be construed broadly, and for example, "connected" may be either fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium.
The application provides a probe card, which comprises a PCB board, a transducer and a plurality of probes, wherein the transducer is arranged between the PCB board and the probes. A land array is formed on one side surface of the PCB board, and as shown in fig. 1, the transducer has a first surface 101 interfacing with the land array and a second surface 102 interfacing with a number of probes.
As shown in fig. 1 and 14, the converter 10 includes a substrate 1, a plurality of metal pins 2 penetrating the substrate 1, and a rewiring layer 3 formed on the second surface 102, where the plurality of metal pins 2 are configured to be arranged in one-to-one correspondence with the pad array on the PCB board, so as to realize that the plurality of metal pins 2 are in one-to-one opposite and electrically conductive connection with the pad array when the converter 10 is docked with the PCB board. The rewiring layer 3 is internally provided with a plurality of metal connectors 4, one end of each metal connector 4 is respectively in butt joint and conduction with a plurality of metal pins 2 on the substrate 1, and the other end is respectively in butt joint and conduction with a plurality of probes. When the converter 10 is in butt joint with the PCB and the probes, the bonding pad array, the metal pins 2, the metal connectors 4 and the probes are in butt joint in sequence, so that the electrical conduction between the PCB and the probes is realized.
The rewiring technology changes the pin position of the integrated circuit chip/packaging substrate which is originally designed through the wafer level or MEMS metal rewiring layer manufacturing process and the bump manufacturing process, so that the probe card can be suitable for different packaging forms.
The positions of the plurality of metal pins 2 on the substrate 1 are arranged according to the pad array of the PCB board, the positions of the lead-in ends of the plurality of metal contacts 4 of the converter 10 are arranged according to the positions of the plurality of metal pins 2, and the positions of the lead-out ends of the metal contacts 4 are arranged according to the positions of the plurality of probes. The converter 10 of the application realizes the electric connection between the PCB and the probes of different probe arrays by changing the positions of the leading-out ends of the metal connectors 4 between the PCB and the probes, thereby improving the suitability of the probe card.
In the embodiment of the present application, the transducer 10 is a ceramic transducer, and the substrate made of ceramic has excellent electrical insulation properties, high heat conduction characteristics, excellent soldering property and high adhesion strength. The pad array of the PCB is a BGA pad array, and the arrangement positions of the probes are in one-to-one correspondence with the welding pin positions of the chip to be tested, so that the electric connection between the chip to be tested and the PCB is realized.
The application also provides a packaging method of the converter for the probe card, which comprises the steps of forming a plurality of metal connectors 4 respectively connected with a plurality of metal pins 2 and a plurality of probes on the second surface 102 of the converter through a rewiring process, wherein the leading-out ends of the metal connectors 4 are in one-to-one correspondence with the distribution positions of the plurality of probes, so that when the converter 10 is in butt joint with the probes, the metal connectors 4 are in butt joint with the corresponding probes to realize conductive connection.
The packaging method comprises the following steps:
s1, cleaning the surface of the converter 10, manufacturing a first seed layer on the second surface 102, and performing photoetching by using a first mask (refer to FIG. 1);
s2, electroplating the first metal, and forming a first metal layer 41 (refer to FIG. 2 and FIG. 3) after photoresist removal and corrosion;
s3, spin-coating a first photoresist layer on the surface of the first metal layer 41, performing photoetching by using a second mask plate to form a plurality of first through holes 51 connected with the first metal layer 41, wherein the first through holes 51 deviate from the positions of the metal pins 2 of the converter 10, and the first photoresist layer is solidified to form a first dielectric layer 5 (refer to FIG. 4);
s4, carrying out organic cleaning on the converter 10, and manufacturing a second seed layer on the surface of the first dielectric layer 5;
s5, photoetching on the second seed layer by utilizing a third mask plate, so that windows are formed at corresponding positions of the plurality of first through holes 51 (refer to FIG. 5);
s6, electroplating the first metal to form a first metal lead 42 (refer to FIG. 6) electrically connected with the first metal layer 41 in the first through hole 51;
s7, grinding the converter to ensure that the leading-out end of the first metal lead 42 is flush with the surface of the ground first dielectric layer 5 (refer to FIG. 7);
s8, carrying out organic cleaning on the converter, and continuously manufacturing a third seed layer on the second surface;
s9, forming a plurality of windows corresponding to the plurality of first metal leads 42 respectively by using a fourth mask plate for photoetching (refer to FIG. 8);
s10, electroplating a second metal, photoresist removing and corrosion, and forming a second metal layer 43 (refer to fig. 9 and 10) which is electrically connected with a plurality of first metal leads 42;
s11, continuously spin-coating a second photoresist on the second metal layer 43, forming a plurality of second through holes 61 communicated with the second metal layer 43 by utilizing fifth mask photoetching, and curing the second photoresist to form a second dielectric layer 6 (refer to FIG. 11);
s12, performing organic cleaning on the converter again, and manufacturing a third seed layer on the surface of the second medium layer 6;
s13, photoetching by using a sixth mask plate, and forming a plurality of windows at a plurality of second through holes 61 respectively (refer to FIG. 12);
s14, electroplating second metal to form second metal leads 44 (refer to FIG. 13) electrically connected with the second metal layers 43 in the second through holes 61;
s15, grinding the converter to form a flat surface (see fig. 14).
As shown in fig. 13 and 14, the metal connector 4 includes a first metal layer 41, a first metal lead 42, a second metal layer 43, and a second metal lead 44, and the first metal layer 41, the first metal lead 42, the second metal layer 43, and the second metal lead 44 in the rewiring layer 3 are electrically connected in order.
Before step S1, the measurement needs to be performed on the plurality of metal pins 2 and the plurality of probes on the substrate 1, the measurement includes measuring the positions and the sizes of the metal pins 2 and the probes, and manufacturing a first mask, a second mask, a third mask, a fourth mask, a fifth mask and a sixth mask according to the measurement results, so that the opening positions of the through holes on the rewiring layer 3 are accurate, the positions of the first metal layer 41, the first metal lead 42, the second metal layer 43 and the second metal lead 44 are accurately arranged, the metal pins 2, the first metal layer 41, the first metal lead 42, the second metal layer 43 and the second metal lead 44 can be sequentially connected in a conductive manner, and the lead-out ends of the second metal lead 44 are ensured to be matched with the probe array.
The grinding techniques in step S7 and step S15 are chemical mechanical polishing techniques, and step S7 and step S15 respectively perform chemical mechanical polishing on the surface of the transducer 10, so that the transducer 10 obtains a surface that is flat and free from scratches and contamination, and the transducer 10 is convenient for the next process.
According to the converter 10 in the probe card, the rewiring layer 3 on the substrate 1 is redistributed by the packaging method according to the positions of the probes butted with the chip to be tested, so that the leading-out ends of the metal connectors 4 correspond to the probes one by one, namely, the metal connectors 4 of the converter 10 are matched with the probe array, and when the converter 10 is butted with the PCB and the probes, the converter 10 is in conductive connection with the PCB and the probes. After the converter 10 in the probe card is packaged by the method, the lead-in end of the metal connector 4 is in butt joint with a plurality of metal pins 2 of the converter 10, the position of the lead-out end of the metal connector 4 is redistributed according to the position of the probe array, and finally the metal connector 4 is matched with the pad array of the PCB and the probe arrays of a plurality of probes.
The foregoing has shown and described the basic principles, principal features and advantages of the application. It will be understood by those skilled in the art that the present application is not limited to the foregoing embodiments, which have been described in the foregoing embodiments and description merely illustrates the principles of the application, and various changes and modifications may be made therein without departing from the spirit and scope of the application, the scope of which is defined in the appended claims, specification and their equivalents.
Claims (7)
1. The utility model provides a probe card, includes PCB board, converter and a plurality of probe, one side surface of PCB board be formed with the pad array, the converter have with the first surface of pad array butt joint and with a plurality of probe butt joint's second surface, its characterized in that: the converter comprises a substrate, a plurality of metal pins penetrating through the substrate and a rewiring layer formed on the second surface of the converter, wherein the metal pins are arranged in one-to-one correspondence with the bonding pad arrays on the PCB, the rewiring layer is provided with a plurality of metal connecting pieces, one end part of each metal connecting piece is respectively arranged in one-to-one correspondence with the metal pins on the converter and is electrically communicated with the metal pins, and the other end part of each metal connecting piece is respectively arranged in one-to-one correspondence with the probes and is electrically communicated with the probes.
2. A probe card according to claim 1, wherein: the converter is a ceramic converter.
3. A probe card according to claim 1, wherein: the pad array of the PCB is a BGA pad array.
4. A probe card according to claim 1, wherein: the arrangement positions of the probes are in one-to-one correspondence with the welding pin positions of the chip to be tested.
5. A method for packaging a transducer of a probe card, the transducer having a first surface interfacing with an array of pads of a PCB and a second surface interfacing with a plurality of probes, the method comprising: and forming a plurality of metal connectors respectively connecting the plurality of metal pins on the converter with the plurality of probes on the second surface of the converter through a rewiring process, wherein the leading-out ends of the metal connectors are in one-to-one correspondence with the distribution positions of the plurality of probes.
6. The packaging method according to claim 5, comprising the steps of:
s1, cleaning the surface of the converter, manufacturing a first seed layer on the second surface, and photoetching by using a first mask;
s2, electroplating the first metal, and forming a first metal layer after photoresist removal and corrosion;
s3, spin-coating a first photoresist layer on the surface of the first metal layer, and carrying out photoetching by using a second mask plate to form a plurality of first through holes connected with the first metal layer, wherein the first through holes deviate from the positions of metal pins of the converter, and a first dielectric layer is formed after the first photoresist layer is solidified;
s4, carrying out organic cleaning on the converter, and manufacturing a second seed layer on the surface of the first dielectric layer;
s5, photoetching on the second seed layer by using a third mask plate to form windows at the positions corresponding to the plurality of first through holes;
s6, electroplating first metal to form a first metal lead which is electrically connected with the first metal layer in the first through hole;
s7, grinding the converter.
7. The packaging method according to claim 6, further comprising the step of, after step S7:
s8, carrying out organic cleaning on the converter, and continuously manufacturing a third seed layer on the second surface;
s9, photoetching by using a fourth mask plate to form a plurality of windows corresponding to the plurality of first metal leads respectively;
s10, electroplating second metal, removing photoresist and corroding to form a second metal layer which is electrically connected with the plurality of first metal leads;
s11, continuously spin-coating a second photoresist on the second metal layer, forming a plurality of second through holes communicated with the second metal layer by utilizing a fifth mask plate for photoetching, and curing the second photoresist to form a second dielectric layer;
s12, carrying out organic cleaning on the converter again, and manufacturing a third seed layer on the surface of the second dielectric layer;
s13, photoetching by using a sixth mask plate, and forming a plurality of windows at the second through holes respectively;
s14, electroplating second metal to form a plurality of second metal leads which are electrically connected with the second metal layer in the second through holes;
s15, grinding the converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310893632.4A CN116953313A (en) | 2023-07-20 | 2023-07-20 | Probe card and packaging method of transducer of probe card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310893632.4A CN116953313A (en) | 2023-07-20 | 2023-07-20 | Probe card and packaging method of transducer of probe card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116953313A true CN116953313A (en) | 2023-10-27 |
Family
ID=88447157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310893632.4A Pending CN116953313A (en) | 2023-07-20 | 2023-07-20 | Probe card and packaging method of transducer of probe card |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116953313A (en) |
-
2023
- 2023-07-20 CN CN202310893632.4A patent/CN116953313A/en active Pending
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