CN116940720A - Seed substrate for epitaxial growth and method for producing same, and semiconductor substrate and method for producing same - Google Patents
Seed substrate for epitaxial growth and method for producing same, and semiconductor substrate and method for producing same Download PDFInfo
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Abstract
The purpose is to obtain a high quality and inexpensive composition containing few crystal defects such as AlN, al x Ga 1‑x N(0<X<1) And a seed substrate for epitaxial growth of group III nitride such as GaN and the like, and for scale-free epitaxial growth. The seed substrate for epitaxial growth includes a support substrate, a planarization layer of 0.5 to 3 μm provided on an upper surface of the support substrate, and a seed layer provided on an upper surface of the planarization layer. The support substrate includes a core comprising a group III nitride polycrystalline ceramic and an encapsulation layer of 0.05 to 1.5 μm encapsulating the core. By inducing stacking faults by oxidation10 pieces/cm 2 The following Si<111>A seed layer is provided by performing thin film transfer on a surface layer of 0.1 to 1.5 μm of the single crystal.
Description
Technical Field
The present invention relates to a material such as aluminum nitride (AlN), aluminum gallium nitride (Al) x Ga 1-x N(0<x<1) Group III nitride with few defects such as gallium nitride (GaN) and excellent characteristics, and a seed substrate for epitaxial growth without scale, and a method for producing the same. More specifically, it relates to a high quality and inexpensive material such as AlN, A with little crystal defects, warpage and voids lx Ga 1-x N(0<X<1) A seed substrate for epitaxial growth of group III nitride such as GaN and a method for producing the same.
Background
The group III nitride crystal substrate such as AlN and GaN has a wide band gap, and has a light-emitting property of a short wavelength and excellent high-frequency characteristics under high withstand voltage. Therefore, the group III nitride substrate is expected to be applied to devices such as Light Emitting Diodes (LEDs), lasers, schottky diodes, power devices, and high frequency devices. For example, with respect to an AlN-based crystal substrate, due to recent epidemic of coronaviruses and the like, alN and/or Al are particularly used for the purpose of removing bacteria and viruses x Ga 1-X N(0.5<X<1) The deep ultraviolet region (UVC; 200-280 nm) is increasing. However, at present these AlN and/or Al x Ga 1-X N(0.5<X<1) The single crystal substrate of (a) has many defects, and various devices manufactured by the method have no expected characteristics at low quality and high price. Therefore, the wide spread and expansion of the use of these substrates is limited. On the other hand, the GaN-based crystal substrate followsWith the start of 5G communication and the progress of EV of vehicles, higher high-frequency characteristics and larger withstand voltage performance are demanded. As a result, there is also a great demand for epitaxial and scale-free GaN-based crystal substrates having few crystal defects at low cost. However, gaN-based crystal substrates have many crystal defects and have low quality, similar to AlN-based substrates, but they are expensive. Therefore, the wide use of the GaN-based substrate for devices is hindered, and further improvement is desired.
For example, as described in non-patent document 1 and non-patent document 2, alN has no melting point, so it is difficult to produce an AlN single crystal substrate by a melting method commonly used for silicon (Si) single crystals or the like. They are therefore usually produced by sublimation (Raleigh method) using silicon carbide (SiC) or AlN as seed, at 1700 to 2250deg.C, at N 2 The manufacturing is carried out under atmosphere. Alternatively, as disclosed in patent document 1 and non-patent document 3, they are produced by a Hydride Vapor Phase Epitaxy (HVPE) method on a sapphire substrate or an AlN substrate obtained by a sublimation method. Since AlN single crystals manufactured by the sublimation method require high temperature at the time of crystal growth, only small-diameter substrates having diameters of 2 to 4 inches are currently available due to the limitations of equipment, and they are very expensive. The dislocation density of the AlN single crystal obtained was<10 5 cm -2 The crystals are colored by contamination with carbon and metal impurities originating from, for example, charcoal materials such as crucibles and insulating materials, but on the other hand, have the disadvantage of low resistivity and low UV transmittance. On the other hand, alN single crystals manufactured by a Hydride Vapor Phase Epitaxy (HVPE) method on a sapphire substrate are relatively inexpensive and little colored, but dislocation density of the AlN crystal is high and resistivity is low due to the difference in lattice constant between AlN and sapphire. AlN crystals obtained by HVPE deposition on sublimation-process AlN substrates have relatively low dislocation density, but are opaque to deep UV light emission, and have low resistivity due to contamination of the colorant from the base substrate AlN. In addition, since the expensive sublimation AlN crystal is used as a base substrate serving as a seed crystal, it has a disadvantage of extremely high cost.
For GaN substrates, bulk GaN substrates produced by growing GaN crystals in liquid such as liquid ammonia or Na flux have relatively few defects and high quality, but they are extremely expensive because of the need for high-temperature and high-pressure equipment. In addition, the AlN substrate is used as a base substrate serving as a seed crystal as it is, similarly to the AlN substrate by the sublimation method, and therefore, the cost is extremely high. On the other hand, if the sapphire substrate and other substrates are epitaxially grown using the MOCVD method or the hydride vapor phase epitaxy method (HVPE method, or THVPE method) for growing crystals in the vapor phase, in principle, it is possible to achieve a high quality or a large size of crystals. However, in practice, since the lattice constant and the thermal expansion coefficient are significantly different between the generated GaN crystal and the sapphire of the base substrate, a large number of crystal defects and cracks are generated during production, and high quality crystals cannot be obtained.
As one of solutions to these problems, patent document 2 discloses a so-called QST (trade name) substrate having a ceramic core with AlN and a silicon oxide film made of SiO 2 /P-Si/SiO 2 /Si 3 N 4 Support substrate of encapsulating layer of AlN ceramic core by multilayer film, such as SiO on upper surface of support substrate 2 A planarization layer and a film on the upper surface of the planarization layer, to which Si is transferred <111>A seed layer as a seed.
However, this method tends to produce differences in thermal expansion coefficients between the various multilayer films that encapsulate the core, or between the encapsulation layer, planarization layer, and seed layer. In addition, cracks, chipping, strain, or the like are generated between layers formed by an encapsulation layer, a planarizing layer, a seed layer, or an epitaxial deposition process in a subsequent process or the like based on thermal stress due to a difference in thermal expansion coefficient. As a result, it was found that contamination and various deformations caused by impurity diffusion in the AlN ceramic core are caused in the seed crystal, adversely affecting the subsequent epitaxial growth, and a low-quality epitaxial growth film having many crystal defects is formed.
Thus, alN and/or Al for a light-emitting diode used in a deep ultraviolet region (UVC; 200-280 nm) of an extremely short wavelength, for example, is particularly required to have few crystal defects and high characteristics x Ga 1-x N(0<X<1) Substrate, or accompanying 5G communicationGaN crystal substrates suitable for high frequency and high withstand voltage, etc. are not easily obtained with few crystal defects, high quality and low cost, and new solutions are also required.
Accordingly, the present inventors have made various studies to solve the above-mentioned problems, and as a result, have achieved the present invention. That is, one of the important constituent elements of the present invention is to minimize the difference in thermal expansion coefficient between the respective multilayer films of the encapsulating core, or between the sealing layer, the planarizing layer, and the seed layer, and optimize the thicknesses between the encapsulating layer, the planarizing layer, and the seed layer in a balanced manner, wherein a stress adjustment layer is added according to the optimization of the composition and thickness of the encapsulating layer and/or as needed to achieve the minimization of thermal stress, further reducing the stressing.
On the other hand, although the effect of the seed crystal has been understood so far, no intensive study has been made on its basic properties. In particular, the causal relationship between the basic properties of Si <111> seed crystals and subsequent epitaxial films has not been fully studied. Therefore, the present inventors have conducted studies on the effect of the basic properties of Si <111> seed crystals on the epitaxial film by optimizing the composition of each layer and minimizing the thermal stress between each layer, as much as possible excluding the deformation due to the thermal stress difference occurring between each layer and the contamination from the core, and the like.
As a result, alN and Al are obtained at low cost with less defects and high characteristics x Ga 1-x N(0<X<1) Seed substrate for epitaxial growth of group III nitride such as GaN, and the like, in addition to the strain and contamination described above, oxidation induced stacking fault (OSF) pair Si described in patent document 3<111>The nature of the seed crystal has a significant impact. Namely, si is found<111>The fewer OSF in the seed crystal, the fewer defects in the epitaxial film, and the better the device characteristics thereafter.
It is generally believed that the amount of oxidation induced stacking faults (OSF) in Si <111> seeds has little effect on defects in the epitaxial film, as there are many crystal defects in conventional epitaxial films. However, the present inventors have reviewed the case where defects during epitaxial deposition are more pronounced, and found that there is a significant causal relationship between Si <111> seed characteristics and defects in epitaxial films, which is another important component of the present invention, and completed the present invention.
Prior art literature
Patent literature
Patent document 1: JP6042545B
Patent document 2: JP6626607B
Patent document 3: JP2936916B
Non-patent literature
Non-patent document 1: japanese Journal of Applied Physics; vol.46, no.17,2007, pp.L389-L391
Non-patent document 2: SEI Technical Review; no.177, pp.88-91
Non-patent document 3: fujikura Technical Review; no.119,2010, vol.2, pp.33-38
Non-patent document 4: LEDs Magazine Japan; december 2016, pp.30-31
Disclosure of Invention
Problems to be solved by the invention
The present invention has been made in view of the above circumstances, and an object thereof is to obtain a high-quality and inexpensive material such as AlN, al having few crystal defects x Ga 1-X N(0<X<1) And a seed substrate for epitaxial growth of group III nitride such as GaN and the like, and for scale-free epitaxial growth. In order to achieve the object, in the seed substrate for epitaxial growth of the present invention, by optimizing between each of the multilayer films encapsulating the core serving as the base substrate, or the encapsulating layer, the planarizing layer, and the Si<111>The composition and thickness between the seed layers minimizes the difference in thermal expansion coefficients and reduces stress. Oxidation induced stacking fault (OSF) was set to 10 per cm 2 The following Si<111>A thin film of 0.1 to 1.5 μm of single crystal was transferred to the upper surface of the planarization layer and used as a seed layer. The number of oxidation-induced stacking faults (OSF) (in units of/cm) was measured by the evaluation method of patent document 3 2 ). Although it becomes more difficult to measure the defect density as the thickness of the seed layer becomes thinner, it is expected that the defect density will not beAs the film is transferred.
In the present invention, it is important to minimize the difference in thermal expansion coefficient between the respective multilayer films, or between the encapsulation layer, the planarization layer and the seed layer as much as possible. For this purpose, the composition and thickness of the encapsulation layer, planarization layer and seed layer must be optimized in a balanced manner. In particular, by optimizing the composition and thickness of the encapsulation layer and/or adding a stress adjustment layer as needed to reduce stress, and by oxidation inducing a stacking fault (OSF) of 10 pieces/cm on the upper surface of the planarization layer as a seed layer 2 The following Si<111>Thin film transfer of 0.1 to 1.5 μm of single crystal, expected crystal defects are low, excellent characteristics and low cost can be achieved.
Solution for solving the problem
In order to achieve the above object, a seed substrate for epitaxial growth according to the present invention includes a support substrate, a planarization layer having a thickness of 0.5 to 3.0 μm provided on an upper surface of the support substrate, and a seed layer provided on an upper surface of the planarization layer. The support substrate includes a core of group III nitride polycrystalline ceramic and an encapsulation layer of 0.05 to 1.5 μm encapsulating the core. The seed layer induces stacking fault by oxidation to 10 per cm 2 The following Si<111>The surface layer of 0.1-1.5 mu m of the single crystal is provided by film transfer.
In the present invention, the group III nitride polycrystalline ceramic forming the core may be an AlN ceramic.
In the present invention, the encapsulating layer may include at least Si 3 N 4 Is a layer of (c).
In the present invention, the planarization layer may be made of SiO 2 And/or silicon oxynitride (Si) x O y N z ) Or AlAs.
In the present invention, the resistivity (room temperature) of Si <111> forming the seed layer may be 1KΩ·cm or more.
In the present invention, a stress adjustment layer may be provided on the bottom surface of the support substrate.
In the present invention, the encapsulation layer may be deposited by an LPCVD method.
In the present invention, it is possible toSiO is formed on one side or the whole surface of the upper surface of the support substrate by one of a plasma CVD method, an LPCVD method and a low pressure MOCVD method 2 And/or silicon oxynitride (Si) x O y N z ) Or AlAs is made as a planarizing layer.
In the present invention, OSF of 10 pieces/cm can be obtained by subjecting hydrogen and/or He to ion implantation 2 Si having a resistivity (room temperature) of 1kΩ·cm or more<111>In the single crystal, a seed layer is then provided by transferring a thin film of 0.1 to 1.5 μm by physical means at a temperature of 450 ℃ or less.
In the present invention, the stress adjustment layer may be selected from SiO having a thermal expansion coefficient capable of correcting warpage after the planarization layer is provided 2 、Si 3 N 4 Amorphous Si, poly-Si, etc., or combinations thereof. Here, when compatibility with an electrostatic chuck of a process apparatus is even considered in a device manufacturing process, at least poly-Si prepared by a method selected from the group consisting of a sputtering method, a plasma CVD method, and an LPCVD method is suitable for supporting the underlying layer of the substrate. Furthermore, siO is interposed between the poly-Si layer and the support substrate 2 And/or silicon oxynitride (Si) x O y N z ) To increase the affinity between the encapsulation layer and the stress modifying layer is suitable. When the poly-Si film is used as the stress adjustment film and the chuck film of the electrostatic chuck, poly-Si may be directly deposited, or amorphous Si may be deposited as described above and then polycrystallized by heating or laser irradiation. The reason why the poly-Si film is placed on the bottom layer is that when considering compatibility with the electrostatic chuck of the process equipment, the smaller the distance between the surface of the electrostatic chuck and the chuck-compatible film, and the lower the resistivity of the chuck-compatible film, the stronger the electrostatic attraction force.
The semiconductor substrate according to an embodiment of the present invention is characterized in that a group III-V semiconductor thin film is deposited on the upper surface of the seed substrate for epitaxial growth of any one of the above. The group III-V semiconductor thin film may be a nitride semiconductor thin film containing Ga and/or Al.
The method for manufacturing a seed substrate for epitaxial growth according to an embodiment of the present invention includes the steps of: preparing a core comprising a group III nitride polycrystalline ceramic; general purpose medicineOver-depositing an encapsulation layer to encapsulate the core to obtain a support substrate, the encapsulation layer having a thickness of 0.05-1.5 μm; depositing a planarization layer on the upper surface of the support substrate, the planarization layer having a thickness of 0.5 to 3.0 μm; and by making oxidation-induced stacking fault (OSF) 10 pieces/cm 2 The following Si<111>A surface layer of 0.1 to 1.5 μm of the single crystal is subjected to thin film transfer, and a seed layer is provided on the upper surface of the planarizing layer.
In the present invention, the encapsulation layer may be deposited by an LPCVD method.
In the present invention, siO can be formed on one side or the entire surface of the upper surface of the support substrate by one of the plasma CVD method, the LPCVD method and the low pressure MOCVD method 2 And/or silicon oxynitride (Si) x O y N z ) Or AlAs is made as a planarizing layer.
In the present invention, stacking faults of 10 per cm can be induced by subjecting hydrogen and/or He to ion implantation oxidation 2 Si having a resistivity (room temperature) of 1kΩ·cm or more<111>In the single crystal, si is transferred below 450 ℃ by physical means<111>A seed layer is provided on a thin film of 0.1 to 1.5 μm of the single crystal.
The present invention may further include the step of providing a stress adjustment layer on the bottom surface of the support substrate. The stress adjustment layer may have a thermal expansion coefficient capable of further correcting warpage after the planarization layer is provided, and may be made of poly-Si prepared by a method selected from at least a sputtering method and an LPCVD method.
The method of manufacturing a semiconductor substrate according to an embodiment of the present invention includes the steps of: manufacturing a seed substrate for epitaxial growth by any of the above methods; and depositing a III-V semiconductor film on the upper surface of the seed substrate for epitaxial growth.
ADVANTAGEOUS EFFECTS OF INVENTION
The invention can provide a light-emitting diode used in the deep ultraviolet region (UVC; 200-280 nm), such as AlN and/or Al x Ga 1-X N(0<X<1) Epitaxial and scale-free group III nitride such as substrate, or GaN crystal substrate suitable for high frequency and high withstand voltage with 5G communication or EV formationThe seed substrate for epitaxial growth has few defects, high quality and low cost.
Drawings
Fig. 1 is a view showing a cross-sectional structure of a seed substrate 1.
Fig. 2 is a diagram showing a process for manufacturing the seed substrate 1.
Detailed Description
Embodiments of the present invention will be described in detail below, but the present invention is not limited thereto.
Fig. 1 shows a cross-sectional structure of a seed substrate for epitaxial growth of group III nitride (hereinafter referred to as "seed substrate") 1. The seed substrate 1 shown in fig. 1 has a structure in which a planarizing layer 4 and a Si <111> seed layer 2 are stacked on a supporting substrate 3. In addition, the stress adjustment layer 5 is provided on a surface (bottom surface) of the support substrate 3 opposite to the surface on which the planarizing layer 4 is stacked, as necessary.
The support substrate 3 has a core 31 serving as a core material of the support substrate 3, and an encapsulating layer 32 covering the core 31.
The core 31 is formed of a group III nitride polycrystalline ceramic. In particular, alN, si can be used 3 N 4 GaN or a mixture of these materials. Polycrystalline AlN ceramics are suitable because they have a lattice constant and a coefficient of thermal expansion close to those of the target group III nitride crystal, have high thermal conductivity, and are inexpensive. In device processing, wafers with mirror finish of 200 to 1000 μm should be selected, and these wafers can be processed on a semiconductor production line. The AlN ceramics are produced by various methods, but a so-called sheet-forming/atmospheric sintering method is generally used due to its productivity. In the sheet forming/atmospheric sintering method, alN powder, a sintering agent, an organic binder and a solvent are mixed to produce a wafer-like green sheet, which is then degreased, at N 2 Sintering and polishing in an atmosphere to produce a product. The sintering agent may be selected from Y 2 O 3 、Al 2 O 3 And CaO, etc., but Y 2 O 3 It is generally suitable because it exhibits the highest thermal conductivity in the substrate after sintering.
If AlN ceramic is used as the core 31 as it is, thenDuring sintering, the raw materials AlN and Y 2 O 3 Metal impurities in the powder, as well as carbon, oxygen and other impurities from insulating materials, furnace materials, containers, etc., become sources of contamination, resulting in adverse effects such as crystal defects and coloration in the target single crystal.
Thus, an encapsulation layer 32 is provided that encapsulates and encapsulates the polycrystalline ceramic core 31. Specifically, when encapsulating layer 31 with encapsulating layer 32, the layers including encapsulating layer 32 must be considered in terms of their composition and thickness so that thermal stress is as small as possible and thermal conductivity is as large as possible. In the present invention, from the viewpoint of manufacturing cost, the total thickness of the encapsulating layer 32 is preferably optimized in the range of 0.05 to 1.5 μm.
The composition of the encapsulating layer 32 may be appropriately selected in consideration of the thermal expansion coefficient and the thermal conductivity, but in order to enhance the impurity diffusion preventing ability thereof, it is preferable to use at least a material made of silicon nitride (Si 3 N 4 ) The film is constructed to cover and encapsulate the entire core.
If desired, for example, if electrostatic clamping is desired, the encapsulation layer 32 may be provided with p-Si as a layer for electrostatic clamping. The p-Si layer may be deposited on AlN ceramic and Si 3 N 4 Between layers, or may be together with or below a stress modifying layer 5 described below. In this case, if p-Si and AlN cores are combined with Si 3 N 4 If the adhesion between the layers is insufficient, siO with high adhesion can be inserted in consideration of the affinity and thermal expansion coefficient between the layers 2 Or silicon oxynitride (Si) x O y N z ) Is a film of (a).
For the seed substrate for epitaxial growth of group III nitride such as GaN for high frequency applications, particularly for applications such as gigahertz wave or millimeter wave very high frequency, the resistivity (room temperature) of the Si <111> seed layer 2 is preferably 1kΩ·cm or more in order to avoid high frequency loss in devices manufactured using an epitaxial layer grown on the seed substrate. This is because the Si <111> seed layer 2 having a resistivity (room temperature) of 1kΩ·cm or less will cause high frequency loss due to gigahertz waves or millimeter waves, cause device heat generation and high power consumption, and cannot provide sufficient characteristics.
When a p-Si film is provided for an electrostatic chuck, its resistance should be as high as possible to provide the necessary attraction force. The p-Si film may be deposited on the lower layer of the core 31 as far as possible from the seed layer 2 on which the epitaxial film is stacked, or on the lower portion of the stress adjustment layer 5, or may be deposited in multiple layers simultaneously with the stress adjustment layer 5. The high-resistance p-Si has low high-frequency loss and, when placed on the bottom of the support substrate 3, it is close to the electrostatic chuck, so that a sufficient electrostatic force can be obtained even with high resistance. Therefore, the adsorption of the substrate is sufficiently possible without doping. To further reduce high frequency loss, it is more desirable to remove the p-Si layer by regrinding the substrate at the end of device fabrication. When the stress adjustment layer 5 is provided, it is preferable to maintain the p-Si resistance as high as possible, but the minimum amount of boron (B), phosphorus (p) or other dopant required to generate the necessary electrostatic force is not limited.
In the encapsulation layer 32, if the thickness of each layer becomes too thick, the stress between each layer increases due to the difference in thermal expansion coefficient, resulting in delamination between each layer. Therefore, even if films of various compositions are selected and combined, it is undesirable for the thickness of the encapsulating layer 32 to be greater than 1.5 μm. On the other hand, a thickness of 0.05 μm or less is insufficient for preventing diffusion of impurities in terms of the function of sealing impurities. It is understood that the thickness of the encapsulating layer 32 is preferably in the range of 0.05 to 1.5 μm. The deposition method of the encapsulation layer may be selected from conventional deposition methods such as MOCVD, atmospheric pressure CVD, LPCVD, sputtering, and the like. LPCVD is particularly preferable due to film quality, film coverage, and impurity diffusion preventing ability.
A planarization layer 4 of 0.5 to 3 μm is stacked on at least the encapsulation layer 32 on the upper surface of the support substrate 3. The planarization layer 4 is selected from SiO 2 、Al 2 O 3 、Si 3 N 4 SiC or silicon oxynitride (Si) x O y N z ) Such as a common ceramic membrane material, or Si, gaAs, alAs, which is commonly used as a sacrificial layer for etching and the like. Preferably selected is SiO which is easily ground or polished during planarization and easily separated when a solid substrate is obtained 2 And/or silicon oxynitride (Si) x O y N z ) Or AlAs。
From a cost standpoint, the planarizing layer 4 is typically stacked on only one side of the encapsulating layer 32, but if the warpage is large, the planarizing layer may be deposited to cover the entire encapsulating layer 32. The thickness of the planarizing layer 4 must be thick enough to fill voids and irregularities in the core 31 and the encapsulating layer 32, etc., and smooth enough to transfer the seed. However, too thick planarization layer 4 is undesirable because it may cause warpage and cracking of seed substrate 1. Therefore, it is preferable to provide a planarizing layer having a thickness of 0.5 to 3 μm at least on the upper surface of the supporting substrate. This is because, if the thickness is less than 0.5 μm, it is almost impossible to fill voids and irregularities in the AlN ceramic core 31 and the encapsulating layer 32, and if the thickness is 3 μm or more, warpage of the planarizing layer 4 may occur.
In terms of film quality and deposition efficiency required for the planarizing layer 4, a plasma CVD method, an LPCVD method, or a low pressure MOCVD method is suitable for deposition of the planarizing layer 4. For stacked SiO according to film conditions 2 And/or silicon oxynitride (Si) x O y N z ) Or AlAs is heat treated to quench or CMP polished to achieve smoothness, in preparation for thin film transfer of seed layer 2 described below.
The seed crystal is selected to have a crystal structure similar to that of AlN or Al as the subject of the invention x Ga 1-x N(0<X<1) A substrate having a crystal structure of group III nitride such as GaN. Thus, si is<111>SiC, SCAM, alN, alGaN, sapphire, etc. are candidate materials, but from the viewpoint of easiness of large-diameter production, availability of commercial products, and low cost, si<1111>Is suitable. As described above, in Si<111>In the crystal, oxidation induced stacking fault (OSF) was 10 pieces/cm 2 The following Si<111>Single crystals are particularly suitable.
This is because Si is used as a seed for the next process of epitaxial deposition<111>OSF10 pieces/cm of seed crystal 2 In the following, the epitaxially deposited crystals have fewer defects after the seed, resulting in superior device characteristics and high yield, which results in low cost. On the other hand, when OSF exceeds 10 pieces/cm 2 In the case of epitaxially deposited crystals The defects of (c) greatly increase, resulting in poor device characteristics, which inevitably reduce yield and result in high costs.
When the epitaxial and scale-free substrates obtained by epitaxial deposition on the seed substrate 1 are used for high-frequency devices, particularly 5G and above devices, si <111> seed crystals having a resistivity (room temperature) of 1kΩ·cm or more are preferably selected. This is because if the resistivity (room temperature) of the Si <111> seed crystal is less than kΩ·cm, its resistance causes high-frequency loss, thereby increasing power consumption and generating heat, degrading device characteristics.
The ion implantation of the Si <111> seed is performed limited to the kind of hydrogen and/or helium (He) ions which have little influence on the resistance of the single crystal substrate, and then the ion implanted surface of the Si <111> seed is bonded to the upper surface of the planarization layer 4, and the thin film of 0.1 to 1.5 μm is peeled off and transferred to the planarization layer 4 using a physical means such as nails at 450 ℃ or less to form the seed layer 2. Unlike heavy elements such as boron (B), light elements such as hydrogen and He are suitable for ion implantation into the seed crystal, because ion implantation has little damage to the seed crystal and does not reduce its electrical resistance. In addition, the peeling and transfer at a low temperature of 450 ℃ or less can prevent thermal damage to Si <111> seed crystals, which is unavoidable in the usual smart cut method of thermal peeling and transfer at a high temperature of 700 ℃ or more.
The transfer thickness of the seed layer 2 is preferably 0.1 to 1.5 μm. At the time of ion implantation, the thickness of the damage layer alone is close to 0.1 μm, and if the thickness is less than 0.1 μm, a proper seed crystal cannot be obtained. In addition, the ion implanter requires high output ion energy for a transfer thickness of 1.5 μm or more, and becomes large in size, requiring a large investment, which is uneconomical. Although it may be difficult to directly measure the defect density when the thickness of the seed layer 2 is thinned (e.g., 1.0 μm or less), it is expected that the defect density does not change due to thin film transfer, and thus the OSF defect density in the seed layer 2 is estimated to be 10 pieces/cm 2 Hereinafter, with Si<111>The OSF defect density of the seed is the same.
More specifically, after ion implantation of hydrogen and/or He into the seed crystal to a depth of 0.2 to 3.5 μm, the upper surface of the above planarization layer 4 and the ion implantation surface of the seed crystal are bonded. The seed crystals may then be stripped by air pressure, nails, or other physical means at a temperature below 450 ℃. This is because stress and thermal damage caused by impurity diffusion and thermal stress can easily occur in the seed crystal of the transfer film at a high temperature exceeding 450 ℃.
Then, the upper surface of the transfer film may be subjected to CMP polishing and/or slight etching with a chemical substance to remove the unavoidable ion implantation damage layer, thereby obtaining a seed single crystal film (seed layer 2) having a thickness of 0.1 to 1.5 μm. If higher uniformity is required for ion implantation, siO may be deposited on the ion implanted surface of the seed substrate prior to ion implantation, if desired 2 Etc.
In the present invention, a stress adjustment layer 5 may be further added to the bottom surface of the support substrate 3, if necessary. For the stress adjustment layer 5, a film material and a thickness having a thermal expansion coefficient capable of correcting warpage of the seed substrate 1 caused by forming the planarization layer 4 are selected. For example, the stress adjustment layer 5 may be selected from SiO, alone or in combination 2 、Si 3 N 4 Amorphous Si, poly-Si, etc. Here, when compatibility with an electrostatic chuck of a process apparatus is even considered in a device manufacturing process, at least poly-Si prepared by a method selected from the group consisting of a sputtering method, a plasma CVD method, and an LPCVD method is suitable for supporting the underlying layer of the substrate. In general, it is suitable to deposit poly-Si (p-Si) as the stress adjustment layer 5, which is also compatible with electrostatic chucks. From the standpoint of warp correction and affinity with the encapsulation layer 32, siO 2 And/or silicon oxynitride (Si) x O y N z ) Etc. may be interposed between the poly-Si and the encapsulation layer. When a poly-Si film, which also serves as a clamping film of an electrostatic chuck, is used as the stress adjustment layer 5, poly-Si may be directly deposited, or amorphous Si may be deposited and then polycrystallized by heating or laser irradiation. By providing the poly-Si film as the lowermost layer, the distance between the electrostatic chuck surface and the chuck-compatible film can be shortened, and the resistivity of the film can be reduced to increase electrostatic attraction force.
Next, with reference to fig. 2, a process of a method of manufacturing a seed substrate for epitaxial growth of a group III nitride system according to an embodiment of the present invention will be described. If a suitable method for forming the respective layers has been described in conjunction with the composition of the respective portions of the seed substrate 1, redundant description is omitted here.
First, a core 31 made of nitride ceramics is prepared (S01 in fig. 2). Next, an encapsulating layer 32 having a thickness of 0.05 to 1.5 μm is deposited to encapsulate the core 31, and a supporting substrate 3 is obtained (S02 in fig. 2). In this case, the encapsulating layer 32 may be deposited by using an LPCVD method. Next, a planarization layer 4 having a thickness of 0.5 to 3.0 μm is deposited on the upper surface of the support substrate 3 (S03 in fig. 2). A stress adjustment layer 5 is deposited on the bottom surface of the support substrate 3 as necessary (S04 in fig. 2). The planarization layer 4 and the stress adjustment layer 5 may be deposited simultaneously.
In addition to S01 to S04, a Si <111> single crystal substrate 20 as a seed for lift-off transfer of the seed layer 2 is prepared (S11 in fig. 2). Next, ion implantation is performed from one surface (ion implantation surface) of the single crystal substrate 20, and a peeling position (embrittlement layer) 21 is formed in the single crystal substrate 20 (S12 in fig. 2).
Next, the ion implantation surface of the single crystal substrate 20 is bonded to the planarizing layer 4 formed on the supporting substrate 3 to obtain a bonded substrate (S21 in fig. 2). Then, the single crystal substrate 20 is separated at the peeling position 21 of the single crystal substrate 20 in the bonded substrate (S22 in fig. 2). In this way, the single crystal film of Si <111> is thin-film transferred as the seed layer 2 onto the planarizing layer 4 on the support substrate 3. On the other hand, when another group III nitride composite substrate is manufactured by polishing the surface again to form an ion implantation surface, the remaining portion of the separated Si <111> single crystal substrate 20 may be reused for transferring the seed layer.
The constitution and the manufacturing method of the seed substrate 1 for epitaxial growth are described above. The invention is the synergistic effect of the following two important components: 1) Minimizing thermal stress by optimizing the composition and thickness of the layers, particularly the encapsulation layer, and 2) growing excellent epitaxial film crystals by using excellent seed crystals. Next, 3) further reducing the stress using a stress adjustment layer as needed, and 4) ion implantation of light elements limited to hydrogen and/or He and film transfer by physical means such as nails at 450 ℃ or less are also effective. The present invention makes it possible to economically obtain an epitaxial substrate and a scale-free substrate having very little warpage, voids, crystal defects, etc., and very little high-frequency loss in the device.
The substrate according to the present invention significantly improves the characteristics of devices such as light emitting diodes for deep ultraviolet region (UVC; 200-280 nm), high frequency devices for 5G communication and EV vehicles, and high voltage devices, while also significantly improving the manufacturing yield of the devices.
Examples
The present invention will be described more specifically below by referring to examples and comparative examples, but the present invention is not limited to these examples.
Example 1
(preparation of support substrate)
A support substrate 3 having a polycrystalline ceramic core 31 covered with an encapsulating layer 32 is prepared. Commercially available AlN substrates were used for the polycrystalline ceramic core 31. By mixing 100wt% of AlN powder and 5wt% of Y 2 O 3 As a sintering agent with an organic binder and a solvent to prepare a green sheet, and then at 1900 ℃ under N 2 Degreasing and sintering the AlN substrate in an atmosphere to prepare the AlN substrate. A workpiece polished to phi 8 inches x t725 μm on both sides was used. The entire AlN ceramic core 31 was covered with a 0.1 μm thick silicon oxynitride layer by LPCVD, and then with another LPCVD apparatus, a 0.4 μm thick Si layer was formed 3 N 4 The layer encapsulates the entire core, forming an encapsulating layer 32. The total thickness of the encapsulation layer 32 was 0.5 μm. For planarization purposes, siO 6 μm thick was deposited by using a plasma CVD method (ICP-CVD apparatus) 2 Si further stacked on one side of only the upper surface 3 N 4 On the layer. Then, after baking at 1000 ℃, the SiO was polished by CMP 2 Planarization to a thickness of 2 μm (ra=0.2 nm) provides for film transfer of the seed.
(preparation of seed crystal)
Si with a diameter of 8 inches and a thickness of 725 μm was prepared<111>Monocrystalline substrate as seed crystal substrate. By the evaluation method described in patent document 3, the Si<111>Oxidation induced stacking fault (OSF) of single crystal substrate of 8/cm 2 And a resistivity (room temperature) of 1.5KΩ·cm. At a depth of 100keV, 0.6 μm and 8X 10 on Si substrate 17 cm -2 Is subjected to ion implantation of hydrogen at a dose of (a).
The 0.6 μm partial thin film of the surface layer of the ion-implanted Si <111> single crystal was transferred to the planarization layer 4 (2 μm thickness) of the support substrate 3 previously prepared. The cross section of the Si <111> single crystal damaged during ion implantation and transfer was lightly polished with CMP, and the thickness of the Si <111> single crystal layer was reduced to 0.4 μm, serving as the seed layer 2. As a result of ensuring a balance of film thicknesses of the encapsulation layer 32, the planarizing layer 4, and the seed layer 2 with respect to respective thermal stresses, the resulting seed substrate 1 is free from cracks, delamination, and warpage.
The Si <111> single crystal substrate remaining after film transfer can be reused as many seeds as possible by repeating ion implantation, which is very economical.
A seed substrate 1 having a planarizing layer 4 of 2 μm thickness and a Si <111> single crystal seed layer 2 of 0.4 μm thickness on a supporting substrate 3 having an AlN ceramic core 31 and an encapsulating layer 32 was obtained. The characteristics of the seed substrate 1 as a seed substrate for epitaxial growth of GaN were briefly evaluated as follows.
The seed substrate 1 described above is placed in a reactor of an MOCVD equipment, and epitaxial growth is performed. In this process, an epitaxial layer is deposited in order of AlN and AlGaN from the seed substrate 1 side toward the growth direction, and then GaN is epitaxially grown. The structure of the epitaxial layer is not limited thereto, and for example, alGaN may not be deposited, or AlN may be further deposited after AlGaN deposition. In this evaluation, a 100nm AlN layer and a 150nm AlGaN layer were formed. The total thickness of the epitaxial layer was 5 μm. During epitaxial growth, TMAL (trimethylaluminum) can be used as the Al source, TMGa (trimethylgallium) can be used as the Ga source, NH 3 May be used as the N source, but is not limited to these. The carrier gas may be N 2 And H 2 Or any one of them. The treatment temperature is preferably about 900 to 1200 ℃.
Then, in order to evaluate the dislocation density, etching pits were generated by a molten alkali (KOH) etching method, and Etching Pit Density (EPD) was measured. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate crystallinity.
As a result, EPD showed 0.2X10 4 cm -2 Is a very low dislocation density of (c). XRC measurement on the Ga (0002) plane of the substrate resulted in a full width at half maximum FWHM of 135 arcsec (hereinafter referred to simply as "FWHM of 0002 XRC"), resulting in a high quality GaN single crystal. These results indicate that the seed substrate 1 in this example has excellent characteristics as a seed substrate for epitaxial growth. When such an epitaxial substrate having an epitaxial layer on the seed substrate 1 is used for a 30GHz/20Gbps high frequency device, the surface temperature of the device is 43 ℃ and there is no temperature rise due to high frequency loss, which causes a significant problem.
Comparative example 1
Use of an oxidation induced stacking fault (OSF) of 16 pieces/cm with a diameter of 8 inches 2 Single crystal Si having resistivity (room temperature) of 0.2KΩ·cm<111>The single crystal substrate was used as a seed substrate, and the thin film was transferred to the seed layer 2 having a thickness of 1.3 μm. Except for this, the seed substrate 1 was manufactured under the same conditions as in example 1. In the same manner as in example 1, gaN of 5 μm was deposited on the seed substrate 1 by the MOCVD method. As a result, EPD shows 15×10 4 cm -2 Is a very large dislocation density. Further, the FWHM of 0002XRC was 930 arc seconds, resulting in GaN single crystal having poor crystallinity compared with example 1. When the epitaxial substrate is used for a 30GHz/20Gbps high-frequency device, the surface temperature of the device is as high as 125 ℃ due to high-frequency loss, and thus long-term use is impossible.
Example 2
(preparation of support substrate)
A support substrate 3 having a polycrystalline ceramic core 31 covered with an encapsulating layer 32 is prepared. As the polycrystalline ceramic core 31, the same commercially available AlN substrate as in example 1 was used. SiO with thickness of 0.3 μm by LPCVD method 2 The layer covered the entire AlN ceramic core 31 and was then coated with Si 0.8 μm thick using another LPCVD apparatus 3 N 4 The layer encapsulates the entire core, forming an encapsulating layer 32. The total thickness of the encapsulating layer 32 is1.1 μm. For the purpose of further planarization, 5 μm of silicon oxynitride is stacked on the Si on the upper layer of the encapsulation layer 32 alone by LPCVD method 3 N 4 On the layer. Thereafter, the silicon oxynitride layer was subjected to CMP polishing to a thickness of 2.5 μm. At this stage, the entire substrate is significantly warped, about 30 μm. In order to correct warpage, a 5 μm thick silicon oxide layer and a 0.2 μm thick undoped poly-Si layer also serving as an electrostatic chuck adsorption layer were deposited on the bottom surface by a plasma CVD method as the stress adjustment layer 5. As a result, warpage is eliminated, and the electrostatic chuck can be sufficiently attached and removed.
(preparation of seed crystal)
Si with a diameter of 8 inches and a thickness of 725 μm was prepared<111>The single crystal substrate serves as a seed substrate. By the evaluation method described in patent document 3, the Si <111>Oxidation induced stacking fault (OSF) of 0/cm for single crystal substrate 2 And the resistivity (room temperature) was 2.3kΩ·cm. At a depth of 130keV, 1.4 μm and 9.5X10 on Si substrate 17 cm -2 Is subjected to ion implantation of hydrogen at a dose of (a).
The 1.4 μm partial film of the surface layer of the ion-implanted Si <111> single crystal was transferred to the planarization layer 32 (2.5 μm thick) of the support substrate 3 previously prepared. The cross section of the Si <111> single crystal damaged during ion implantation and transfer was lightly polished with CMP, and the thickness of the Si <111> single crystal layer was reduced to 1 μm, serving as the seed layer 2. As a result of ensuring a balance of film thicknesses of the encapsulation layer 32, the planarizing layer 4, and the seed layer 2 with respect to respective thermal stresses, the resulting seed substrate 1 is free from cracks, delamination, and warpage.
As in example 1, the Si <111> single crystal substrate remaining after film transfer can be reused as many seeds as possible by repeating ion implantation, which is very economical.
A seed substrate 1 having a 2.5 μm thick planarizing layer 4 and a 1 μm thick Si <111> single crystal seed layer 2 on a supporting substrate 3 having an AlN ceramic core 31 and an encapsulating layer 32 was obtained. The characteristics of the seed substrate 1 as a seed substrate for epitaxial growth of AlN were briefly evaluated as follows.
Using AlCl 3 And NH 3 As a raw material, an AlN single crystal of 600 μm was deposited on the seed substrate 1 by the THVPE method. The deposited AlN single crystal was sliced with a wire saw and polished to produce a smooth phi 8-inch substrate. The AlN single-crystal substrate after dicing was not colored, and the light transmittance at a wavelength of 220nm was about 80% at a film thickness of 100. Mu.m. Then, the substrate was used as a seed substrate for epitaxial growth of AlN, and the following brief evaluation was performed.
AlN was deposited on a substrate by MOCVD method, etching pits were generated by a molten alkali (KOH) etching method to evaluate dislocation density, and EPD was measured as in the evaluation of example 1. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate crystallinity.
As a result, EPD showed 0.5X10 4 cm -2 Is a very low dislocation density of (c). Further, the FWHM of 0002XRC was 110 arcsec, and a high-quality AlN single crystal was obtained. The AlN single crystal substrate has very few defects as an LED substrate in a deep ultraviolet region, and is an excellent substrate having excellent device characteristics and low cost.
Example 3
The planarization layer 4 is two layers of SiO with a total thickness of 2.5 μm 2 AlAs structure consisting of an AlAs underlayer 2 μm thick and SiO 0.5 μm thick 2 And an upper layer. Except for this, a seed substrate 1 for epitaxial growth was obtained under the same conditions as in example 1.
The Si <111> single crystal substrate remaining after film transfer can be reused as many seeds as possible by repeating ion implantation, which is very economical.
The support substrate 3 having a structure with an AlN ceramic core 31 and an encapsulating layer 32 and SiO having a total thickness of 2.5 μm were obtained 2 Composite planarising layer 4 of AlAs and Si with thickness of 0.4 μm on composite planarising layer 4<111>Seed substrate 1 of monocrystalline seed layer 2. Using this seed substrate 1 as a seed substrate for epitaxial growth of GaN, a thick film of GaN was epitaxially grown.
After depositing a 30 μm GaN film on the seed substrate 1 by MOCVD method, siO was deposited 2 The planarization layer 4 of/AlAs is dissolved in HF solution to obtainA GaN scale-free substrate having a thickness of about 30 μm.
To evaluate the dislocation density of the GaN scale-free substrate, etching pits were generated by a molten alkali (KOH) etching method as in the evaluation in example 1, and EPD was measured. In addition, X-ray rocking curve (XRC) measurements were performed to evaluate crystallinity.
As a result, EPD showed 0.05X10 4 cm -2 Is a very low dislocation density of (c). Further, the FWHM of 0002XRC was 101 arcsec, and a high-quality GaN single crystal was obtained. These values indicate that the seed substrate 1 in this example is extremely excellent as a seed substrate for epitaxial growth to obtain a scale-free substrate. The GaN scale-free substrate obtained by epitaxial growth using the seed substrate 1 was used for a high frequency device of 30GHz/20 Gbps. The surface temperature of the device was 38 ℃, indicating that the substrate was excellent with low heat generation due to high frequency loss.
Description of the reference numerals
1. Seed substrate
2. Seed layer
3. Support substrate
4. Planarization layer
5. Stress adjustment layer
20. Monocrystalline substrate of seed crystal
21. Stripping position
Claims (21)
1. A seed substrate for epitaxial growth, comprising:
a support substrate;
a planarization layer provided on an upper surface of the support substrate, the planarization layer having a thickness of 0.5 to 3.0 [ mu ] m; and
a seed layer disposed on an upper surface of the planarization layer,
wherein the support substrate comprises:
a core formed from a group III nitride polycrystalline ceramic; and
an encapsulating layer encapsulating the core, the encapsulating layer having a thickness of 0.05 to 1.5 μm, and
the seed layer is prepared by inducing stacking fault of 10 per cm by oxidation 2 The following are the followingSi of (2)<111>The surface layer of 0.1-1.5 mu m of the single crystal is provided by film transfer.
2. A seed substrate for epitaxial growth, comprising:
a support substrate;
a planarization layer provided on an upper surface of the support substrate, the planarization layer having a thickness of 0.5 to 3.0 [ mu ] m; and
a seed layer disposed on an upper surface of the planarization layer,
wherein the support substrate comprises:
a core formed from a group III nitride polycrystalline ceramic; and
an encapsulating layer encapsulating the core, the encapsulating layer having a thickness of 0.05 to 1.5 μm, and
The oxidation induced stacking fault of the seed layer is 10 per cm 2 The thickness of the seed layer is 0.1-1.5 μm.
3. The seed substrate for epitaxial growth according to claim 1 or 2, wherein the group III nitride polycrystalline ceramic forming the core is an AlN ceramic.
4. The seed substrate for epitaxial growth according to any one of claims 1 to 3, wherein the encapsulation layer comprises at least Si 3 N 4 Is a layer of (c).
5. The seed substrate for epitaxial growth according to any one of claims 1 to 4, wherein the planarizing layer comprises SiO 2 And/or silicon oxynitride (Si) x O y N z ) Or AlAs.
6. The seed substrate for epitaxial growth according to any one of claims 1 to 5, wherein the resistivity (room temperature) of Si <111> forming the seed layer is 1kΩ -cm or more.
7. The seed substrate for epitaxial growth according to any one of claims 1 to 6, further comprising a stress adjustment layer on a bottom surface of the support substrate.
8. The seed substrate for epitaxial growth according to claim 7, wherein the stress adjustment layer has a thermal expansion coefficient capable of further correcting warpage after the provision of the planarization layer, and comprises polycrystalline Si prepared by a method selected from at least a sputtering method, a plasma CVD method, and an LPCVD method.
9. The seed substrate for epitaxial growth according to claim 7 or 8, wherein the stress adjustment layer is provided immediately below the bottom surface of the support substrate with SiO interposed therebetween 2 And/or silicon oxynitride (Si) x O y N z ) poly-Si of (a).
10. The seed substrate for epitaxial growth according to any one of claims 1 to 9, wherein the encapsulation layer is deposited by an LPCVD method.
11. The seed substrate for epitaxial growth according to any one of claims 1 to 10, wherein SiO is deposited on one side or the entire surface of the upper surface of the support substrate by one of a plasma CVD method, an LPCVD method and a low-pressure MOCVD method 2 And/or silicon oxynitride (Si) x O y N z ) Or AlAs to form the planarization layer.
12. The seed substrate for epitaxial growth according to any one of claims 1 to 10, wherein stacking faults are induced to 10 per cm by subjecting hydrogen and/or He to ion implantation oxidation 2 Si having a resistivity (room temperature) of 1kΩ·cm or more<111>In the single crystal, si is transferred below 450 ℃ by physical means<111>The seed layer is provided as a thin film of 0.1 to 1.5 μm of a single crystal.
13. A semiconductor substrate, wherein a group III-V semiconductor thin film is deposited on an upper surface of the seed substrate for epitaxial growth according to any one of claims 1 to 12.
14. The semiconductor substrate according to claim 13, wherein the group III-V semiconductor thin film is a nitride semiconductor thin film containing Ga and/or Al.
15. A method for manufacturing a seed substrate for epitaxial growth, comprising:
preparing a core composed of a group III nitride polycrystalline ceramic;
obtaining a support substrate by depositing an encapsulation layer to encapsulate the core, the encapsulation layer having a thickness of 0.05 to 1.5 μm;
depositing a planarization layer on an upper surface of the support substrate, the planarization layer having a thickness of 0.5 to 3.0 μm; and
by inducing stacking faults by oxidation to 10 per cm 2 The following Si<111>A surface layer of 0.1 to 1.5 μm of the single crystal is subjected to thin film transfer, and a seed layer is provided on the upper surface of the planarization layer.
16. The method for manufacturing a seed substrate for epitaxial growth according to claim 15, wherein the encapsulation layer is deposited by an LPCVD method.
17. The method for producing a seed substrate for epitaxial growth according to claim 15 or 16, wherein SiO is deposited on one side or the entire surface of the upper surface of the supporting substrate by one of a plasma CVD method, an LPCVD method and a low-pressure MOCVD method 2 And/or silicon oxynitride (Si) x O y N z ) Or AlAs to form the planarization layer.
18. The method for producing a seed substrate for epitaxial growth according to any one of claims 15 to 17, wherein in the step of providing the seed layer, stacking faults are induced to 10 pieces/cm by subjecting hydrogen and/or He to ion implantation oxidation 2 Si having a resistivity (room temperature) of 1kΩ·cm or more<111>In the single crystal, si is transferred below 450 ℃ by physical means<111>The seed layer is provided as a thin film of 0.1 to 1.5 μm of a single crystal.
19. The method for producing a seed substrate for epitaxial growth according to any one of claims 15 to 18, further comprising providing a stress adjustment layer on a bottom surface of the support substrate.
20. The method for manufacturing a seed substrate for epitaxial growth according to claim 19, wherein the stress adjustment layer has a thermal expansion coefficient capable of further correcting warpage after the planarization layer is provided, and is composed of polycrystalline Si prepared by a method selected from at least a sputtering method, a plasma CVD method, and an LPCVD method.
21. A method of manufacturing a semiconductor substrate, comprising:
manufacturing a seed substrate for epitaxial growth by the method for manufacturing a seed substrate for epitaxial growth according to any one of claims 15 to 20; and
and depositing a III-V semiconductor film on the upper surface of the seed substrate for epitaxial growth.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| JP2021-038731 | 2021-03-10 | ||
| JP2021-098993 | 2021-06-14 | ||
| JP2021098993 | 2021-06-14 | ||
| PCT/JP2022/009490 WO2022191079A1 (en) | 2021-03-10 | 2022-03-04 | Seed substrate for epitaxial growth use and method for manufacturing same, and semiconductor substrate and method for manufacturing same |
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| CN116940720A true CN116940720A (en) | 2023-10-24 |
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| CN202280020112.6A Pending CN116940720A (en) | 2021-03-10 | 2022-03-04 | Seed substrate for epitaxial growth and method for producing same, and semiconductor substrate and method for producing same |
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