CN116940119A - Manufacturing method of SONOS device - Google Patents

Manufacturing method of SONOS device Download PDF

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Publication number
CN116940119A
CN116940119A CN202310891144.XA CN202310891144A CN116940119A CN 116940119 A CN116940119 A CN 116940119A CN 202310891144 A CN202310891144 A CN 202310891144A CN 116940119 A CN116940119 A CN 116940119A
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CN
China
Prior art keywords
type
region
type source
iopldd
fabricating
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Pending
Application number
CN202310891144.XA
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Chinese (zh)
Inventor
侯新亚
刘政红
齐瑞生
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202310891144.XA priority Critical patent/CN116940119A/en
Publication of CN116940119A publication Critical patent/CN116940119A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a manufacturing method of a SONOS device, which comprises the following steps: step one, providing a semiconductor substrate, completing a process before the P-type source and drain injection process ring, and canceling the IOPLDD process ring in the process before the P-type source and drain injection process ring, wherein the IOPLDD is an input/output P-type lightly doped drain. Step two, performing a P-type source drain injection process loop, comprising: and step 21, forming a mask layer and patterning. And step 22, performing IOPLDD injection by using the mask layer as a mask to form an IOPLDD region. And step 23, performing P-type source-drain injection by using the mask layer as a mask to form a P-type source-drain region, wherein the junction depth of the IOPLDD region is larger than that of the P-type source-drain region. The invention can reduce the process cost and shorten the production period.

Description

Manufacturing method of SONOS device
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a SONOS device.
Background
With the continuous improvement of the integration level requirements of FLASH memory (FLASH) storage devices in the market, the contradiction between the reliability of data storage of the traditional FLASH device and the working speed, power consumption, size and the like of the device is increasingly highlighted. The SONOS memory has the characteristics of small cell size, low operation voltage, compatibility with CMOS technology and the like, and the continuous improvement of the SONOS technology promotes the development of the semiconductor memory to the directions of miniaturization, high performance, large capacity, low cost and the like.
SONOS represents an overlapped layer of substrate Silicon, a first Oxide layer, a second Nitride layer, a third Oxide layer and a polysilicon gate, wherein the first Oxide layer is used as a tunneling Oxide layer, the second Nitride layer is used as a storage layer, and the third Oxide layer is used as a blocking layer, and the first Oxide layer, the second Nitride layer and the third Oxide layer form an ONO layer.
The SONOS structure in the SONOS memory replaces a floating gate structure in the traditional FLASH memory device, and is a charge trap type memory.
As shown in fig. 1A to 1D, the device structure is schematically shown in the steps of the manufacturing method of the prior SONOS device; the prior manufacturing method of the SONOS device comprises the following steps:
step one, performing an input-output P-type lightly doped drain (IOPLDD) process loop (loop), the IOPLDD loop comprising:
step 11, as shown in fig. 1A, a photolithography process for defining an implantation region of an IOPLDD ion implantation (implant) is performed, including photoresist coating, exposure and development, and the semiconductor substrate 1 and the patterned first photoresist layer 2 are shown in fig. 1A.
In step 12, as shown in fig. 1B, IOPLDD ion implantation is performed to form an IOPLDD region (not shown). Arrow 3 in fig. 1B represents IOPLDD ion implantation.
The first step may be preceded by other process steps for forming the SONOS memory device, and the first step may be followed by a plurality of other process steps for forming the SONOS memory device, and then the second step is performed.
Step two, performing a P-type source drain (PP S/D) process loop (PP S/D loop), comprising:
in step 21, as shown in fig. 1C, a photolithography process for defining an implantation region of PP S/D ion implantation is performed, including photoresist coating, exposure and development, and in fig. 1C, the semiconductor substrate 1 and the patterned second photoresist layer 4 are shown.
In step 22, as shown in fig. 1D, PP S/D ion implantation is performed to form P-type source/drain regions (not shown). Arrow line 5 in fig. 1D represents PP S/D ion implantation.
Generally, the PP S/D ion implantation includes implantation conditions such as implant1/2/3, for p+ source drain implantation, P-type LDD implantation, pocket (pocket) implantation, and the like, respectively.
The existing method has the following defects:
IOPLDD loop requires an additional mask, which greatly increases cost.
A large amount of raw materials and equipment are consumed, and the production period is prolonged.
Disclosure of Invention
The invention aims to provide a manufacturing method of a SONOS device, which can reduce the process cost and shorten the production period.
In order to solve the technical problems, the manufacturing method of the SONOS device provided by the invention comprises the following steps:
step one, providing a semiconductor substrate, completing a process before a P-type source drain injection process ring, and canceling an IOPLDD process ring in the process before the P-type source drain injection process ring, wherein IOPLDD is an input/output P-type lightly doped drain.
Step two, carrying out the P-type source drain injection process loop, which comprises the following steps:
and 21, forming a mask layer, patterning the mask layer, opening a P-type source drain injection region by the patterned mask layer, and covering the outside of the P-type source drain injection region.
And step 22, performing IOPLDD injection by using the mask layer as a mask to form an IOPLDD region.
And step 23, performing P-type source-drain injection by using the mask layer as a mask to form a P-type source-drain region, wherein the junction depth of the IOPLDD region is larger than that of the P-type source-drain region.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
In a further improvement, in the first step, the process steps before the P-type source drain injection process ring are completed include: forming a gate structure.
In a further improvement, in step 21, the mask layer is made of photoresist;
and forming the photoresist by adopting a photoetching process and patterning the photoresist.
In a further improvement, in the second step, the method further comprises:
and step 24, performing P-type LDD injection to form an LDD region, wherein the junction depth of the LDD region is smaller than that of the P-type source drain region.
In a further improvement, in the second step, the method further comprises:
and 25, performing N-type pocket implantation to form an N-type pocket region.
A further improvement is the integration of SONOS devices, input-output devices and logic devices simultaneously on the semiconductor substrate.
The SONOS device is an N-type device;
the input/output device comprises an N-type device and a P-type device;
the logic device includes an N-type device and a P-type device.
The further improvement is that the grid structure comprises a first grid structure of the SONOS device, the first grid structure comprises an ONO layer and a polysilicon gate, and the ONO layer is formed by stacking a first oxide layer, a second nitride layer and a third oxide layer;
the gate structure includes a second gate structure of the input-output device and a third gate structure of the logic device;
the second gate structure comprises a first gate oxide layer and a polysilicon gate which are sequentially overlapped;
the third gate structure comprises a second gate oxide layer and a polysilicon gate which are sequentially overlapped;
the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer.
In a further improvement, in step 21, the opened P-type source drain implant region includes a source drain implant region of a P-type input-output device.
Unlike the prior art that the IOPLDD process ring is required to be carried out independently, the IOPLDD process ring is omitted, and the IOPLDD injection step is placed in the P-type source drain injection process ring, so that the injection region of the IOPLDD injection is defined simultaneously by adopting a graphical definition process in the P-type source drain injection process ring, and therefore, a photomask for defining the injection region of the IOPLDD injection at one time can be saved, the process cost can be greatly reduced, and the performance of a device can be maintained; meanwhile, other steps except for IOPLDD injection in the whole IOPLDD process ring are omitted, including main photoetching measurement CD, overlay accuracy (OVL) measurement, photoresist removal and the like, so that a large amount of raw materials and equipment are saved, and the production period is shortened.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIGS. 1A-1D are schematic views of a device structure at various steps in a method of fabricating a prior art SONOS device;
FIG. 2 is a flow chart of a method of fabricating a SONOS device in accordance with an embodiment of the present invention;
fig. 3A-3B are schematic device structures at each step of a method for fabricating a SONOS device according to an embodiment of the present invention.
Detailed Description
FIG. 2 is a flow chart of a method of fabricating a SONOS device in accordance with an embodiment of the present invention; fig. 3A to 3B are schematic views of device structures in steps of a method for manufacturing a SONOS device according to an embodiment of the present invention; the manufacturing method of the SONOS device comprises the following steps:
step one, as shown in fig. 3A, a semiconductor substrate 101 is provided, a process before a P-type source/drain implantation process is completed, and an IOPLDD process loop is canceled in the process before the P-type source/drain implantation process loop, where IOPLDD is an input/output P-type lightly doped drain.
In the method of the embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.
The process steps before the completed P-type source drain injection process ring comprise: forming a gate structure.
On the semiconductor substrate 101, SONOS devices, input-output devices, and logic devices are integrated at the same time.
The SONOS device is an N-type device;
the input/output device comprises an N-type device and a P-type device;
the logic device includes an N-type device and a P-type device.
The grid structure comprises a first grid structure of the SONOS device, the first grid structure comprises an ONO layer and a polysilicon gate, and the ONO layer is formed by stacking a first oxide layer, a second nitride layer and a third oxide layer;
the gate structure includes a second gate structure of the input-output device and a third gate structure of the logic device;
the second gate structure comprises a first gate oxide layer and a polysilicon gate which are sequentially overlapped;
the third gate structure comprises a second gate oxide layer and a polysilicon gate which are sequentially overlapped;
the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer.
Step two, carrying out the P-type source drain injection process loop, which comprises the following steps:
in step 21, as shown in fig. 3A, a mask layer 102 is formed and the mask layer 102 is patterned, and the patterned mask layer 102 opens the P-type source-drain implantation region and covers the outside of the P-type source-drain implantation region.
In the method of the embodiment of the present invention, the mask layer 102 is made of photoresist;
and forming the photoresist by adopting a photoetching process and patterning the photoresist. Patterning requires definition using a photomask.
In step 21, the opened P-type source drain implant region includes a source drain implant region of a P-type input-output device.
In step 22, as shown in fig. 3B, the IOPLDD is implanted using the mask layer 102 as a mask to form an IOPLDD region (not shown).
In step 23, as shown in fig. 3B, P-type source-drain implantation is performed to form a P-type source-drain region (not shown) by using the mask layer 102 as a mask, where the junction depth of the IOPLDD region is greater than the junction depth of the P-type source-drain region.
The method of the embodiment of the invention further comprises the following steps:
and step 24, performing P-type LDD injection to form an LDD region, wherein the junction depth of the LDD region is smaller than that of the P-type source drain region.
And 25, performing N-type pocket implantation to form an N-type pocket region.
As can be seen from steps 22 to 25, in the second step of the method according to the embodiment of the present invention, 4 ion implantations are simultaneously performed, but only one layer of mask is used for defining, and in fig. 3B, the arrow lines corresponding to reference numeral 103 indicate ion implantations.
Unlike the prior art that an IOPLDD process ring is required to be carried out independently, the embodiment of the invention cancels the IOPLDD process ring, places the step of IOPLDD injection in a P-type source drain injection process ring, thus, adopts a graphical definition process in the P-type source drain injection process ring to simultaneously define an injection region of IOPLDD injection, and additionally adds one IOPLDD injection in the P-type source drain injection process ring to compensate the injection in the IOPLDD loop after canceling the IOPLDD loop, so that the embodiment of the invention can save a photomask for defining the injection region of IOPLDD injection once, thereby greatly reducing the process cost, but simultaneously keeping the performance of devices; meanwhile, other steps except for IOPLDD injection in the whole IOPLDD process ring are omitted, including CD measurement by main photoetching, OVL measurement, photoresist removal and the like, so that a large amount of raw materials and equipment are saved, and the production period is shortened.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (10)

1. A method of fabricating a SONOS device, comprising the steps of:
step one, providing a semiconductor substrate, completing a process before a P-type source drain injection process ring, and canceling an IOPLDD process ring in the process before the P-type source drain injection process ring, wherein IOPLDD is an input/output P-type lightly doped drain;
step two, carrying out the P-type source drain injection process loop, which comprises the following steps:
step 21, forming a mask layer and patterning the mask layer, wherein the patterned mask layer opens a P-type source drain injection region and covers the outside of the P-type source drain injection region;
step 22, performing IOPLDD injection by using the mask layer as a mask to form an IOPLDD region;
and step 23, performing P-type source-drain injection by using the mask layer as a mask to form a P-type source-drain region, wherein the junction depth of the IOPLDD region is larger than that of the P-type source-drain region.
2. The method of fabricating a SONOS device of claim 1, further comprising: the semiconductor substrate includes a silicon substrate.
3. The method of fabricating a SONOS device of claim 1, further comprising: in the first step, the process steps before the P-type source drain injection process ring are completed include:
forming a gate structure.
4. The method of fabricating a SONOS device of claim 1, further comprising: in step 21, the mask layer is made of photoresist;
and forming the photoresist by adopting a photoetching process and patterning the photoresist.
5. The method of fabricating a SONOS device of claim 1, further comprising: in the second step, the method further comprises:
and step 24, performing P-type LDD injection to form an LDD region, wherein the junction depth of the LDD region is smaller than that of the P-type source drain region.
6. The method of fabricating a SONOS device of claim 5, further comprising: in the second step, the method further comprises:
and 25, performing N-type pocket implantation to form an N-type pocket region.
7. The method of fabricating a SONOS device of claim 3, further comprising: and the SONOS device, the input/output device and the logic device are integrated on the semiconductor substrate at the same time.
8. The method of fabricating a SONOS device of claim 7, further comprising: the SONOS device is an N-type device;
the input/output device comprises an N-type device and a P-type device;
the logic device includes an N-type device and a P-type device.
9. The method of fabricating a SONOS device of claim 8, further comprising: the grid structure comprises a first grid structure of the SONOS device, the first grid structure comprises an ONO layer and a polysilicon gate, and the ONO layer is formed by stacking a first oxide layer, a second nitride layer and a third oxide layer;
the gate structure includes a second gate structure of the input-output device and a third gate structure of the logic device;
the second gate structure comprises a first gate oxide layer and a polysilicon gate which are sequentially overlapped;
the third gate structure comprises a second gate oxide layer and a polysilicon gate which are sequentially overlapped;
the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer.
10. The method of fabricating a SONOS device of claim 8, further comprising: in step 21, the opened P-type source drain implant region includes a source drain implant region of a P-type input-output device.
CN202310891144.XA 2023-07-19 2023-07-19 Manufacturing method of SONOS device Pending CN116940119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310891144.XA CN116940119A (en) 2023-07-19 2023-07-19 Manufacturing method of SONOS device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310891144.XA CN116940119A (en) 2023-07-19 2023-07-19 Manufacturing method of SONOS device

Publications (1)

Publication Number Publication Date
CN116940119A true CN116940119A (en) 2023-10-24

Family

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Country Status (1)

Country Link
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