CN116938742A

CN116938742A - Network chip networking simulation verification system

Info

Publication number: CN116938742A
Application number: CN202311002002.XA
Authority: CN
Inventors: 周鹏; 孙向东
Original assignee: New H3C Semiconductor Technology Co Ltd
Current assignee: New H3C Semiconductor Technology Co Ltd
Priority date: 2023-08-09
Filing date: 2023-08-09
Publication date: 2023-10-24

Abstract

The embodiment of the application provides a network chip networking simulation verification system, which is used for packaging a service flow table into a first configuration message by a master control upper computer and sending the first configuration message to a network switch. The network switch forwards the received first configuration message to the FPGA single board, and then the FPGA single board analyzes the first configuration message to obtain a service flow table. The packet transmitter constructs a first service message and transmits the first service message to the FPGA single board. And the FPGA single board forwards the received first service message according to the service flow table. After receiving the second service message, the packet transmitter performs chip function verification according to the first service message and the second service message. According to the scheme of the application, the coverage verification of each scene function of the networking model of the network chip is completed by simulating the network chip function through the FPGA single board, so that the cost is saved, the chip design quality is improved, and the accuracy and stability of the chip in use under the networking scene are ensured.

Description

Network chip networking simulation verification system

Technical Field

The application relates to the technical field of communication, in particular to a network chip networking simulation verification system.

Background

With the development of integrated circuits, the design of chips is more and more complex, and the application scenes of chips are wider. In the chip design process, chip verification plays a decisive role in success or failure of the chip, so that the chip verification stage needs to be full and complete.

At present, the chip verification scheme is completed by adopting a simulation verification platform, and the main simulation verification platforms comprise prototype verification platforms such as EDA (Electronic design automation ), simulation (hardware simulation), FPGA (Field Programmable Gate Array ) and the like. The EDA prototype verification platform has a low simulation speed and is generally suitable for chip module level verification in the initial stage of chip verification. The verification is mainly completed by an emulsion or FPGA prototype verification platform for the system level.

At present, the application scene of part of network communication chips is very complex, and most of the network communication chips relate to networking scenes among multiple chips. With the above prototype verification platform, a prototype verification apparatus is typically capable of simulating only one chip function. Therefore, the single prototype verification platform is difficult to simulate a networking model verification scene requiring a plurality of chips due to resource limitation. For such a scenario verification of a network of multiple chips, multiple prototype verification platforms are required to simulate multiple chips. However, such prototype verification platforms are very expensive and very expensive to maintain, and this solution clearly increases the verification costs considerably. If the networking model of the chip to be verified needs a large number of chips, the scheme is too high in cost to be realized basically. Secondly, the operation frequency of the prototype verification platform is generally low, and when a large number of register configurations and Static Random-Access Memory (SRAM)/external storage read-write operations exist in the chip, the operation time is long, and the verification time cost is indirectly increased.

Disclosure of Invention

The embodiment of the application aims to provide a network chip networking simulation verification system so as to realize the purposes of saving the chip verification cost, shortening the chip verification period and improving the quality of chip design. The specific technical scheme is as follows:

the application provides a network chip networking simulation verification system, which comprises: the system comprises a master control upper computer, a network switch, a packet transmitter and at least one FPGA single board, wherein the master control upper computer and each FPGA single board are connected to the same network switch, and each FPGA single board is pre-configured as a chip to be verified;

the master control upper computer is used for packaging a service flow table into a first configuration message and sending the first configuration message to the network switch;

the network switch is used for forwarding the received first configuration message to the FPGA single board;

the FPGA single board is used for analyzing the first configuration message to obtain the service flow table;

the packet transmitter is used for constructing a first service message and transmitting the first service message to the FPGA single board;

the FPGA single board is further used for forwarding the received first service message according to the service flow table;

The packet transmitter is further configured to receive a second service packet, where the second service packet is a service packet forwarded by one or more FPGA boards, and perform chip function verification according to the first service packet and the second service packet.

Optionally, the FPGA board includes a configuration interface and at least one service interface;

the FPGA single board is specifically used for receiving a configuration message sent by the master control upper computer through a configuration interface;

the FPGA single board is specifically further configured to receive the first service message through a service interface, search a service flow table based on address information of the first service message, determine a destination service interface connected to a next FPGA single board, and send the first service message through the destination service interface.

Optionally, the master control upper computer is further configured to store a plurality of device identifiers, where the device identifiers respectively mark media access control MAC addresses of the FPGA boards, and each FPGA board is preset with a MAC address corresponding to the FPGA board.

Optionally, the master control upper computer is further configured to encapsulate the register configuration information into a second configuration packet, and send the second configuration packet to the network switch;

The network switch is further configured to forward the received second configuration message to the FPGA board;

the FPGA single board is further used for analyzing the second configuration message to obtain the register configuration information, and initializing and configuring the register according to the register configuration information.

Optionally, the FPGA board is specifically configured to parse the second configuration message to obtain the register configuration information, and perform initialization configuration on the service interface and the service forwarding unit in the FPGA board according to the register configuration information.

Optionally, the FPGA board is further configured to query, after receiving the configuration packet, whether the MAC address carried by the configuration packet is consistent with a MAC address preset by itself, and if not, discard the configuration packet; the configuration message is a first configuration message or a second configuration message.

Optionally, the configuration message transferred between the master control upper computer and the FPGA board is encapsulated based on a custom private protocol.

Optionally, the FPGA board is further configured to determine whether the identifier of the configuration packet is consistent with the identifier of the packet based on the custom private protocol encapsulation sent by the master control upper computer when the MAC address carried by the configuration packet is consistent with the MAC address preset by the FPGA board, and if not, discard the configuration packet.

Optionally, performing chip function verification according to the first service packet and the second service packet may include one or more of the following:

according to whether the loads of the first service message and the second service message are consistent;

judging whether the performance of a network chip set network simulation verification system forwarding message reaches a preset standard or not according to the first service message and the second service message;

judging whether packet error and packet loss occur in the process of forwarding the message by a network chip set network simulation verification system according to the first service message and the second service message;

judging whether a system abnormality problem exists in the process of forwarding the message by the network chip set network simulation verification system according to the first service message and the second service message.

Optionally, the service interface of the FPGA board is connected with the service interface of another FPGA board through a hot plug optical module.

The embodiment of the application has the beneficial effects that:

the network chip networking simulation verification system provided by the embodiment of the application comprises a master control upper computer, a network switch, a packet transmitter and at least one FPGA single board, wherein the master control upper computer and each FPGA single board are connected into the same network switch, and each FPGA single board is pre-configured as a chip to be verified. The master control upper computer is used for packaging the service flow table into a first configuration message and sending the first configuration message to the network switch. The network switch forwards the received first configuration message to the FPGA single board, and then the FPGA single board analyzes the first configuration message to obtain a service flow table. After the configuration is completed, the packet transmitter constructs a first service message and transmits the first service message to the FPGA single board. And the FPGA single board forwards the received first service message according to the service flow table. After receiving the second service message, the packet transmitter performs chip function verification according to the first service message and the second service message, wherein the second service message is a service message forwarded by one or more FPGA single boards. According to the scheme of the application, the coverage verification of each scene function of the networking model of the network chip is completed by simulating the network chip function through the FPGA single board, so that the cost is saved, the chip design quality is improved, and the accuracy and stability of the chip in use under the networking scene are ensured. Register configuration data exchange is realized between the master control upper computer and the FPGA single board through a custom private protocol configuration message, so that the FPGA single board does not need to realize protocol stack development work, and development cost is saved.

Compared with the prior art, the running frequency of the FPGA single board is generally about 30M-50M, and the running frequency of other prototype verification platforms in the prior art is about 1M. Therefore, the chip simulation verification is carried out based on the FPGA single board, and the chip verification period can be effectively shortened.

Of course, it is not necessary for any one product or method of practicing the application to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and other embodiments may be obtained according to these drawings to those skilled in the art.

FIG. 1 is a diagram of a prototype verification platform multi-chip networking in the prior art;

fig. 2 is a schematic structural diagram of a network chipset network simulation verification system according to an embodiment of the present application;

FIG. 3 is a flow chart of a business interface data processing provided by an embodiment of the present application;

fig. 4 is a correlation diagram of a master control upper computer and an FPGA board provided by an embodiment of the present application;

FIG. 5 is a block diagram of a configuration interface data processing provided by an embodiment of the present application;

FIG. 6 is a schematic flow chart of a configuration method of a single board register of an FPGA according to an embodiment of the present application;

FIG. 7 is a flow chart of a response mechanism according to an embodiment of the present application;

FIG. 8 is a schematic flow chart of a method for configuring and processing a single board register of an FPGA according to an embodiment of the present application;

fig. 9 is a schematic flow chart of a network chipset network simulation verification method according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art based on the present application are included in the scope of protection of the present application.

Currently, the chip verification scheme is implemented by adopting a simulation verification platform, and for the mainstream prototype verification platform, such as FPGA, emulation, one prototype verification device can only simulate one chip function. The current application scenarios of the partial network communication chips are very complex, and most of the application scenarios involve networking scenarios among multiple chips, and for the scenario verification of networking of the multiple chips, multiple prototype verification platforms are required to simulate the multiple chips. As shown in fig. 1, fig. 1 is a diagram of a prototype verification platform multi-chip networking in the prior art. The prototype verification platform multi-chip networking diagram shown in fig. 1 comprises n prototype verification platforms, each prototype verification platform mainly comprises a storage module 101, an internal chip module SRAM102, a key interface comprising a PCIe (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) interface 103 and a plurality of service interfaces 104 (service interface 1-service interface n), wherein the PCIe interface 103 is used as a chip configuration management interface and is mainly responsible for a chip register access path. The service interface may be any one of Ethernet interface, an Interlaken (an interconnection protocol optimized for realizing high bandwidth and reliable packet transmission) interface, flexE (Flexible Ethernet ) interface, and the like, and may be defined according to requirements.

However, the disadvantage of using the prototype verification platform to perform network chipset network simulation verification is also obvious, firstly, the prototype verification platform is expensive, the maintenance cost is high, and if a plurality of prototype verification devices are used, the verification cost is greatly increased. And if the networking model of the chip to be verified needs a large number of chips, the scheme may be too high in cost to be realized basically. Second, the prototype verification platform generally has a low operating frequency, and when there are a large number of register configurations and SRAM/external memory read/write operations in the chip, the running time is long, which indirectly increases the verification time cost.

In order to solve the above technical problems, the present application provides a network chipset network simulation verification system, as shown in fig. 2, fig. 2 is a schematic structural diagram of the network chipset network simulation verification system provided by the embodiment of the present application. The network chip networking simulation verification system comprises a master control upper computer, a network switch, a packet transmitter and at least one FPGA single board, wherein the master control upper computer and each FPGA single board are connected into the same network switch.

The master control upper computer 201 is configured to encapsulate the service flow table into a first configuration message, and send the first configuration message to the network switch.

In this embodiment, the master control upper computer needs to initialize a table structure required for forwarding the chip service, and encapsulates the service flow table into a first configuration message. Common traffic flow tables may include Table tables, hash tables, ultraIp tables, and the like. The management of the table entries can be performed according to actual service requirements.

The host computer 201 may be a PC (Personal Computer ) or a Server (Server). The master control upper computer can be connected with a network switch through a NIC (Network Interface Card ).

The network switch 202 is configured to forward the received first configuration message to the FPGA board.

A network switch can be understood as a device that extends a network and is used to forward configuration messages sent by a host computer. The master control upper computer can be connected with more FPGA single boards through the network switch.

In this embodiment, after receiving the first configuration message, the network switch forwards the first configuration message to the configuration interface of each FPGA board in the network chipset network.

And the FPGA single board receives a configuration message sent by the master control upper computer through the configuration interface. For example, the network switch is connected with three FPGA boards, namely fpga_1, fpga_2 and fpga_3. After receiving the configuration message sent by the master control upper computer, the network switch forwards the configuration message to the configuration interface of the FPGA_1, the configuration interface of the FPGA_2 and the configuration interface of the FPGA_3 respectively.

The FPGA board 203 is configured to parse the first configuration packet to obtain a service flow table.

In this embodiment, each FPGA board is configured in advance as a chip to be verified. Specifically, the FPGA hardware device can be started, a file comprehensively generated by the source codes of the chip to be verified is loaded, the FPGA hardware is initialized, and the FPGA single board is configured as the chip to be verified.

It will be appreciated by those skilled in the art that the FPGA board configured as the chip to be verified has modules such as a data processing module, a service processing module, a register access module, and the like.

In this embodiment, the FPGA board receives, through the configuration interface, a first configuration message sent by the network switch. After receiving the first configuration message, the FPGA board analyzes the first configuration message to obtain a service flow table, and stores the service flow table in a storage space of the FPGA board.

The packet sender 204 is configured to construct a first service packet, and send the first service packet to the FPGA board.

The packet transmitter transmits the constructed first service message to the service interface of each FPGA single board.

For example, there are three FPGA boards in the network chipset, respectively fpga_1, fpga_2 and fpga_3, and then the packet sender sends the first service packet to the service interface of fpga_1, the service interface of fpga_2 and the service interface of fpga_3.

The FPGA board 203 is further configured to forward the received first service packet according to the service flow table.

In this embodiment, after the FPGA board receives the first service packet sent by the packet sender through one service interface, the FPGA board performs the chip service data processing logic, which may refer to that the chip service forwarding module in the FPGA board performs the service flow table lookup based on the address information of the first service packet, determines the destination service interface connected to the next FPGA board, and sends the first service packet through the destination service interface connected to the next FPGA board, and the next FPGA board that receives the first service packet performs the same operation as the foregoing step. The structure of the traffic flow table entry is typically a key-result structure, that is, the corresponding result can be found in the traffic flow table by means of a key (key, which can be understood as address information) in the first traffic message. Because the information related to the forwarding of the first service message is stored in the result, the chip service forwarding module can determine a destination service interface connected with the next FPGA single board through the information, and send the first service message to the next FPGA single board to be transmitted through the destination service interface. The address information may be determined according to its own service, and may be, for example, an IP (Internet Protocol ) address, a MAC (Medium Access Control, media access control) address, or the like.

For example, the fpga_1 has three service interfaces, namely a service interface 11, a service interface 12 and a service interface 13, after the fpga_1 receives a first service packet sent by the packet transmitter through the service interface 11, according to key1 in the first service packet, a result1 corresponding to the key1 is determined through a service flow table, and then a destination service interface is determined to be the service interface 13 according to information stored in the result1, where a chip service forwarding module in the fpga_1 may forward the first service packet to the fpga_2 through the service interface 13. After receiving the first service message sent by the fpga_1, the fpga_2 executes the same operation executed by the fpga_1.

Referring to fig. 3, fig. 3 is a flow chart of service interface data processing provided by the embodiment of the present application, where after constructing a first service message, a packet sender sends the first service message to a service interface of each FPGA board. Taking the first service message transmission direction as fpga_0 to fpga_n as an example. After receiving the first service message sent by the packet transmitter through the service interface 1, the fpga_0 determines result0 corresponding to the key0 through the service flow table according to the key0 in the first service message, and then determines that the target service interface is the service interface 2 according to the information stored in the result0, and at this time, the chip service forwarding module in the fpga_0 may forward the first service message to the fpga_n through the service interface 2. The fpga_n also performs the same operation after receiving the first service packet through the service interface 3, determines that the destination service interface is the service interface 4, and forwards the first service packet.

In this embodiment, the FPGA board includes a configuration interface and at least one service interface. Service interfaces among the FPGA single boards are connected through optical fibers or Cable (Cable television Cable) wires, so that transmission of service messages across the FPGA single boards is realized. The service interface supports common network interfaces such as Ethernet interface, interlaken interface, flexE interface and the like.

The packet transmitter 204 is further configured to receive a second service packet, where the second service packet is a service packet forwarded by one or more FPGA boards, and perform chip function verification according to the first service packet and the second service packet.

The packet transmitter transmits the first service message to the service interface of the FPGA single board, and receives the second service message through the service interface of the FPGA single board, wherein the second service message is the service message forwarded by one or more FPGA single boards.

It can be understood that the first service message is a generic name of the service message originally sent by the packet sender, and the second service message is a generic name of the service message finally received by the packet sender, so that chip function verification can be performed according to the first service message and the second service message.

In this embodiment, performing chip function verification according to the first service packet and the second service packet may include judging whether the performance of the forwarding message of the network chipset network emulation and verification system accords with the expectation according to whether the load of the first service packet sent by the packet sender is consistent with the load of the second service packet received by the packet sender, judging whether the packet error and packet loss occur in the forwarding message of the network chipset network emulation and verification system according to the first service packet and the second service packet, judging whether the system abnormality problem exists in the forwarding message of the network chipset network emulation and verification system according to the first service packet and the second service packet, or judging other indexes.

By adopting the network chip networking simulation verification system provided by the embodiment of the application, the master control upper computer encapsulates the service flow table into the first configuration message and sends the first configuration message to the network switch. The network switch forwards the received first configuration message to the FPGA single board, and then the FPGA single board analyzes the first configuration message to obtain a service flow table. The packet transmitter constructs a first service message and transmits the first service message to the FPGA single board. And the FPGA single board forwards the received first service message according to the service flow table. After receiving the second service message, the packet transmitter performs chip function verification according to the first service message and the second service message, wherein the second service message is a service message forwarded by one or more FPGA single boards. In the scheme of the application, the coverage verification of each scene function of the networking model of the network chip is completed by simulating the network chip function through the FPGA single board, so that the cost is saved, the chip design quality is improved, and the accuracy and the stability of the chip in use under the networking scene are ensured. Register configuration data exchange is realized between the master control upper computer and the FPGA single board through a custom private protocol configuration message, so that the FPGA single board does not need to realize protocol stack development work, and development cost is saved.

And compared with the prior art, the running frequency of the FPGA single board is generally about 30M-50M, and the running frequency of other prototype verification platforms in the prior art is about 1M. Therefore, the chip simulation verification is carried out based on the FPGA single board, and the chip verification period can be effectively shortened.

In order to enable the master control upper computer to more conveniently and accurately correspond to each FPGA single board, a plurality of devices (device identifiers) are also stored in the master control upper computer, and the device identifiers respectively mark the MAC addresses, namely the physical addresses, of the FPGA single boards. Each FPGA single board is preset with a unique MAC address corresponding to the FPGA single board.

In this embodiment, in order to further explain the association relationship between the device and the MAC address of the FPGA board. Taking fig. 4 as an example, as shown in fig. 4, fig. 4 is a correlation diagram of a master control upper computer and an FPGA board provided by an embodiment of the present application. Each FPGA single board is preset with a unique MAC address corresponding to the FPGA single board. n FPGA boards correspond to n MAC addresses, and the MAC address of each FPGA board is unique. The FPGA boards are distinguished by the lowest byte of the MAC address, for example, MAC address 0 of fpga_0 is xx: xx: xx: xx:01, the MAC address 1 of FPGA_1 is xx: xx: xx:02, and the MAC address n-1 of FPGA_n-1 is xx: xx: xx: n. And storing a plurality of devices which are respectively in one-to-one correspondence with the FPGA single boards in the master control upper computer. The device marks the MAC addresses of the FPGA single boards respectively. The lowest bytes of the preset MAC addresses of the FPGA boards are sequentially incremented, as illustrated in fig. 4, and in fig. 4, n FPGA boards are provided, so that the lowest bytes of the MAC addresses of the FPGA boards are sequentially 1, 2, 3, …, and n (1 n is not less than 255) corresponding to n FPGA boards. Corresponding to the MAC addresses of n FPGA boards, the device may be correspondingly the lowest byte of the MAC address minus 1. For example, also taking n FPGA boards as an example, the devid changes stored in the host computer may be 0, 1, 2, n-1 (1 n 255). Based on the method, the master control upper computer can accurately access the FPGA single board corresponding to the device only by the control program according to the device. Through the embodiment, the efficient management of a plurality of FPGA single boards in the system can be realized, when the FPGA single boards in the system are dynamically added or deleted, the master control upper computer can quickly sense, the management cost caused by the change of a networking model can be effectively reduced, the one-to-many configuration management mode of the master control upper computer and the FPGA single boards is realized, and the flexibility and the accuracy of the master control upper computer on the chip configuration management are improved.

For example, the control program of the host computer can access the FPGA_0 with the MAC address of xx: xx: xx: xx:01 through the device_0. Or the control program of the master host computer can access the FPGA_n-1 with the MAC address of xx, 0n through the device_n-1.

In this embodiment, the configuration interface of the FPGA board is connected to the network switch through the daughter card. The daughter card may be a PHY (Physical Layer chip) daughter card. The daughter card and the network switch can be connected through optical fibers or twisted pair wires. There is a communication interface between the MAC and PHY daughter cards, and common communication interfaces are GMII (Gigabit Medium Independent Interface, gigabit media independent interface), RGMII (Reduced Gigabit Media Independent Interface, simplified gigabit media independent interface), and the like.

In this embodiment, taking the daughter card as the PHY daughter card and the interface as the RGMII as an example, as shown in fig. 5, fig. 5 is a configuration interface data processing block diagram provided in the embodiment of the present application. The FPGA single board is connected with the network switch through the PHY sub-card. After the network switch sends the second configuration message to the PHY sub-card, the FPGA single board acquires the second configuration message in the PHY sub-card through RGMII, and then analyzes the second configuration message through the data processing module to analyze the register configuration information in the second configuration message. The register configuration information may include register addresses and data. After the analysis is carried out to obtain the register configuration information, the register configuration information is transmitted to a chip register access module through an internal bus of the FPGA single board, and the register access operation is completed. And initializing and configuring the register according to the register configuration information. Specifically, the initializing configuration of the register may be initializing configuration of the service interface and the service forwarding unit in the FPGA board. Because the FPGA board is preconfigured as the chip to be verified, the service forwarding unit in the FPGA board is initialized, which may refer to initializing some registers related to the service forwarding unit in the chip to be verified in this step.

Because the master control upper computer sends the configuration message to the network switch, the network switch forwards the configuration message to each FPGA single board, and therefore the FPGA single board needs to determine whether the configuration message is the configuration message sent to itself or not after receiving the configuration message. The judgment can be performed by inquiring whether the MAC address carried by the configuration message is consistent with the MAC address preset by the configuration message. If so, then subsequent steps may be performed based on the configuration message. If not, discarding the configuration message. The configuration message comprises a first configuration message or a second configuration message.

In order to further save development cost, in the embodiment of the application, the configuration message transmitted between the master control upper computer and the FPGA single board is packaged based on a custom private protocol. For example, the message used in the scheme of the application can be a two-layer message, compared with the common message in the prior art, the message is more complex, the development cost is high, and the custom private protocol configuration message used in the scheme does not need to realize protocol stack development work, so that the development work of an FPGA platform is reduced, and the development cost is saved.

Based on the configuration message of the self-defined private protocol, the FPGA single board needs to judge whether the identification number of the configuration message is consistent with the identification number of the configuration message based on the self-defined private protocol package and sent by the master control upper computer after receiving the configuration message consistent with the self MAC address and sent by the network switch. As the network switch may send some generic standard messages. Therefore, by judging the identification number of the message, whether the message is the first configuration message or the second configuration message sent by the master control upper computer can be distinguished.

In the embodiment of the application, chip function verification can be performed according to the first service message and the second service message, and the chip function verification can be realized in one or more of the following modes:

and carrying out chip function verification according to whether the payload (load) of the first service message is consistent with that of the second service message. Or judging whether the performance of the network chip set network simulation verification system forwarding message reaches a preset standard according to the first service message and the second service message. Those skilled in the art will appreciate that bandwidth, latency, etc. may be used to determine the performance of the forwarding message. Or judging whether packet error and packet loss occur in the process of forwarding the message by the network chip networking simulation verification system according to the first service message and the second service message. Or judging whether the network chip set network simulation verification system has a system abnormality problem in the process of forwarding the message according to the first service message and the second service message, wherein the abnormality problem can comprise the problems of abnormal restarting of the system, hanging death in the running process of a certain FPGA single board and the like. Specifically, the output ports of the FPGA boards are connected to the input ports of the packet transmitter, the first service packet sent by the packet transmitter is forwarded by the FPGA boards and then is returned to the packet transmitter as the second service packet, and the connection relationship (through supporting the connection of the hot plug optical module) between the output interfaces of the FPGA boards and the input ports of the packet transmitter can be preset. Based on the method, the packet transmitter can judge whether an abnormality occurs in a certain FPGA single board in the system by judging whether the service message from the certain FPGA single board is normally received or not, so that the chip function verification is realized.

Or, the chip function verification can be performed by other indexes such as system stability verification, ultra-long time streaming test, long-time work of the chip, whether the chip forwarding function is normal, whether the performance meets the standard, and the like.

By the verification method, coverage verification of each scene function of the multi-chip networking model can be achieved, and the accuracy and stability of the chip in use under networking scenes are ensured.

In the embodiment of the application, the service interface of the FPGA single board is connected with the service interface of another FPGA single board through the supporting hot plug optical module. The optical module of the FPGA single board service interface supports dynamic hot plug, can conveniently and rapidly switch the form of the networking model, can effectively cover each networking scene of multiple chips, ensures the completeness of the chip verification stage and the design quality of the chip, and improves the success rate of chip design.

For example, when the fpga_1 is required to be connected with the fpga_2, the fpga_1 and the fpga_2 are connected with the optical module. If the FPGA_1 is required to be connected with the FPGA_3, the FPGA_2 connected with the optical module can be pulled out, and then the FPGA_3 is inserted into the optical module, so that the network chip networking model can be quickly switched.

Before the first configuration message is sent to perform flow table configuration, a register in the FPGA board needs to be initialized, and a specific flow is shown in fig. 6, and fig. 6 is a schematic flow diagram of a method for configuring a register in the FPGA board, where the steps include:

and step S601, starting the FPGA hardware equipment, loading a file comprehensively generated by the chip source codes, and initializing the FPGA hardware.

And powering on the FPGA single board equipment, loading a file comprehensively generated by the source codes of the chip to be verified to the FPGA single board, initializing the hardware environment of the FPGA single board, and configuring the FPGA single board as the chip to be verified. The initialization of the configuration interface of the FPGA single board is completed in the step, and the FPGA single board is bound according to the pre-allocated MAC address.

Step S602, the master control upper computer runs a control program and initializes parameters of the master control upper computer network card.

The master control upper computer runs the control program to configure the master control upper computer network card, and the hybrid mode of the master control upper computer network card can be started, so that the messages between the master control upper computer and the FPGA single board are ensured not to be discarded by the network card.

Step S603, the control program of the master control upper computer initiates a configuration access request and waits for response data of the FPGA single board.

In the embodiment of the application, a Request-Response waiting mechanism is adopted for the sending and receiving of the messages so as to ensure that the sending and receiving of all the messages of the control program of the master control upper computer can be successfully completed. The Request-Response waiting mechanism refers to that after a client (master host) sends a Request to a server (FPGA board), the client waits for a Response from the server to the Request. The client does not continue to execute in the process of waiting for the response, and does not continue to execute the subsequent operation until the response of the server is received. Fig. 7 is a schematic flow chart of a response mechanism according to an embodiment of the present application, as shown in fig. 7. After sending Request (configuration message), the control program of the master control upper computer enters wait state to wait for Response data of the FPGA single board. If the main control upper computer receives the response data of the FPGA single board within the specified time, the successful execution of the current configuration message transmission is indicated. Otherwise, if the main control upper computer does not receive the response data of the FPGA single board within the specified time, the main control upper computer control program reports the abnormal result of the access timeout, which indicates that the sending and executing of the configuration message fails.

By adopting a Request-Response waiting mechanism, the master control upper computer can know whether the message sent by the master control upper computer is received by the FPGA single board or not, and can ensure that the sequence of the message received by the FPGA single board is consistent with the sequence of the message sent by the master control upper computer, thereby improving the reliability.

In step S604, the FPGA board parses the configuration access request of the host computer control program and responds to the parsing request.

After the FPGA single board collects a configuration access request (namely, a second configuration message containing register configuration information) of the configuration interface through the RGMII interface, the second configuration message is analyzed to obtain register configuration information, the register configuration information can comprise an address and data accessed by a register, then the address and the data are sent to the register through an FPGA internal bus to access, and an access result is sent to a master control upper computer.

Step S605, the master control upper computer control program processes the FPGA single board response data.

And the master control upper computer analyzes the access result sent by the FPGA, if yes, the master control upper computer firstly compares whether the destination MAC address and the source MAC address meet the expectations or not, and then extracts the content of a register data field in the configuration message. In the case of a register write operation, it is only necessary to determine whether the destination MAC address and the source MAC address meet the expectations.

In order to further explain the register initialization step of the FPGA single board, the embodiment of the application provides a method for configuring and processing the register of the FPGA single board. As shown in fig. 8, fig. 8 is a flow chart of a method for processing configuration of a single board register of an FPGA according to an embodiment of the present application, where,

Step S801, start.

Step S802, the FPGA single board collects data of the configuration interface through RGMII.

In this embodiment, the configuration interface of the FPGA board is connected to the port of the network switch through an external PHY daughter card. The FPGA single board collects data (second configuration message) of the configuration interface through RGMII, and the RGMII is an Ethernet communication interface which can be used for communication between the MAC and the PHY sub-card.

Step S803, analyzing the destination MAC and the source MAC, and comparing and judging.

In this embodiment, after the master control upper computer sends the second configuration message to the network switch, the network switch forwards the received second configuration message to each FPGA board in the network chipset network model. Therefore, after receiving the second configuration message, the FPGA board analyzes the destination MAC and the source MAC of the second configuration message.

Step S804, whether the destination MAC is consistent with the MAC of the host computer, and whether the source MAC is consistent with the master host computer.

After resolving the destination MAC address and the source MAC address, the FPGA single board needs to judge whether the destination MAC address is consistent with the MAC address of the FPGA single board. If not, it is indicated that the second configuration message is not sent to the device itself, so that step S806 may be executed, the message is discarded, the next flow is entered, and the step of collecting the data of the configuration interface by the FPGA board through the RGMII is executed. The FPGA board can determine whether the second configuration message is sent by the master host computer by determining whether the source MAC is consistent with the master host computer. If the source MAC address is detected to be inconsistent with the master control upper computer, the second configuration message is sent by a machine of the non-master control upper computer, and the configuration message can be directly discarded.

Step S805, determining whether the message type is consistent with the message sent by the master control host computer.

In this embodiment, the message may be configured using a custom private protocol. Therefore, after receiving the second configuration message, the FPGA board needs to determine whether the type (identifier number) of the second configuration message is consistent with the identifier number of the custom private protocol configuration message sent by the master control upper computer. If not, it is indicated that the received configuration message is not the second configuration message sent by the master control upper computer, so that step S806 is executed, the message is discarded, and the next flow is entered.

Step S806, discarding the message and entering the next flow.

In this embodiment, when the destination MAC address is inconsistent with the MAC address of the host computer, the source MAC address is inconsistent with the host computer, or the message type is inconsistent with the second configuration message sent by the host computer, the message needs to be discarded, and the step of collecting the second configuration message of the configuration interface by the FPGA board through the RGMII is performed.

In step S807, the operation type of the register and the register address and data are parsed, and the address and data are sent to the inside of the chip for access.

After receiving the second configuration message, the FPGA board (chip) analyzes the second configuration message to obtain register configuration information, where the register configuration information may include an operation type of a register, a register address and data, and then sends the register address and data to the FPGA board for register configuration.

Step S808, if the read operation is performed, packaging the data read out by the chip into a message and sending the message to the master control upper computer; if the operation is writing operation, the received message is sent to the master control upper computer.

Step S809 ends.

In this embodiment, the operation type of the register may be a read operation or a write operation. If the read operation is performed, the FPGA single board can package the read data into a message, the MAC address of the master control upper computer is used as a destination MAC address, the MAC address of the FPGA single board is used as a source MAC address, and the message is sent to the master control upper computer. If the write operation is performed, the FPGA single board performs the exchange between the destination MAC address and the source MAC address of the second configuration message, and sends the second configuration message to the master control upper computer.

Based on a network chipset network simulation verification system, the embodiment of the application correspondingly provides a network chipset network simulation verification method, as shown in fig. 9, fig. 9 is a flow diagram of the network chipset network simulation verification method provided by the embodiment of the application, wherein,

step S901, starting FPGA hardware equipment, loading a file comprehensively generated by chip source codes, and initializing FPGA hardware.

And starting the FPGA hardware equipment by powering on, loading a file comprehensively generated by the source codes of the chip to be verified, initializing the FPGA single board hardware, and configuring the FPGA single board as the chip to be verified.

For example, one chip to be verified is chip 1, and the fpga_1 board may be configured as chip 1 by starting the FPGA hardware device and loading a file generated by integrating source codes of chip 1.

Step S902, the master control upper computer runs a control program and initializes each module of the FPGA single board in the networking model to be verified.

The master control upper computer runs a control program, encapsulates the register configuration information into a second configuration message, and sends the second configuration message to the network switch. After receiving the second configuration message, the network switch forwards the second configuration message to each FPGA single board in the networking model to be verified, wherein each FPGA single board is pre-configured as a chip to be verified. The FPGA single board analyzes the received second configuration message to obtain the register configuration information. And initializing each module register according to the register configuration information.

Step S903, the main control upper computer control program initializes the table required by the service forwarding of the chip and issues the table items required by the service forwarding.

In this embodiment, the master control upper computer service flow table is encapsulated into a first configuration message, a table required for forwarding the FPGA board service is initialized, the first configuration message is sent to the network switch, and the network switch forwards the first configuration message to the FPGA board after receiving the first configuration message.

Step S904, a first service message is constructed from the packet transmitter and sent to the FPGA single board, and after the first service message is forwarded in the multi-chip network according to the table item configuration, the obtained second service message is returned to the packet transmitter, and the packet transmitter compares and judges the sent first service message with the received second service message.

The first service message is a service message originally sent by the packet transmitter, and the second service message is a service message finally received by the packet transmitter after passing through one or more FPGA single boards, so that chip function verification can be performed according to the first service message and the second service message.

In this embodiment, the FPGA board is configured as a chip to be verified by simulating the chip function of the FPGA board, then the second configuration message is sent by the master control upper computer to initialize the registers in each FPGA board, and then the service flow table is configured by the first configuration message. Constructing a first service message by a packet transmitter, transmitting the first service message to the configured FPGA single boards for forwarding, and finally receiving a second service message by the packet transmitter, wherein the second service message is the service message forwarded by one or more FPGA single boards. Therefore, the chip function verification can be performed according to the first service message and the second service message. By adopting the scheme to carry out chip simulation verification, the cost is saved, the chip design quality is improved, and the accuracy and stability of the chip in use under a networking scene are ensured. And because the running frequency of the FPGA single board is far higher than that of other prototype verification platforms in the prior art, the chip simulation verification is performed based on the FPGA single board, so that the chip verification period can be effectively shortened.

In the above embodiments, the implementation may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A network chipset network emulation verification system, the system comprising: the system comprises a master control upper computer, a network switch, a packet transmitter and at least one Field Programmable Gate Array (FPGA) single board, wherein the master control upper computer and each FPGA single board are connected into the same network switch, and each FPGA single board is pre-configured as a chip to be verified;

2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the FPGA single board comprises a configuration interface and at least one service interface;

3. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the master control upper computer is further used for storing a plurality of device identifiers which are respectively in one-to-one correspondence with the FPGA single boards, wherein the device identifiers are respectively used for marking Media Access Control (MAC) addresses of the FPGA single boards, and each FPGA single board is preset with a unique MAC address corresponding to the FPGA single board.

4. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the master control upper computer is further used for packaging the register configuration information into a second configuration message and sending the second configuration message to the network switch;

5. The system of claim 4, wherein the system further comprises a controller configured to control the controller,

the FPGA board is specifically configured to parse the second configuration message to obtain the register configuration information, and perform initialization configuration on the service interface and the service forwarding unit in the FPGA board according to the register configuration information.

6. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the FPGA single board is further used for inquiring whether the MAC address carried by the configuration message is consistent with the MAC address preset by the FPGA single board after receiving the configuration message, and discarding the configuration message if not; the configuration message is a first configuration message or a second configuration message.

7. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the configuration message transmitted between the master control upper computer and the FPGA single board is packaged based on a custom private protocol.

8. The system of claim 7, wherein the system further comprises a controller configured to control the controller,

the FPGA single board is further configured to determine whether the identification number of the configuration message is consistent with the identification number of the configuration message based on the custom private protocol encapsulation sent by the master control upper computer when the MAC address carried by the configuration message is consistent with the MAC address preset by the FPGA single board, and discard the configuration message if not.

9. The system of claim 1, wherein the performing chip function verification according to the first service message and the second service message may include one or more of:

judging whether packet error and/or packet loss occurs in the process of forwarding the message by the network chip set network simulation verification system according to the first service message and the second service message;

10. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the service interface of the FPGA single board is connected with the service interface of another FPGA single board through a hot plug supporting optical module.