CN116938232A - On-chip clock frequency reference circuit with low calibration cost and high frequency stability - Google Patents
On-chip clock frequency reference circuit with low calibration cost and high frequency stability Download PDFInfo
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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Abstract
The invention discloses an on-chip clock frequency reference circuit with low calibration cost and high frequency stability, which comprises a numerical control oscillator, a time-to-digital converter based on reverse saturation current reference and a digital loop control logic circuit. The invention uses a diode circuit type temperature sensor based on capacitance discharge and two closed loop structures (a temperature linearity compensation loop and an oscillation frequency locking loop) to replace the FLL combined with the traditional phase detection circuit and the temperature sensor, can eliminate variable factors related to temperature, and finally obtains clock frequency which is irrelevant to the temperature, thereby greatly improving the frequency stability and realizing the clock frequency reference with low calibration cost and high frequency stability.
Description
Technical Field
The invention belongs to the technical field of CMOS clock frequency reference, and particularly relates to an on-chip clock frequency reference circuit with low calibration cost and high frequency stability.
Background
The clock frequency reference On chip (On-chip clock frequency reference) is used in almost all electronic fields of communications, internet of things, mobile devices, systems On chip, etc. For example, a clock is indispensable in a bluetooth low energy design and a microprocessor control unit; in radio devices, a high precision reference clock with a frequency higher than 24MHz is often required; on mobile devices such as cell phones, a lot of crystal with better stability is used as a clock frequency reference source.
The literature [ Li Xu et al, "A0.51nW 32kHz Crystal Oscillator Achieving 2ppb Allan Deviation Floor Using High-Energy-to-Noise-Ratio Pulse Injection," ISSCC, pp.62-64, feb 2020] proposes to design a crystal oscillator circuit with an Ilen bias of about 2ppb using high Energy-to-Noise pulse injection. The literature [ D.Yoon et al, "" A5.58nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks, "" IEEE JSSC, vol.51, no.2, pp.509-522, feb.2016] proposes to replace the conventional amplifier with a pulse drive, the pulse drive is generated by accurate timing of a DLL, and the method can obtain extremely low-voltage oscillation amplitude, thereby realizing low-power design, reaching design indexes of 5.58nW and voltage sensitivity of 30.3ppm/V, but having the disadvantages of high cost, large occupied area and increased difficulty in integrated circuit design at the same Time; in addition, there are resonators made of MEMS, which can realize a high-precision frequency reference, but the cost of integration is also high.
Important indicators of the evaluation clock include the following: precision (ppm/. Degree.C.), voltage sensitivity (ppm/V), allen deviation (ppm), power efficiency (uW/MHz), the advantages of the crystal oscillator are: the frequency stability is good, but the volume is huge, the integration is difficult, and the cost is high. LC time constant frequency references have a very stable output frequency, but the output frequency typically reaches GHz level, consuming power consumption in the mW level, and scaling it to the MHz range requires an LC tank that will significantly increase the chip area. For example, literature [ A.S. Delke, A. -J.Annema, M.S.O.Alink, Y.Jin, J.Verlinden, and B.Nauta, "A columns-based frequency reference achieving a single-trim.+ -. 120ppm accuracy from-50 to 170_C," Proc.IEEE Custom Intgr.circuits conf. (CICC), oct.2020, pp.1-4, doi:10.1109/CICC48029.2020.9075878]Provides a single-point frequency calibration high-precision method based on ColpittsLC oscillator of degree of precision from-50 to 170 ℃ of + -120 ppm, power consumption of 3.5mW, voltage sensitivity of 220ppm/V without power supply regulation [4] 。
The RC time constant frequency base rule is smaller in area, lower in power consumption and beneficial to the development of integration under any standard CMOS process, but the performance is easily affected by PVT, so that the RC time constant frequency base rule is limited to be widely used; thus, it is now an objective to integrate the individual modules of the frequency reference on-chip with a temperature stability of less than 3ppm/°c and a power consumption of less than 10pJ/cycle. Literature [ Gürleyük,Sining Pan,Kofi A.A.Makinwa,“A 16MHz CMOS RC Frequency Reference With±90ppm Inaccuracy From-45℃to 85℃,”IEEE J.Solid-State Circuits,vol.57,no.8,pp.2429–2437,Aug.2022]FLL is used to lock the output frequency of DCO to the frequency phase of the Wien bridge RC filter, but since on-chip resistors and capacitors are used, the characteristics of the filter are related to temperature, and a Wheatstone bridge temperature sensor and a filter output phase digital control signal for controlling DCO are needed to compensate the temperature coefficient. In order to improve the precision of the frequency reference, a resistor and a capacitor in the Wien-bridge adopt a P-type polysilicon resistor and an MIM capacitor respectively; for Wheatstone bridge, in order to optimize the energy efficiency, the temperature sensitivity of the amplifier should be maximum, so that the offset voltage and the impact of flicker noise of the first-stage amplifier can be eliminated by adopting a siliconizing diffusion resistor and a P-type polysilicon resistor and a chopper technology, and finally, the design index that the frequency error is +/-90 ppm, the voltage sensitivity is 0.12%/V and the Allen deviation is 320ppb when the temperature range is changed from-45 ℃ to 85 ℃ is realized.
In summary, the clock frequency is affected by temperature, voltage and process, and the discharge of the diode with biased capacitance is closely related to the temperature, so an on-chip clock frequency reference circuit with low calibration cost and high frequency stability is provided, and a closed loop is formed by the diode discharge, the ADC, the DCO and the digital control logic module, so that the influence of the temperature on the frequency can be eliminated, and a clock signal with high frequency stability is obtained.
Disclosure of Invention
In view of the above, the invention provides an on-chip clock frequency reference circuit with low calibration cost and high frequency stability, which has the advantages of on-chip integration, high frequency stability and low calibration cost.
An on-chip clock frequency reference circuit of low calibration cost and high frequency stability, comprising:
a digital control oscillator for generating a clock signal with a specific frequency according to a frequency control word (Frequency Controlled Word) provided by the digital processing module;
the time-to-digital converter based on reverse saturation current reference firstly divides the frequency of the clock signal to obtain two discharge times t 1 And t 2 Further to discharge time t 1 And t 2 Quantization is performed to obtain two different sets of codewords, one set of which is DOUT (t 1 ) With temperature and discharge time t 1 In relation, the other set of code words DOUT (Δt) is only temperature dependent;
a digital processing module for processing two groups of code words DOUT (t 1 ) And DOUT (delta t) is processed to eliminate the temperature-related variable, so that the output frequency control word is used for controlling the output signal frequency of the numerical control oscillator, thereby forming a closed loop and realizing the purpose of automatic frequency calibration.
Further, the frequency of the output clock signal of the digital control oscillator is controlled by a frequency control word, and the larger the frequency control word is, the higher the frequency of the output signal is; conversely, the smaller the frequency control word, the lower the output signal frequency.
Further, the time-to-digital converter includes:
a first frequency divider according to the frequency division number D div Dividing the clock signal to obtain a basic discharge period t div ；
A second frequency divider based on the frequency division number N 1 For basic discharge period t div Frequency division is carried out to obtain discharge time t 1 ；
A third frequency divider based on the frequency division number N 2 For basic discharge period t div Frequency division is carried out to obtain discharge time t 2 ；
Analog-to-digital conversion module based on diode discharge according to reference voltage V ref Fixed temperature T 0 Reverse saturation current I s (T 0 ) For discharge time t 1 And t 2 Quantization is carried out to obtain code word D t1 And D t2 ；
Digital processing module I, which uses multi-channel multiplexing technique to code word D t1 And D t2 Modulation and demodulation processing is performed to obtain codeword DOUT (t 1 ) And DOUT (t) 2 )，DOUT(t 2 ) With temperature and discharge time t 2 Correlation;
a subtracter for dividing DOUT (t 1 ) Subtract DOUT (t) 2 ) Resulting in codeword DOUT (Δt).
Further, the frequency division number D div To gain-adjust codeword DOUT (delta t), the frequency division number N 1 And N 2 Are all given and N 2 Greater than N 1 。
Further, the analog-to-digital conversion module includes:
diode discharge circuit I based on capacitance for t-charging internal pre-charged capacitance 1 Long discharge, discharge current and reverse saturation current I s (T 0 ) Correlating to obtain the discharge voltage V of the capacitor d1 The discharge voltage V d1 Temperature and discharge time t 1 Correlation;
diode discharge circuit II based on capacitance for t-charging internal pre-charged capacitance 2 Long discharge, discharge current and reverse saturation current I s (T 0 ) Correlating to obtain the discharge voltage V of the capacitor d2 The discharge voltage V d2 Temperature and discharge time t 2 Correlation;
multiplexer for multiplexing discharge voltage V d1 And V d2 Sequentially outputting the signals to an analog-to-digital converter on one channel;
analog-to-digital converter for converting discharge voltage V d1 And V d2 Conversion to the corresponding codeword D t1 And D t2 ；
Demultiplexer for dividing code word D t1 And D t2 Separated from one channel and output as two codewords.
Further, the digital processing module I comprises an accumulation module and a moving average processing module, wherein the accumulation module is used for integrating the code word D t1 And D t2 Each of which is accumulated for N times; the length of the moving average processing module is L, which is used for storing the data accumulated for N times in a register and then carrying out the averaging operation of dividing by L, the length exceeding 4 follows the principle of 'first in first out', namely, the first entered data is removed, new data is stored, then carrying out the averaging operation of dividing by L, and N and L are given values.
Further, the digital processing module comprises a period calculation module, a subtracter and a digital integrator, wherein the period calculation module is used for calculating the period of two groups of code words DOUT (t 1 ) And DOUT (Δt) to eliminate the temperature variation, thereby obtaining a value t of the period out The subtracter divides the value t out Subtracting the reference time t ref A time error is obtained and a digital integrator is used to accumulate this error as a frequency control word for the digitally controlled oscillator.
Further, the digitally controlled oscillator comprises a current mirror, an RC circuit, a comparator, a delay chain, a buffer, and a D flip-flop, wherein:
the current mirror is used for carrying out mirror image replication of a certain multiple on the current input by the band gap reference to obtain two paths of currents with different magnitudes;
the RC circuit utilizes the two paths of currents to flow through the resistor and the capacitor respectively, so that reference voltage is generated on the resistor, and capacitor voltage is generated after the capacitor is charged;
the comparator is used for comparing the capacitance voltage with the reference voltage, and an output signal of the comparator sequentially passes through the delay chain and the buffer and is input to the clock end of the D trigger;
the delay chain changes the transmission delay of the output signal of the comparator by using the adjustment code word in a coarse adjustment and fine adjustment mode, so as to control the output frequency of the numerical control oscillator;
the buffer is used for enhancing the driving capability of the output signal of the comparator and shaping the output signal of the comparator, and simultaneously, the signal is used for controlling the charge and discharge of the capacitor in the RC circuit;
the D trigger is used for carrying out frequency division on the output signal of the comparator to obtain a clock signal with the duty ratio of 50% as the output of the numerical control oscillator.
In summary, in order to improve the frequency stability of the clock source, reduce the calibration cost and improve the chip integration level, the circuit of the present invention uses the temperature linearity compensation loop and the oscillation frequency locking loop to eliminate the temperature related variables through the capacitor-based diode discharge and the time-to-digital converter, thereby achieving the on-chip integrated goals of high frequency stability and low calibration cost.
Drawings
FIG. 1 is a block diagram of a system architecture of an on-chip clock frequency reference circuit of the present invention.
FIG. 2 is a schematic diagram of an embodiment of an on-chip clock frequency reference circuit according to the present invention.
Fig. 3 is a schematic structural diagram of a digitally controlled oscillator according to the present invention.
Fig. 4 is a schematic diagram of a structure of an analog-to-digital converter based on diode discharge.
Fig. 5 (a) to 5 (d) are schematic diagrams of the diode discharge circuit in four modulation cases, respectively.
FIG. 6 shows the in-phase and anti-phase discharge t after demodulation of the ADC output code word 1 、t 2 And a simulation result diagram corresponding to time.
FIG. 7 is a schematic diagram of the simulation results of the output frequency of the present invention with temperature.
Fig. 8 is a schematic diagram of a temperature linearity compensation loop and a digital processing module thereof according to the present invention.
Fig. 9 is a schematic diagram of an oscillation frequency locked loop and a digital processing module thereof according to the present invention.
Detailed Description
In order to more particularly describe the present invention, the following detailed description of the technical scheme of the present invention is provided with reference to the accompanying drawings and the specific embodiments.
As shown in fig. 1, the on-chip clock frequency reference circuit with low calibration cost and high frequency stability of the invention comprises a digital controlled oscillator DCO, a time-to-digital converter based on reverse saturation current reference, and a digital processing module DSP, and the working principle is as follows: firstly, the frequency generated by the numerically controlled oscillator DCO is divided to obtain two discharge periods, and then the discharge periods are passed through a time-digital conversion module based on reverse saturation current reference, wherein the input comprises a reference voltage V ref And a fixed temperature T 0 Reverse saturation current I s (T 0 ) And discharge time t, which are independent of temperature; then, the discharge time t is outputted through the time-to-digital converter based on the reverse saturation current reference 1 Corresponding codeword and discharge time difference (Δt=t 2 -t 1 ) The resulting codeword in which the discharge time t 1 The corresponding code word is related to the discharge time and the temperature, and the code word obtained by the discharge time difference delta t is only related to the temperature; finally, the variables related to the temperature are eliminated through a digital processing module DSP, and the frequency control word obtained through output is used for controlling the frequency of a numerical control oscillator DCO, so that a closed loop is formed, and the purpose of automatic frequency calibration is achieved.
As shown in fig. 2, the time-to-digital converter based on the reverse saturation current reference in the present invention includes an analog-to-digital converter based on diode discharge, a frequency divider, a subtracter and a digital processing module I; as shown in fig. 3, the digitally controlled oscillator is composed of an RC circuit, a current mirror, a comparator, a D flip-flop, a delay chain, and a switch, wherein the current mirror is used for mirror-image copying the current input from the bandgap reference (Bandgap Reference, BGR) by a certain multiple to obtain the current size wanted by the system; the RC circuit has the function that currents with different magnitudes respectively flow through the resistor and the capacitor, so that a reference voltage exists on the resistor, and the voltage of the capacitor is continuously increased in the charging process; the comparator is used for comparing the voltage of the capacitor in the charging process with the reference voltage on the resistor, if the charging voltage on the capacitor is higher than the reference voltage on the resistor, the comparator outputs a high level, and simultaneously discharges the capacitor through the switch, so that the comparator outputs a low level again, and then the switch discharging the capacitor is disconnected, so that the capacitor is charged again, and the comparison result of periodic variation is generated; the purpose of the delay chain is to change the delay time of the delay chain by adjusting the code word so as to control the change of the output frequency; the D flip-flop divides the frequency by two to obtain a clock frequency with a duty cycle of 50%. The frequency adjustment of the numerically controlled oscillator is divided into coarse adjustment and fine adjustment, the purpose of the coarse adjustment is to adjust the frequency to about 20M, and then the fine adjustment is performed to make the frequency output be precise 20M, so that the frequency range which can be adjusted by the coarse adjustment is large, and the frequency range which can be adjusted by the fine adjustment is small. The rough adjustment changes the current flowing into the delay chain by adjusting the code word, thereby changing the delay of the delay chain, finally achieving the purpose of adjusting the frequency, and the rough adjustment has large adjustable frequency range because the changed current changes greatly; the fine tuning is to convert the multi-bit digital signal into a single-bit data stream by a Delta Sigma Modulation (DSM), so as to change the magnitude of the current flowing into the delay chain, but since the fine tuning has little current change, the effect on the frequency adjustment is not very great; the clock signal generated by the DCO is both output and input to the digital loop control logic module.
The invention can give an initial code word to the NC oscillator in a reset state to generate a frequency, then the frequency is divided by a frequency divider, and the frequency division numbers are respectively discharged by a diode 1 (N 1 T is set to div )、t 2 (N 2 T is set to div ) After time, the voltage on the capacitor array is obtained by the difference of two groups of output code words obtained by ADC quantization, and the two groups of output code words are used as a basic discharge period t of the diode div . The circuit comprises two closed loops: the first loop is D obtained by differencing two sets of digital codewords of the ADC div As the frequency division number of DCO, then the DCO is discharged to the diode 1 And t 2 Time, and then the ADC quantifies discharge t respectively 1 、t 2 Obtaining D from the voltage across the capacitive array after time t1 And D t2 Thus, a temperature linearity compensation loop is formed; the second loop is to discharge the output of ADC 1 Codeword D of time t1 And output discharge t 2 Codeword D of time t2 D obtained by making difference div And D t1 The multiplication, subtraction and accumulation are performed to obtain a frequency control word for controlling the frequency output of the digitally controlled oscillator DCO, called an oscillation frequency locked loop.
How the temperature dependent variable is eliminated by the loop will be described in detail below so that the stability of the clock output frequency is improved.
Discharge t through diode 1 The voltage over time can be expressed as:
wherein: m is the diode ideality factor, which is 1 for a silicon diode; k is Boltzmann constant, 1.38×10 -23 J/K; q is the charge of the electron, 1.6x10 -19 C。
If orderThen equation (1) may be rewritten as:
similarly, discharge t through diode 2 The voltage over time can be expressed as:
the voltage difference corresponding to the two different discharge times can be expressed as:
then, the codeword or DOUT (Δt) corresponding to the voltage difference obtained through the ADC quantization can be expressed as:
wherein: alpha represents t 2 /t 1 。
The codeword after the gain adjustment module can be expressed as:
this is the frequency division number used for clock frequency division, where the temperature T can be expressed as:
then the resulting time period t div Can be expressed as:
t div ＝D div *t osc (8)
then t 1 Can be represented as N1 t div ，t 2 Can be represented as N2 t div Then equation (1) can be expressed as:
similarly, discharge t obtained by ADC quantization 1 The codeword corresponding to the time voltage can be expressed as:
if order D t1 ＝KD div The final frequency representation is obtained by transformation as:
wherein:I S (T0) is the reverse saturation current at temperature T0, independent of temperature; k is a proportionality coefficient, the more its bits, D t1 ＝KD div The better this condition is satisfied, the more stable the frequency is. Therefore, it can be seen from the final frequency expression that after passing through the second loop, there is no temperature-dependent variable in the expression, so the frequency is independent of the temperature, and the effect of the temperature on the frequency is eliminated. In addition, since B contains reverse saturation current I S (T0) the reference voltage divided by the reverse saturation current corresponds to R in the RC time constant, while +.>The time-to-digital converter based on reverse saturation current reference is designed to achieve the aim of outputting code words in a linear positive correlation with temperature, and meanwhile, R which does not change with temperature is obtained.
The specific implementation structure of the diode discharge-based analog-to-digital converter is shown in fig. 4, and the purpose of the analog-to-digital converter is to convert the discharge time into corresponding digital output code words, so that the digital signal can be processed correspondingly. Firstly, a diode discharge circuit based on capacitance converts discharge time into corresponding discharge voltage difference; then, the voltage difference corresponding to the two different discharge times is outputted to the analog-to-digital converter on one channel in sequence through the multiplexer, and the advantage is that the signals of the two discharge times are not interfered with each other, and the two times can be quantized through one quantization channel to ensureThe quantization gain is kept unchanged, and finally, the multiplexing technology is adopted to avoid the problem of low-frequency nonlinearity of the ADC, including low-frequency noise and offset voltage; then, the voltage difference information is converted into corresponding digital code words through an analog-to-digital converter, so that a quantization function is realized; finally, the two output code words are separated from one channel through a demultiplexer to obtain two code words, wherein one code word is a discharge time t 1 The resulting code word, another route is defined by the discharge time t 2 The resulting codeword. After passing through a time-to-digital converter based on reverse saturation current reference, two code words D t1 And D t2 Are all in a linear positive correlation with temperature.
The invention adopts a multiplexing modulation mode, can ensure that the transfer function of each data conversion is not changed, saves the area and the power consumption, and can be realized by controlling the sampling process of the analog-to-digital converter.
First, the working principle of an analog-to-digital converter is introduced, wherein the analog-to-digital converter adopts a basic successive approximation type ADC (analog-to-digital converter), and comprises a sampling capacitor, a switch, a comparator and a digital control logic circuit; the sampling capacitor adopts a top plate for sampling, namely the sampled polar plate is also connected with VDD and GND power supply signals, so the design has the advantages of simple digital logic and faster conversion process; the upper polar plate of the switch capacitor array is sampled, the lower polar plate is connected to the input end of the comparator, the sampling capacitor is controlled by a switch, and the switch comprises a bootstrap switch, a transmission gate switch and an AT switch. To prevent the variation of the input signal from affecting the sampling rate, a bootstrap switch is generally used as the sampling switch; in order to sample and obtain a signal with full swing, a complementary transmission gate switch is generally adopted; to prevent current leakage and clock feedthrough, an AT switch is typically employed. When the in-phase capacitor array and the anti-phase capacitor array are both in the sampling phase, the successive approximation phase is started, namely, the first two input voltages are compared through a comparator, and if the in-phase terminal voltage is larger than the anti-phase terminal voltage, the comparison result outputs a high level; otherwise, if the voltage of the opposite phase terminal is larger than the voltage of the same phase terminal, the comparison result outputs a low level; and then the digital control logic controls the capacitance switching on the switched capacitor array according to the output result of the comparator so as to complete analog-to-digital conversion until the comparison of all bits is completed, and the N-bit conversion code word of the ADC is output.
In order to obtain two codewords corresponding to different discharge times in continuous time, a multiplexing mode can be adopted, namely, two paths of signals occupy different time gaps on the same channel, the two paths of signals are separated and do not interfere with each other, then voltage differences obtained in the two different discharge times are quantized into digital codewords through an ADC (analog to digital converter), the processing has the advantages that firstly, conversion from the discharge time to the codewords is completed, secondly, quantization gain can be kept unchanged by quantizing the two times through one quantization channel, and finally, the multiplexing technology is adopted to avoid the problem of low-frequency nonlinearity of the ADC, including low-frequency noise and offset voltage.
The modulation is realized by the control signal output by the digital loop control logic, and the control signal is divided into four cases, fig. 5 (a) is the first case, and the V sampled by the in-phase switch capacitor cm The voltage is connected to the non-inverting terminal of the comparator, and the up-sampling of the inverting switch capacitor is performed by discharging t through the diode 1 The voltage across the capacitor array in time, thus quantified by the ADC, is the in-phase discharge t 1 Codeword of time, where t 1 Is N 1 Frequency division period t div 。
FIG. 5 (b) is a second case of modulation, in which the plates on the in-phase switched capacitor array are always connected to V cm There is no discharge phase, so that V is sampled cm Voltage is charged to V by the polar plate on the reversed-phase capacitor array cm Then discharge t 2 Time (i.e. N 2 Frequency division period t div ) The method comprises the steps of carrying out a first treatment on the surface of the When sampling is finished, the ADC starts to perform successive approximation quantization on the voltage difference of the two input ends, and finally in-phase discharge t is obtained 2 Codeword of time, where t 2 Is N 2 Frequency division period t div 。
FIG. 5 (c) is a third case of modulation in which the plates on the switched capacitor array are always connected to V cm There is no discharge phase, so that V is sampled cm Voltage is charged to V by the polar plate on the in-phase capacitor array cm Then discharge t 1 Time (i.e. N 1 Frequency division period t div ) The method comprises the steps of carrying out a first treatment on the surface of the When sampling is finished, the ADC starts to perform successive approximation quantization on the voltage difference of the two input ends, and finally obtains the reversed phase discharge t 1 Codeword of time, where t 1 Is N 1 Frequency division period t div The method comprises the steps of carrying out a first treatment on the surface of the At this time, the reverse phase discharge t 1 The code word of time just coincides with the in-phase discharge t 1 The codewords of time are opposite.
FIG. 5 (d) is a fourth case of modulation, where the plates on the switched capacitor array are always connected to V cm There is no discharge phase, so that V is sampled cm Voltage is charged to V by the polar plate on the in-phase capacitor array cm Then discharge t 2 Time (i.e. N 2 Frequency division period t div ) The method comprises the steps of carrying out a first treatment on the surface of the When sampling is finished, the ADC starts to perform successive approximation quantization on the voltage difference of the two input ends, and finally obtains the reversed phase discharge t 2 Codeword of time, where t 2 Is N 2 Frequency division period t div The method comprises the steps of carrying out a first treatment on the surface of the At this time, the reverse phase discharge t 2 The code word of time just coincides with the in-phase discharge t 2 The codewords of time are opposite.
The aim of demodulation is to separate the code word multiplexed before into two channels, namely the effect of the demultiplexer, so that the demodulated code word is ensured to be consistent with the code word in modulation, and the accuracy of data conversion is improved.
As can be seen from fig. 6, the forward discharge and the reverse discharge t 1 The time-corresponding code words are identical, the forward discharge and the reverse discharge t 2 The time corresponding code words are consistent because the input end inverts and then performs the complementary code taking operation on the output code words during the modulation, which is equivalent to the code words with the same phase discharge corresponding time. In addition, between in-phase and anti-phase discharge codewords are all 0 codewords, because this channel corresponds to discharge t 1 Time code word, and orthogonal to it, discharge time t 2 The corresponding codeword, the second channel, can be found by superimposing the two channel information in the time domain, which is the forward discharge t 1 Time, forward discharge t 2 Time, reverse discharge t 1 Time, reverse discharge t 2 And (5) alternately operating state modes in time. So, demodulation can obtain two-way code word information, i.e. one channel is in-phase and reverse-phase discharge t 1 Time-corresponding codeword D t1 Another channel is in-phase and anti-phase discharge t 2 Time-corresponding codeword D t2 Thus, the subsequent data processing of two paths of code words is convenient, and the influence of temperature on frequency is eliminated.
FIG. 7 shows the simulation result of the output frequency variation along with the temperature, the abscissa shows the temperature variation from-40 ℃ to 105 ℃, and the ordinate shows the output frequency variation, so that after the temperature linearity compensation loop and the oscillation frequency locking loop are passed, the output frequency is stabilized at about 20M, and the temperature stability of the output frequency is calculated to achieve +/-9.493 ppm/DEG C.
The purpose of the temperature linearity compensation loop is to realize that the frequency obtained by dividing the frequency of the DCO through the loop is in linear positive correlation with the temperature, so that the temperature-related variable is eliminated in the frequency locking loop. As shown in fig. 8, the digital processing module I specifically includes a discharge count control module, a modulation control module, a demodulation module, an accumulation module, a moving average processing module, a frequency division module, a diode working state controller module, and a diode charge-discharge control module, where the discharge count control module mainly controls a state machine of the ADC to jump to a next state after completing sampling of discharge for a certain time during sampling; the modulation control module is a switch control logic for controlling the forward or reverse discharge of the diode; the demodulation module judges whether to perform the operation of taking the complementary code according to the working mode of forward or reverse discharge of the output code word of the ADC; the accumulation module discharges the same phase or opposite phase t 1 Time codeword and in-phase or anti-phase discharge t 2 The code words of the time are accumulated for N times respectively; the length of the moving average module is L, namely, data accumulated for N times each time is stored in a register and then divided by L to perform an averaging operation, the length exceeding four is in accordance with the principle of 'first in first out', namely, the data which enters first is removed, new data is stored, and then the L number averaging operation is performed; the frequency dividing module averages the slidingThe obtained data of the two channels are subtracted, and the difference value is used as the frequency division number of the clock frequency; the diode working state control machine module is used for realizing the working state of the diode bias capacitor in each state by using a state machine in the sampling stage of the ADC; the diode charge-discharge control module is a switch for controlling charge-discharge according to the state machine of the diode to make it complete forward discharge t 1 Time, reverse phase discharge t 1 Time, forward discharge t 2 Time and the reverse discharge T2 time. The temperature linearity compensation loop is D obtained by differencing two groups of digital code words of ADC div As a frequency division number of DCO and then is given to the diode discharge t 1 And t 2 Time, and then the ADC quantifies discharge t respectively 1 ,t 2 Obtaining D from the voltage across the capacitive array after time t1 And D t2 . Thus, the DCO, the frequency divider, the capacitor-based diode discharge circuit, the multiplexer, the ADC, the demultiplexer, the digital processing module I and the subtracter form a temperature linearity compensation loop, and as can be seen from the formula (10), the discharge t obtained through ADC quantization is realized through the loop 1 The code word corresponding to the time voltage is in linear positive correlation with the temperature, and discharge t is similarly carried out 2 The codeword corresponding to the time voltage is also linearly and positively correlated with temperature.
The purpose of the oscillation frequency locked loop is to eliminate the temperature dependent variable so that the temperature dependent variable factor is not included in the final frequency expression, thereby achieving the goal that the output frequency does not vary with temperature. As shown in fig. 9, the digital processing module II specifically includes a period calculating module, a subtracter and a digital integrator, the period calculating module calculates two input codewords to eliminate temperature variation, so as to obtain a period value, and then the period value is different from a reference time, and the digital integrator is used for accumulating the error as a frequency control word of DCO; the DCO, the time-to-digital converter based on the reverse saturation current reference and the digital processing module II thus form an oscillation frequency locked loop, by which it can be seen from equation (11) that the temperature dependent variables are eliminated, so that the frequency variation is independent of the temperature.
The embodiments described above are described in order to facilitate the understanding and application of the present invention to those skilled in the art, and it will be apparent to those skilled in the art that various modifications may be made to the embodiments described above and that the general principles described herein may be applied to other embodiments without the need for inventive faculty. Therefore, the present invention is not limited to the above-described embodiments, and those skilled in the art, based on the present disclosure, should make improvements and modifications within the scope of the present invention.
Claims (8)
1. An on-chip clock frequency reference circuit with low calibration cost and high frequency stability, comprising:
the digital control oscillator generates a clock signal with specific frequency according to the frequency control word provided by the digital processing module;
the time-to-digital converter based on reverse saturation current reference firstly divides the frequency of the clock signal to obtain two discharge times t 1 And t 2 Further to discharge time t 1 And t 2 Quantization is performed to obtain two different sets of codewords, one set of which is DOUT (t 1 ) With temperature and discharge time t 1 In relation, the other set of code words DOUT (Δt) is only temperature dependent;
a digital processing module for processing two groups of code words DOUT (t 1 ) And DOUT (delta t) is processed to eliminate the temperature-related variable, so that the output frequency control word is used for controlling the output signal frequency of the numerical control oscillator, thereby forming a closed loop and realizing the purpose of automatic frequency calibration.
2. The on-chip clock frequency reference circuit of claim 1, wherein: the frequency of the output clock signal of the digital control oscillator is controlled by a frequency control word, and the larger the frequency control word is, the higher the frequency of the output signal is; conversely, the smaller the frequency control word, the lower the output signal frequency.
3. The on-chip clock frequency reference circuit of claim 1, wherein: the time-to-digital converter includes:
a first frequency divider according to the frequency division number D div Dividing the clock signal to obtain a basic discharge period t div ；
A second frequency divider based on the frequency division number N 1 For basic discharge period t div Frequency division is carried out to obtain discharge time t 1 ；
A third frequency divider based on the frequency division number N 2 For basic discharge period t div Frequency division is carried out to obtain discharge time t 2 ；
Analog-to-digital conversion module based on diode discharge according to reference voltage V ref Fixed temperature T 0 Reverse saturation current I s (T 0 ) For discharge time t 1 And t 2 Quantization is carried out to obtain code word D t1 And D t2 ；
Digital processing module I, which uses multi-channel multiplexing technique to code word D t1 And D t2 Modulation and demodulation processing is performed to obtain codeword DOUT (t 1 ) And DOUT (t) 2 )，DOUT(t 2 ) With temperature and discharge time t 2 Correlation;
a subtracter for dividing DOUT (t 1 ) Subtract DOUT (t) 2 ) Resulting in codeword DOUT (Δt).
4. An on-chip clock frequency reference circuit as recited in claim 3, wherein: the frequency division number D div To gain-adjust codeword DOUT (delta t), the frequency division number N 1 And N 2 Are all given and N 2 Greater than N 1 。
5. An on-chip clock frequency reference circuit as recited in claim 3, wherein: the analog-to-digital conversion module includes:
diode discharge circuit I based on capacitance for t-charging internal pre-charged capacitance 1 Long discharge, discharge current and reverse saturation current I s (T 0 ) Correlating to obtain the discharge voltage V of the capacitor d1 The discharge ofVoltage V d1 Temperature and discharge time t 1 Correlation;
diode discharge circuit II based on capacitance for t-charging internal pre-charged capacitance 2 Long discharge, discharge current and reverse saturation current I s (T 0 ) Correlating to obtain the discharge voltage V of the capacitor d2 The discharge voltage V d2 Temperature and discharge time t 2 Correlation;
multiplexer for multiplexing discharge voltage V d1 And V d2 Sequentially outputting the signals to an analog-to-digital converter on one channel;
analog-to-digital converter for converting discharge voltage V d1 And V d2 Conversion to the corresponding codeword D t1 And D t2 ；
Demultiplexer for dividing code word D t1 And D t2 Separated from one channel and output as two codewords.
6. An on-chip clock frequency reference circuit as recited in claim 3, wherein: the digital processing module I comprises an accumulation module and a moving average processing module, wherein the accumulation module is used for integrating the code word D t1 And D t2 Each of which is accumulated for N times; the length of the moving average processing module is L, which is used for storing the data accumulated for N times in a register and then carrying out the averaging operation of dividing by L, the length exceeding 4 follows the principle of 'first in first out', namely, the first entered data is removed, new data is stored, then carrying out the averaging operation of dividing by L, and N and L are given values.
7. The on-chip clock frequency reference circuit of claim 1, wherein: the digital processing module comprises a period calculation module, a subtracter and a digital integrator, wherein the period calculation module is used for calculating the period of two groups of code words DOUT (t 1 ) And DOUT (Δt) to eliminate the temperature variation, thereby obtaining a value t of the period out The subtracter divides the value t out Subtracting the reference time t ref Obtaining time error and digital integralThe accumulator is used to accumulate this error as a frequency control word for the numerically controlled oscillator.
8. The on-chip clock frequency reference circuit of claim 1, wherein: the numerical control oscillator comprises a current mirror, an RC circuit, a comparator, a delay chain, a buffer and a D trigger, wherein:
the current mirror is used for carrying out mirror image replication of a certain multiple on the current input by the band gap reference to obtain two paths of currents with different magnitudes;
the RC circuit utilizes the two paths of currents to flow through the resistor and the capacitor respectively, so that reference voltage is generated on the resistor, and capacitor voltage is generated after the capacitor is charged;
the comparator is used for comparing the capacitance voltage with the reference voltage, and an output signal of the comparator sequentially passes through the delay chain and the buffer and is input to the clock end of the D trigger;
the delay chain changes the transmission delay of the output signal of the comparator by using the adjustment code word in a coarse adjustment and fine adjustment mode, so as to control the output frequency of the numerical control oscillator;
the buffer is used for enhancing the driving capability of the output signal of the comparator and shaping the output signal of the comparator, and simultaneously, the signal is used for controlling the charge and discharge of the capacitor in the RC circuit;
the D trigger is used for carrying out frequency division on the output signal of the comparator to obtain a clock signal with the duty ratio of 50% as the output of the numerical control oscillator.
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