CN116936534A

CN116936534A - Semiconductor device and method of forming the same

Info

Publication number: CN116936534A
Application number: CN202310797613.1A
Authority: CN
Inventors: 李旭峯; 曾于平; 黄立贤; 庄曜群; 卢胤龙
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-06-30
Filing date: 2023-06-30
Publication date: 2023-10-24

Abstract

A method of forming a semiconductor device includes depositing a first dielectric layer on a first substrate of a first device die, etching the first dielectric layer to form a trench, depositing a metal material in the trench and on a top surface of the first dielectric layer, and performing a Chemical Mechanical Polishing (CMP) process to remove a portion of the metal material from the top surface of the first dielectric layer to form a first metal pad. After execution of the CMP process, the method selectively etches the first metal pad to form a recess at an edge portion of the first metal pad, deposits a second dielectric layer on a second substrate of the second device die, forms the second metal pad in the second dielectric layer, and bonds the second device die to the first device die. The second dielectric layer is bonded to the first dielectric layer, and the second metal pad is bonded to the first metal pad. The embodiment of the invention also provides a semiconductor device.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present invention relate to semiconductor devices and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. Such scaling also increases the complexity of processing and manufacturing ICs,

For example, packages for integrated circuits are becoming more complex, with more device dies packaged in the same package to achieve more functionality. For example, integrated system on chip (SoIC) has been developed to include multiple device dies, such as a processor and a memory cube, in the same package. The SoIC may include device dies formed using different techniques and have different functions bonded to the same device die, thus forming a system. This may save manufacturing costs and optimize device performance. To bond the device die together, the two metal pads are pressed against each other at an elevated temperature, and the interdiffusion of the metal pads bonds the metal pads. Coefficient of Thermal Expansion (CTE) mismatch between the metal pads and the surrounding dielectric layer can weaken the bond strength. Therefore, further development of the bonding structure is required to enhance the circuit performance and reliability to solve these problems.

Disclosure of Invention

Some embodiments of the present invention provide a method of forming a semiconductor device, the method comprising: depositing a first dielectric layer on a first substrate of a first device die; etching the first dielectric layer to form a trench; depositing a metal material in the trench and on a top surface of the first dielectric layer; performing a Chemical Mechanical Polishing (CMP) process to remove a portion of the metal material from the top surface of the first dielectric layer, wherein a remaining portion of the metal material in the trench forms a first metal pad; selectively etching the first metal pad to form a groove at an edge portion of the first metal pad after the performing of the chemical mechanical polishing process; depositing a second dielectric layer on a second substrate of a second device die; forming a second metal pad in the second dielectric layer; and bonding the second device die to the first device die, wherein the second dielectric layer is bonded to the first dielectric layer and the second metal pad is bonded to the first metal pad.

Further embodiments of the present invention provide a method of forming a semiconductor device, the method comprising: forming a first device structure, comprising: depositing a first dielectric layer; forming a first metal pad in the first dielectric layer; and selectively etching an edge portion of the first metal pad to form a first groove; forming a second device structure comprising: depositing a second dielectric layer; forming a second metal pad in the second dielectric layer; and selectively etching an edge portion of the second metal pad to form a second groove; and bonding the second device structure to the first device structure, wherein the second metal pad is bonded to the first metal pad and the second dielectric layer is bonded to the first dielectric layer.

Still further embodiments of the present invention provide a semiconductor device including: a first device structure, the first device structure comprising: a first dielectric layer; a first metal pad in the first dielectric layer; and a first void located at an edge portion of the first metal pad; and a second device structure, the second device structure comprising: a second dielectric layer in contact with the first dielectric layer; a second metal pad in the second dielectric layer and in contact with the first metal pad; and a second void located at an edge portion of the second metal pad.

Drawings

The invention is best understood from the following detailed description when read in connection with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a flow chart of a method of forming a package according to some embodiments of the invention.

Fig. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 and 23 illustrate cross-sectional views of a package during a manufacturing process according to the method of fig. 1 in accordance with aspects of the present invention.

Fig. 12A, 12B, 12C, and 12D illustrate cross-sectional views of bond pads according to some embodiments of the present invention.

24A, 24B, 24C, 24D, 24E, 24F, 24G, 24H and 24I illustrate cross-sectional views of metal-to-metal joints according to some embodiments of the invention.

Fig. 25A and 25B illustrate cross-sectional views of a TSV landed on a bond pad with a recess according to some embodiments of the invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, of different components for use with the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact.

Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, in the present invention, forming an element on another element, connecting an element to another element, and/or coupling an element to another element may include embodiments in which elements are formed in direct contact, and may also include embodiments in which additional elements may be interposed between elements so that elements may not be in direct contact. Further, for example, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above …," "below …," "below …," "upper," "lower," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.), are used to simplify the relationship of one component to another of the present invention. Spatially relative terms are intended to encompass different orientations of the device in which the component is included. Further, when values or ranges of values are described using "about," "approximately," etc., the term is intended to include values within +/-10% of the described values unless otherwise indicated. For example, the term "about 5nm" encompasses a size range from 4.5nm to 5.5 nm.

Various embodiments of integrated system on chip (SoIC) packages and methods of forming the same are provided. Specifically, a bonded structure having a stress buffer region (or stress relief region) is provided. Some variations of some embodiments are discussed below. Like reference numerals are used to denote like elements through the various views and illustrated embodiments. According to some embodiments, an intermediate stage of forming a SoIC package is shown. It should be understood that although SoIC packages are used as examples to explain the concept of embodiments of the present invention, embodiments of the present invention can be readily applied to other bonding methods and structures in which metal pads and vias are bonded to one another.

Shown in fig. 1 is a method 10 including semiconductor fabrication to form a semiconductor device. The method 10 is merely an example and is not intended to limit the present invention beyond what is explicitly recited in the scope. Additional operations may be provided before, during, and after the method 10, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of the method. The method 10 is described below in conjunction with fig. 2-25B, with fig. 2-25B showing cross-sectional views of a semiconductor device according to various stages of the method 10 in accordance with some embodiments of the invention.

At operation 12 (fig. 1), the method 10 provides (or is provided with) a single substrate 102, such as shown in fig. 2. In fig. 2 through 13, a plurality of device structures 100 are formed on a single substrate 102, and then the plurality of device structures 100 are singulated to form individual device structures 100 (refer to fig. 13). For example, the device structure 100 may be an Application Specific Integrated Circuit (ASIC) chip, an analog chip, a sensor chip, a wireless radio frequency chip, a voltage regulator chip, or a memory chip. The region labeled "100" in fig. 2-11 represents the region where the device structure 100 shown in fig. 13 is formed, and the region labeled "104" represents the scribe line region 104 between adjacent device structures 100.

The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor wafer, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. Typically, SOI substrates include a layer of semiconductor material formed on an insulator layer. For example, the insulator layer may be a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulator layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multi-layer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, and/or GaInAsP; or a combination thereof.

In some embodiments, the substrate 102 and components formed thereon are used to form a device die, an integrated circuit die, and the like. In the depicted embodiment, integrated circuit device region 106 is formed on a top surface of substrate 102. Exemplary integrated circuit devices may include Complementary Metal Oxide Semiconductor (CMOS) transistors, fin field effect transistors (finfets), resistors, capacitors, diodes, and the like, or combinations thereof. Details of the integrated circuit devices are not shown here. In other embodiments, the substrate 102 is used to form an interposer structure. In such an embodiment, active devices such as transistors are not formed on the substrate 102. Passive components such as capacitors, resistors, inductors, and the like may be formed in the substrate 102. In some embodiments where the substrate 102 is part of an interposer structure, the substrate 102 may also be a dielectric substrate. In some embodiments, through holes (not shown) may be formed to extend through the substrate 102 in order to interconnect components on opposite sides of the substrate 102.

At operation 14 (fig. 1), the method 10 forms an inter-layer dielectric (ILD) layer 108 over the substrate 102 and forms an interconnect structure 112 over the ILD 108, such as shown in fig. 3. ILD layer 108 fills the spaces between the gate stacks of transistors (not shown) in integrated circuit device region 106. In some embodiments, ILD layer 108 is formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), fluorine doped silicate glass (FSG), tetraethyl orthosilicate (TEOS), and the like. ILD layer 108 may be formed using spin coating, flowable Chemical Vapor Deposition (FCVD), chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), low Pressure Chemical Vapor Deposition (LPCVD), and the like.

Contact plugs 110 are formed in ILD layer 108 and contact plugs 110 are used to electrically connect the integrated circuit device to the metal lines and vias above. In some embodiments, the contact plug 110 is formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multilayers thereof. Forming the contact plug 110 may include forming a contact opening in the ILD layer 108, filling a conductive material into the contact opening, and performing a planarization, such as a Chemical Mechanical Polishing (CMP) process, to level a top surface of the contact plug 110 with a top surface of the ILD layer 108.

The interconnect structure 112 provides wiring and electrical connections between devices formed in the substrate 102, and may be, for example, a redistribution structure or the like. Interconnect structure 112 may include a plurality of insulating layers 114, and the plurality of insulating layers 114 may be inter-metal dielectric (IMD) layers. Each insulating layer 114 includes conductive features such as metal lines 116 and vias 118 formed therein in a metallization layer. In other embodiments, for example, the metal lines may be redistribution layers. The conductive features may be electrically connected to active and/or passive devices of the substrate 102 through the contact plugs 110.

In fig. 3, the conductive features of interconnect structure 112 formed in topmost insulating layer 114 are individually labeled as metal pads 120. The metal pads 120 may serve as a means for connecting subsequently formed conductive features (e.g., conductive pads, bond Pad Vias (BPVs), etc.) to the interconnect structure 112. In some embodiments, the conductive features of the topmost insulating layer 114 may also include metal lines or vias, which are not separately shown in fig. 3.

In some embodiments, insulating layer 114 may be made of a low-k dielectric material having a k value of less than about 3.0. The insulating layer 114 may be made of an Extremely Low K (ELK) dielectric material having a k value less than 2.5. In some embodiments, insulating layer 114 may be made of an oxygen-containing and/or carbon-containing low-k dielectric material, hydrogen Silsesquioxane (HSQ), methyl Silsesquioxane (MSQ), or the like, or a combination thereof. In some embodiments, some or all of the insulating layer 114 is formed of a non-low-k dielectric material, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), or the like. In some embodiments, an etch stop layer (not shown) is formed between insulating layers 114, which may be formed of silicon carbide, silicon nitride, or the like. In some embodiments, the insulating layer 114 is made of a porous material, such as SiOCN, siCN, siOC, siOCH, etc., and the insulating layer 114 may be formed by a spin-on or deposition process, such as Plasma Enhanced Chemical Vapor Deposition (PECVD), CVD, PVD, etc. In some embodiments, the interconnect structure 112 may include one or more other types of layers, such as a diffusion barrier layer (not shown).

In some embodiments, the interconnect structure 112 may be formed using a single damascene process and/or a dual damascene process, a via-first process, or a metal-first process. In an embodiment, insulating layer 114 is formed and openings (not shown) are formed therein using acceptable photolithography and etching techniques. A diffusion barrier layer (not shown) may be formed in the opening and may include a material such as TaN, ta, tiN, ti, coW, and may be formed in the opening using a deposition process such as CVD, atomic Layer Deposition (ALD), or the like. A conductive material made of copper, aluminum, nickel, tungsten, cobalt, silver, combinations thereof, or the like may be formed in the opening, and may be formed over the diffusion barrier in the opening using an electrochemical plating process, CVD, ALD, PVD, or the like, or combinations thereof. For example, after forming the conductive material, a planarization process such as CMP may be used to remove excess conductive material, thereby leaving conductive features in the openings of the respective insulating layers 114. The process may then be repeated to form additional insulating layers 114 and conductive features therein. In some embodiments, the topmost insulating layer 114 and the metal pads 120 formed therein may be formed to have a thickness greater than the thickness of the other insulating layers 114 of the interconnect structure 112. In some embodiments, the one or more topmost conductive components are dummy metal lines or dummy metal pads 120 that are electrically isolated from the substrate 102.

At operation 16 (fig. 1), the method 10 forms a cap layer 122 over the interconnect structure 112, with one or more openings formed in the cap layer 122, such as shown in fig. 4. The cover layer 122 may include one or more layers of one or more materials. For example, the capping layer 122 may include one or more layers of silicon nitride, silicon oxide, silicon oxynitride, or the like, or a combination thereof. The cap layer 122 may be formed using a suitable process, such as CVD, PECVD, PVD, ALD, or the like, or a combination thereof. In some embodiments, the capping layer 122 may be formed to have a thickness greater than that of the topmost insulating layer 114. Suitable photolithography and etching techniques may be used to form the openings in the cap layer 122. A photoresist may be formed over the capping layer 122, and the photoresist may be patterned, and then the patterned photoresist may be used as an etch mask. The capping layer 122 may be etched using a suitable wet and/or dry etching process. An opening is formed to expose a portion of the metal pad 120 for electrical connection.

At operation 18 (fig. 1), the method 10 forms a conductive pad 124 over the cap layer 122, such as shown in fig. 5. One or more conductive pads 124 may be formed to extend through openings in the cap layer 122 to make electrical connection with one or more metal pads 120 of the interconnect structure 112. In some embodiments, the conductive pads 124 may be formed by first depositing a blanket layer of conductive material, such as aluminum. For example, CVD, PVD, or the like may be used to deposit an aluminum layer over the cap layer 122, openings, and metal pads 120. A photoresist layer (not separately shown) may then be formed over the aluminum layer, and the aluminum layer may be etched to form the conductive pads 124. In other embodiments, the conductive pad 124 is formed by first forming a seed layer over the cap layer 122 and the opening. In some embodiments, the seed layer is a metal layer comprising one or more layers, which may be formed of different materials. For example, a seed layer may be formed using PVD or the like. A photoresist is formed over the seed layer and patterned, and a conductive material is formed in the openings of the photoresist and over the exposed portions of the seed layer. In some embodiments, the conductive material may be formed using a plating process, such as using an electroplating or electroless plating process, or the like. The conductive material may include one or more materials such as copper, titanium, tungsten, gold, cobalt, or the like, or combinations thereof. The photoresist and portions of the seed layer on which the conductive material is not formed are then removed using, for example, a suitable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, an acceptable etching process (such as a wet etching process or a dry etching process) may be used to remove the remaining exposed portions of the seed layer. The conductive material and the remainder of the seed layer form conductive pads 124. In other embodiments, other techniques may be used to form conductive pads 124, and all such techniques are considered to be within the scope of the present disclosure. In some embodiments, the conductive material of the conductive pad 124 may be different than the conductive material of the metal pad 120. For example, the conductive pad 124 may be aluminum and the metal pad 120 may be copper, although other conductive materials may be used.

In some embodiments, conductive pads 124 electrically connected to interconnect structure 112 may be used as test pads before additional processing steps are performed. For example, the conductive pads 124 may be probed as part of a wafer acceptance test, a circuit test, a Known Good Die (KGD) test, or the like. Probing may be performed to verify the function of active or passive devices of the substrate 102 or corresponding electrical connections within the substrate 102 or interconnect structure 112. Probing may be performed by contacting probes 126 to conductive pads 124. Accordingly, the conductive pads 124 may also be referred to as probe pads 124. The probes 126 may be part of a probe card that includes a plurality of probes 126 that may be connected to test equipment, for example.

At operation 20 (fig. 1), method 10 deposits dielectric layers 130, 132, and 134 over capping layer 122, such as shown in fig. 6. Dielectric layers 130 and 134 may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, or the like. Dielectric layer 132 is formed of a dielectric material that is different from the dielectric materials of dielectric layers 130 and 134. For example, the dielectric layer 132 may be formed of silicon nitride, silicon carbide, or the like. Dielectric layer 132 is also referred to as Etch Stop Layer (ESL) 132. Each of the dielectric layers 130, 132, and 134 may be formed using a deposition process such as CVD, PECVD, PVD, ALD. The dielectric layer 130 may be formed to have a thickness greater than that of the conductive pad 124 such that the material of the dielectric layer 130 laterally surrounds the conductive pad 124 and such that the dielectric layer 130 may be planarized without exposing the conductive pad 124.

At operation 22 (fig. 1), the method 10 forms a trench 136 and a via opening 138, such as shown in fig. 7. To form the trenches 136 and via openings 138, a photoresist (not shown) and/or a hard mask (not shown) may be formed over the dielectric layer 134 and patterned to help form the trenches 136 and via openings 38. According to some embodiments of the present invention, an anisotropic etch is performed to form trenches 136 and the etch stops on etch stop layer 132. Another anisotropic etch is then performed by etching the exposed lower portions of the etch stop layer 132 and the dielectric layer 130 to form via openings 138. In some embodiments, the etch stop layer 132 is not formed and the trench 136 and the via opening 138 are formed in a single dielectric layer. Etching may be performed using a timed pattern to allow etching (to form trenches 136) to stop at an intermediate level between the top and bottom surfaces of the single dielectric layer. The via opening 138 and the trench 136 expose the metal pad 120 to allow subsequently formed Bond Pad Vias (BPVs) and bond pads to make electrical connection with the interconnect structure 112 through the metal pad 120. Notably, to increase uniformity of bond pad distribution, dummy bond pads may be formed in areas where bond pads are scarce to facilitate subsequent bonding processes to avoid warpage. For example, because the probe pad 124 may be separated from the adjacent metal pad 120 by a distance of between about 10 μm to about 50 μm and the probe pad 124 is not further connected to the bond pad, the area surrounding the probe pad 124 may represent a bond pad rarefaction area. Dummy bond pads may be formed in such areas to increase bond pad distribution density. In the illustrated embodiment, some trenches 136 are formed over probe pads 124 without receiving an additional etching process to form via openings 138 therein to expose the probe pads. In a subsequent process, dummy bond pads will be formed in these trenches.

At operation 24 (fig. 1), the method 10 fills the trench 136 and the via opening 138 with a conductive material, such as shown in fig. 8. The barrier layer 140 is conformally deposited. The barrier layer 140 may be, for example, a liner, diffusion barrier layer, adhesive layer, or the like. Barrier layer 140 may include one or more layers including titanium, titanium nitride, tantalum nitride, the like, or combinations thereof. A barrier layer 140 may be deposited as a blanket layer over the sidewalls and bottom surfaces of the trenches 136 and via openings 138. For example, the barrier layer 140 may be formed using Atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like. Next, a metallic material 142 is deposited, for example, by electrochemical plating (ECP). The metal material 142 fills the trench 136 and the remainder of the via opening 138. The metal material 142 also includes portions that are located above the top surface of the dielectric layer 134. The metal material 142 may comprise copper or a copper alloy, or another metal material that may be diffused in a subsequent annealing process, such that a metal-to-metal direct bond may be formed. In some embodiments, the metallic material 142 is copper and the probe pad 124 is formed substantially of aluminum.

At operation 26 (fig. 1), the method 10 performs a planarization process, such as a CMP process, to remove the metal material 142 and the excess portion of the barrier layer 140 until the dielectric layer 134 is exposed, such as shown in fig. 9. The barrier layer 140 and the remainder of the metallic material 142 define Bond Pad Vias (BPVs) 146, bond pads 148a, 148b, 148c (collectively bond pads 148). Fig. 9 shows a metal pad for bonding. It should be understood that the metal lines may also be formed simultaneously as metal pads. Bond pads 148 include bond pads 148a and dummy bond pads 148b for bonding to the device die, and bond pads 148c (or metal pads 148 c) for landing through vias. Bond pads 148a and 148c are electrically coupled to interconnect structure 112 through BPV 146. Dummy pad 148b is electrically isolated from interconnect structure 112.

At operation 28 (fig. 1), the method 10 performs a singulation process along the scribe area 104 to separate adjacent device structures 100, such as shown in fig. 10. The backside of the substrate 102 is attached to the frame 150 by an adhesive layer 152 prior to the singulation process. In some embodiments, the adhesive layer 152 includes a Die Attach Film (DAF) such as epoxy, phenolic, acrylic rubber, silica filler, or combinations thereof, and the adhesive layer 152 is applied using lamination techniques. The frame 150 comprises, for example, a silicon-based material (such as glass or silicon oxide) or other material (such as aluminum oxide, metal, ceramic, polymer, any combination of these materials, etc.). However, any other suitable alternative materials and forming methods may alternatively be utilized. The singulation process may include a plasma cutting process, a laser cutting process, a sawing process, or a combination thereof. In the depicted embodiment, the singulation process is a plasma dicing process, and a patterned resist layer 154 is formed on the front side of the device structure 100 (either before or after attaching the frame 150), with the openings exposing the scribe areas 104. The process gas for plasma cutting may include C ₄ F ₆ Or a fluorine-based gas at a temperature below 200 ℃ at an RF power of greater than 50W and at a pressure below 3 torr. The process gas anisotropically etches through scribe area 104. The patterned resist layer 154 is then removed using, for example, a suitable ashing or stripping process, such as using an oxygen plasma or the like. In some embodiments, singulated device structures 100 that are probed and found to be Known Good Die (KGD) (described in fig. 5 above) are used in subsequent processing steps to join with another device structure 200 (see fig. 14).

At operation 30 (fig. 1), the method 10 performs a surface treatment process 158 to form a recess around the bond pad 148 as a stress buffer (or stress relief region), such as shown in fig. 11 and 12A-12D, in some embodiments, the surface treatment process 158 comprises a series of wet cleaning processes. In a further embodiment, the surface treatment process 158 includes a first wet cleaning process that removes the remaining residue of the patterned resist layer 154 and metal oxide formed on the bond pad 148 during a previous operation and a second wet cleaning process that forms a recess around the bond pad 148.

The first wet cleaning process may be performed by using a cleaning solution. Exemplary cleaning solutions include ozone deionized water (O) ₃ DI) cleaning solution or SPM cleaning solution. The SPM cleaning wash includes a mixture of sulfuric acid, hydrogen peroxide solution, and pure water. Metal oxide and other remaining residues are removed from the front side of the device structure 100 in a first wet cleaning process.

The second wet clean process may be a selective wet etch process using a suitable etching solution. The second wet cleaning process uses a different etching solution than the first wet cleaning process. The etching solution may be an alkaline solution or an acidic solution. Exemplary etching solutions include mixtures of methane, sulfinylbis (methane) (sulfinylbis (methane)), hydroxylamine, and water. The etching solution has a selectivity of the bonding metal relative to the bonding dielectric layer of about 30:1 to about 100:1 such that the dielectric material of the dielectric layer 134 surrounding the bonding metal experiences negligible etching loss. The etching solution may be applied for a duration of about 10 seconds to about 150 seconds.

The region 159 including the bond pad 148 and the BPV 146 in fig. 11 is depicted in fig. 12A and 12B-12D, respectively, to illustrate cross-sectional views of the region 159 before and after receiving the surface treatment process 158, respectively. Referring to fig. 12A, each of the bond pad 148 and BPV 146 includes a portion of the barrier layer 140 and the metallic material 142. The metal material 142 includes an edge portion and an intermediate portion between the edge portions. Barrier layer 140 is interposed between metallic material 142 and the dielectric materials of dielectric layers 130, 132, and 134. After the planarization process at operation 26 with reference to fig. 9, the top surfaces of dielectric layer 134, barrier layer 140, and metallic material 142 are substantially coplanar (flush). In the embodiment depicted in fig. 12A, there is no recess (gap) in the bond pad 148 and the dielectric material surrounding it. The metallic material in bond pad 148 and the dielectric material surrounding it have different Coefficients of Thermal Expansion (CTE). For example, bond pad 148 may comprise copper and dielectric layer 134 may comprise an organic dielectric material such as a polymer. Copper has a CTE of about 16.7ppm/C, while the polymer dielectric layer may have a CTE of about 22-28 ppm/C or higher. CTE mismatch between the material layers in the areas with bond pads tends to cause warpage after bonding.

Referring to fig. 12B, a selective wet etching process during the surface treatment process 158 recesses an edge portion of the metal material 142 and a top portion of the barrier layer 140, thereby forming a groove 160. The groove 160 is a portion of a groove ring that surrounds the bond pad 148 from a top view. That is, the groove 160 may form a loop near the edge of the bond pad 148, and some sidewalls of the metal material 142 and some sidewalls of the barrier layer 140 are exposed in the groove 160. The grooves 160 have a depth D1 in the range of about 50nm to about 300nm and a width D2 in the range of about 50nm to about 300 nm. In the embodiment depicted in fig. 12B, barrier layer 140 experiences more etching loss than metallic material 142, and depth D1 is measured at the pit between barrier layer 140 and the exposed sidewall of dielectric layer 134. The selective wet etch process during the surface treatment process 158 may also cause the top surface of the intermediate portion of the metallic material 142 to be recessed. Metallic material 142Height difference Δh between the highest point and the lowest point of the top surface of the intermediate portion of (a) ₁ The (recess depth) may be in the range between about 1nm to about 50 nm.

Fig. 12C shows an alternative embodiment. The edge portion of the metal material 142 may be recessed more than the barrier layer 140 such that the protrusion of the barrier layer 140 is formed in the bottom of the groove 160, and the depth D1 is measured at the pit between the metal material 142 and the sidewall of the barrier layer 140. Fig. 12D shows another alternative embodiment. The top surface of barrier layer 140 remains substantially coplanar (flush) with the top surface of dielectric layer 134 and the sidewalls of dielectric layer 134 are not exposed in recess 160. The depth D1 is measured at the pit between the metal material 142 and the sidewall of the barrier layer 140.

In various embodiments, grooves 160 allow some room for expansion of the metallic material during thermal cycling (such as pre-annealing and annealing). Thus reducing the stress experienced by the joined structure. In the illustrated embodiment, a selective etching process in forming the grooves 160 is performed after the singulation process at operation 28. In an alternative embodiment, a selective etching process in forming the grooves 160 may be performed prior to the singulation process at operation 28, such as after the planarization process at operation 26 and prior to the deposition of the patterned resist layer 154 and attachment of the frame 150. A separate wet clean process may be performed after operation 28 to remove remaining particles of patterned resist layer 154 and metal oxide from bond pads 148.

At operation 32 (fig. 1), the method 10 attaches the device structure 100 to a carrier structure 170, such as shown in fig. 13, through an adhesive layer 172 using, for example, a pick and place process. The carrier structure 170 may be a silicon substrate (e.g., a silicon wafer), a glass substrate, an organic substrate (e.g., a panel), or the like. Adhesive layer 172 may be substantially similar to adhesive layer 152 discussed above. In some embodiments, a dielectric region 174 (also referred to as a "gap-fill dielectric" region) is formed around the device structure 100. Dielectric region 174 may be made of one or more layers of silicon oxide, PSG, BSG, BPSG, FSG, silicon nitride, or the like, or a combination thereof. A deposition process such as CVD, PECVD, PVD, or the like, or a combination thereof, may be used to form the dielectric material of dielectric region 174.

At operation 34 (fig. 1), the method 10 forms a device structure 200 attached to a frame 250 by an adhesive layer 252 for singulation by scribe areas 204 exposed in openings of a patterned resist layer 254, such as shown in fig. 14. The device structure 200 and its formation may be substantially the same or similar to the device structure 100 described above. The device structure 200 will be bonded to the device structure 100 in a subsequent bonding process. For example, the device structure 200 may be an Application Specific Integrated Circuit (ASIC) chip, an analog chip, a sensor chip, a wireless radio frequency chip, a voltage regulator chip, or a memory chip. Device structure 200 and device structure 100 may be the same type of die or different types of die. In some embodiments, the device structure 200 is an active component or a passive component. In the illustrated embodiment, device structure 200 is smaller than the total area of device structure 100. The device structure 100 may also be referred to as an underlying die (base die). In some other embodiments, the size of device structure 200 is larger than the size of device structure 100, and device structure 200 is an underlying die.

Similar to device structure 100, device structure 200 includes a substrate 202, an integrated circuit device region 206, an interconnect structure 212 including metal lines 216 and vias 218 embedded in an insulating layer, and metal pads 220. The material composition and formation of substrate 202, integrated circuit device region 206, interconnect structure 212, metal pad 220, adhesion layer 252, frame 250, and patterned resist layer 254 may be substantially similar to that of substrate 102, integrated circuit device region 106, interconnect structure 212, metal pad 120, adhesion layer 152, frame 150, and patterned resist layer 154, respectively, discussed above, and are not repeated here for simplicity. After singulation of the device structure 200, the patterned resist layer 254 is then removed using, for example, a suitable ashing or stripping process, such as using an oxygen plasma or the like.

In the depicted embodiment, a through-hole 228 is formed in the substrate 202. In some embodiments, when the substrate 202 is a silicon-containing substrate, the through-holes 228 may also be considered through-silicon-vias. In some embodiments, the through-holes 228 extend into the substrate 202 and will be exposed from the backside of the substrate 202 after the backside grinding process. In other words, the through-hole 228 may extend between two opposing surfaces of the substrate 202. The through via 228 may also be referred to as a Through Substrate Via (TSV). In some embodiments, TSV 228 comprises copper, copper alloy, aluminum alloy, or a combination thereof. In some embodiments, TSV 228 further includes a diffusion barrier (not shown) located between the conductive via and substrate 202. The diffusion barrier layer may comprise Ta, taN, ti, tiN, coW or a combination thereof.

At operation 36 (fig. 1), the method 10 inverts the device structure 200 and attaches the front side of the device structure 200 to a carrier structure 270, such as shown in fig. 15, through an adhesive layer 272 using, for example, a pick and place process. The carrier structure 2700 may be a silicon substrate (e.g., a silicon wafer), a glass substrate, an organic substrate (e.g., a panel), or the like. Adhesive layer 272 may be substantially similar to adhesive layer 152 discussed above. In some embodiments, a dielectric region 274 (also referred to as a "gap-fill dielectric" region) is formed around the device structure 200. The dielectric region 274 may be made of one or more layers of silicon oxide, PSG, BSG, BPSG, FSG, silicon nitride, the like, or a combination thereof. The dielectric material of the dielectric region 274 may be formed using a deposition process such as CVD, PECVD, PVD, or the like, or a combination thereof.

At operation 38 (fig. 1), the method 10 performs a backside grinding process to thin the device structure 200 from the backside, such as shown in fig. 16. The back side grinding may be performed by performing a rough grinding step and a fine grinding step with a grinding wheel. As a result, the substrate 202 may be worn away to a thickness of about 15um to about 30 um. After backside grinding, TSV 228 is exposed.

At operation 40 (fig. 1), method 10 deposits a dielectric layer 234 over device structure 200 and forms bond pads 248 in dielectric layer 234, such as shown in fig. 17. The dielectric layer 234 may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, dielectric layer 234 is formed of silicon oxide, silicon oxynitride, silicon oxycarbide, or the like, and dielectric layer 234 is deposited using a deposition process such as CVD, PECVD, PVD, ALD. A trench (not shown) is then formed, exposing the backside of TSV 228. In some embodiments, an anisotropic etch is performed to form the trench. The trench is filled with a conductive material. The barrier layer 240 is conformally deposited. The barrier layer 240 may be, for example, a liner, diffusion barrier layer, adhesive layer, or the like. The barrier layer 240 may include one or more layers including titanium, titanium nitride, tantalum nitride, and the like, or combinations thereof. A barrier layer 240 may be deposited as a blanket layer over the sidewalls and bottom surface of the trench, and the barrier layer 240 may be in contact with the backside of TSV 228. For example, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like may be used to form the barrier layer 240. Next, a metallic material 242 is deposited, for example, by electrochemical plating (ECP). The metal material 242 fills the remainder of the trench. The metal material 242 may comprise copper or a copper alloy, or another metal material that may be diffused in a subsequent annealing process, such that a metal-to-metal direct bond may be formed. In some embodiments, the metallic material 242 in the device structure 200 and the metallic material 142 in the device structure 100 are the same metallic material, such as copper. A planarization process, such as a CMP process, may be performed to remove the metal material 242 and the excess portion of the barrier layer 240 until the dielectric layer 234 is exposed. The barrier layer 240 and the remaining portion of the metallic material 242 collectively define a bond pad 248. Bond pad 248 includes a bond pad 248a in physical contact with TSV 228 and a dummy bond pad 248b electrically floating in dielectric layer 234. The dummy bond pads 248b in the device structure 200 will bond with the dummy bond pads 148b in the device structure 100 to increase the uniformity of the distribution of the bond structures.

At the end of operation 40, method 10 may perform a surface treatment process on device structure 200. The surface treatment may include a first wet cleaning process similar to the first wet cleaning process in the surface treatment process 158 discussed above that removes residues and metal oxides from the backside of the device structure 200. Alternatively, the surface treatment may also include a second wet cleaning process (or selective etching process) similar to the second wet cleaning process in the surface treatment process 158 in forming a recessed ring around the bond pad 248. In some embodiments, the formation of the recess at the edge portion of the bond pad 248 in the device structure 200 may be skipped. Alternatively, a groove at an edge portion of the bond pad 248 may be formed in the device structure 200, but the formation of a groove at an edge portion of the bond pad 148 is skipped in the device structure 100. That is, according to some embodiments, either device structure 100 and device structure 200 may have grooves surrounding the respective bond pads, or both.

At operation 42 (fig. 1), the method 10 bonds the device structure 200 to the device structure 100, such as shown in fig. 18. The bonded device structures 100 and 200 are collectively referred to as device structure 300. Bonding of device structure 200 to device structure 100 may be achieved by hybrid bonding. Bond pad 248 is bonded to bond pad 148, for example, by a metal-to-metal direct bond. In some embodiments, the metal-to-metal direct bond is a copper-to-copper direct bond. Specifically, bond pads 248a are bonded to respective bond pads 148a, thereby electrically coupling interconnect structures 212 and 112; the dummy bond pads 248b are bonded to the corresponding dummy bond pads 148b, thereby improving the uniformity of the bonded structure. In the embodiment shown in fig. 18, the bond pads 248 have a size that is larger than the size of the corresponding bond pads 148. Alternatively, the bond pads 248 may have a size that is equal to or smaller than the size of the corresponding bond pads 148. Further, dielectric layer 234 is bonded to dielectric layer 134 by a dielectric-to-dielectric bond, which may be a fusion bond, for example, creating a Si-O-Si bond. Dielectric layer 234 is further bonded to the dielectric material in gap-fill dielectric region 174 by a dielectric-to-dielectric bond.

To achieve hybrid bonding, device structure 200 is first pre-bonded to device structure 100 by lightly pressing device structure 200 against device structure 100. After pre-bonding, an anneal is performed to cause interdiffusion of metal in bond pad 148 and corresponding overlying bond pad 248. In some embodiments, the annealing temperature may be in a range between about 250 ℃ to about 550 ℃. In some embodiments, the annealing time may be in a range between about 1.5 hours and about 8.0 hours. By hybrid bonding, the bond pads 248 are bonded to the corresponding bond pads 148 by direct metal bonding caused by metal interdiffusion.

Regions 259 including bond pad 248, bond pad 148, and BPV 146 in fig. 18 are depicted in fig. 24A and 24B-24I, respectively, to illustrate cross-sectional views of regions 259 with grooves 160 after pre-bonding and before and after annealing, respectively. It will be appreciated that for simplicity, grooves 160 having the profile depicted in fig. 12B are shown, but other profiles such as those depicted in fig. 12C and 12D may equally be applicable. Fig. 24A shows region 259 prior to annealing. The groove 160 is part of a groove ring of the bond pad 148. In the embodiment depicted in fig. 24A, bond pad 248 is free of grooves and bond pad 248 has a size that is larger than the size of bond pad 148 such that grooves 160 are covered by metallic material 242. The covered groove 160 may also be referred to as a void 160 or a void ring 160. The concave profile of the intermediate portion of the metal material 142 is also covered with the metal material 242 to form the space 161 therebetween. In the depicted embodiment, barrier layer 140 does not contact barrier layer 240.

In some embodiments, fig. 24B shows region 259 after annealing. The metal material 142 bonds with the metal material 242 due to interdiffusion of the bond pads 148 and 248. The formation of grooves 160 advantageously reduces the stresses generated in the joined structure. For example, the CTE of the metallic materials 142 and 242 is significantly different from the CTE of the dielectric layers 134 and 234, and the grooves 160 allow some room for expansion of the metallic materials during thermal cycling (such as pre-annealing and annealing). Thus reducing the stress experienced by the joined structure. After annealing, the shape and size of the grooves 160 and voids 161 may be different from those before annealing due to diffusion of the metal material. For example, the size of the void 161 may be smaller than the size before annealing, and the size of the groove 160 may be smaller than the size before annealing. After annealing, the grooves 160 may have a depth D1 in the range of about 50nm to about 300nm and a width D2 in the range of about 50nm to about 300 nm. The range of D1 and D2 is not trivial. If the range is below 50nm, the space provided by the grooves 160 may not be sufficient to compensate for the CTE mismatch. If the range is greater than 300nm, material discontinuities at the grooves may instead become non-trivial in introducing additional warpage. Fig. 24C is similar to fig. 24B. One difference is that voids 161 may disappear after annealing. Fig. 24D shows an embodiment in which a groove 260 is also formed in an edge portion of the bonding pad 248. Due to the larger size of bond pad 248, groove 260 may be larger than groove 160. In the embodiment depicted in fig. 24D, grooves 260 and 160 are not merged. The recess 260 is covered by the dielectric layer 134. A concave profile is also present in the central portion of the metallic material 242. The voids may be combined into voids 161 to form larger voids in the central portion of the joined structure.

Fig. 24E illustrates an embodiment in which bond pads 148 and 248 have similar dimensions such that grooves 160 and 260 are bonded. Since groove 160 may be part of a first groove ring and groove 260 may be part of a second groove ring, the first groove ring and the second groove ring may be combined with each other to form a combined groove ring. The voids of the central portion of the joined structure also merge to form larger voids. Fig. 24F is similar to fig. 24E. One difference is that voids 161 may disappear after annealing.

24G, 24H, and 24I illustrate cross-sectional views of bond pads 148 and 248 after annealing, according to some embodiments in which bond pad 248 is misaligned with bond pad 148. In fig. 24G, some of the grooves 160 are still covered by the metal material 242, while some of the grooves 160 are covered by the dielectric layer 234 and the barrier layer 240. The void 161 may be present in a central portion of the engagement structure. In fig. 24H, some of the grooves 160 covered by the metal material 242 may be filled and disappear by the metal material 242 due to interdiffusion, and some of the grooves 160 covered by the dielectric layer 234 may remain. The void 161 may disappear due to interdiffusion. In fig. 24I, due to misalignment in forming a void extending from the edge of the bonding pad 248 to the central portion of the bonding pad 148, a groove 260 formed at the edge portion of the bonding pad 248 may merge with the void 161.

At operation 44 (fig. 1), the method 10 forms a dielectric via (TDV) 276 connected to the bond pad 148c, such as shown in fig. 19. Forming TDV276 may include removing adhesive layer 272 and carrier structure 270 from device structure 200 in an etching process or a grinding process to expose gap-fill dielectric region 274, performing an etching process to form a through-hole to expose bond pad 148c, and filling the through-hole with a conductive material. The through-holes extend through the gap-fill dielectric region 274 and the dielectric layer 234.TDV 276 may include metallic materials such as tungsten, aluminum, copper, and the like. A conductive barrier layer (such as titanium, titanium nitride, tantalum nitride, etc.) may also be formed under the metal material. Planarization, such as CMP, is performed to remove the excess portion of the metallization material and the remaining portion of the metal material forms TDV 276.

Region 278 in fig. 19 including TDV276, bond pad 148c, and BPV146 is depicted in fig. 25A. TDV276 contacts a central portion of metallic material 142 and fills the concave space due to the concave profile. That is, the bottom surface of TDV276 may have a convex profile. The recess 160 is covered by a dielectric layer 234. Fig. 25B is similar to fig. 25A. One difference is that misalignment causes some grooves 160 to be filled and vanished with the metallic material of TDV 276. Some of the grooves 160 remain covered by the dielectric layer 234.

At operation 46 (fig. 1), the method 10 forms a passivation layer, a metal pad, and an overlying dielectric layer, such as shown in fig. 20. A passivation layer 302 (sometimes referred to as passivation-1) is formed over the metal pad 220 and a via 304 is formed in the passivation layer 302 to electrically connect to the interconnect structure 212 through the metal pad 220. A metal pad 306 is formed over passivation layer 302 and metal pad 306 is electrically coupled to interconnect structure 212 through via 304. The metal pads 306 may be aluminum pads or aluminum copper pads, and other metal materials may also be used. A passivation layer 308 (sometimes referred to as passivation-2) is formed over the passivation layer 302. Each of passivation layers 302 and 308 may be a single layer or a composite layer and may be formed of a non-porous material. In some embodiments, one or both of passivation layers 302 and 308 are composite layers including a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. Passivation layers 302 and 308 may also be formed of other non-porous dielectric materials such as Undoped Silicate Glass (USG), silicon oxynitride, and the like. Next, the passivation layer 308 is patterned such that portions of the passivation layer 308 overlie edge portions of the metal pad 306 and portions of the metal pad 306 are exposed through openings in the passivation layer 308. Post-formation passivation interconnect (PPI) 310, which may include forming a metal seed layer and forming a patterned mask layer (not shown) over the metal seed layer, and plating the PPI 310 in the patterned mask layer. The patterned mask layer and portions of the metal seed layer that overlap the patterned mask layer are then removed in an etching process. The polymer layer 312 is then formed, and the polymer layer 312 may be formed of PBO, polyimide, or the like. Subsequently, an Under Bump Metal (UBM) 314 is formed, and the UBM 314 is connected to the PPI 310. In some embodiments, each of UBM 314 includes a barrier layer (not shown) and a seed layer (not shown) located over the barrier layer. The barrier layer may be a titanium layer, a titanium nitride layer, a tantalum nitride layer, or a layer formed of a titanium alloy or a tantalum alloy. The material of the seed layer may comprise copper or a copper alloy. Other metals may also be included in UBM 314, such as silver, gold, aluminum, palladium, nickel alloys, tungsten alloys, chromium alloys, and combinations thereof.

Fig. 21 shows an alternative embodiment to fig. 20 in which, unlike bond pads 148a and 148c, dummy bond pad 148b is not recessed in an edge portion to form a groove 160. A resist layer may be deposited over the dummy bond pad 148b to protect the dummy bond pad 148b from receiving the surface treatment process 158 discussed above. The resist layer is then removed using, for example, a suitable ashing or stripping process, such as using an oxygen plasma or the like. Fig. 22 is similar to fig. 21 in that, unlike the bonding pad 148a, the bonding pad 148c and the dummy bonding pad 148b are not recessed in the edge portion to form a groove 160. A resist layer may be deposited over the bond pads 148c and dummy bond pads 148b to protect the bond pads from receiving the surface treatment process 158 discussed above. The resist layer is then removed using, for example, a suitable ashing or stripping process, such as using an oxygen plasma or the like.

Fig. 20-22 illustrate a back-facing structure in which device structure 100 has its front side facing the back side of device structure 200. Fig. 23 shows an alternative embodiment of a face-to-face structure in which device structure 100 has its front side facing the front side of device structure 200. In particular, TSV 228 is located at the front side of bonded device structure 300, and TSV 228 is connected to metal pad 306 through via 304, and bond pad 248 and the corresponding BPV are formed under metal pad 220 and bonded to bond pad 148. In the illustrated embodiment, bond pad 248 has a similar size as bond pad 148, and grooves 160 and 260 merge into a larger groove, although other embodiments depicted in fig. 24B-24F are equally applicable.

Embodiments of the present invention have several advantageous features. By forming a groove around the bond pad, stresses in the bond structure, particularly in thermal cycling, are reduced. Thus improving the reliability of the joint structure.

In one exemplary aspect, the present invention relates to a method. The method includes depositing a first dielectric layer on a first substrate of a first device die; etching the first dielectric layer to form a trench; depositing a metal material in the trench and on a top surface of the first dielectric layer; performing a Chemical Mechanical Polishing (CMP) process to remove a portion of the metal material from the top surface of the first dielectric layer, wherein a remaining portion of the metal material in the trench forms a first metal pad; selectively etching the first metal pad to form a groove at an edge portion of the first metal pad after the performing of the CMP process; depositing a second dielectric layer on a second substrate of a second device die; forming a second metal pad in the second dielectric layer; and bonding the second device die to the first device die, wherein the second dielectric layer is bonded to the first dielectric layer and the second metal pad is bonded to the first metal pad. In some embodiments, in a top view, the groove is part of a groove ring surrounding the first metal pad. In some embodiments, the selective etching is a wet etching process. In some embodiments, the etchant of the wet etching process includes a mixture of sulfinylbis (sulfoximines) and hydroxylamine. In some embodiments, the selectively etching also forms a recessed profile in a middle portion of the first metal pad. In some embodiments, after bonding, a void is formed between the recessed profile of the first metal pad and the second metal pad. In some embodiments, the second metal pad has a size that is larger than the size of the first metal pad, and after bonding, the groove is covered by the second metal pad. In some embodiments, the width of the grooves is in the range of about 50nm to about 300nm and the depth of the grooves is in the range of about 50nm to about 300 nm. In some embodiments, the method further comprises: the second metal pad is selectively etched to form a groove at an edge portion of the second metal pad. In some embodiments, after bonding, the grooves at the edge portion of the first metal pad merge with the grooves at the edge portion of the second metal pad.

In another exemplary aspect, the invention is directed to a method. The method includes forming a first device structure, forming a second device structure, and bonding the second device structure to the first device structure. In some embodiments, forming the first device structure includes: depositing a first dielectric layer; forming a first metal pad in the first dielectric layer; and selectively etching an edge portion of the first metal pad to form a first groove. In some embodiments, forming the second device structure includes: depositing a second dielectric layer; forming a second metal pad in the second dielectric layer; and selectively etching an edge portion of the second metal pad to form a second groove. In some embodiments, the second metal pad is bonded to the first metal pad, and the second dielectric layer is bonded to the first dielectric layer. In some embodiments, the second metal pad is larger than the first metal pad, and the first groove is spaced apart from the second groove. In some embodiments, the first groove merges with the second groove after engagement. In some embodiments, after bonding, the top surface of the first metal pad and the top surface of the second metal pad form a void therebetween. In some embodiments, the first metal pad includes a barrier layer and a metal material surrounded by the barrier layer, and after selectively etching, a top surface of the barrier layer is substantially coplanar with a top surface of the first dielectric layer. In some embodiments, the forming of the first device structure further includes forming a first dummy metal pad in the first dielectric layer, the forming of the second device structure further includes forming a second dummy metal pad in the second dielectric layer, and after bonding, the second dummy metal pad is bonded to the first dummy metal pad, and in a top view, the recessed ring surrounds the bonded first dummy metal pad and second dummy metal pad. In some embodiments, the bonding includes annealing that reduces the size of the first groove and the second groove.

In yet another exemplary aspect, the present invention relates to a semiconductor device. The semiconductor device includes: a first device structure and a second device structure. In some embodiments, the first device structure includes: a first dielectric layer, a first metal pad in the first dielectric layer; and a first void located at an edge portion of the first metal pad. In some embodiments, the second device structure includes: a second dielectric layer in contact with the first dielectric layer, a second metal pad in the second dielectric layer and in contact with the first metal pad, and a second void at an edge portion of the second metal pad. In some embodiments, the first void is connected to the second void in forming a void ring surrounding the first metal pad and the second metal pad. In some embodiments, the second metal pad is larger than the first metal pad, and the second void is larger than the first void.

The foregoing outlines features of a drop-on embodiment so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A method of forming a semiconductor device, comprising:

depositing a first dielectric layer on a first substrate of a first device die;

etching the first dielectric layer to form a trench;

depositing a metal material in the trench and on a top surface of the first dielectric layer;

performing a Chemical Mechanical Polishing (CMP) process to remove a portion of the metal material from the top surface of the first dielectric layer, wherein a remaining portion of the metal material in the trench forms a first metal pad;

selectively etching the first metal pad to form a groove at an edge portion of the first metal pad after the performing of the chemical mechanical polishing process;

depositing a second dielectric layer on a second substrate of a second device die;

forming a second metal pad in the second dielectric layer; and

the second device die is bonded to the first device die, wherein the second dielectric layer is bonded to the first dielectric layer and the second metal pad is bonded to the first metal pad.

2. The method of claim 1, wherein the groove is part of a groove ring surrounding the first metal pad in a top view.

3. The method of claim 1, wherein the selectively etching is a wet etching process.

4. The method of claim 3, wherein the etchant of the wet etching process comprises a mixture of sulfinyl bis and hydroxylamine.

5. The method of claim 1, wherein the selectively etching further forms a recessed profile in a middle portion of the first metal pad.

6. The method of claim 5, wherein after the bonding, a void is formed between the recessed profile of the first metal pad and the second metal pad.

7. The method of claim 1, wherein the second metal pad has a size that is larger than a size of the first metal pad, and the groove is covered by the second metal pad after the bonding.

8. The method of claim 1, wherein the grooves have a width in the range of about 50nm to about 300nm and a depth in the range of about 50nm to about 300 nm.

9. A method of forming a semiconductor device, comprising:

forming a first device structure, comprising:

depositing a first dielectric layer;

forming a first metal pad in the first dielectric layer; and

Selectively etching an edge portion of the first metal pad to form a first groove;

forming a second device structure comprising:

depositing a second dielectric layer;

forming a second metal pad in the second dielectric layer; and

selectively etching an edge portion of the second metal pad to form a second groove; and

the second device structure is bonded to the first device structure, wherein the second metal pad is bonded to the first metal pad and the second dielectric layer is bonded to the first dielectric layer.

10. A semiconductor device, comprising:

a first device structure, the first device structure comprising:

a first dielectric layer;

a first metal pad located in the first dielectric layer; and

a first void located at an edge portion of the first metal pad; and

a second device structure, the second device structure comprising:

a second dielectric layer in contact with the first dielectric layer;

a second metal pad located in the second dielectric layer and in contact with the first metal pad; and

and a second void located at an edge portion of the second metal pad.