CN116936467A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN116936467A
CN116936467A CN202310472801.7A CN202310472801A CN116936467A CN 116936467 A CN116936467 A CN 116936467A CN 202310472801 A CN202310472801 A CN 202310472801A CN 116936467 A CN116936467 A CN 116936467A
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Prior art keywords
layer
dielectric layer
interlayer dielectric
etch
etch stop
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CN202310472801.7A
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Inventor
饶孟桓
黄麟淯
苏焕杰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/892,864 external-priority patent/US20230420566A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN116936467A publication Critical patent/CN116936467A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The method comprises the following steps: a structure is provided having a gate structure, source/drain electrodes, a first Etch Stop Layer (ESL), a first interlayer dielectric (ILD) layer, a second ESL, and a second ILD layer. The method comprises the following steps: forming a first etching mask; performing a first etch on the second ILD layer, the second ESL, and the first ILD layer through the first etch mask to form a first trench; depositing a third dielectric layer in the first trench; forming a second etching mask; and performing a second etch on the second ILD layer, the second ESL, the first ILD layer, and the first ESL through the second etch mask, thereby forming a second trench, wherein the second trench exposes some of the source/drain electrodes, and the third dielectric layer resists the second etch. The method further comprises the steps of: a metal layer is deposited in the second trench. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present application relate to semiconductor structures and methods of forming the same.
Background
The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. This shrinking also increases the complexity of processing and manufacturing ICs, which requires similar developments in IC processing and manufacturing in order to achieve these advances.
For example, as scaling continues, isolation between adjacent source/drain (S/D) contacts becomes an issue. Methods and structures for increasing isolation between adjacent S/D contacts are highly desirable.
Disclosure of Invention
Some embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a structure having a gate structure, source/drain electrodes adjacent to the gate structure, a first etch stop layer over the source/drain electrodes and the gate structure, a first interlayer dielectric layer over the first etch stop layer, a second etch stop layer over the gate structure, the first etch stop layer and the first interlayer dielectric layer, and a second interlayer dielectric layer over the second etch stop layer; forming a first etch mask providing a first opening over the second interlayer dielectric layer; performing a first etch on the second interlayer dielectric layer, the second etch stop layer, and the first interlayer dielectric layer through the first opening, thereby forming a first trench; depositing a third dielectric layer in the first trench, wherein the third dielectric layer has a different material than the second interlayer dielectric layer; forming a second etch mask, the second etch mask providing a second opening exposing portions of the second interlayer dielectric layer and the third dielectric layer; performing a second etch on the second interlayer dielectric layer, the second etch stop layer, the first interlayer dielectric layer, and the first etch stop layer through the second opening, thereby forming a second trench, wherein the second trench exposes some of the source/drain electrodes, wherein the third dielectric layer resists the second etch; and depositing a metal layer in the second trench.
Other embodiments of the present application provide a method of forming a semiconductor structure, comprising: providing a structure having a semiconductor fin, an isolation structure adjacent a lower portion of the semiconductor fin, a source/drain electrode over the semiconductor fin, a gate structure over a channel region of the semiconductor fin, a first etch stop layer over the source/drain electrode, the isolation structure and the gate structure, a first interlayer dielectric layer over the first etch stop layer, a second etch stop layer over the gate structure, the first etch stop layer and the first interlayer dielectric layer, and a second interlayer dielectric layer over the second etch stop layer; forming a first etch mask providing a first opening over the second interlayer dielectric layer; performing a first etch on at least the second interlayer dielectric layer, the second etch stop layer, and the first interlayer dielectric layer through the first opening to create a first trench; filling the first trench with one or more third dielectric layers having a different material than the second interlayer dielectric layer; forming a second etch mask that provides a second opening directly over the second interlayer dielectric layer and the one or more third dielectric layers; performing a second etch through the second opening on at least the second interlayer dielectric layer, the second etch stop layer, the first interlayer dielectric layer, and the first etch stop layer, thereby creating a second trench exposing some of the source/drain electrodes, wherein the second etch is adjusted not to etch the one or more third dielectric layers; and forming source/drain contact plugs in the second trenches.
Still further embodiments of the present application provide a semiconductor structure comprising: a gate structure; source/drain electrodes adjacent to the gate structure; a first etch stop layer over the source/drain electrodes and the gate structure; a first interlayer dielectric layer over the first etch stop layer; a second etch stop layer over the gate structure, the first etch stop layer, and the first interlayer dielectric layer; a second interlayer dielectric layer over the second etch stop layer; a first dielectric structure disposed between adjacent ones of the gate structures from a top view and extending vertically from a top surface of the second interlayer dielectric layer to a point within or below the first interlayer dielectric layer; and source/drain contacts extending through the first and second interlayer dielectric layers and the first and second etch stop layers and bonded on some of the source/drain electrodes.
Drawings
The various aspects of the application are best understood from the following detailed description when read in conjunction with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A and 1B illustrate a flowchart of a method of forming a semiconductor device according to an embodiment of the present invention.
Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A and 14A are top views of portions of a semiconductor device during various stages of manufacture according to the methods of fig. 1A and 1B, in accordance with an embodiment of the invention.
Fig. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B and 14B are cross-sectional views of portions of the semiconductor device along lines B-B of fig. 2A-14A, respectively, during various stages of fabrication according to the methods in fig. 1A and 1B, according to embodiments of the invention.
Fig. 2C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C and 14C are cross-sectional views of portions of the semiconductor device along the C-C line of fig. 2A-14A, respectively, during various stages of fabrication according to the methods in fig. 1A and 1B, according to embodiments of the invention.
Fig. 15, 16 and 17 are cross-sectional views of a portion of the semiconductor device along line B-B of fig. 2A during various stages of fabrication according to the method of fig. 1A and 1B, in accordance with an embodiment of the present invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, when a numerical value or range of numerical values is described using "about," "approximately," etc., the term encompasses numerical values within certain variations (such as +/-10% or other variations) of the numerical values described, as would occur to those of skill in the art in view of the specific techniques disclosed herein, unless otherwise indicated. For example, the term "about 5nm" may encompass a size range from 4.5nm to 5.5nm, 4.0nm to 5.0nm, and the like.
The present invention relates generally to semiconductor devices and methods of manufacture, and more particularly to source/drain (S/D) contacts and methods of forming the same. In the present invention, a source/drain (S/D) may refer to a source or a drain of a transistor, individually or collectively depending on the context. The source/drain contacts refer to metal contacts or metal compounds bonded to the S/D electrodes or regions. Forming S/D contacts typically involves multiple processes. One process is to etch the dielectric layer over the S/D electrode through an etch mask so that the S/D electrode can be exposed for making connections to the S/D contacts. The etching of the dielectric layer may be anisotropic or isotropic. Sometimes, portions of the etch mask may be narrower, such as at or near the Critical Dimension (CD) of the fabrication process, and these narrower portions of the etch mask may be stripped before or during the etch process. Thus, two contact holes may be unexpectedly merged into one, and two S/D contacts may be unexpectedly shorted. The present invention solves the above and other problems by using a process comprising: forming one or more plug dielectric layers at locations where the S/D contacts are designed to be spaced apart; forming a patterned mask; and performing an etching process to form the S/D contact hole by using the patterned mask and the one or more plug dielectric layers together as an etching mask. Due to the presence of one or more plug dielectric layers, the S/D contacts are safely isolated from each other according to design.
The disclosed methods and structures may be applied to ICs with FinFET, full gate-all-around (GAA) transistors, or other types of transistors. GAA transistors refer to transistors having a gate stack (which includes a gate electrode and a gate dielectric layer) surrounding the transistor channel, such as vertically stacked full-gate horizontal nanowire or nanoplatelet MOSFET devices. Various aspects of the invention will be further discussed with reference to fig. 2A-14C, with fig. 2A-14C showing an exemplary IC having finfets. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other structures (such as ICs with GAA transistors) for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein.
Fig. 1A and 1B illustrate a flow chart of a method 10 of forming a semiconductor device 200 (or semiconductor structure 200) in accordance with various aspects of the invention. The method 10 is merely an example and is not intended to limit the present invention beyond what is explicitly recited in the claims. Additional operations may be provided before, during, and after the method 10, and some of the operations described may be replaced, eliminated, or repositioned for additional embodiments of the method. The method 10 is described below in connection with fig. 2A-14C, with fig. 2A-14C showing portions of the semiconductor device 200 at various stages of the manufacturing process. In particular, fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, and 14A are top views of portions of the semiconductor device 200; fig. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, and 14B are cross-sectional views of portions of the semiconductor device 200 along the "B-B" line of fig. 2A to 14A, respectively; and fig. 2C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, and 14C are cross-sectional views of portions of the semiconductor device 200 along the "C-C" line of fig. 2A to 14A, respectively. The "B-B" line is along the channel length (or gate length, lg) direction, and the "C-C" line is perpendicular to the channel length direction.
The semiconductor device 200 is provided for illustrative purposes and is not necessarily limiting embodiments of the invention to any number of devices, any number of regions, or any configuration of structures or regions. Further, the semiconductor device 200 may be an intermediate device or portion thereof fabricated during processing of the IC, which may include Static Random Access Memory (SRAM) and/or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs such as finfets and full-gate devices, metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. The semiconductor device 200 is shown in fig. 2A-14C as having finfets. In alternative embodiments, the semiconductor device 200 may have GAA or other types of transistors. Fig. 2A to 14C have been simplified for clarity to better understand the inventive concepts of the present invention. Additional components may be added to semiconductor device 200 and some of the components described below may be replaced, modified, or eliminated in other embodiments of semiconductor device 200.
In operation 12, the method 10 (fig. 1A) provides an intermediate structure of a semiconductor device 200, embodiments of which are shown in fig. 2A-2C. Referring to fig. 2A through 2C, a semiconductor device 200 includes a substrate 201 and various components built into or on the substrate 201. In the depicted embodiment, semiconductor device 200 includes a semiconductor fin 202 protruding from a substrate 201 and an S/D electrode 260 disposed over semiconductor fin 202. Semiconductor fin 202 extends longitudinally in the "X" direction. The semiconductor fin 202 includes channel regions 204, each of the channel regions 204 connecting two S/D electrodes 260 and functioning as a transistor channel. The semiconductor device 200 also includes an isolation structure 203, such as a Shallow Trench Isolation (STI), to isolate active regions, such as the semiconductor fins 202, from each other. In an alternative embodiment in which the transistor is a GAA transistor, the channel region 204 includes a plurality of semiconductor channels stacked vertically. The semiconductor device 200 further includes a gate structure 240 located over the channel region 204 and a gate spacer 247 located on a sidewall of the gate structure 240. Gate structure 240 is disposed over isolation structure 203 and on three sides of channel region 204. In the depicted embodiment, the semiconductor device 200 further includes a gate cap 357 located on top of the gate structure 240, a first Etch Stop Layer (ESL) 269, a first interlayer dielectric (ILD) layer 270, a second ESL 369, a second ILD layer 370. These elements will be described further below.
In an embodiment, the substrate 201 is a bulk silicon substrate (i.e., comprising bulk single crystal silicon). In various embodiments, the substrate 201 may include other semiconductor materials such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, siGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or combinations thereof. In alternative embodiments, the substrate 201 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.
Semiconductor fin 202 may include one or more layers of semiconductor material, such as silicon or silicon germanium. Semiconductor fin 202 may be formed by any suitable method. For example, semiconductor fin 202 may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing creation of patterns with, for example, smaller pitches than are obtainable using single, direct photolithography processes. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and then the remaining spacers or mandrels can be used as masking elements to pattern the semiconductor fins 202. For example, the masking element may be used to etch a recess in a semiconductor layer over the substrate 201 or in the substrate 201, leaving the semiconductor fin 202 on the substrate 201.
Isolation structure 203 may comprise silicon oxide (SiO) 2 ) Silicon nitride (Si) 3 N 4 ) Silicon oxynitride (SiON), fluorine doped silicate glass (FSG), low-k dielectric materials, and/or other suitable insulating materials. In an embodiment, isolation structure 203 is formed by etching a trench in or over substrate 201 (e.g., as part of the process of forming semiconductor fin 202), filling the trench with an insulating material, and performing a Chemical Mechanical Planarization (CMP) process and/or an etchback process on the insulating material, leaving the remaining insulating material as isolation structure 203. Other types of isolation structures may also be suitable, such as field oxide and local oxidation of silicon (LOCOS). Isolation structure 203 may comprise a multi-layer structure, for example, with one or more liner layers (e.g., silicon nitride) on the surfaces of substrate 201 and semiconductor fin 202 and one or moreA main isolation layer (e.g., silicon dioxide) over the pad layer.
The S/D electrode 260 comprises an epitaxially grown semiconductor material, such as epitaxially grown silicon, germanium, or silicon germanium. The S/D electrode 260 may be formed by any epitaxial process including Chemical Vapor Deposition (CVD) techniques (e.g., vapor phase epitaxy and/or ultra-high vacuum CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S/D electrode 260 may be doped with an n-type dopant and/or a p-type dopant. In some embodiments, for n-type transistors, the S/D electrode 260 comprises silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming Si: C epitaxial S/D features, si: P epitaxial S/D features, or Si: C: P epitaxial S/D features). In some embodiments, for p-type transistors, the S/D electrode 260 comprises silicon germanium or germanium, and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming Si: ge: B epitaxial S/D features). The S/D electrode 260 may include a plurality of epitaxial semiconductor layers having different doping concentration levels. In some embodiments, an annealing process (e.g., rapid Thermal Annealing (RTA) and/or laser annealing) is performed to activate the dopants in the epitaxial S/D electrode 260. The top surface of the S/D electrode 260 may be planar in some embodiments, and may not be planar in some other embodiments.
In the depicted embodiment, each gate structure 240 includes a gate dielectric layer 349 and a gate electrode 350. The gate dielectric layer 349 may include a high-k dielectric material such as HfO 2 、HfSiO、HfSiO 4 、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlO x 、ZrO、ZrO 2 、ZrSiO 2 、AlO、AlSiO、Al 2 O 3 、TiO、TiO 2 、LaO、LaSiO、Ta 2 O 3 、Ta 2 O 5 、Y 2 O 3 、SrTiO 3 、BaZrO、BaTiO 3 (BTO)、(Ba、Sr)TiO 3 (BST), hafnium oxide-aluminum oxide (HfO) 2 -Al 2 O 3 ) Alloys, other suitable high-k dielectric materials, or combinations thereof. The gate dielectric layer 349 may be deposited by chemical oxidation, thermal oxidation, atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), and/or othersFormed by a suitable method. In some embodiments, each gate structure 240 further includes an interfacial layer between the gate dielectric layer 349 and the channel region 204. The interfacial layer may comprise silicon dioxide, silicon oxynitride, or other suitable materials. In some embodiments, the gate electrode 350 includes an n-type or p-type work function metal layer and a metal fill layer. For example, the n-type work function metal layer may include a metal having a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof. For example, the p-type work function metal layer may include a metal having a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or a combination thereof. For example, the metal fill layer may include aluminum, tungsten, cobalt, copper, and/or other suitable materials. The gate electrode 350 may be formed by CVD, PVD, plating, and/or other suitable process. Because gate structure 240 includes a high-k dielectric layer and a metal layer, they are also referred to as high-k metal gates.
In some embodiments, gate spacers 247 comprise a dielectric material, such as a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). In an embodiment, the gate spacer 247 may include La 2 O 3 、Al 2 O 3 、ZnO、ZrN、Zr 2 Al 3 O 9 、TiO 2 、TaO 2 、ZrO 2 、HfO 2 、Y 2 O 3 AlON, taCN, zrSi or other suitable material. For example, a dielectric layer (such as a silicon nitride layer) comprising silicon and nitrogen may be deposited over the dummy gate stack (which is then replaced by the high-k metal gate 240) and then etched (e.g., anisotropically etched) to form the gate spacers 247. In some embodiments, gate spacer 247 comprises a multi-layer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers, are formed adjacent to the gate structure 240.In an embodiment, for example, the gate spacers 247 may have a thickness of about 1nm to about 40 nm.
In some embodiments, the gate cap 357 may comprise tungsten (W), cobalt (Co), ruthenium (Ru), other suitable metals, or combinations thereof, and may be formed by CVD, PVD, ALD. In some embodiments, gate cap 357 may have a thickness of about 1nm to about 4 nm. In an embodiment, the top surfaces of gate cap 357 and gate spacer 247 are substantially coplanar. In some embodiments, gate cap 357 is omitted.
The ESL 269 is located on the sidewalls of the gate spacers 247 and over the S/D electrodes 260. ILD layer 270 is located over ESL 269 and fills the space between adjacent gate structures 240 and S/D electrodes 260. In some embodiments, ESL 269 has a conformal shape, i.e., it has a substantially uniform thickness over the underlying structure including isolation structures 203, S/D electrodes 260, and gate spacers 247. In an embodiment, the top surface of gate cap 357, or the top surface of gate structure 240 (if gate cap 357 is omitted), is substantially coplanar with the topmost surfaces of ESL 269 and ILD layer 270. ESL 369 is disposed over the top surface of gate cap 357 or on the top surface of gate structure 240 (if gate cap 357 is omitted), gate spacers 247, ESL 269, and ILD layer 270. ILD layer 370 is disposed over ESL 369. In an embodiment, each of ESLs 269 and 369 may include Si 3 N 4 、SiCN、SiC、SiOC、SiOCN、HfO 2 、ZrO 2 、ZrAlO x 、HfAlO x 、HfSiO x 、Al 2 O 3 Or other suitable material; and may be formed by CVD, PVD, ALD or other suitable methods. In an embodiment, each of ILD layers 270 and 370 may comprise an oxide formed of tetraethyl orthosilicate (TEOS) (e.g., using CVD to react TEOS with oxygen to deposit silicon oxide), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), FSG, phosphosilicate glass (PSG), boron doped silicate glass (BSG), low-k dielectric material, other suitable dielectric material, or combinations thereof. Each of ILD layers 270 and 370 may be formed by PECVD (plasma enhanced CVD), FCVD (flowable CVD), or other suitable methods.
In operation 14, the method 10 (fig. 1A) forms an etch mask 360 over the semiconductor device 200, such as shown in fig. 3A-3C. The etch mask 360 includes a resist (or photoresist) layer 363 over the hard mask layer 361. The hard mask layer 361 may include a nitrogen-free antireflective layer (NFARL), carbon-doped silicon dioxide (e.g., siO) 2 C), titanium nitride (TiN), titanium oxide (TiO) 2 ) Boron Nitride (BN) and/or other suitable materials. Operation 14 includes a variety of processes including deposition, photolithography, and etching processes. For example, operation 14 may deposit a hard mask layer 361 over the semiconductor device 200 and spin-coat a resist layer 363 on the hard mask layer 361. Operation 14 then performs a photolithography process that includes exposing the resist layer 363 to radiant energy (e.g., DUV light or EUV light) and developing the exposed resist layer 363 in a developing solution. After development, the resist layer 363 is patterned into a resist pattern (referred to as a resist pattern 363) that provides the respective openings 362. The opening 362 is located directly above the region where one or more plug dielectric layers 273 (fig. 5A-5C) are to be formed. The hard mask layer 361 is then etched through the openings 362 to create a patterned hard mask (referred to as a hard mask pattern 361). In some embodiments, the resist pattern 363 is removed after the hard mask pattern 361 is formed.
In operation 16, the method 10 (fig. 1A) etches the semiconductor device 200 to form the trench 272 with the etch mask 360 (either the hard mask pattern 361 or both the hard mask pattern 361 and the resist pattern 363) in place, as shown in fig. 4A-4C. In an embodiment, operation 16 applies one or more etching processes to the semiconductor device 200. In addition, one or more etching processes are tuned to be selective to the materials of ILD layers 370 and 270 and ESLs 369 and 269. The etch mask 360 may be partially consumed during the etching process. In an embodiment, any remaining portions of the etch mask 360 may be removed after the formation of the trenches 272. In alternative embodiments, any remaining portions of the etch mask 360 may remain after the formation of the trenches 272 and be subsequently removed in a CMP process that polishes one or more plug dielectric layers 273 (see fig. 5A-5C). The depth of the grooves 272 may vary in various embodiments. For example, in the embodiment depicted in fig. 4B-4C, the channel 272 reaches and exposes the ESL 269, and may extend partially into the ESL 269. In an alternative embodiment depicted in fig. 10B-10C, the trench 272 (in which the dielectric plug 273 is formed) does not reach the ESL 269 and stops in the ILD 270. In another alternative embodiment depicted in fig. 12B-12C, the trench 272 (in which the dielectric plug 273 is formed) extends completely through the ESL 269 and exposes the S/D electrode 260 and/or isolation structure 203. In addition, the groove 272 is formed to have tapered sidewalls. The sidewall angle will be described when discussing fig. 9A to 9C. Furthermore, in various embodiments, the sidewalls of trench 272 may or may not be planar, depending on the materials of ILD layers 370 and 270 and ESLs 369 and 269 and the etchant used. For example, when a single etch process is used to etch ILD layers 370 and 270 and ESLs 369 and 269, the sidewalls of trench 272 may not be planar due to the different materials in ILD layers 370 and 270 and ESLs 369 and 269.
In operation 18, the method 10 (fig. 1A) deposits one or more plug dielectric layers (or dielectric plugs) 273 over the semiconductor device 200 that fill the trenches 272, such as shown in fig. 5A-5C. In an embodiment, the patterned hard mask 361 is completely removed prior to operation 18. In an alternative embodiment, patterned hard mask 361, or portions thereof, are not removed prior to operation 18. The dielectric plug 273, or at least a top portion thereof, comprises a material different from the material comprised in the ILD layer 370 in order to achieve etch selectivity in a subsequent etching process (discussed below in operation 22). In an embodiment, the dielectric plug 273 includes La 2 O 3 、Al 2 O 3 、AlON、ZrO 2 、HfO 2 、Si 3 N 4 、ZnO、ZrN、ZrAlO、TiO 2 、Ta 2 O 5 、Y 2 O 3 TaCN, siOCN, siOC, siCN or combinations thereof. The dielectric plugs 273 may be deposited using CVD, FCVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or a combination thereof. Subsequently, the method 10 (fig. 1A) performs a CMP process on the dielectric plugs 273 and patterned hard mask 361 (if present) in operation 18 until the ILD layer 370 is exposed, such as fig. 5B-5BShown in 5C. In an embodiment, ILD layer 370 functions as a CMP stop. The remaining portion of the dielectric plug 273 fills the trench 272.
In operation 20, the method 10 (fig. 1A) forms a second etch mask 463 over the ILD layer 370 and the dielectric plug 273, such as shown in fig. 6A-6C. In an embodiment, the etch mask 463 includes a resist pattern, such as etch mask 360, over the hard mask pattern. In another embodiment, the etch mask 463 includes only a resist pattern. The etch mask 463 may be formed using deposition, photolithography, and etching processes, such as those discussed with respect to operation 14. The etch mask 463 provides respective openings 464 directly above the areas where one or more S/D contacts 282 (fig. 8A-8C) are to be formed. The etch mask 463 covers the gate structure 240 and the gate spacers 247 from subsequent etching processes. In addition, the opening 464 is aligned with the dielectric plug 273. In other words, the dielectric plug 273 or a major portion thereof is exposed through the opening 464.
In operation 22, method 10 (fig. 1B) etches ILD layers 370 and 270 and ESLs 369 and 269 to expose S/D electrode 260, thereby creating S/D contact holes 465, such as shown in fig. 7A-7C. The dielectric plug 273 and the etch mask 463 collectively function as an etch mask during the etching process, which provides manufacturing process margin and prevents hard mask stripping problems associated with other methods. Taking the dielectric plug 273 (right) in fig. 7C as an example, the length of the dielectric plug 273 in the "X" and "Y" directions may be very small, such as at or near the Critical Dimension (CD) of the fabrication process. In some approaches, a small hard mask is used in place of the dielectric plugs 273. The small hard mask may delaminate during the etching process, for example, due to insufficient adhesion, excessive lateral etching, etc. When this occurs, the two contact holes on the right side of fig. 7C will become one, resulting in a short defect. In contrast, the use of dielectric plug 273 does not have such a delamination problem because it is formed deeper in dielectric layers 370, 270, 369, and 269.
Another advantage of using the dielectric plug 273 and the etch mask 463 together as an etch mask is to mitigate the effect of etch loading between the long contact hole 465 and the short contact hole 465 (having a length defined along the "Y" direction in fig. 7A). Typically, during etching, some polymer (such as a polymer comprising F, N, O and/or other materials) may be grown on the sidewalls of the contact holes. Such polymers may slow the lateral etching in the "X" direction. In general, the longer the contact hole, the lower the aspect ratio (defined as the ratio of the height of the contact hole to the length of the contact hole). In general, the lower the aspect ratio of the contact hole, the more polymer is generated on the sidewall of the contact hole during etching, and the less etching is laterally along the "X" direction. Therefore, when the two contact holes have a large difference in their aspect ratio, their dimensions in the "X" direction may also have a large difference. When a hard mask is used in place of dielectric plug 273, the hole (during etching) will have a higher aspect ratio in cross-section along the "C-C" line than this embodiment, as the hard mask will be formed over ILD layer 370. In contrast, the hard mask is not present in the cross-sectional view along the "C-C" line, as shown in FIG. 6C. Thus, with this embodiment, the aspect ratios of the different contact holes have small differences, which results in small differences in the widths of the contact holes in the "X" direction.
In operation 24, the method 10 (fig. 1B) removes the etch mask 463, e.g., using resist stripping, etching, and/or other suitable methods.
In operation 26, the method 10 (FIG. 1B) forms respective structures in the contact holes 465. For example, the method 10 may form a liner 281 on the sidewalls of the contact hole 465, a silicide layer 280 at the bottom of the contact hole 465, and an S/D contact 282 (or S/D contact plug 282) on the silicide layer 280 and the liner 281, such as shown in fig. 8A-8C. Liner 281 may include La 2 O 3 、Al 2 O 3 、AlON、ZrO 2 、HfO 2 、Si 3 N 4 、ZnO、ZrN、ZrAlO、TiO 2 、Ta 2 O 5 、Y 2 O 3 TaCN, siOCN, siOC, siCN or combinations thereof, and may be deposited using CVD, PVD, ALD, other suitable methods, or combinations thereof. The liner 281 may be deposited along the surface of the contact hole 465, including at the bottom of the contact hole 465, and then etched back. The liner 281 may be about 1nm to about 5nm thick. In some embodimentsThe pad 281 is omitted.
To form silicide layer 280, method 10 may deposit one or more metals in contact hole 465, perform an annealing process to semiconductor device 200 to cause a reaction between the one or more metals and S/D electrode 260 to produce silicide layer 280, and remove unreacted portions of the one or more metals, leaving silicide layer 280 in contact hole 465. Silicide layer 280 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (nipesi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In some embodiments, silicide layer 280 is omitted.
In an embodiment, the S/D contact 282 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the S/D contact 282 includes a barrier layer as an outer layer, and the barrier layer may include TiN, taN, tiSiN or other suitable material.
In an embodiment, the method 10 performs a CMP process to remove excess material of the S/D contacts 282 located over the top surface of the semiconductor device 200 in operation 26. This exposes the ILD layer 370 and the top surface of the dielectric plug 273, such as shown in fig. 8A-8C. Referring to fig. 8A-8C, the dielectric plugs 273 isolate adjacent S/D contacts 282 from each other. Because the dielectric plugs 273 are formed before the S/D contacts 282 and serve as cutting members (or spacers) for the S/D contacts 282, they are also referred to as pre-cut or reverse cut dielectric plugs, and the S/D contacts 282 are pre-cut or reverse cut by the dielectric plugs 273.
In operation 28, the method 10 (fig. 1B) forms S/D contact vias 480 on the S/D contacts 282, such as shown in fig. 9A-9C. This involves a variety of processes including deposition and etching. For example, the method 10 may form one or more dielectric layers 470 over the ILD layer 370 and dielectric plugs 273, perform an etching process to form vias over the S/D contacts 282, and deposit S/D contact vias 480 in the vias. Dielectric layer 470 may include a dielectric material similar to ILD layer 370 and/or ESL 369. The S/D contact via 480 may include one or more conductive materials, such as Co, W, ru, al, mo, ti, tiN, tiSi, coSi, niSi, taN, ni, tiSiN or a combination thereof, and may be formed by CVD, PVD, plating, and/or other suitable processes. The S/D contact via 480 penetrates the dielectric layer 470 atop the S/D contact 282 and makes electrical contact with the S/D contact 282. In some embodiments, the S/D contact via 480 may be partially bonded to the dielectric plug 273 and may be in direct contact with the dielectric plug 273.
Referring to fig. 9A-9C, in an embodiment, the dielectric plug 273 has a thickness T1 (in the "Z" direction) in a range from about 40nm to about 100 nm. In addition, the dielectric plugs 273 have inclined sidewalls identical to the inclined sidewalls of the trenches 272 (see fig. 4A to 4C). In a cross-sectional view along the "B-B" line (fig. 9B), dielectric plugs 273 form an angle α1 with the top surface of ILD layer 370 and an angle α2 with the top surface of ESL 269 (or the bottom surface of ILD layer 370). In an embodiment, the angle α1 may be in a range of about 90.5 degrees to about 100 degrees, and the angle α2 may be in a range of about 80 degrees to about 89.5 degrees. In a cross-sectional view along the "C-C" line (fig. 9C), dielectric plugs 273 form an angle α3 with the top surface of ILD layer 370 (or the top surface of S/D contacts 282) and an angle α4 with the top surface of ESL 269 (or the bottom surface of ILD layer 370). In an embodiment, angle α3 may be in the range of about 90.5 degrees to about 100 degrees, and angle α4 may be in the range of about 80 degrees to about 89.5 degrees. The sloped sidewalls and the angle described above improve the dielectric filling of the trench 272 such that the dielectric plugs 273 are formed free of voids.
In operation 30, the method 10 (fig. 1B) performs further fabrication of the semiconductor device 200. For example, method 10 may form gate vias that are bonded to gate structure 240 and/or gate cap 357. The method 10 may also form a multilevel interconnect structure over the dielectric layer 470 and the S/D contact via 480.
Fig. 10A to 10C illustrate another embodiment of the semiconductor device 200. In this embodiment, the trench 272 (see fig. 4A-4C) does not reach the ESL 269 and stops within the ILD layer 270. Thus, the dielectric plug 273 does not reach the ESL 269, and the bottom surface of the dielectric plug 273 is located a distance P1 above the bottom surface of the ILD layer 270. In an embodiment, the distance P1 is in the range of about 1nm to about 30 nm. Furthermore, in the embodiment depicted in fig. 10B-10C, the bottom surface of the dielectric plug 273 is below the top surface of the ILD layer 270. In alternative embodiments, the bottom surface of dielectric plug 273 may be located over the top surface of ILD layer 270 or over the topmost surface of ESL 269. Since the trench 272 is shallower in this embodiment than in the embodiments shown in fig. 9A-9C, this embodiment makes dielectric filling of the trench 272 easier. Other aspects of this embodiment are the same as those of the embodiment shown in fig. 9A to 9C.
Fig. 11A to 11C illustrate another embodiment of the semiconductor device 200. In this embodiment, trenches 272 are partially etched in ESL 269 (see fig. 4A-4C). Thus, the dielectric plug 273 is also partially located in the ESL 269, and the bottom surface of the dielectric plug 273 is located below the bottom surface of the ILD layer 270 and above the bottom-most surface of the ESL 269. In addition, the bottom surface of the dielectric plug 273 is higher than the bottom surface of the source/drain contact 282. Other aspects of this embodiment are the same as those of the embodiment shown in fig. 9A to 9C.
Fig. 12A to 12C show another embodiment of the semiconductor device 200. In this embodiment, the channel 272 (see fig. 4A-4C) extends completely through the ESL 269. Thus, the dielectric plug 273 completely penetrates the ESL 269 and the bottom surface of the dielectric plug 273 directly contacts the S/D electrode 260 and/or the isolation structure 203. Other aspects of this embodiment are the same as those of the embodiment shown in fig. 9A to 9C.
Fig. 13A to 13C illustrate another embodiment of the semiconductor device 200. In this embodiment, each dielectric plug 273 includes two portions, a lower portion 273L and an upper portion 273U. First the lower portion 273L is deposited in the trench 272, and then the upper portion 273U is deposited on top of the lower portion 273L. In an embodiment, the two portions 273L and 273U comprise different dielectric materials. For example, lower portion 273L may include a material more suitable for filling narrow holes than the material in upper portion 273U, while upper portion 273U may include a material ratio relative to ILD layer 370Lower portion 273L provides a more etch selective material. In various embodiments, upper portion 273U may include La 2 O 3 、Al 2 O 3 、AlON、ZrO 2 、HfO 2 、Si 3 N 4 、ZnO、ZrN、ZrAlO、TiO 2 、Ta 2 O 5 、Y 2 O 3 TaCN, siOCN, siOC, siCN, or combinations thereof, and the lower portion 273L may include La 2 O 3 、Al 2 O 3 、AlON、ZrO 2 、HfO 2 、Si 3 N 4 、ZnO、ZrN、ZrAlO、TiO 2 、Ta 2 O 5 、Y 2 O 3 TaCN, siOCN, siOC, siCN, or combinations thereof, which is different from the material in the upper portion 273U. Further, in the embodiment depicted in fig. 13B-13C, the top surface of the lower portion 273L is below the top surface of the ILD layer 270. In alternative embodiments, the top surface of lower portion 273L may be located above the top surface of ILD layer 270 or above the topmost surface of ESL 269. In various embodiments, upper portion 273U has a thickness T2 that may range from about 10nm to about 30 nm. In various embodiments, lower portion 273L has a thickness T3 that may range from about 10nm to about 30 nm. Other aspects of this embodiment are the same as those of the embodiment shown in fig. 9A-9C (such as sloped sidewalls and angles), fig. 10A-10C (e.g., the bottom surface of lower portion 273L may be located above ESL 269), fig. 11A-11C (e.g., lower portion 273L may extend partially into ESL 269), and fig. 12A-12C (e.g., lower portion 273L may completely penetrate ESL 269 and be bonded to S/D electrode 260 and/or isolation structure 203).
Fig. 14A to 14C illustrate another embodiment of the semiconductor device 200. In this embodiment, the semiconductor device 200 further includes a dielectric liner 271 on the sidewalls and bottom of each dielectric plug 273. The dielectric liner 271 may comprise Si 3 N 4 SiCN or other suitable material. In an embodiment, the dielectric liner 271 comprises a dielectric material having a lower dielectric constant (lower k) than the material in the dielectric plug 273. The dielectric liner 271 may help prevent material migration of the dielectric plug 273To the gate structure 240 and oxidize the gate structure 240. In an embodiment, the dielectric liner 271 has a thickness of about 1nm to about 5 nm. Other aspects of this embodiment are the same as those of the embodiment shown in fig. 9A-9C (such as sloped sidewalls and angles). Further, a dielectric liner 271 may be provided in the embodiments shown in fig. 10A to 10C, 11A to 11C, 12A to 12C, 13A to 13C, and their modifications. Some non-limiting examples are shown in fig. 15-17.
Although not intended to be limiting, one or more embodiments of the present invention provide a number of benefits to semiconductor devices and their formation processes. For example, embodiments of the present invention provide a process for forming S/D contacts. Before forming the S/D contacts, dielectric plugs are formed that serve as spacers or isolation between adjacent S/D contacts. During the process of forming the contact holes, the dielectric plugs help prevent hard mask stripping problems and mitigate etch loading effects between the short and long contacts. The provided subject matter can be easily integrated into existing IC manufacturing flows and can be applied to many different process nodes.
In one exemplary aspect, the invention relates to a method comprising: a structure is provided having a gate structure, source/drain electrodes adjacent the gate structure, a first etch stop layer over the source/drain electrodes and the gate structure, a first interlayer dielectric layer over the first etch stop layer, a second etch stop layer over the gate structure, the first etch stop layer and the first interlayer dielectric layer, and a second interlayer dielectric layer over the second etch stop layer. The method further comprises the steps of: forming a first etch mask over the second interlayer dielectric layer providing a first opening; and performing a first etch on the second interlayer dielectric layer, the second etch stop layer, and the first interlayer dielectric layer through the first opening, thereby forming a first trench. The method further comprises the steps of: a third dielectric layer is deposited in the first trench, wherein the third dielectric layer has a different material than the second interlayer dielectric layer. The method further comprises the steps of: forming a second etch mask, the second etch mask providing a second opening exposing portions of the second interlayer dielectric layer and the third dielectric layer; and performing a second etch on the second interlayer dielectric layer, the second etch stop layer, the first interlayer dielectric layer, and the first etch stop layer through the second opening, thereby forming a second trench, wherein the second trench exposes some of the source/drain electrodes, wherein the third dielectric layer is resistant to the second etch. The method further comprises the steps of: a metal layer is deposited in the second trench.
In an embodiment, the method further comprises: the second etch mask is removed prior to depositing the metal layer. In another embodiment, the method further comprises: forming a third interlayer dielectric layer over the second interlayer dielectric layer, the third dielectric layer, and the metal layer; etching the third interlayer dielectric layer to form a via hole exposing the metal layer; and forming a metal via in the via. In a further embodiment, at least one of the metal vias is disposed directly above the third dielectric layer.
In an embodiment of the method, the first etch also etches the first etch stop layer. In another embodiment, the method further comprises: a dielectric liner layer is formed on the surface of the first trench prior to depositing the third dielectric layer, wherein the third dielectric layer is deposited on the dielectric liner layer.
In some embodiments of the method, the second interlayer dielectric layer comprises SiO 2 And the third dielectric layer comprises La 2 O 3 、Al 2 O 3 、AlON、ZrO 2 、HfO 2 、Si 3 N 4 、ZnO、ZrN、ZrAlO、TiO 2 、Ta 2 O 5 、Y 2 O 3 TaCN, siOCN, siOC or SiCN. In some embodiments, the third dielectric layer includes a first sub-layer and a second sub-layer over the first sub-layer, wherein a top surface of the first sub-layer is below a top surface of the second etch stop layer, wherein the first sub-layer and the second sub-layer include different dielectric materials.
In some embodiments of the method, the structure further comprises an isolation structure adjacent the gate structure and the source/drain electrodes and below the first etch stop layer, wherein the first trench exposes a portion of the isolation structure. In some embodiments, the first trench exposes at least one of the source/drain electrodes.
In another exemplary aspect, the invention relates to a method comprising: a structure is provided having a semiconductor fin, an isolation structure adjacent a lower portion of the semiconductor fin, source/drain electrodes located over the semiconductor fin, a gate structure located over a channel region of the semiconductor fin, a first etch stop layer located over the source/drain electrodes, the isolation structure and the gate structure, a first inter-layer dielectric layer located over the first etch stop layer, a second etch stop layer located over the gate structure, the first etch stop layer and the first inter-layer dielectric layer, and a second inter-layer dielectric layer located over the second etch stop layer. The method further comprises the steps of: forming a first etch mask over the second interlayer dielectric layer providing a first opening; performing a first etch on at least the second interlayer dielectric layer, the second etch stop layer, and the first interlayer dielectric layer through the first opening to create a first trench; filling the first trench with one or more third dielectric layers having a different material than the second interlayer dielectric layer; forming a second etch mask, the second etch mask providing a second opening directly over the second interlayer dielectric layer and the one or more third dielectric layers; performing a second etch on at least the second interlayer dielectric layer, the second etch stop layer, the first interlayer dielectric layer, and the first etch stop layer through the second opening, thereby creating a second trench exposing some of the source/drain electrodes, wherein the second etch is adapted not to etch the one or more third dielectric layers; and forming source/drain contact plugs in the second trenches.
In an embodiment, the method further comprises: the first etch mask is removed prior to filling the first trench with the one or more third dielectric layers.
In another embodiment, filling the first trench with one or more third dielectric layers includes: depositing one or more third dielectric layers in the first trench and over the second interlayer dielectric layer; and performing a Chemical Mechanical Planarization (CMP) process on the one or more third dielectric layers.
In some embodiments, one or more third dielectric layers are in direct contact with the first etch stop layer. In some embodiments, the one or more third dielectric layers are in direct contact with the isolation structure.
In yet another exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: a gate structure; source/drain electrodes adjacent to the gate structure; a first etch stop layer over the source/drain electrodes and the gate structure; a first interlayer dielectric layer over the first etch stop layer; a second etch stop layer over the gate structure, the first etch stop layer and the first interlayer dielectric layer; a second interlayer dielectric layer over the second etch stop layer; a first dielectric structure disposed between adjacent gate structures from a top view and extending vertically from a top surface of the second interlayer dielectric layer to a point within or below the first interlayer dielectric layer; and source/drain contacts extending through the first and second interlayer dielectric layers and the first and second etch stop layers and bonded on some of the source/drain electrodes.
In some embodiments, the semiconductor structure further comprises: a third interlayer dielectric layer over the second interlayer dielectric layer, the first dielectric structure and the source/drain contacts; and a metal via in the third interlayer dielectric layer and bonded on the source/drain contact. In a further embodiment, at least one of the metal vias is disposed directly above one of the first dielectric structures.
In some embodiments, the semiconductor structure further comprises: an isolation structure adjacent to the gate structure and the source/drain electrodes and below the first etch stop layer, wherein one of the first dielectric structures is in direct contact with the isolation structure. In some embodiments, one of the first dielectric structures is in direct contact with one of the source/drain electrodes.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing a structure having a gate structure, source/drain electrodes adjacent to the gate structure, a first etch stop layer over the source/drain electrodes and the gate structure, a first interlayer dielectric layer over the first etch stop layer, a second etch stop layer over the gate structure, the first etch stop layer and the first interlayer dielectric layer, and a second interlayer dielectric layer over the second etch stop layer;
forming a first etch mask providing a first opening over the second interlayer dielectric layer;
performing a first etch on the second interlayer dielectric layer, the second etch stop layer, and the first interlayer dielectric layer through the first opening, thereby forming a first trench;
depositing a third dielectric layer in the first trench, wherein the third dielectric layer has a different material than the second interlayer dielectric layer;
forming a second etch mask, the second etch mask providing a second opening exposing portions of the second interlayer dielectric layer and the third dielectric layer;
performing a second etch on the second interlayer dielectric layer, the second etch stop layer, the first interlayer dielectric layer, and the first etch stop layer through the second opening, thereby forming a second trench, wherein the second trench exposes some of the source/drain electrodes, wherein the third dielectric layer resists the second etch; and
A metal layer is deposited in the second trench.
2. The method of claim 1, further comprising:
the second etch mask is removed prior to depositing the metal layer.
3. The method of claim 1, further comprising:
forming a third interlayer dielectric layer over the second interlayer dielectric layer, the third dielectric layer, and the metal layer;
etching the third interlayer dielectric layer to form a via hole exposing the metal layer; and
and forming a metal through hole in the through hole.
4. The method of claim 3, wherein at least one of the metal vias is disposed directly above the third dielectric layer.
5. The method of claim 1, wherein the first etch also etches the first etch stop layer.
6. The method of claim 1, further comprising:
a dielectric liner layer is formed on a surface of the first trench prior to depositing the third dielectric layer, wherein the third dielectric layer is deposited on the dielectric liner layer.
7. The method of claim 1, wherein the second interlayer dielectric layer comprises SiO 2 And the third dielectric layer comprises La 2 O 3 、Al 2 O 3 、AlON、ZrO 2 、HfO 2 、Si 3 N 4 、ZnO、ZrN、ZrAlO、TiO 2 、Ta 2 O 5 、Y 2 O 3 TaCN, siOCN, siOC or SiCN.
8. The method of claim 1, wherein the third dielectric layer comprises a first sub-layer and a second sub-layer over the first sub-layer, wherein a top surface of the first sub-layer is below a top surface of the second etch stop layer, wherein the first sub-layer and the second sub-layer comprise different dielectric materials.
9. A method of forming a semiconductor structure, comprising:
providing a structure having a semiconductor fin, an isolation structure adjacent a lower portion of the semiconductor fin, source/drain electrodes over the semiconductor fin, a gate structure over a channel region of the semiconductor fin, a first etch stop layer over the source/drain electrodes, the isolation structure and the gate structure, a first interlayer dielectric layer over the first etch stop layer, a second etch stop layer over the gate structure, the first etch stop layer and the first interlayer dielectric layer, and a second interlayer dielectric layer over the second etch stop layer;
forming a first etch mask providing a first opening over the second interlayer dielectric layer;
performing a first etch on at least the second interlayer dielectric layer, the second etch stop layer, and the first interlayer dielectric layer through the first opening, thereby creating a first trench;
Filling the first trench with one or more third dielectric layers having a different material than the second interlayer dielectric layer;
forming a second etch mask that provides a second opening directly over the second interlayer dielectric layer and the one or more third dielectric layers;
performing a second etch through the second opening on at least the second interlayer dielectric layer, the second etch stop layer, the first interlayer dielectric layer, and the first etch stop layer, thereby creating a second trench exposing some of the source/drain electrodes, wherein the second etch is adjusted not to etch the one or more third dielectric layers; and
source/drain contact plugs are formed in the second trenches.
10. A semiconductor structure, comprising:
a gate structure;
source/drain electrodes adjacent to the gate structure;
a first etch stop layer over the source/drain electrodes and the gate structure;
a first interlayer dielectric layer over the first etch stop layer;
a second etch stop layer over the gate structure, the first etch stop layer, and the first interlayer dielectric layer;
A second interlayer dielectric layer over the second etch stop layer;
a first dielectric structure disposed between adjacent ones of the gate structures from a top view and extending vertically from a top surface of the second interlayer dielectric layer to a point within or below the first interlayer dielectric layer; and
source/drain contacts extend through the first and second interlayer dielectric layers and the first and second etch stop layers and are bonded on some of the source/drain electrodes.
CN202310472801.7A 2022-06-28 2023-04-27 Semiconductor structure and forming method thereof Pending CN116936467A (en)

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