CN116935790A

CN116935790A - OLED circuit, OLED display panel, display screen and electronic equipment

Info

Publication number: CN116935790A
Application number: CN202210360040.1A
Authority: CN
Inventors: 孙建明
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2022-04-07
Filing date: 2022-04-07
Publication date: 2023-10-24
Also published as: WO2023193489A1

Abstract

The application discloses an OLED circuit, an OLED display panel, a display screen and electronic equipment, and relates to the technical field of display. In the OLED circuit, an N-th line scanning synchronous circuit is electrically connected with an M-th line environment photon pixel circuit, and the N-th line scanning synchronous circuit is used for providing a first control signal for the M-th line environment photon pixel circuit; the N-th row enabling synchronous circuit is electrically connected with the M-th row environment photon pixel circuit and is used for providing a third control signal for the M-th row environment photon pixel circuit; the M-th row of environment photon pixel circuit is used for resetting under the control of the first control signal, and is also used for collecting environment light under the control of the third control signal when the N-1 row of OLED sub-pixel circuit, the N row of OLED sub-pixel circuit and the N+1 row of OLED sub-pixel circuit do not emit light, and generating a first-level environment light signal. Therefore, the OLED sub-pixel can adapt to high refresh rate, and can collect ambient light in a non-luminous stage of the OLED sub-pixel, so that the detection accuracy is improved.

Description

OLED circuit, OLED display panel, display screen and electronic equipment

Technical Field

The application relates to the technical field of display, in particular to an OLED circuit, an OLED display panel, a display screen and electronic equipment.

Background

In the prior art, the display brightness of a display screen in an electronic device can be manually adjusted by manipulation of a user. In addition, an ambient light sensor can be arranged in the electronic equipment to sense the intensity of ambient light, so that the electronic equipment can adaptively adjust the display brightness of the display screen according to the intensity of ambient light.

With the further development of the full screen, the hole digging scheme is no longer applicable, so that the related technical scheme places the ambient light sensor below the display screen, and detection realized based on the mode of setting under the screen is inaccurate, and is not applicable to high refresh frequency. Therefore, a new scheme is needed that can improve detection accuracy and accommodate high refresh frequencies.

Disclosure of Invention

The application provides an OLED circuit, an OLED display panel, a display screen and electronic equipment, which not only can adapt to high refresh rate, but also can collect ambient light when the OLED sub-pixel circuits in the same row and two adjacent rows do not emit light, and the detection accuracy is improved.

In order to achieve the above purpose, the application adopts the following technical scheme:

in a first aspect, an ambient photon pixel circuit is provided, disposed in an OLED display panel, the ambient photon pixel circuit comprising: the device comprises an ambient light resetting sub-circuit, a photoelectric conversion sub-circuit and a switch control sub-circuit, wherein the ambient light resetting sub-circuit, the photoelectric conversion sub-circuit and the switch control sub-circuit are electrically connected with a first node;

The ambient light resetting sub-circuit is further electrically connected with a first control end and a resetting control end, and is used for inputting the voltage of the resetting control end to the first node under the control of the voltage from the first control end;

the photoelectric conversion sub-circuit is also electrically connected with the grounding terminal, and is used for converting ambient light into voltage and providing the voltage to the first node;

the switch control sub-circuit is further electrically connected with a third control end and a primary ambient light output end, and is used for outputting the voltage at the first node as the primary ambient light signal by the primary ambient light output end under the control of the third control end in a non-light-emitting stage of the OLED sub-pixel circuit.

Alternatively, the ambient light reset circuit may input the voltage of the reset control terminal to the first node under the control of the voltage from the first control terminal when the OLED sub-pixel circuits in the same row are in the light emitting stage, so as to implement the reset.

Optionally, the switch control sub-circuit may output, by the primary ambient light output terminal, the voltage at the first node as the primary ambient light signal under the control of the third control terminal when the OLED sub-pixel circuits in the same row, the OLED sub-pixel circuits in the previous row, and the OLED sub-pixel circuits in the next row are all in the non-light emitting stage.

The embodiment of the application provides an environment photon pixel circuit, wherein a first control end controls an environment light resetting sub-circuit to be conducted in a light emitting stage of an OLED sub-pixel circuit, so that voltage provided by a resetting control end is input to a first node, and residual voltage is eliminated; then, in the non-light-emitting stage of the OLED sub-pixel circuit, the third control end can control the switch control sub-circuit to be conducted, so that the voltage obtained by collecting and converting the ambient light by the photoelectric conversion sub-circuit can be output through the first node and the switch control sub-circuit. Therefore, the influence of light intensity generated by the luminous stage of the OLED sub-pixel circuit on the environment sub-pixel circuit can be avoided by matching the working process of the environment sub-pixel circuit and the OLED sub-pixel circuit, so that the environment sub-pixel circuit only collects the environment light in the non-luminous stage of the OLED sub-pixel circuit, and the collection accuracy can be improved.

In a possible implementation manner of the first aspect, the ambient light resetting sub-circuit includes a first transistor;

the grid electrode of the first transistor is electrically connected with the first control end, the first electrode of the first transistor is electrically connected with the reset control end, and the second electrode of the first transistor is electrically connected with the first node.

In a possible implementation manner of the first aspect, the photoelectric conversion sub-circuit includes a photodiode and a first capacitor;

a first end of the photodiode is electrically connected with the first node, and a second end of the photodiode is electrically connected with the grounding end;

the first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the grounding end.

The photodiode is used for generating charges under the illumination of ambient light to form current so as to form a voltage difference between the first node and the grounding terminal and realize photoelectric conversion. The first capacitance is the capacitance generated by the photodiode itself.

In a possible implementation manner of the first aspect, the switch control sub-circuit includes a second transistor;

the grid electrode of the second transistor is electrically connected with the third control end, the first electrode of the second transistor is electrically connected with the first node, and the second electrode of the second transistor is electrically connected with the first-stage ambient light output end.

In a second aspect, an OLED circuit is provided and applied to an OLED display panel, where the OLED display panel includes a plurality of sub-pixels arranged in an array; the OLED circuit includes: a multi-line scanning synchronization circuit and a multi-line enabling synchronization circuit;

The OLED circuit further includes:

the OLED sub-pixel circuits are positioned in each sub-pixel, and the environment sub-pixel circuits are positioned in part of the sub-pixels, wherein the OLED sub-pixel circuits in the N th row and the environment sub-pixel circuits in the M th row are positioned in the same row of sub-pixels, N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1;

the N-th line scanning synchronization circuit is electrically connected with the M-th line environment photon pixel circuit and is used for providing a first control signal for the M-th line environment photon pixel circuit;

the nth row enable synchronous circuit is electrically connected with the mth row environment photon pixel circuit and is used for providing a third control signal for the mth row environment photon pixel circuit;

the M-th row of environment photon pixel circuits are used for resetting under the control of the first control signal, and are also used for collecting environment light under the control of the third control signal when the N-1-th row of OLED sub-pixel circuits, the N-th row of OLED sub-pixel circuits and the N+1-th row of OLED sub-pixel circuits do not emit light, and generating a first-level environment light signal.

The embodiment of the application provides an OLED circuit, which is provided with a scanning synchronous circuit to provide a first control signal for the current-row environment photon pixel circuit so as to reset the current-row environment photon pixel circuit. And a third control signal is provided for the current line of the environment photon pixel circuits by adding an enabling synchronous circuit so as to control the environment photon pixel circuits of the current line to collect and output the environment light when the same line and two adjacent lines of OLED sub-pixel circuits do not emit light. Therefore, the influence of light intensity generated by the luminous phase of the OLED sub-pixel circuit on the environment sub-pixel circuit can be avoided by matching the working process of the environment sub-pixel circuit and the OLED sub-pixel circuit, so that the environment sub-pixel circuit only collects the environment light in the non-luminous phase of the same row and two adjacent rows of OLED sub-pixel circuits, and the collection accuracy can be improved. In addition, the acquisition process may be applicable to high refresh rate displays.

In a possible implementation manner of the second aspect, the OLED circuit further includes: a multi-line scanning circuit and a multi-line enabling circuit;

the scanning output end of each row of scanning circuits is electrically connected with the scanning end of the OLED sub-pixel circuits in the same row, each row of scanning circuits is used for providing scanning signals for the OLED sub-pixel circuits in the same row, and the OLED sub-pixel circuits are used for receiving the voltages provided by the data lines under the control of the scanning signals provided by the scanning circuits in the same row;

the enabling output end of each row of enabling circuits is electrically connected with the enabling end of the OLED sub-pixel circuits in the same row, each row of enabling circuits is used for providing enabling signals for the OLED sub-pixel circuits in the same row, and the OLED sub-pixel circuits are used for not emitting light under the control of the enabling signals provided by the enabling circuits in the same row;

the scanning output end of the N-1 line scanning circuit is electrically connected with the scanning synchronous input end of the N line scanning synchronous circuit, the scanning synchronous output end of the N line scanning synchronous circuit is electrically connected with the first control end of the M line environment photon pixel circuit, and the N line scanning synchronous circuit is also electrically connected with the amplifying control end; the N-th line scanning synchronous circuit is used for providing the first control signal for the first control end of the M-th line environment photon pixel circuit under the common control of the scanning signal provided by the N-1-th line scanning circuit and the amplifying control signal provided by the amplifying control end;

The enable output end of the N-1 row enable circuit is electrically connected with the first enable input end of the N row enable synchronous circuit, the enable output end of the N+1 row enable circuit is electrically connected with the second enable input end of the N row enable synchronous circuit, the enable synchronous output end of the N row enable synchronous circuit is electrically connected with the third control end of the M row environment photon pixel circuit, and the N row enable synchronous circuit is used for providing the third control signal for the third control end of the M row environment photon pixel circuit under the control of the enable signal provided by the N-1 row enable circuit and the enable signal provided by the N+1 row enable circuit.

In the implementation mode, the scanning signals provided by the scanning circuit on the previous line are multiplexed by adding the scanning synchronous circuit; and then, the first control signal provided for the current row of environment photon pixel circuits is controlled together according to the first control signal and the amplification control signal provided by the amplification control terminal so as to reset the current row of environment photon pixel circuits.

In the implementation manner, the enabling synchronous circuits are additionally arranged, so that enabling signals provided by the enabling circuits in the upper row and the lower row can be multiplexed, and the enabling circuits in the upper row and the lower row can control the corresponding OLED sub-pixel circuits to be in a non-luminous stage and simultaneously control the third control signals provided for the environmental photon pixel circuits in the current row according to the two enabling signals so as to control the environmental photon pixel circuits in the current row to collect and output environmental light.

In a possible implementation manner of the second aspect, the sub-pixels include sub-pixels of F colors, and the OLED circuit further includes: f ambient light amplifying circuits and analog amplifying circuits, wherein F is an integer greater than or equal to 3;

the scanning synchronous output end of the N-M+1 line scanning synchronous circuit is electrically connected with the second control ends of the F ambient light amplifying circuits respectively, the N-M+1 line scanning synchronous circuit is used for providing a second control signal for the second control ends of the F ambient light amplifying circuits, and the F ambient light amplifying circuits are used for resetting under the common control of the second control signal and the amplifying control signals from the amplifying control ends;

the first-stage ambient light output ends of the ambient light amplifying circuits in the same-color sub-pixels are electrically connected with 1 ambient light amplifying circuit, and the ambient light amplifying circuits are used for integrating the first-stage ambient light signals acquired once or a plurality of times by the ambient light amplifying circuits in a plurality of rows of the same-color sub-pixels to generate second-stage ambient light signals;

the second-stage ambient light output ends of the F ambient light amplifying circuits are electrically connected with the analog amplifying circuit, and the F ambient light amplifying circuits are further used for providing the second-stage ambient light signals for the analog amplifying circuit under the common control of the second control signals and the amplifying control signals from the amplifying control ends, and the analog amplifying circuit is used for amplifying the second-stage ambient light signals and converting the second-stage ambient light signals into ambient light data.

In the implementation mode, the charge generated by the plurality of rows of ambient photon pixel circuits can be collected and integrated through the additional arrangement of the ambient light amplifying circuit and then output to the additional arrangement of the analog amplifying circuit to be converted into ambient light data.

The application also multiplexes the signals output by the scanning synchronization circuits of the corresponding rows of the 1 st row of the ambient light amplifying circuit, namely multiplexes the first control signals corresponding to the 1 st row of the ambient light amplifying circuit, and provides the multiplexed first control signals as the second control signals to the second control end of the ambient light amplifying circuit so as to realize the purpose of resetting the ambient light amplifying circuit. Because the signal output by the scanning synchronization circuit combines the state of the amplification control signal of the amplification control end, the ambient light amplifying circuit is not reset when the ambient light amplifying circuit outputs, namely, the analog amplifying circuit works, and the ambient photon pixel circuit is reset only when the ambient light amplifying circuit does not work.

In a possible implementation manner of the second aspect, the nth row enable synchronization circuit includes: a first inverting sub-circuit, a second inverting sub-circuit, and an enable synchronous output sub-circuit;

the first inverting sub-circuit is electrically connected with a first enabling input end and the enabling synchronous output sub-circuit, and is used for providing a first inverting signal which is inverted with the first enabling signal to the enabling synchronous output sub-circuit under the control of a first enabling signal from the first enabling input end, wherein the first enabling signal is an enabling signal provided by an enabling output end of the N-1 th enabling circuit;

the second inverting sub-circuit is electrically connected with the second enabling input end and the enabling synchronous output sub-circuit, and is used for providing a second inverting signal which is inverted with the second enabling signal to the enabling synchronous output sub-circuit under the control of a second enabling signal from the second enabling input end, wherein the second enabling signal is an enabling signal provided by an enabling output end of the (n+1) th enabling circuit;

the enabling synchronous output sub-circuit is further electrically connected with a first power supply voltage end, a second power supply voltage end and an enabling synchronous output end, and the enabling synchronous output sub-circuit is used for transmitting the first voltage provided by the first power supply voltage end or the second voltage provided by the second power supply voltage end to the enabling synchronous output end for output under the control of the first inverted signal and the second inverted signal.

In this implementation manner, the first enable signal and the second enable signal are received and inverted by the first inverting sub-circuit and the second inverting sub-circuit in the enable synchronization circuit, and then the output of the enable synchronization output sub-circuit is controlled by the inverted two signals, so that the purpose of controlling one output signal by the two enable signals can be achieved.

In a possible implementation manner of the second aspect, the first inverting sub-circuit includes a third transistor and a fourth transistor;

a gate of the third transistor is electrically connected to the first enable input terminal, a first pole of the third transistor is electrically connected to a third power supply voltage terminal, and a second pole of the third transistor is electrically connected to a second node;

the grid electrode and the second electrode of the fourth transistor are electrically connected with a fourth power supply voltage end, and the first electrode of the fourth transistor is electrically connected with the second node.

In a possible implementation manner of the second aspect, the second inverting sub-circuit includes a fifth transistor and a sixth transistor;

the grid electrode of the fifth transistor is electrically connected with the second enabling input end, the first electrode of the fifth transistor is electrically connected with the third power supply voltage end, and the second electrode of the fifth transistor is electrically connected with the third node;

The grid electrode and the second electrode of the sixth transistor are electrically connected with a fourth power supply voltage end, and the first electrode of the sixth transistor is electrically connected with the third node.

In a possible implementation manner of the second aspect, the enabling synchronous output sub-circuit includes a seventh transistor, an eighth transistor, and a ninth transistor;

the grid electrode of the seventh transistor is electrically connected with the second node, the first electrode of the seventh transistor is electrically connected with the second electrode of the eighth transistor, and the second electrode of the seventh transistor is electrically connected with the fourth power supply voltage end;

a grid electrode of the eighth transistor is electrically connected with the third node, and a first electrode of the eighth transistor is electrically connected with the enabling synchronous output end;

the grid electrode of the ninth transistor is electrically connected with the fourth power supply voltage end, the first electrode of the ninth transistor is electrically connected with the third power supply voltage end, and the second electrode of the ninth transistor is electrically connected with the enabling synchronous output end.

In a possible implementation manner of the second aspect, the nth row scanning synchronization circuit includes: the scanning synchronous inverting sub-circuit and the scanning synchronous output sub-circuit are electrically connected;

The scanning synchronous inverting sub-circuit is further electrically connected with the amplifying control end, a third power supply voltage end and a fourth power supply voltage end, and is used for providing a third inverting signal which is in phase opposition with the amplifying control signal to the scanning synchronous output sub-circuit under the control of the amplifying control signal from the amplifying control end, wherein the third inverting signal is a third voltage provided by the third power supply voltage end or a fourth voltage provided by the fourth power supply voltage end;

the scan synchronous output sub-circuit is further electrically connected with a scan synchronous input end, the third power supply voltage end, the fourth power supply voltage end and a scan synchronous output end, and the scan synchronous output sub-circuit is used for transmitting the third voltage provided by the third power supply voltage end or the fourth voltage provided by the fourth power supply voltage end to the scan synchronous output end for output under the control of the third inversion signal and the scan signal from the scan synchronous input end.

In the implementation manner, the amplification control signal provided by the amplification control end is inverted through the scanning synchronous inverting sub-circuit, and then the output of the scanning synchronous output sub-circuit is controlled by the voltage after the inversion and the scanning signal provided by the scanning synchronous input end, so that the first control signal can be controlled jointly according to the scanning signal of the previous line and the amplification control signal provided by the amplification control end, and the aim of resetting the ambient photon pixel circuit when the ambient light amplifying circuit does not work and not resetting the ambient photon pixel circuit when the ambient light amplifying circuit works is fulfilled.

In a possible implementation manner of the second aspect, the scan synchronous inverting sub-circuit includes: a twelfth transistor and a thirteenth transistor;

a gate of the thirteenth transistor is electrically connected to the amplification control signal terminal, a first pole of the thirteenth transistor is electrically connected to the third power supply voltage terminal, and a second pole of the thirteenth transistor is electrically connected to the first pole of the twelfth transistor;

the grid electrode and the second electrode of the twelfth transistor are electrically connected with the fourth power supply voltage end.

In a possible implementation manner of the second aspect, the scan synchronous output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fourteenth transistor;

the grid electrode of the eleventh transistor is electrically connected with the fourth power supply voltage end, the first electrode of the eleventh transistor is electrically connected with the third power supply voltage end, and the second electrode of the eleventh transistor is electrically connected with the scanning synchronous output end;

the grid electrode of the tenth transistor is electrically connected with the scanning synchronous input end, the first electrode of the tenth transistor is electrically connected with the scanning synchronous output end, and the second electrode of the tenth transistor is electrically connected with the first electrode of the fourteenth transistor;

The gate of the fourteenth transistor is electrically connected to the second pole of the thirteenth transistor, and the second pole of the fourteenth transistor is electrically connected to the fourth power supply voltage terminal.

In a possible implementation manner of the second aspect, the ambient light amplifying circuit includes: an amplifying reset sub-circuit, an integrating sub-circuit and an amplifying output sub-circuit;

the amplifying reset sub-circuit is electrically connected with the second control end, the reset control end and the integration sub-circuit, and is used for providing the voltage from the reset control end for the integration sub-circuit under the control of the second control signal from the second control end so as to reset the integration sub-circuit;

the integration sub-circuit is also electrically connected with a first-stage ambient light output end of an ambient light sub-pixel circuit in the plurality of rows of same-color sub-pixels, a first power supply voltage end and the amplifying output sub-circuit, and is used for integrating a first-stage ambient light signal output by the first-stage ambient light output end to generate a second-stage ambient light signal;

the amplifying output sub-circuit is electrically connected with the amplifying control end and the secondary environment light output end, and the amplifying output sub-circuit is used for transmitting the secondary environment light signal to the secondary environment light output end for output under the control of the amplifying control signal from the amplifying control end.

Because each row corresponds the same color ambient photon pixel circuit and connects the same detection signal line, a plurality of detection signal lines that the same corresponding ambient photon pixel circuit of multirow connects are connected with the first-level ambient light output end electricity of the ambient light amplifying circuit, from this, when the ambient photon pixel circuit carries out the short integration by row, can be in proper order with the signal that each row was gathered by row transmission to this ambient light amplifying circuit and accumulate, just so be equivalent to carrying out long integration to the ambient light of this kind of color, thereby can improve the accuracy of detection.

In the implementation manner, the amplifying reset sub-circuit in the ambient light amplifying circuit resets the integrating sub-circuit under the control of the second control end, then the integrating sub-circuit carries out long integration on the signals provided by the first-stage ambient light output ends of the multi-row ambient light pixel circuit, and then the amplifying output sub-circuit outputs the signals under the control of the voltage of the amplifying control end, so that the detection accuracy can be improved.

In a possible implementation manner of the second aspect, the amplifying and resetting sub-circuit includes: a fifteenth transistor;

the grid electrode of the fifteenth transistor is electrically connected with the second control end, the first electrode of the fifteenth transistor is electrically connected with the integration sub-circuit, and the second electrode of the fifteenth transistor is electrically connected with the reset control end.

In a possible implementation manner of the second aspect, the integrating sub-circuit includes: a third capacitor and a sixteenth transistor;

a first end of the third capacitor is electrically connected with the first power supply voltage end and a first pole of the sixteenth transistor, a second end of the third capacitor is electrically connected with a first-level ambient light output end of an ambient photon pixel circuit in a plurality of rows of same-color sub-pixels, and a first pole of the fifteenth transistor is electrically connected with a grid electrode of the sixteenth transistor;

a second pole of the sixteenth transistor is electrically connected to the amplified output subcircuit.

In a possible implementation manner of the second aspect, the amplifying output sub-circuit includes: a seventeenth transistor;

the grid electrode of the seventeenth transistor is electrically connected with the amplification control end, the first electrode of the seventeenth transistor is electrically connected with the second electrode of the sixteenth transistor, and the second electrode of the seventeenth transistor is electrically connected with the second-level ambient light output end.

In a third aspect, there is provided a driving method of an ambient photon pixel circuit as in the first aspect or any possible implementation manner of the first aspect, the driving method comprising:

In a reset stage, the ambient light reset sub-circuit inputs the voltage provided by the reset control terminal into the first node under the control of the voltage from the first control terminal;

in the output stage, the switch control sub-circuit outputs the voltage generated by the photoelectric conversion sub-circuit by the primary ambient light output terminal under the control of the voltage from the third control terminal.

The embodiment of the application provides a driving method of an environment photon pixel circuit, wherein in the light emitting stage of an OLED sub-pixel circuit, a first control end controls an environment light resetting sub-circuit to be conducted, so that voltage provided by a resetting control end is input to a first node Q1, and residual voltage is eliminated; then, in the non-light-emitting stage of the OLED sub-pixel circuit, the third control end can control the switch control sub-circuit to be conducted, so that the voltage obtained by collecting and converting the ambient light by the photoelectric conversion sub-circuit can be output through the first node and the switch control sub-circuit. Therefore, the influence of light intensity generated by the luminous stage of the OLED sub-pixel circuit on the environment sub-pixel circuit can be avoided by matching the working process of the environment sub-pixel circuit and the OLED sub-pixel circuit, so that the environment sub-pixel circuit only collects the environment light in the non-luminous stage of the OLED sub-pixel circuit, and the collection accuracy can be improved.

In a fourth aspect, there is provided a driving method of an OLED circuit as in the second aspect or any possible implementation manner of the second aspect, the driving method of the OLED circuit including:

in the ith stage, the nth row scanning synchronous circuit provides a first control signal for the mth row environment photon pixel circuit, and the mth row environment photon pixel circuit resets under the control of the first control signal;

in the (i+2) -th stage, the Nth row enable synchronous circuit provides a third control signal for the Mth row of environment photon pixel circuits, and when the Nth row-1 OLED sub-pixel circuit, the Nth row OLED sub-pixel circuit and the (n+1) -th row OLED sub-pixel circuit do not emit light, the Mth row of environment photon pixel circuits collect environment light under the control of the third control signal and generate a first-stage environment light signal.

The embodiment of the application provides a driving method of an OLED circuit, which is characterized in that a scanning synchronous circuit is additionally arranged to provide a first control signal for the current-row environment photon pixel circuit so as to reset the current-row environment photon pixel circuit. And a third control signal is provided for the current line of the environment photon pixel circuits by adding an enabling synchronous circuit so as to control the environment photon pixel circuits of the current line to collect and output the environment light when the same line and two adjacent lines of OLED sub-pixel circuits do not emit light. Therefore, the influence of light intensity generated by the luminous phase of the OLED sub-pixel circuit on the environment sub-pixel circuit can be avoided by matching the working process of the environment sub-pixel circuit and the OLED sub-pixel circuit, so that the environment sub-pixel circuit only collects the environment light in the non-luminous phase of the same row and two adjacent rows of OLED sub-pixel circuits, and the collection accuracy can be improved. In addition, the acquisition process may be applicable to high refresh rate displays.

In a possible implementation manner of the fourth aspect, in the ith stage, the nth row scanning synchronization circuit provides a first control signal to the mth row ambient photon pixel circuit, including:

in the ith stage, an enabling output end of the N-1 row enabling circuit provides an enabling signal for an enabling end of the N-1 row OLED sub-pixel circuit, and the N-1 row OLED sub-pixel circuit does not emit light under the control of the enabling signal provided by the N-1 row enabling circuit; i is an integer greater than or equal to 1;

the scanning output end of the N-1 line scanning circuit provides a scanning signal to the scanning synchronous input end of the N line scanning synchronous circuit, and the N line scanning synchronous circuit provides the first control signal to the first control end of the M line environment photon pixel circuit under the control of the scanning signal provided by the N-1 line scanning circuit and the amplifying control signal provided by the amplifying control end;

in the i+2 th stage, the nth row enable synchronizing circuit provides a third control signal to the mth row ambient photon pixel circuit, including:

in the (i+2) -th stage, the enabling output end of the (n+1) -th row enable circuit provides an enabling signal for the enabling end of the (n+1) -th row OLED sub-pixel circuit, and the (n+1) -th row OLED sub-pixel circuit does not emit light under the control of the enabling signal provided by the (n+1) -th row enable circuit;

The enable output end of the (N-1) -th enable circuit provides an enable signal to the first enable input end of the (N) -th enable synchronous circuit, the enable output end of the (N+1) -th enable circuit provides an enable signal to the second enable input end of the (N) -th enable synchronous circuit, and the (N) -th enable synchronous circuit provides the third control signal to the third control end of the (M) -th environment photon pixel circuit under the control of the enable signal provided by the (N-1) -th enable circuit and the enable signal provided by the (N+1) -th enable circuit;

the driving method of the OLED circuit further comprises the following steps:

in the (i+1) -th stage, the enable output end of the Nth row of enable circuit provides an enable signal for the enable end of the Nth row of OLED sub-pixel circuits, and the Nth row of OLED sub-pixel circuits do not emit light under the control of the enable signal provided by the Nth row of enable circuit;

the scanning output end of the Nth row scanning circuit provides scanning signals for the scanning end of the Nth row OLED sub-pixel circuit, and the Nth row OLED sub-pixel circuit receives the voltage provided by the data signal line.

It will be appreciated that stage i+1 follows stage i, and precedes stage i+2.

In the implementation manner, the driving method of the OLED circuit provided by the application multiplexes the scanning signals provided by the scanning circuit of the last row through the scanning synchronous circuit; and then, the first control signal provided for the current row of environment photon pixel circuits is controlled together according to the first control signal and the amplification control signal provided by the amplification control terminal so as to reset the current row of environment photon pixel circuits.

In this implementation manner, the driving method of the OLED circuit provided by the present application further multiplexes the enable signals provided by the two adjacent upper and lower rows of enable circuits through the enable synchronization circuit, so that the two adjacent upper and lower rows of enable circuits can control the third control signal provided to the present row of ambient photon pixel circuits together according to the two enable signals while controlling the respective corresponding OLED sub-pixel circuits to be in a non-light-emitting stage, so as to control the present row of ambient photon pixel circuits to collect and output ambient light.

In a possible implementation manner of the fourth aspect, the driving method of the OLED circuit further includes:

in the (i+3) th stage, an enable output end of an N-1 row enable circuit provides an enable signal for an enable end of an N-1 row OLED sub-pixel circuit, and the N-1 row OLED sub-pixel circuit emits light under the control of the enable signal provided by the N-1 row enable circuit;

The enable output end of the (N-1) -th row enable circuit provides an enable signal to the first enable input end of the (N) -th row enable synchronous circuit, the enable output end of the (N+1) -th row enable circuit provides an enable signal to the second enable input end of the (N) -th row enable synchronous circuit, the (N) -th row enable synchronous circuit provides a third control signal to the third control end of the (M) -th row environment photon pixel circuit under the control of the enable signal provided by the (N-1) -th row enable circuit and the enable signal provided by the (N+1) -th row enable circuit, and the (M) -th row environment photon pixel circuit finishes the acquisition of the environment light under the control of the third control signal.

It should be appreciated that stage i+3 follows stage i+2.

before the i-th stage, the F ambient light amplifying circuits are reset under the control of the amplifying control signals provided by the amplifying control end and the second control signals provided by the scanning synchronous output end of the N-M+1 row scanning synchronous circuit to the second control end.

In the implementation manner, the application multiplexes the signals output by the scanning synchronization circuits of the corresponding rows of the 1 st row of the ambient light amplifying circuits, namely multiplexes the first control signals corresponding to the 1 st row of the ambient light amplifying circuits, and provides the multiplexed first control signals as the second control signals to the second control end of the ambient light amplifying circuits so as to realize the purpose of resetting the ambient light amplifying circuits. Because the signal output by the scanning synchronization circuit combines the state of the amplification control signal of the amplification control end, the ambient light amplifying circuit is not reset when the ambient light amplifying circuit outputs, namely, the analog amplifying circuit works, and the ambient photon pixel circuit is reset only when the ambient light amplifying circuit does not work.

In a possible implementation manner of the fourth aspect, the driving method further includes:

in the ith stage and the (i+1) th stage, the F ambient light amplifying circuits do not work under the control of the amplifying control signals provided by the amplifying control end and the second control signals provided by the scanning synchronous output end of the N-M+1 th line scanning synchronous circuit to the second control end;

in the (i+2) -th stage, the F ambient light amplifying circuit integrates the first-stage ambient light signal output by the M-th ambient photon pixel circuit under the control of the amplifying control signal provided by the amplifying control end and the second control signal provided by the scanning synchronous output end of the N-M+1-th line scanning synchronous circuit to the second control end;

after the i+3 stage, the F ambient light amplifying circuits provide second ambient light signals generated by integrating the multi-row ambient photon pixel circuits one or more times for the analog amplifying circuits under the control that the amplifying control signals provided by the amplifying control end and the scanning synchronous output end of the N-M+1 row scanning synchronous circuit provide second control signals for the second control end.

In the implementation mode, the application also collects and integrates charges generated by the plurality of rows of ambient photon pixel circuits through the ambient light amplifying circuit, and then outputs the charges to the additionally arranged analog amplifying circuit to be converted into ambient light data.

In a fifth aspect, there is provided an OLED display panel including: a substrate such as an OLED circuit as described in the first aspect or any possible implementation of the first aspect above.

The OLED subpixel circuit of the OLED circuit includes: a light emitting element;

the ambient photon pixel circuit in the OLED circuit is disposed between the substrate base and the light emitting element.

It should be understood that the ambient light sensor provided by the present application may be an ambient photon pixel circuit, or may include other circuits or elements besides the ambient photon pixel circuit, which is not limited in any way by the embodiments of the present application.

The application provides an OLED display panel, because the environment photon pixel circuit is integrated in the OLED display panel, the environment photon pixel circuit is not influenced by the light transmittance of a display screen when the external environment light intensity is collected, and therefore, the detection precision of the environment light can be improved.

In a possible implementation manner of the fifth aspect, the OLED subpixel circuit in the OLED display panel further includes: the OLED sub-pixel driving circuit is used for driving the light-emitting element to emit light;

Wherein the OLED sub-pixel driving circuit and the ambient photon pixel circuit are arranged on the same layer.

In the implementation mode, the process steps can be reduced through the arrangement of the same layer, and the preparation efficiency is improved.

In a possible implementation manner of the fifth aspect, the photodiode in the ambient photon pixel circuit includes: a first electrode, a photoelectric material layer and a second electrode which are stacked;

wherein the first electrode is positioned at one side close to the substrate base plate and parallel to the substrate base plate.

In a possible implementation manner of the fifth aspect, the second transistor in the ambient photon pixel circuit is electrically connected to the first electrode and is used for transmitting a voltage on the first electrode.

In a sixth aspect, there is provided a display screen comprising an OLED display panel as described in the first aspect or any possible implementation of the first aspect above.

In a seventh aspect, an electronic device is provided, which comprises a display screen according to the sixth aspect.

The embodiment of the application provides an OLED circuit, an OLED display panel, a display screen and electronic equipment, wherein the ambient light sensor is integrated in the display screen by changing the setting position of the ambient light sensor, so that the interference of the transmittance of the display screen can be reduced when the ambient light sensor collects the external ambient light intensity; in addition, the ambient photon pixel circuit included in the ambient light sensor can be matched with the OLED sub-pixel circuit, and the ambient photon pixel circuit is subjected to photoelectric conversion only when the OLED sub-pixel circuit which is positioned in the same row or the same row and adjacent rows with the ambient photon pixel circuit is in a non-luminous stage, so that the influence of pixel luminescence of a display screen on ambient light collected by the ambient light sensor can be reduced, and the purposes of accurately detecting the external ambient light intensity and being suitable for electronic equipment with high refresh frequency can be achieved.

Drawings

Fig. 1 is a schematic diagram of an application scenario provided in an embodiment of the present application;

fig. 2 is a schematic top view of an electronic device according to an embodiment of the present application;

fig. 3 is a schematic layout diagram of sub-pixels in a second display area according to an embodiment of the present application;

FIG. 4 is a schematic cross-sectional view of the second display area of FIG. 3 along the direction AA';

FIG. 5 is another cross-sectional view of the second display area of FIG. 3 along the direction AA';

fig. 6 is a schematic diagram of arrangement of subpixels in a first display area according to an embodiment of the present application;

FIG. 7 is a schematic cross-sectional view of the first display area of FIG. 6 along the BB' direction;

FIG. 8 is another cross-sectional schematic view of the first display area shown in FIG. 6 along the BB' direction;

fig. 9 is a schematic structural diagram of an OLED circuit according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of an OLED subpixel circuit according to an embodiment of the present application;

FIG. 11 is a schematic diagram of an ambient photon pixel circuit according to an embodiment of the present application;

FIG. 12 is a schematic diagram of another embodiment of an ambient photon pixel circuit;

FIG. 13 is a timing diagram of driving an ambient photon pixel circuit according to an embodiment of the present application;

FIG. 14 is a schematic diagram of an architecture of an ambient photon pixel circuit and an OLED sub-pixel circuit included in an OLED circuit in a first display area according to an embodiment of the present application;

FIG. 15 is a schematic diagram of an architecture of an ambient light sub-pixel circuit, an OLED sub-pixel circuit, and a driving circuit included in an OLED circuit in a first display area according to an embodiment of the present application;

FIG. 16 is a schematic diagram of an enabling circuit according to an embodiment of the present application;

FIG. 17 is a schematic diagram of a configuration of an enable synchronization circuit according to an embodiment of the present application;

FIG. 18 is a schematic diagram of another synchronization enabling circuit according to an embodiment of the present application;

FIG. 19 is a schematic diagram of a connection structure between an enable circuit and an enable synchronization circuit according to an embodiment of the present application;

FIG. 20 is a schematic diagram of a scan circuit according to an embodiment of the present application;

fig. 21 is a schematic structural diagram of an ambient light amplifying circuit according to an embodiment of the present application;

FIG. 22 is a schematic diagram of another ambient light amplifying circuit according to an embodiment of the present application;

fig. 23 is a schematic diagram of a scan synchronization circuit according to an embodiment of the present application;

FIG. 24 is a schematic diagram of another scan synchronization circuit according to an embodiment of the present application;

Fig. 25 is a schematic diagram of a connection structure between a scan circuit and a scan synchronization circuit according to an embodiment of the present application;

fig. 26 is a driving timing diagram corresponding to the OLED circuit shown in fig. 15.

Reference numerals:

1-a display area; 11-a first display area, 12-a second display area; 2-pixels; 3-subpixels; 4-a first zone; 5-a second zone; 10-a substrate base; a 20-OLED element; 30-a color filter layer; 31-a red filter unit; a 32-green filter unit; a 33-blue filter unit; a 60-drive transistor; 71-anode; 72-an organic material functional layer; 721-hole injection layer; 722-a hole transport layer; 723-a layer of luminescent material; 724-an electron transport layer; 725-electron injection layer; 73-cathode; BM-black matrix; 80-packaging layer; 90-planarizing the layer; 91-a first planarization layer; 92-a second planarization layer; 100-an electronic device; 110-a display screen; a 111-OLED display panel; 120-an ambient light sensor; 121-a photodiode; 1211-a first electrode; 1212-a second electrode; 1213-a layer of photovoltaic material; a 200-OLED circuit; 210-OLED subpixel circuits; an L-light emitting element; 220-an ambient photon pixel circuit; 221-an ambient light reset sub-circuit; 222-a photoelectric conversion sub-circuit; 223-a switch control sub-circuit; 230-enable (Emit) circuitry; 240-enable (Emit) synchronization circuitry; 241-a first inverting subcircuit; 242-a second inverting subcircuit; 243-enable synchronous output subcircuit; a 250-Scan (Scan) circuit; 260-Scan (Scan) synchronization circuitry; 261-scanning a synchronous inverter circuit; 262-scanning a synchronous output sub-circuit; 270-an ambient light amplifying circuit; 271-amplifying reset sub-circuit; 272-an integrating sub-circuit; 273-amplifying the output sub-circuit; 280-an analog amplifying circuit; vdata-data voltage terminal; VDD-a first supply voltage terminal; VSS-a second power supply voltage terminal; VGH-third supply voltage terminal; VGL-fourth supply voltage terminal; s1 (N) -Nth row first control end; s2 (N) -Nth row second control end; s3 (N) -Nth row third control end; e1-an amplifying control end; vref—reset control terminal; scanN-nth line scan end; an EmitN-Nth row enable terminal; out 1-the first-order ambient light output; d1-a photodiode; q1-a first node; q2-a second node; q3-a third node; in 2-secondary ambient light input; out 2-secondary ambient light output; in 3-three stage ambient light input; out 3-three stage ambient light output; emIn 1-a first enable input; emIn 2-a second enable input; an EOut-enable output; emOut-enabled synchronization output; SOut-scan output; scIn-scan sync input; scOut-scanning synchronization output terminal; t21-first transistor; t22-a second transistor; t41-a third transistor; t42-fourth transistor; t43-fifth transistor; t44-sixth transistor; t45-seventh transistor; t46-eighth transistor; t47-ninth transistor; t61-tenth transistor; t62-eleventh transistor; t63-twelfth transistor; t64-thirteenth transistor; t65-fourteenth transistor; t71-fifteenth transistor; t72-sixteenth transistor; t73-seventeenth transistor; c1-a first capacitance; c2-a second capacitance; and C3-a third capacitor.

Detailed Description

The technical scheme of the application will be described below with reference to the accompanying drawings.

In the description of the embodiments of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B; "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, in the description of the embodiments of the present application, "plurality" means two or more than two.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

First, some terms in the embodiments of the present application are explained for easy understanding by those skilled in the art.

1. Black matrix (black matrix, BM)

In order to ensure the filtering effect of the color filter layer, a black opaque shading layer is coated between the filter units included in the color filter layer to shade light, so that cross color is avoided.

2. Color filter (color filter, CF)

The color filter layer is an optical filter for expressing color, which can precisely select the light wave of the small range wave band to be passed, and reflect other wave bands which are not wanted to be passed. The color filter layer provided by the embodiment of the application is used for filtering white light into light rays with different colors.

The foregoing is a simplified description of the terminology involved in the embodiments of the present application, and is not described in detail below.

Fig. 1 illustrates an application scenario to which an embodiment of the present application is applicable.

As shown in fig. 1, taking an electronic device as an example of a mobile phone, in the night scene, the street lamp emits intense light to illuminate nearby very bright, while a surrounding area without lamplight is very dark, and when a user walks from a dark place to the place under the street lamp, the light of the surrounding environment changes from weak to strong, so that the light changes greatly.

During this walk, the user is playing a game using the cell phone. Because the light change of the surrounding environment is very strong, if the mobile phone keeps a fixed display brightness all the time, the mobile phone can be clearly displayed in a dark area, and the user can watch the mobile phone more comfortably; under the street lamp, the display brightness is too large relative to the brightness difference of the street lamp, so that the display is unclear, and the watching experience of a user is influenced.

Aiming at the problems, in the prior art, an ambient light sensor is additionally arranged in the electronic equipment to sense the intensity of ambient light, so that the electronic equipment can adaptively adjust the brightness of the display screen according to the intensity of the ambient light. For example, the display brightness may be turned up when the ambient light is strong, and turned down when the ambient light is weak. Therefore, the effect of reducing the power consumption of the product while meeting the demands of users can be achieved. Therefore, the ambient light sensor is widely applied to electronic devices such as mobile phones, notebooks, tablet computers and the like.

Currently, electronic devices integrated with ambient light sensors are often provided with a through hole or a recess for placing the ambient light sensor. With further development of the full screen, the hole digging scheme is no longer applicable, and thus, the related art scheme places the ambient light sensor under the display screen. Based on the under-screen setting mode, one ambient light detection method can be called an under-screen matting scheme, and the other ambient light detection method can be called an under-screen short integration scheme.

The under-screen image matting scheme is to use an ambient light sensor to detect the external ambient light intensity of the screen and the luminous intensity of the pixels in the display screen at the same time, and then subtract the luminous intensity of the pixels in the display screen through a software algorithm, so that the external ambient light intensity can be obtained. However, this approach is limited to the detection of the intensity of the light emitted by the pixels in the display screen. When the detection of the luminous intensity of the pixels in the display screen is inaccurate, the detection result of the external environment light intensity is directly affected.

The under-screen short integration scheme refers to that when the display screen is refreshed under the control of an enabling signal, a plurality of rows of pixels in the display screen are closed and are refreshed in a rolling way, and by utilizing the principle, the ambient light sensor can detect the external ambient light intensity when a plurality of rows of pixels corresponding to the upper part of the physical position of the ambient light sensor are in a closed state. Although this scheme is not limited to the effect of the luminous intensity of all the pixels in the display screen compared with the previous scheme, in order to improve the visual enjoyment of the user, the refresh rate of the existing display screen is higher and higher, and in the case of a high refresh frequency, the rows of pixels in the display screen corresponding to the upper part of the ambient light sensor cannot be all in the off state, so that the pixels in the luminous state at the part corresponding to the upper part of the ambient light sensor at the high refresh frequency will interfere with the pixels in the non-luminous state, and further interfere with the detection, thereby affecting the detection accuracy of the external ambient light intensity. That is, the "short integration scheme under screen" also has limitations and is not applicable to electronic devices with high refresh frequencies.

For example, when the ambient light sensor detects the external ambient light intensity, the pixels above the ambient light sensor are required to be all in the off state in order to avoid interference caused by the light emission of the pixels above the ambient light sensor. For example, an ambient light sensor typically has a width of 4mm, and a corresponding number of rows of pixels 4mm wide above the ambient light sensor are required to be in an off state. However, under the high refresh frequency, the width of the pixels which do not emit light is far less than 4mm, for example, the pixels may be only 2mm or 3mm, and other pixels beyond the range of 2mm or 3mm emit light, so that the purpose that all the pixels corresponding to the upper part of the ambient light sensor are in the closed state cannot be realized, and further the accurate detection of the external ambient light intensity cannot be realized.

Since the sensitivity of the ambient light sensor is determined by the size of the sensitive area of the ambient light sensor, if the ambient light sensor with smaller width is selected to adapt to the high refresh frequency, the device requirements of the ambient light sensor are higher, and on the other hand, the signal collected by the ambient light sensor will be easily disturbed in the transmission process, so that the sensitivity of the ambient light sensor is affected, and the detection accuracy is further affected.

In summary, the above-mentioned "under-screen matting scheme" and "under-screen short integration scheme" have respective corresponding defects, and therefore, a new technical scheme capable of improving detection accuracy and adapting to high refresh frequency is required.

In view of the above, the embodiment of the application provides an OLED circuit, an OLED display panel, a display screen and an electronic device, in which the ambient light sensor is integrated in the display screen by changing the setting position of the ambient light sensor, so that the ambient light sensor can reduce the interference of the transmittance of the display screen when collecting the external ambient light intensity; in addition, the ambient photon pixel circuit included in the ambient light sensor can be matched with the OLED sub-pixel circuit, and the ambient photon pixel circuit is subjected to photoelectric conversion only when the OLED sub-pixel circuit which is positioned in the same row or the same row and adjacent rows with the ambient photon pixel circuit is in a non-luminous stage, so that the influence of pixel luminescence of a display screen on ambient light collected by the ambient light sensor can be reduced, and the purposes of accurately detecting the external ambient light intensity and being suitable for electronic equipment with high refresh frequency can be achieved.

It should be noted that, the ambient light sensor provided by the embodiment of the present application may be an ambient photon pixel circuit, or the ambient light sensor provided by the embodiment of the present application may include other circuits or elements besides the ambient photon pixel circuit, which is not limited in any way by the embodiment of the present application.

The following describes related devices and circuits provided in the embodiments of the present application in detail with reference to the accompanying drawings.

Referring to fig. 2, fig. 2 shows a schematic top view of an electronic device 100 to which an embodiment of the present application is applied.

It should be understood that the type of the electronic device 100 is not specifically limited in the embodiments of the present application, and in some embodiments, the electronic device 100 may be an IOT (internet of things ) device such as a smart phone, a wearable device (e.g., a smart bracelet, a smart watch, an earphone, etc.), a tablet computer, a laptop (laptop), a handheld computer, a notebook computer, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a cellular phone, a personal digital assistant (personal digital assistant, PDA), an augmented reality (Augmented reality, AR), a Virtual Reality (VR) device, or a television, a large screen, a printer, a projector, etc.

As shown in fig. 2, taking the electronic device 100 as an example of a mobile phone, the electronic device 100 includes a display 110.

The display screen 110 may be used to display images or video, the display screen 110 including a display panel. The display panel may employ an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a micro OLED (Micro OLED), and the like. In some embodiments, the electronic device 100 may include 1 or N display screens 110, N being a positive integer greater than 1. The electronic device 100 includes 1 display screen 110, and the display screen 110 includes an OLED display panel 111.

Wherein the OLED display panel 111 includes an ambient light sensor 120. The ambient light sensor 120 is used to sense ambient light level. The electronic device 100 may adaptively adjust the brightness of the display screen 110 based on the perceived ambient light level. The ambient light sensor 120 may be used to automatically adjust white balance when taking a photograph. When the electronic device 100 further includes a proximity light sensor, the ambient light sensor 120 may also cooperate with the proximity light sensor to detect whether the electronic device 100 is in a pocket to prevent false touches.

It should be understood that, in the embodiment of the present application, since the ambient light sensor 120 is integrated in the OLED display panel 111, the ambient light sensor 120 is not affected by the light transmittance of the display screen 110 when collecting the external ambient light intensity, so that the detection accuracy of the ambient light can be improved.

As shown in fig. 2, the ambient light sensor 120 may be set at a partial position in the display area 1 of the OLED display panel 111 from a top view. The display area 1 refers to an area of the OLED display panel 111 for displaying images or videos. For example, the ambient light sensor 120 corresponds to a rectangular shape in plan view, which is located at a partial position in the display area 1 of the OLED display panel 111. Of course, the ambient light sensor 120 may be set in the entire display area 1 of the OLED display panel 111, that is, the top-view size of the ambient light sensor 120 is the same as the size of the display area 1 of the OLED display panel 111.

The shape, size and setting position of the ambient light sensor 120 in the plane view can be set and modified as required, and only the sensitivity is required, which is not limited in the embodiment of the present application.

If the size of the ambient light sensor 120 is small, in order to avoid the ambient light sensor 120 being touched and blocked by the hand when the user uses the electronic device 100, the ambient light sensor 120 may be set at a position where the user's hand is not easily touched and blocked. Taking fig. 2 as an example, the ambient light sensor 120 may be set at a position above the OLED display panel 111. Here, the display area 1 including the ambient light sensor 120 may be referred to as a first display area 11, the remaining display areas 1 may be referred to as a second display area 12, and structures inside display panels corresponding to the first display area 11 and the second display area 12 may be different.

Based on the above, the electronic device 100 may further include a processor, an external memory interface, an internal memory, a universal serial bus interface, a charge management module, a power management module, a battery, and the like.

The above-described structure does not constitute a specific limitation on the electronic apparatus 100. In other embodiments of the application, electronic device 100 may include more or fewer components than those shown above, or electronic device 100 may include a combination of some of the components shown above, or electronic device 100 may include sub-components of some of the components shown above. The components shown above may be implemented in hardware, software, or a combination of software and hardware.

Referring to fig. 3 to 5, fig. 3 is a schematic layout view of the sub-pixels 3 in the second display area 12 according to the embodiment of the present application, fig. 4 is a schematic cross-sectional view of the second display area 12 along the AA 'direction shown in fig. 3, and fig. 5 is another schematic cross-sectional view of the second display area 12 along the AA' direction shown in fig. 3.

Alternatively, as one implementation, as shown in fig. 3, each pixel 2 in the OLED display panel 111 may include three sub-pixels 3, for example, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, respectively. The red subpixel R is used to emit red light, the green subpixel G is used to emit green light, and the blue subpixel B is used to emit blue light.

The first direction x is assumed to be a row direction, the second direction y is assumed to be a column direction, and the first direction x and the second direction y are perpendicular to each other.

The subpixels 3 in the OLED display panel 111 may be arranged in a stripe manner. For example, in the first direction x, the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B are sequentially arranged, and the sub-pixels 3 in the second direction y are all of the same color.

Alternatively, as an achievable manner, as shown in fig. 4, the OLED display panel 111 may include a substrate base 10, and an OLED element 20 disposed on one side of the substrate base 10, and the OLED display panel 111 further includes a color filter layer 30 disposed on the light emitting side of the OLED element 20 in the thickness direction.

Wherein each sub-pixel 3 corresponds to one OLED element 20, the plurality of OLED elements 20 may be used to emit red light, green light and blue light, respectively, or the OLED elements 20 may be all used to emit white light, and the color filter layer 30 is used to filter the white light into light of different colors.

For example, the color filter layer 30 includes a red filter unit 31, a green filter unit 32, and a blue filter unit 33, the red filter unit 31 may filter white light into red, the green filter unit 32 may filter white light into green, and the blue filter unit 33 may filter white light into blue, whereby filter units of different colors are laid in different sub-pixels 3, and a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B may be formed. Alternatively, the red-emitting OLED element 20 corresponds to the red filter unit 31, the green-emitting OLED element 20 corresponds to the green filter unit 32, and the blue-emitting OLED element 20 corresponds to the blue filter unit 33 to form the red, green, and blue sub-pixels R, G, and B.

It should be understood that the red filter unit 31, the green filter unit 32, and the blue filter unit 33 are bandpass filters.

Alternatively, as one possible way, as shown in fig. 5, the OLED element 20 includes an anode 71 and a cathode 73 that are stacked, and an organic material functional layer 72 that is disposed between the anode 71 and the cathode 73. The organic material functional layer 72 may include a light emitting material layer 723, and the organic material functional layer 72 may further include a hole transport layer (hole transport layer, HTL) 722 disposed between the anode 71 and the light emitting material layer 723, and an electron transport layer (electron transport layer, ETL) 724 disposed between the cathode 73 and the light emitting material layer 723.

In order to be able to improve efficiency of electron and hole injection into the light emitting material layer 723, the organic material functional layer 72 may further include a hole injection layer (hole injection Layer, HIL) 721 disposed between the anode 71 and the hole transport layer 722, and an electron injection layer (electron inject Layer, EIL) 725 disposed between the cathode 73 and the electron transport layer 724.

Wherein the anode 71 is located between the cathode 73 and the substrate 10, the cathode 73 comprised by different sub-pixels 3 may be laid out in whole layers.

The light emission principle of the OLED element 20 is as follows: by applying a voltage to the anode 71 and the cathode 73 through a circuit in which the anode 71 and the cathode 73 are connected, holes are injected by the anode 71, electrons are injected by the cathode 73, and the formed electrons and holes meet at the light emitting material layer 723 to generate excitons, thereby exciting the light emitting material layer 723 to emit light.

The material of the anode 71 may be selected from, for example, according to the light emission type of the OLED element 20: silver (Ag), indium Tin Oxide (ITO) or nickel-chromium alloy (Ni: cr alloy), etc.; the material of the light emitting material layer 723 may be tris (8-hydroxyquinoline) aluminum (Alq 3) or the like, and white light is emitted by a three-primary color multilayer film light emitting combination. The materials of the cathode 73 may include: cuPc (copper phthalocyanine) or magnesium silver alloy (Mg: ag alloy), and the like.

As shown in fig. 5, at a side of the OLED element 20 near the substrate 10, the OLED display panel 111 further includes an OLED subpixel driving circuit, which may include 1 or more driving transistors (thin film transistor, TFT) 60, the driving transistors 60 for providing a voltage to the anode 71.

Optionally, as shown in fig. 5, in order to avoid cross-color between the sub-pixels 3, a black matrix is also made between two adjacent filter units. In addition, an encapsulation layer 80 may be further disposed between the cathode 73 and the color filter layer 30 for encapsulation, and a planarization layer 90 may be further disposed between the driving transistor 60 and the anode 71 for planarization.

It should be noted that, as shown in fig. 3 to 5, each pixel 2 in the OLED display panel 111 includes three sub-pixels 3, which is only an example, and each pixel 2 may also include four sub-pixels 3, for example, a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W, respectively. At this time, the white sub-pixel W does not include a filter unit, and the white sub-pixel W can directly use the white light generated by the OLED element 20 for emitting.

It should be understood that the number, the corresponding color, and the arrangement of the sub-pixels 3 included in each pixel 2 in the OLED display panel 111 may be specifically set according to needs, for example, in terms of arrangement, the sub-pixels 3 in the OLED display panel 111 may also be arranged in a delta manner, which is not limited in any way by the embodiment of the present application.

On the basis of the above, in the pixels produced with the current industrial process capability, the area actually used for light emission only occupies a small part (for example, about 5%) of the whole pixel, and the rest of the area is not utilized, so in the first display area 11 of the OLED display panel 111 provided in the embodiment of the present application, the ambient light sensor 120 may be integrated in the area where the sub-pixel 3 does not emit light, and the area not blocked by the anode 71 is utilized to detect the intensity of the external ambient light.

Referring to fig. 6 to 8, fig. 6 is a schematic diagram showing the arrangement of subpixels 3 in the first display area 11 according to the embodiment of the present application, fig. 7 is a schematic diagram showing a cross section of the first display area 11 shown in fig. 6 in the BB 'direction, and fig. 8 is a schematic diagram showing another cross section of the first display area 11 shown in fig. 6 in the BB' direction.

As shown in fig. 6, with respect to the second display area 12, the sub-pixel 3 in the first display area 11 has only an effective light emitting area (first area 4 as shown in fig. 6) as an actual display area corresponding to the sub-pixel 3, and an area other than the effective light emitting area in the sub-pixel 3, second area 5 as shown in fig. 6, as a setting area corresponding to the ambient light sensor 120. Fig. 6 is only an example, and the sizes of the first region 4 and the second region 5 may be divided according to an actual structure, which is not limited in any way by the embodiment of the present application.

It should be noted that, when the ambient light sensor 120 is integrated in the OLED display panel 111, the ambient light sensor 120 and the OLED element 20 may share the color filter layer 30, so, as shown in fig. 6, when each pixel 2 in the OLED display panel 111 includes a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B, the ambient light sensor 120 disposed in the second region 5 of the red sub-pixel R may collect a red channel signal when collecting ambient light, and similarly, the ambient light sensor 120 disposed in the second region 5 of the green sub-pixel G may collect a green channel signal when collecting ambient light, and the ambient light sensor 120 disposed in the second region 5 of the blue sub-pixel B may collect a blue channel signal when collecting ambient light, using the blue filter unit 33.

Further, when each pixel 2 in the OLED display panel 111 includes a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W, the ambient light sensor 120 disposed in the second region 5 of the red sub-pixel R may correspondingly collect a red channel signal using the red filter unit 31, the ambient light sensor 120 disposed in the second region 5 of the green sub-pixel G may correspondingly collect a green channel signal using the green filter unit 32, the ambient light sensor 120 disposed in the second region 5 of the blue sub-pixel B may correspondingly collect a blue channel signal using the blue filter unit 33, and the ambient light sensor 120 disposed in the second region 5 of the white sub-pixel W may correspondingly collect a white channel signal. In other words, the ambient light sensor 120 employs the same channel color as the OLED display panel 111 is for display.

Alternatively, as shown in fig. 7, the OLED display panel 111 located in the first display region 11 further includes an ambient light sensor 120 disposed between the substrate base 10 and the OLED element 20 in the thickness direction with respect to fig. 4. Other structures are otherwise the same as those described in fig. 4, and will not be described again here.

Alternatively, as shown in fig. 8, the ambient light sensor 120 may include a photodiode 121 and a second transistor T22. Among them, the photodiode 121 includes a first electrode 1211, a photoelectric material layer 1213, and a second electrode 1212, which are disposed parallel to the substrate 10 and stacked, the first electrode 1211 being located at a side close to the substrate 10. The second transistor T22 is electrically connected to the first electrode 1211 for transmitting a voltage on the first electrode 1211.

Alternatively, as shown in fig. 8, the driving transistor 60 and the second transistor T22 are provided in the same layer.

The working principle of the ambient light sensor 120 is as follows: the external ambient light irradiates the photodiode 121, and the photoelectric material layer 1213 performs photoelectric conversion, so that voltages are generated on the first electrode 1211 and the second electrode 1212, and the second transistor T22 and other circuits transmit and collect the voltages of the first electrode 1211 and the second electrode 1212.

It should be noted that, when the ambient light is incident on the ambient light sensor 120, the ambient light is incident on the second electrode 1212 and then is incident on the first electrode 1211, so that the light intensity incident on the first electrode 1211 is not affected, the second electrode should be made of a transparent material, and in order to enhance the detection of the ambient light and avoid the light intensity from affecting the device under the first electrode 1211, the first electrode 1211 should be made of an opaque and high-reflectivity metal, for example, the material of the first electrode 1211 may be molybdenum (Mo). The material of the photovoltaic material layer 1213 may be amorphous silicon (a-Si), cadmium antimonide (CdTe), copper indium gallium tin (CIGS), an organic photovoltaic material, or other photovoltaic-like materials. The photovoltaic material selected is required to not cause too much photovoltaic performance degradation below a certain temperature threshold (e.g., below 250 ℃) after device formation.

The second electrode 1212 is a metal oxide transparent conductive film, and for example, a material of the second electrode 1212 may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In addition, the photodiode 121 may be packaged by a chemical vapor deposition (chemical vapor deposition, CVD) or physical vapor deposition (physical vapor deposition, PVD) process, or the like.

As shown in fig. 8, between the OLED subpixel driving circuit and the first electrode 1211, a first planarization layer 91 may be disposed to perform planarization, and/or, between the second electrode 1212 and the OLED element 20, a second planarization layer 92 may be disposed to perform planarization.

Note that the structure shown in fig. 8 does not constitute a specific limitation on the structure in which the ambient light sensor 120 is integrated in the OLED display panel 111. In other embodiments of the present application, the OLED display panel 111 may include more or fewer components than those shown in FIG. 8, or the electronic device 100 may include a combination of some of the components shown in FIG. 8, or the OLED display panel 111 may include sub-components of some of the components shown in FIG. 8.

Fig. 2 to 8 described above describe in detail the OLED display panel 111, the display screen 110, and the electronic device 100 integrated with the ambient light sensor 120, and the related circuits provided in the OLED display panel 111 are described in detail below.

Referring to fig. 9, fig. 9 is a schematic structural diagram of an OLED circuit 200 according to an embodiment of the present application.

On the OLED display panel 111, the display area 1 includes a second display area 12 of the non-integrated ambient light sensor 120 shown in fig. 3, and further includes a first display area 11 of the integrated ambient light sensor 120 shown in fig. 6. Of course, the OLED display panel 111 further includes a non-display area, i.e., a remaining area except the display area 1, which may be used to set related circuits to drive the circuits located in the display area 1 to realize display and ambient light detection.

As shown in fig. 9, the second display area 12 includes a plurality of sub-pixels 3 arranged in an array. The first region 4 of each sub-pixel 3 is correspondingly provided with an OLED sub-pixel circuit 210, and the second region 5 is correspondingly provided with an ambient sub-pixel circuit 220.

The second display area 12 further includes: a plurality of data signal lines, a plurality of first power voltage lines, a plurality of second power voltage lines, a plurality of scan signal lines, a plurality of enable signal lines, a plurality of control signal lines, and a plurality of detection signal output lines.

The OLED subpixel circuits 210 corresponding to the same row of subpixels 3 are electrically connected to the same scanning signal line and the same enable signal line, the ambient subpixel circuits 220 corresponding to the same row of subpixels 3 are electrically connected to the same control signal line, and the ambient subpixel circuits 220 corresponding to the same row of subpixels 3 may be electrically connected to a plurality of control signal lines. The plurality of scan signal lines are used for providing scan signals for each row of OLED subpixel circuits 210, the plurality of enable signal lines are used for providing enable signals for each row of OLED subpixels, the plurality of control signal lines are used for providing control signals for each row of ambient photon subpixel circuits 220, and the plurality of control signal lines are connected with different control signal lines of the same row of ambient photon subpixel circuits 220 and used for providing different control signals for the row of ambient photon subpixel circuits 220 so as to control the ambient photon pixel circuits 220 to be in different working phases. For example, each of the ambient light sub-pixel circuits 220 corresponding to the same row of sub-pixels 3 is electrically connected to a first control signal line, and each of the ambient light sub-pixel circuits 220 is also electrically connected to a third control signal line, where the first control signal line is used to provide a first control signal for the row of ambient light sub-pixel circuits 220, and the third control signal line is used to provide a third control signal for the row of ambient light sub-pixel circuits 220.

In addition, the ambient light sub-pixel circuits 220 corresponding to the same color in the same row are electrically connected to the same detection signal line, and the plurality of detection signal lines are used for respectively collecting and transmitting the detection signals generated by the ambient light sub-pixel circuits 220 of the same color in each row of ambient light sub-pixel circuits 220.

For example, as shown in fig. 9, the ambient photon pixel circuits 220 include ambient photon pixel circuits 220 corresponding to three primary colors (red, green, and blue), respectively, based on which all the ambient photon pixel circuits 220 corresponding to red in the same row may be electrically connected to one red detection signal line, all the ambient photon pixel circuits 220 corresponding to green may be electrically connected to one green detection signal line, all the ambient photon pixel circuits 220 corresponding to blue may be electrically connected to one blue detection signal line, the red detection signal line may collect and transmit detection signals generated by the ambient photon pixel circuits 220 corresponding to red, the green detection signal line may collect and transmit detection signals generated by the ambient photon pixel circuits 220 corresponding to blue.

Each OLED subpixel circuit 210 corresponding to the same column of subpixels 3 is electrically connected to the same data signal line, the same first power voltage signal line, and the same second power voltage signal line. The data signal lines are used for providing data signals for the corresponding columns of the OLED sub-pixel circuits 210, the plurality of first power supply voltage signals are used for providing first power supply voltages for each column of the OLED sub-pixel circuits 210, and the plurality of second power supply voltage signal lines are used for providing second power supply voltages for each column of the OLED sub-pixel circuits 210.

As shown in fig. 9, in the non-display region of the OLED display panel 111, the OLED circuit 200 further includes a Scan (Scan) circuit 250, a Scan synchronization circuit 260, an enable (Emit) circuit, and an enable synchronization circuit 240.

Wherein, the scanning circuit 250 is used for providing scanning signals for the scanning signal lines; the enable circuit 230 is used for providing an enable signal for an enable signal line; the scan circuit 250 is further configured to provide a scan signal to the scan synchronization circuit 260, where the scan synchronization circuit 260 is configured to provide a first control signal to the first control terminal S1 of the ambient photon pixel circuit 220 in the second display area 12 according to the scan signal provided by the scan circuit 250 and the amplification control signal provided by the amplification control terminal E1; the enable synchronization circuit 240 may be used to provide a third control signal to the third control terminal S3 of the ambient photon pixel circuit 220 in the second display area 12 under the control of the enable signals provided by the upper and lower row enable circuits 230, for example.

As shown in fig. 9, in the non-display region of the OLED display panel 111, the OLED circuit 200 further includes an ambient light amplifying circuit 270 and an analog amplifying circuit 280. The ambient light amplifying circuit 270 is connected to the plurality of detection signal lines, and is configured to amplify the detection signals generated by the ambient photon pixel circuits 220 in each row collected on the detection signal lines.

It should be understood that, since the color of the filters corresponding to the ambient light sub-pixel circuits 220 is different, the red detection signal lines connected to the ambient light amplifying circuit 270 (F1) may be electrically connected to the ambient light sub-pixel circuits 220 corresponding to red in each row, and the detection signals generated by the ambient light amplifying circuit 270 (F1) corresponding to red in multiple rows may be integrated and amplified; similarly, the green detection signal lines connected to the corresponding green ambient photon pixel circuits 220 in each row are electrically connected to the ambient light amplifying circuit 270 (F2), and the detection signals generated by the corresponding green ambient photon pixel circuits 220 in a plurality of rows are integrated and amplified by the ambient light amplifying circuit 270 (F2); and electrically connecting the blue detection signal lines connected to the corresponding blue ambient photon pixel circuits 220 in each row with the ambient light amplifying circuit 270 (F3), and integrating and amplifying the detection signals generated by the corresponding green ambient photon pixel circuits 220 in a plurality of rows by using the ambient light amplifying circuit 270 (F3).

On this basis, the analog amplifying circuit 280 is configured to amplify and integrate the voltages amplified by the ambient light amplifying circuit 270 (F1), the ambient light amplifying circuit 270 (F2), and the ambient light amplifying circuit 270 (F3), so that the voltages can be converted into ambient light data, thereby realizing detection of ambient light.

The following describes each part of the circuits included in the OLED circuit 200 and the corresponding operation procedure according to the embodiment of the present application.

Referring to fig. 10, fig. 10 is a schematic structural diagram of an OLED sub-pixel circuit 210 according to an embodiment of the present application. The OLED subpixel circuit 210 may be, for example, a 7T1C subpixel circuit.

As shown in fig. 10, the transistor T16 is used for controlling the voltage provided by the reset control terminal Vref to be transmitted to the gate of the transistor T13, and the transistor T17 is used for controlling the voltage provided by the reset control terminal Vref to be transmitted to the light emitting element L; the transistor T11 is used for controlling the voltage provided by the first power voltage terminal VDD to be transmitted to the first terminal of the transistor T13, the transistor T15 is used for controlling the transmission of the voltage provided by the data voltage terminal Vdata, the transistor T14 is used for controlling the on/off of the gate and the second terminal of the transistor T13, the transistor T13 is used for determining the driving current of the OLED sub-pixel circuit 210, the transistor T12 is used for transmitting the driving current from the transistor T13 to the light emitting element L, and the light emitting element L is used for emitting light in response to the driving current.

It should be understood that the light emitting element L is the OLED element 20 shown in the foregoing fig. 5 and 8, and the anode 71 and the cathode 73 connected up and down thereof. The local circuits of the OLED subpixel circuit 210 other than the light emitting element L may be referred to as the OLED subpixel driving circuit described above.

Of course, the OLED sub-pixel circuit 210 may be other sub-pixel circuits such as 2T1C and 6T1C, which is not limited in the embodiment of the present application.

It should be appreciated that, typically, the first power voltage terminal VDD electrically connected to the OLED subpixel circuit 210 is a high level terminal, and may output a constant high voltage; the second power voltage terminal VSS electrically connected to the OLED sub-pixel circuit 210 is a low level terminal, and can output a constant low voltage. The terms "high" and "low" herein merely represent the relative magnitude relationship between the voltages of the inputs. Of course, the second power supply voltage terminal VSS may also be grounded.

Referring to fig. 11, fig. 11 is a schematic structural diagram of an ambient photon pixel circuit 220 according to an embodiment of the application. Fig. 12 is a schematic diagram of another embodiment of an ambient photon pixel circuit 220.

As shown in fig. 11, the ambient photon pixel circuit 220 may include: an ambient light reset sub-circuit 221, a photoelectric conversion sub-circuit 222, and a switch control sub-circuit 223. The ambient light resetting sub-circuit 221, the photoelectric conversion sub-circuit 222, and the switching control sub-circuit 223 are all electrically connected to the first node Q1.

The ambient light reset sub-circuit 221 is further electrically connected to the first control terminal S1 and the reset control terminal Vref; the ambient light resetting sub-circuit 221 is configured to communicate the resetting control terminal Vref with the first node under the control of the voltage from the first control terminal S1, input the voltage provided by the resetting control terminal Vref to the first node Q1, and reset the voltage at the first node Q1.

The photoelectric conversion sub-circuit 222 is also electrically connected to the ground GND; the photoelectric conversion sub-circuit 222 is for converting ambient light into a voltage and supplying the voltage to the first node Q1.

The switch control sub-circuit 223 is further electrically connected to the third control terminal S3 and the primary ambient light output terminal Out 1; the switch control sub-circuit 223 is configured to connect the first node Q1 and the primary ambient light output terminal Out1 under the control of the third control terminal S3 during the non-light emitting stage of the OLED sub-pixel circuit 210, and output the voltage at the first node through the primary ambient light output terminal Out 1.

Note that, for the ambient light sub-pixel circuits 220 located in different rows, the first control signal lines connected to the first control terminal S1 are different, and the timings of the first control signals provided by the different first control signal lines are different, so the timings of the first control signals corresponding to the ambient light sub-pixel circuits 220 in different rows are different.

Similarly, for the environmental photonic pixel circuits 220 located in different rows, the third control signal lines connected to the third control terminal S3 are different, and the timings of the third control signals provided by the different third control signal lines are different, so the timings of the third control signals corresponding to the environmental photonic pixel circuits 220 in different rows are different.

In order to avoid the light-emitting interference of the OLED sub-pixel circuits 210 belonging to the same row as the ambient sub-pixel circuit 220, the third control terminal S3 may provide the third control signal during the non-light-emitting phase of the same row of OLED sub-pixel circuits 210 corresponding to the ambient sub-pixel circuit 220. On this basis, since the adjacent upper row or lower row of OLED subpixel circuits 210 also has light-emitting interference to the current row of ambient subpixel circuits 220, the third control terminal S3 corresponding to the current row of ambient subpixel circuits 220 may also be in a non-light-emitting stage for both the upper row of OLED subpixel circuits 210 and the current row of OLED subpixel circuits 210, or the current row of OLED subpixel circuits 210 and the next row of OLED subpixel circuits 210 are in a non-light-emitting stage, or the third control signal is provided when all of the upper row of OLED subpixel circuits 210, the current row of OLED subpixel circuits 210 and the next row of OLED subpixel circuits 210 are in a non-light-emitting stage.

Of course, in order to avoid the light-emitting interference of more rows of OLED sub-pixel circuits 210, when the adjacent rows of OLED sub-pixel circuits 210 are in the non-light-emitting stage, the third control terminal S3 may provide the third control signal to the current row of ambient photon pixel circuits 220, and the specific row number may be set and modified as required, which is not limited in the embodiment of the present application.

Based on the above, the embodiment of the present application provides an ambient photon pixel circuit, in a light emitting stage of an OLED sub-pixel circuit, a first control terminal controls an ambient light resetting sub-circuit to be turned on, so that a voltage provided by a resetting control terminal is input to a first node Q1, and residual voltage is eliminated; then, in the non-light-emitting stage of the OLED sub-pixel circuit, the third control terminal S3 may control the switch control sub-circuit to be turned on, so that the voltage obtained by collecting and converting the ambient light by the photoelectric conversion sub-circuit may be output through the first node and the switch control sub-circuit. Therefore, the influence of light intensity generated in the light emitting stage of the OLED sub-pixel circuit on the ambient photon pixel circuit can be avoided by matching the working processes of the ambient photon pixel circuit and the OLED sub-pixel circuit, so that the ambient photon pixel circuit only collects ambient light in the non-light emitting stage of the same row and/or adjacent multi-row OLED sub-pixel circuits, and the collection accuracy can be improved.

Alternatively, as one implementation, as shown in fig. 12, the ambient light resetting sub-circuit 221 may include a first transistor T21; the gate of the first transistor T21 is electrically connected to the first control terminal S1, the first pole of the first transistor T21 is electrically connected to the reset control terminal Vref, and the second pole of the first transistor T21 is electrically connected to the first node Q1.

In addition, the ambient light resetting sub-circuit 221 may further include a plurality of transistors connected in parallel to the first transistor T21, and the above is merely an example of the ambient light resetting sub-circuit 221, and other structures having the same functions as those of the ambient light resetting sub-circuit 221 are not described herein, but are also included in the scope of the present application.

Alternatively, as one implementation, as shown in fig. 12, the photoelectric conversion sub-circuit 222 may include a photodiode D1 and a first capacitor C1, where a first terminal of the photodiode D1 is electrically connected to the first node Q1, and a second terminal of the photodiode D1 is electrically connected to the ground terminal GND. The first end of the first capacitor C1 is electrically connected to the first node Q1, and the second end of the first capacitor C1 is electrically connected to the ground GND.

The photodiode D1 is configured to generate electric charges under the illumination of ambient light to form a current, so as to form a voltage difference between the first node Q1 and the ground GND, thereby implementing photoelectric conversion. The first capacitor C1 is a capacitor generated by the photodiode D1 itself.

It should be appreciated that when the photoelectric conversion sub-circuit 222 includes the first capacitor C1, the ambient light resetting sub-circuit 221 may cancel the residual voltage of the first terminal of the first capacitor C1 by inputting the voltage from the reset control terminal Vref to the first node Q1 under the control of the voltage from the first control terminal S1, and reset the first capacitor C1.

In addition, the photoelectric conversion sub-circuit 222 may further include a plurality of capacitors connected in parallel with the first capacitor C1, and the above is merely an example of the photoelectric conversion sub-circuit 222, and other structures having the same functions as those of the photoelectric conversion sub-circuit 222 are not described herein, but are also included in the protection scope of the present application.

Alternatively, as an implementation manner, as shown in fig. 12, the switch control sub-circuit 223 may include a second transistor T22, where a gate of the second transistor T22 is electrically connected to the third control terminal S3, a first pole of the second transistor T22 is electrically connected to the first node Q1, and a second pole of the second transistor T22 is electrically connected to the first-stage ambient light output terminal Out 1.

In addition, the switch control sub-circuit 223 may further include a plurality of transistors connected in parallel with the second transistor T22, and the above is merely an example of the switch control sub-circuit 223, and other structures having functions identical to those of the switch control sub-circuit 223 are not described herein, but should also fall within the protection scope of the present application.

In some embodiments, the first transistor T21 and the second transistor T22 are of the same type, both being N-type or P-type; alternatively, the first transistor T21 and the second transistor T22 may be different in type, where one transistor is N-type and the other transistor is P-type, which is not limited in the embodiment of the present application.

In some embodiments, the first transistor T21 and the second transistor T22 may have a first pole being a drain and a second pole being a source; alternatively, the first pole is the source and the second pole is the drain. The first transistor T21 and the second transistor T22 may be enhancement transistors or depletion transistors according to different transistor conduction manners, and may be specifically selected according to needs, which is not limited in any way in the embodiment of the present application.

Based on the above description of the ambient light sub-pixel circuit 220, the specific operation of the ambient light sub-pixel circuit 220 is described below in conjunction with fig. 13. The first transistor T21 and the second transistor T22 are P-type, for example.

Referring to fig. 13, fig. 13 is a driving timing diagram of an ambient photon pixel circuit 220 according to an embodiment of the application.

As shown in fig. 13, in the light emitting phase of the OLED sub-pixel circuit 210, the operation of the ambient sub-pixel circuit 220 corresponds to a reset phase P1; in the non-light emitting phase of the OLED sub-pixel circuit 210, the operation of the ambient sub-pixel circuit 220 corresponds to the output phase P2. The method comprises the following steps:

It should be understood that the OLED sub-pixel circuit 210 may be the OLED sub-pixel circuit 210 of the same row as the ambient sub-pixel circuit 220, or may be an adjacent row of OLED sub-pixel circuits 210, which may be specifically set as required, which is not limited in any way by the embodiment of the present application.

In the reset phase P1, the first control terminal S1 inputs a low level voltage, the third control terminal S3 inputs a high level voltage, and thus the first transistor T21 is turned on and the second transistor T22 is turned off. Because of the conduction of the first transistor T21, the voltage provided by the reset control terminal Vref may be input to the first node Q1, so as to reset the voltage on the first terminal of the photodiode D1 connected to the first node Q1, and the voltage on the first terminal of the first capacitor C1 connected to the first node Q1, thereby eliminating the influence of the residual voltage during the last acquisition.

In the output stage P2, the first control terminal S1 inputs a high level voltage, the third control terminal S3 inputs a low level voltage, and thus the first transistor T21 is turned off and the second transistor T22 is turned on. Due to the conduction of the second transistor T22, the first-stage ambient light output terminal Out1 can output the voltage generated after the photoelectric conversion of the photodiode D1.

When the OLED sub-pixel circuits 210 belonging to the same row as the ambient sub-pixel circuit 220 are in a non-light emitting stage, the ambient light is collected and converted by using the ambient sub-pixel circuit 220, and although the accuracy of some detection can be improved, the OLED sub-pixel circuits 210 of other rows still have a certain influence on each other if still emitting light, so as to avoid such influence, in the application, the interference of the light intensity emitted by the OLED sub-pixel circuits 210 of other rows on the ambient sub-pixel circuits 220 of the present row is reduced by collecting and converting by using the ambient sub-pixel circuits 220 of the present row when the OLED sub-pixel circuits 210 of the same row as the ambient sub-pixel circuit 220 and one or more adjacent rows are all in the non-light emitting stage.

Here, since the distance between the OLED sub-pixel circuits 210 of the previous and next rows and the ambient sub-pixel circuit 220 of the present row is the nearest, the influence is the greatest, so in order to improve the accuracy of detecting the ambient light, the influence of the light emission of the OLED sub-pixel circuits 210 of the previous and next rows on the ambient sub-pixel circuit 220 of the present row should be mainly considered, and thus, the present application provides an OLED circuit for reducing the influence of the light emission of the OLED sub-pixel circuits 210 of the upper and lower adjacent rows on the ambient light collection of the ambient sub-pixel circuit 220 of the present row.

Illustratively, a row of OLED sub-pixel circuits 210 is driven by a row enable signal. The OLED display panel 111 is refreshed row by row during display, i.e. several rows of pixels are in a non-light emitting phase (dark state) and move down row by row. For example, in the i-th stage of refreshing, the 6 th, 7 th, 8 th, and 9 th row OLED subpixel circuits 210 are in a non-light-emitting stage, and the 10 th, 11 th, etc. row OLED subpixel circuits 210 are in a light-emitting stage; in the i+1th phase, the 7 th, 8 th, 9 th, and 10 th row OLED subpixel circuits 210 are in a non-light-emitting phase, and the 11 th row OLED subpixel circuits 210 are also in a light-emitting phase; in the i+2 stage, the 8 th, 9 th, 10 th, and 11 th row OLED subpixel circuits 210 are in a non-light emitting stage; in the i+3 stage, the 10 th row and 11 th row OLED sub-pixel circuits 210 are in a non-light-emitting stage, and the 9 th row OLED sub-pixel circuit 210 is in a light-emitting stage. The other stages are analogized in order and are not described in detail here.

Taking the row 10 OLED sub-pixel circuit 210 as an example, the row 2 ambient light sub-pixel circuit 220 in the first display area 11 is taken as an ambient light sub-pixel circuit 220 belonging to the same row. In the i-th stage, the row 10 OLED sub-pixel circuit 210 is still in the light emitting stage, so the corresponding row 2 ambient photon pixel circuit 220 cannot be used to collect ambient light; when the i+1th stage is reached, the row 9 and the row 10 OLED sub-pixel circuits 210 are already in the non-light-emitting stage, but the row 11 OLED sub-pixel circuit 210 is still in the light-emitting stage, and at this time, the row 11 OLED sub-pixel circuit 210 also affects the row 2 ambient light sub-pixel circuit 220 corresponding to the row 10 OLED sub-pixel circuit 210, so the row 2 ambient light sub-pixel circuit 220 cannot collect ambient light.

In the i+2 stage, the 9 th row, the 10 th row and the 11 th row of the OLED sub-pixel circuits 210 are all in a non-light emitting stage, and the influence on the 2 nd row of the ambient light sub-pixel circuit 220 corresponding to the 10 th row of the OLED sub-pixel circuits 210 is minimal, so that the 2 nd row of the ambient light sub-pixel circuit 220 can be turned on for ambient light collection and conversion in the two stages. And waiting until the i+3 stage, the 9 th row of OLED sub-pixel circuits 210 is in the light emitting stage again, and when the 2 nd row of ambient light sub-pixel circuits 220 corresponding to the 10 th row of OLED sub-pixel circuits 210 are affected, the 2 nd row of ambient light sub-pixel circuits 220 are turned off.

In combination with the above example, it is determined that the condition for turning on the 2 nd row of ambient light sub-pixel circuits 220 corresponding to the 10 th row of OLED sub-pixel circuits is that the 11 th row of OLED sub-pixel circuits 210 is in a non-light emitting stage; the condition for determining that the row 2 ambient light sub-pixel circuit 220 corresponding to the row 10 OLED sub-pixel circuit 210 is turned off is that the row 9 OLED sub-pixel circuit 210 is in the light emitting stage. In other words, when the 9 th to 11 th row of OLED sub-pixel circuits 210 are in the non-light emitting stage, the 2 nd row of ambient light sub-pixel circuits 220 corresponding to the 10 th row of OLED sub-pixel circuits are turned on, otherwise turned off.

For other rows of the ambient light emitting pixel circuits, in order to eliminate the interference of the two adjacent rows of the ambient light emitting pixel circuits 220 on the self-collected ambient light, the control process corresponding to the other rows of the ambient light emitting pixel circuits 220 is similar to that described above, and will not be repeated here.

The above example will be described in detail with reference to a driving circuit diagram and a timing chart.

Referring to fig. 14 and 15, fig. 14 is a schematic diagram of an architecture of an ambient photon pixel circuit 220 and an OLED sub-pixel circuit 210 included in an OLED circuit 200 in a first display area 11 according to an embodiment of the present application. Fig. 15 is a schematic diagram of an architecture of an ambient light sub-pixel circuit 220, an OLED sub-pixel circuit 210 and a driving circuit included in an OLED circuit 200 in a first display region 11 according to an embodiment of the present application.

As shown in fig. 15, when the 10 th row OLED subpixel circuit 210 is driven, a Scan signal and an enable signal need to be supplied, so that the Scan signal can be supplied to the Scan terminal Scan10 in the 10 th row OLED subpixel circuit 210 by the 10 th row Scan circuit 250 (Scan 10 circuit) and the enable signal can be supplied to the enable terminal Emit10 in the 10 th row OLED subpixel circuit 210 by the 10 th row enable circuit 230 (Emit 10 circuit).

The specific structure of the row 10 OLED subpixel circuit 210 may be shown in fig. 10, and will not be described herein.

As shown in fig. 14 and 15, when the 2 nd row of the ambient light sub-pixel circuits 220 corresponding to the 10 th row of the OLED sub-pixel circuits 210 are driven, the 9 th row of the OLED sub-pixel circuits 210 and the 11 th row of the OLED sub-pixel circuits 210 are matched, and when both are in a non-light-emitting stage, the 2 nd row of the ambient light sub-pixel circuits 220 collect ambient light. Thus, the 9 th row enable circuit 230 (Emit 9 circuit) and the 11 th row enable circuit 230 (Emit 11 circuit) can be synchronized by the 10 th row enable synchronization circuit 240 (Emit 10 synchronization circuit).

When the enable signals provided by the 9 th row enable circuit 230 and the 11 th enable circuit 230 respectively make the 9 th row OLED sub-pixel circuit 210 and the 11 th row OLED sub-pixel circuit 210 in the non-light emitting stage, the 10 th row enable synchronous circuit 240 provides a third control signal for the third control terminal S3 (10) of the 2 nd row ambient photon pixel circuit 220, so as to control the 2 nd row ambient photon pixel circuit 220 to collect and output ambient light. When the 9 th row OLED subpixel circuit 210 and the 11 th row OLED subpixel circuit 210 are both in the non-light-emitting phase, the 10 th row OLED subpixel circuit 210 is also in the non-light-emitting phase.

It should be appreciated that the 9 th row enable circuit 230 is also configured to provide an enable signal to the enable terminal Emit9 of the 9 th row OLED sub-pixel circuit 210, and the 11 th row enable circuit 230 is also configured to provide an enable signal to the enable terminal Emit11 of the 11 th row OLED sub-pixel circuit 210.

The specific structure of the row 2 ambient light sub-pixel circuit 220 may be shown in fig. 11, and will not be described herein.

The embodiment of the application provides an OLED circuit, which is provided with an enabling synchronous circuit, so that enabling signals provided by two adjacent upper and lower rows of enabling circuits can be multiplexed, the enabling synchronous circuit can be controlled together while the two adjacent upper and lower rows of enabling circuits control the corresponding OLED sub-pixel circuits to be in a non-luminous stage, and the enabling synchronous circuit is used for controlling the ambient photon pixel circuits of the current row to collect and output ambient light.

Referring to fig. 16 and 17, fig. 16 is a schematic diagram of an enabling circuit 230 according to an embodiment of the present application, fig. 17 is a schematic diagram of an enabling synchronous circuit 240 according to an embodiment of the present application, fig. 18 is a schematic diagram of another enabling synchronous circuit 240 according to an embodiment of the present application, and fig. 19 is a schematic diagram of a connection structure between an enabling circuit and an enabling synchronous circuit according to an embodiment of the present application.

In the embodiment of the present application, the configuration of each row of the enable circuit 230 is the same, and the configuration of each row of the enable synchronous circuit 240 is the same. Of course, they may be different, and the embodiment of the present application does not limit this.

The enabling circuit 230 is a structure of the related art, and is not described herein.

The enable synchronization circuit 240 is described in detail below.

As shown in fig. 17, the enable synchronization circuit 240 includes: a first inverting sub-circuit 241, a second inverting sub-circuit 242, and an enable synchronous output sub-circuit 243.

The first inverting sub-circuit 241 is electrically connected to the first enable input terminal EmIn1 and the enable synchronous output sub-circuit 243, and the first inverting sub-circuit 241 is configured to provide a first inverting signal, which is inverted with respect to the first enabling signal, to the enable synchronous output sub-circuit 243 under the control of the first enabling signal from the first enable input terminal EmIn 1.

The second inverting sub-circuit 242 is electrically connected to the second enable input terminal EmIn2 and the enable synchronous output sub-circuit 243, and the second inverting sub-circuit 242 is configured to provide a second inverting signal, which is inverted with respect to the second enabling signal, to the enable synchronous output sub-circuit 243 under the control of the second enabling signal from the second enable input terminal EmIn 2.

The enable synchronous output sub-circuit 243 is further electrically connected to the third power supply voltage terminal VGH, the fourth power supply voltage terminal VGL, and the enable synchronous output terminal emmout, and the enable synchronous output sub-circuit 243 is configured to transmit the third voltage provided by the third power supply voltage terminal VGH or the fourth voltage provided by the fourth power supply voltage terminal VGL to the enable synchronous output terminal emmout under the control of the first inverted signal and the second inverted signal.

Here, the inversion refers to changing the high level voltage to the low level voltage or changing the low level voltage to the high level voltage.

It should be understood that, in general, the third voltage provided by the third power voltage terminal VGH is at a high level, the fourth voltage provided by the fourth power voltage terminal VGL is at a low level, for example, the third voltage is 8V, the fourth voltage is-7V, and the voltage can be specifically set according to the needs, which is not limited in the embodiment of the application.

Alternatively, as an implementation manner, the enable synchronous output sub-circuit 243 is configured to transmit the fourth voltage provided by the fourth power voltage terminal VGL to the enable synchronous output terminal EmOut when the first inverted signal and the second inverted signal are both low-level voltages, and otherwise, to output the third voltage provided by the third power voltage terminal VGH to the enable synchronous output terminal EmOut.

It should be appreciated that when the first inverted signal and the second inverted signal are both low level voltages, it is illustrated that the first enable signal and the second enable signal are both high level voltages.

As shown in fig. 19, for the 2 nd row ambient sub-pixel circuit 220 corresponding to the 10 th row OLED sub-pixel circuit 210, the first enable input terminal EmIn1 of the 10 th row enable synchronization circuit 240 may be electrically connected to the enable output terminal EOut of the 9 th row enable circuit 230 corresponding to the 9 th row OLED sub-pixel circuit 210 in a control manner that is turned on when the 9 th row and 11 th row OLED sub-pixel circuits 210 are both in a non-light emitting stage, the second enable input terminal EmIn2 of the 10 th row enable synchronization circuit 240 may be electrically connected to the enable output terminal EOut of the 10 th row enable circuit 230 corresponding to the 11 th row OLED sub-pixel circuit 210, and the enable synchronization output terminal EmOut of the 10 th row enable synchronization circuit 240 may be electrically connected to the third control terminal S3 (10) of the 2 nd row ambient sub-pixel circuit 220.

Thus, the enable signal of the 9 th row enable circuit 230 will be input as a first enable signal to the 10 th row enable synchronization circuit 240, and the enable signal of the 11 th row enable circuit 230 will be input as a second enable signal to the 10 th row enable synchronization circuit 240. In this way, the enable signals provided by the 9 th row enable circuit 230 and the 11 th row enable circuit 230 can control the working condition of the 2 nd row ambient light sub-pixel circuit 220 together through the enable synchronization circuit 240 while controlling the OLED sub-pixel circuits 210 of the respective corresponding rows, so as to achieve the purpose of avoiding the influence of the luminous intensity of the adjacent two rows of OLED sub-pixel circuits 210 when the 2 nd row ambient light sub-pixel circuit 220 collects ambient light.

Based on the above, the embodiment of the application provides an enabling synchronization circuit, which receives and inverts a first enabling signal and a second enabling signal through two sub-circuits of a first inverting sub-circuit and a second inverting sub-circuit, and then controls the output of the enabling synchronization output sub-circuit by using the two inverted signals, thereby achieving the purpose that the two enabling signals control one output signal.

Alternatively, as shown in fig. 18 and 19, the first inverting sub-circuit 241 includes a third transistor T41 and a fourth transistor T42.

A gate of the third transistor T41 is electrically connected to the first enable input terminal EmIn1, a first pole of the third transistor T41 is electrically connected to the third power supply voltage terminal VGH, and a second pole of the third transistor T41 is electrically connected to the second node Q2; the gate and the second pole of the fourth transistor T42 are electrically connected to the fourth power supply voltage terminal VGL, and the first pole of the fourth transistor T42 is electrically connected to the second node Q2.

In addition, the first inverting sub-circuit 241 may further include a plurality of transistors connected in parallel to the third transistor T41 and/or a plurality of transistors connected in parallel to the fourth transistor T42, which is merely an example of the first inverting sub-circuit 241, and other structures having the same functions as those of the first inverting sub-circuit 241 are not described herein, but should also fall within the scope of the present application.

Alternatively, as shown in fig. 18 and 19, the second inverting sub-circuit 242 includes a fifth transistor T43 and a sixth transistor T44.

The gate of the fifth transistor T43 is electrically connected to the second enable input terminal emmin 2, the first pole of the fifth transistor T43 is electrically connected to the third power supply voltage terminal VGH, and the second pole of the fifth transistor T43 is electrically connected to the third node; the gate and the second pole of the sixth transistor T44 are electrically connected to the fourth power supply voltage terminal VGL, and the first pole of the sixth transistor T44 is electrically connected to the third node.

It is understood that the fourth transistor T42 and the sixth transistor T44 function as pull-down resistors. Here, the width-to-length ratio of the third transistor T41 and the fifth transistor T43 may be ten times or more the width-to-length ratio of the fourth transistor T42 and the sixth transistor T44.

In addition, the second inverting sub-circuit 242 may further include a plurality of transistors connected in parallel to the fifth transistor T43 and/or a plurality of transistors connected in parallel to the sixth transistor T44, and the foregoing is merely illustrative of the second inverting sub-circuit 242, and other structures having the same functions as those of the second inverting sub-circuit 242 are not described herein, but should also fall within the scope of the present application.

Alternatively, as shown in fig. 18 and 19, the enable synchronous output sub-circuit 243 includes a seventh transistor T45, an eighth transistor T46, and a ninth transistor T47.

The gate of the seventh transistor T45 is electrically connected to the second node, the first pole of the seventh transistor T45 is electrically connected to the second pole of the eighth transistor T46, and the second pole of the seventh transistor T45 is electrically connected to the fourth power supply voltage terminal VGL; the gate of the eighth transistor T46 is electrically connected to the third node, and the first pole of the eighth transistor T46 is electrically connected to the enable synchronization output terminal EmOut; the gate of the ninth transistor T47 is electrically connected to the fourth power supply voltage terminal VGL, the first pole of the ninth transistor T47 is electrically connected to the third power supply voltage terminal VGH, and the second pole of the ninth transistor T47 is electrically connected to the enable synchronization output terminal EmOut.

It is to be understood that the ninth transistor T47 also functions as a pull-down resistor.

In addition, the synchronous output enabling sub-circuit 243 may further include a plurality of transistors connected in parallel to the seventh transistor T45, and/or a plurality of transistors connected in parallel to the eighth transistor T46, and/or a plurality of transistors connected in parallel to the ninth transistor T47, which are merely exemplary of the synchronous output enabling sub-circuit 243, and other structures having the same functions as the synchronous output enabling sub-circuit 243 are not described herein, but are also within the scope of the present application.

In some embodiments, the third transistor T41 to the ninth transistor T47 are of the same type, and are both N-type or P-type; alternatively, the types of the third transistor T41 to the ninth transistor T47 may be different, wherein one transistor is N-type and the other transistor is P-type, which is not limited in any way by the embodiment of the present application. For example, when the third transistor T41 to the ninth transistor T47 are P-type, in order to make the low-level voltage drop of the output smaller, the threshold voltage of the P-type transistor may be made to be around-0.5V.

In some embodiments, the third to ninth transistors T41 to T47 may have a first electrode being a drain electrode and a second electrode being a source electrode; alternatively, the first pole is the source and the second pole is the drain. The third transistor T41 to the ninth transistor T47 may be enhancement transistors or depletion transistors according to the conduction mode of the transistors, and may be specifically selected according to the need, which is not limited in any way according to the embodiment of the present application.

Based on the above description of the enable synchronization circuit 240, a specific operation procedure of the enable circuit 230 and the enable synchronization circuit 240 will be described below with reference to fig. 14, 15, 16, 18, and 19. The third transistor T41 to the ninth transistor T47 are each P-type, for example.

Referring to fig. 26, fig. 26 is a driving timing diagram of an OLED circuit 200 according to an embodiment of the application.

As shown in fig. 19 and 26, when the row 2 ambient light sub-pixel circuit 220 corresponding to the row 10 sub-pixel circuit is driven, the enable signal Emit9 output from the enable output Eout of the row 9 enable circuit 230 is received by the first enable input terminal emmin 1 of the row 10 enable synchronizing circuit 240, and the enable signal Emit11 output from the enable output Eout of the row 11 enable circuit 230 is received by the second enable input terminal emmin 2.

In the i-th and i+1-th phases, since Emit9 is a high level voltage, emit11 is a low level voltage, the 9 th row OLED subpixel circuit 210 is in a non-light emitting phase, and the 11 th row OLED subpixel circuit 210 is in a light emitting phase.

At this stage, the third transistor T41 is turned off, the fourth transistor T42 is turned on, and the low-level voltage provided from the fourth power voltage terminal VGL is transmitted to the gate of the seventh transistor T45, whereby the seventh transistor T45 is turned on; meanwhile, the fifth transistor T43 is turned on, the high-level voltage provided by the third power voltage terminal VGH is transmitted to the gate of the eighth transistor T46, so that the eighth transistor T46 is turned off, and then, since the transistor 47 is in a normally-on state, the high-level voltage provided by the third power voltage terminal VGH can be outputted from the enable synchronization output terminal EmOut and provided to the third control terminal S3 (10) of the 2 nd row of ambient light sub-pixel circuits 220, so that the 2 nd row of ambient light sub-pixel circuits 220 is turned off, and no ambient light is collected.

In the i+2-th stage, since Emit9 is a high-level voltage and Emit11 is a high-level voltage, the 9 th row OLED subpixel circuit 210 and the 11 th row OLED subpixel circuit 210 are both in a non-light-emitting stage.

At this stage, the third transistor T41 is turned off, the fourth transistor T42 is turned on, and the low-level voltage provided from the fourth power voltage terminal VGL is transmitted to the gate of the seventh transistor T45, whereby the seventh transistor T45 is turned on; meanwhile, the fifth transistor T43 is turned off, the sixth transistor T44 is turned on, and the low-level voltage provided by the fourth power voltage terminal VGL is transmitted to the gate of the eighth transistor T46, so that the eighth transistor T46 is turned on, and then, since both the transistor 45 and the eighth transistor T46 are in the on state, the low-level voltage provided by the fourth power voltage terminal VGL can be output from the enable synchronization output terminal EmOut and provided to the third control terminal S3 (10) of the 2 nd row of ambient light sub-pixel circuits 220, so that the 2 nd row of ambient light sub-pixel circuits 220 are turned on for collecting ambient light.

In the i+3-th stage, since Emit9 is a low level voltage, emit11 is a high level voltage, the 9 th row OLED subpixel circuit 210 is in a light-emitting stage, and the 11 th row OLED subpixel circuit 210 is in a non-light-emitting stage.

At this stage, the third transistor T41 is turned on, and the high-level voltage provided by the third power voltage terminal VGH is transmitted to the gate of the seventh transistor T45, whereby the seventh transistor T45 is turned off; meanwhile, the fifth transistor T43 is turned off, the sixth transistor T44 is turned on, the low-level voltage provided by the fourth power voltage terminal VGL is transmitted to the gate of the eighth transistor T46, so that the eighth transistor T46 is turned on, but the seventh transistor T45 is turned off, and the transistor 47 is in a normally-on state, whereby only the high-level voltage provided by the third power voltage terminal VGH can be outputted from the enable synchronization output terminal EmOut and provided to the third control terminal S3 (10) of the 2 nd row of ambient light sub-pixel circuits 220, thereby turning off the 2 nd row of ambient light sub-pixel circuits 220 and stopping the collection of ambient light.

The embodiment of the application provides a driving method of an enabling synchronous circuit, which is characterized in that a first enabling signal and a second enabling signal are received and inverted through a first inverting sub-circuit and a second inverting sub-circuit, and then the output of the enabling synchronous output sub-circuit is controlled by utilizing the two inverted signals, so that the aim of controlling one output signal by two enabling signals can be fulfilled.

Before driving the row 2 ambient light sub-pixel circuit 220 corresponding to the row 10 OLED sub-pixel circuit 210, the row 2 ambient light sub-pixel circuit 220 is typically reset to eliminate the residual voltage. Thus, the photodiode D1 and the capacitance in the row 2 ambient light sub-pixel circuit 220 may be reset by providing the first control signal to the first control terminal S1 (10) of the row 2 ambient light sub-pixel circuit 220 before the row 9 OLED sub-pixel circuit 210 and the row 11 OLED sub-pixel circuit 210 are both in the non-light emitting phase, i.e. before the i+2 phase, such as the i phase or the i+1 phase.

Thus, as shown in fig. 15, the first control signal may be synchronized with the scanning signal supplied from the 9 th row scanning circuit 250, and the scanning signal supplied from the 9 th row scanning circuit 250 may be supplied as the first control signal to the 2 nd row ambient light sub-pixel circuit 220 corresponding to the 10 th row OLED sub-pixel circuit 210 while the 9 th row scanning circuit 250 (Scan 9 circuit) supplies the scanning signal to the 9 th row OLED sub-pixel circuit 210, thereby controlling the 2 nd row ambient light sub-pixel circuit 220 to reset.

In addition, as shown in fig. 15, when the 2 nd row of the ambient light sub-pixel circuits 220 corresponding to the 10 th row of the OLED sub-pixel circuits 210 are driven, the ambient light amplifying circuit 270 cannot reset the 2 nd row of the ambient light sub-pixel circuits 220 when integrating and amplifying, so that the first control signal required by the 1 st row of the ambient light sub-pixel circuits 220 is also required to be synchronously controlled in combination with the amplifying control signal provided by the amplifying control terminal E1 connected to the ambient light amplifying circuit 270.

For example, in the i-th stage, when the 9 th row scanning circuit 250 supplies the scanning signal to the 9 th row OLED sub-pixel circuit 210 and the ambient light amplifying circuit 270 electrically connected to the 2 nd row ambient light sub-pixel circuit 220 does not integrate and amplify, the first control signal supplied to the first control terminal S1 (10) of the 2 nd row ambient light sub-pixel circuit 220 may be commonly controlled according to the 9 th row scanning signal and the amplifying control signal supplied from the amplifying control terminal E1 to reset the 2 nd row ambient light sub-pixel circuit 220.

The embodiment of the application provides an OLED circuit, which is characterized in that a scanning synchronous circuit is additionally arranged, scanning signals provided by a scanning circuit on the previous line are multiplexed and provided as a first control signal to a photonic pixel circuit in the environment of the current line; and then, the first control signal provided for the current line of the environment photon pixel circuits is controlled together according to the first control signal and the amplification control signal provided by the amplification control end, so that the current line of the environment photon pixel circuits are reset before the enabling synchronous circuit provides the third control signal to control the current line of the environment photon pixel circuits to collect the environment light.

In addition, the first control signal is provided together by the amplification control signal provided by the amplification control end, so that interference to the ambient light amplifying circuit can be avoided, and the aim of resetting the ambient photon pixel circuit when the ambient light amplifying circuit does not work is fulfilled.

On this basis, as shown in fig. 15, the ambient light amplifying circuit 270 also generally needs to be reset, and thus, the first control signal provided to the first control terminal S1 of the row 1 ambient light sub-pixel circuit 220 may be multiplexed and provided to the second control terminal S2 of the ambient light amplifying circuit 270 to reset the ambient light amplifying circuit 270 when it is not integrated.

Since the ambient light amplifying circuit 270 is a circuit for collecting and integrating the charges output from the plurality of rows of ambient light sub-pixel circuits 220, the ambient light amplifying circuit 270 does not need to be reset before each row of ambient light sub-pixel circuits 220 is operated, and only needs to be reset before the 1 st row of ambient light sub-pixel circuits 220 is operated, so that the first control signal provided to the first control terminal S1 of the 1 st row of ambient light sub-pixel circuits 220 can be multiplexed and provided to the second control terminal S2 of the ambient light amplifying circuit 270.

Thus, the second control terminal S2 of the ambient light amplifying circuit 270 should be connected to the Scan output terminal SOut of the Scan synchronization circuit corresponding to the 1 st row of the ambient light sub-pixel circuit 220, for example, in the example of the present application, the 1 st row of the ambient light sub-pixel circuit 220 corresponds to the 9 th row of the Scan synchronization circuit (Scan 9 synchronization circuit), and therefore, the second control terminal S2 of the ambient light amplifying circuit 270 should be connected to the Scan synchronization output terminal ScOut of the 9 th row of the Scan synchronization circuit, so that the Scan signal output by the 9 th row of the Scan synchronization circuit 260 can be used as the second control signal of the ambient light amplifying circuit 270 at the same time as the first control signal corresponding to the 1 st row of the ambient light sub-pixel circuit 220.

It should be noted that, since the charges generated by the plurality of rows of ambient light sub-pixel circuits 220 are transferred to the ambient light amplifying circuit 270 for being collected and integrated, and then output to the analog amplifying circuit 280 for being converted into ambient light data, the ambient light amplifying circuit 270 cannot be reset when the ambient light amplifying circuit 270 outputs, i.e. the analog amplifying circuit 280 operates. Therefore, when the 9 th line scan synchronization circuit provides a signal as the second control signal to trigger the ambient light amplifying circuit 270 to reset, the 9 th line scan synchronization circuit needs to be controlled by considering the state of the amplifying control signal provided by the amplifying control terminal E1.

The embodiment of the application provides an OLED circuit, which can collect and integrate charges generated by a plurality of rows of ambient photon pixel circuits by additionally arranging an ambient light amplifying circuit and then output the charges to the additionally arranged analog amplifying circuit to be converted into ambient light data.

The embodiment of the application also multiplexes the signals output by the scanning synchronization circuits of the corresponding rows of the 1 st row of the ambient light amplifying circuit, namely multiplexes the first control signals corresponding to the 1 st row of the ambient light amplifying circuit, and provides the multiplexed first control signals as the second control signals to the second control end of the ambient light amplifying circuit so as to realize the purpose of resetting the ambient light amplifying circuit. Because the signal output by the scanning synchronization circuit combines the state of the amplification control signal of the amplification control end, the ambient light amplification circuit is not reset when the ambient light amplification circuit outputs, namely, the analog amplification circuit works.

Referring to fig. 20 to 25, fig. 20 is a schematic diagram of a scanning circuit 250 according to an embodiment of the application, and fig. 21 is a schematic diagram of an ambient light amplifying circuit 270 according to an embodiment of the application; fig. 22 is a schematic diagram of another ambient light amplifying circuit 270 according to an embodiment of the present application; fig. 23 is a schematic diagram of a scan synchronization circuit 260 according to an embodiment of the present application; fig. 24 is a schematic diagram of another scan synchronization circuit 260 according to an embodiment of the present application; fig. 25 is a schematic diagram of a connection structure of a scan circuit and a scan synchronization circuit according to an embodiment of the present application.

In the embodiment of the present application, the structure of each row scanning circuit 250 is the same, and the structure of each row scanning synchronization circuit 260 is the same. Of course, they may be different, and the embodiment of the present application does not limit this.

As shown in fig. 20, the scanning circuit 250 has a structure known in the related art, and will not be described herein.

Since the output of the scan synchronization circuit 260 is affected by the amplification control signal provided by the amplification control terminal E1 connected to the ambient light amplification circuit 270, the ambient light amplification circuit 270 will be described in detail.

As shown in fig. 21 and 25, the ambient light amplifying circuit 270 includes: an amplification reset sub-circuit 271, an integration sub-circuit 272, and an amplification output sub-circuit 273.

The amplifying and resetting sub-circuit 271 is electrically connected to the second control terminal S2, the resetting control terminal Vref, and the integrating sub-circuit 272, and the amplifying and resetting sub-circuit 271 is configured to provide the voltage from the resetting control terminal Vref to the integrating sub-circuit 272 under the control of the second control signal from the second control terminal S2, and reset the integrating sub-circuit 272.

The integrating sub-circuit 272 is further electrically connected to the first-stage ambient light output terminal Out1, the first power voltage terminal VDD, and the amplifying output sub-circuit 273 of the plurality of ambient light sub-pixel circuits 220 in the plurality of sub-pixels with the same color, and the integrating sub-circuit 272 is configured to accumulate the first-stage ambient light signals output by the plurality of first-stage ambient light output terminals Out1 to generate a second-stage ambient light signal.

The amplifying output sub-circuit 273 is electrically connected to the amplifying control terminal E1 and the secondary ambient light output terminal Out2, and the amplifying output sub-circuit 273 is configured to transmit the secondary ambient light signal provided by the integrating sub-circuit 272 to the secondary ambient light output terminal Out2 for output under the control of the amplifying control signal from the amplifying control terminal E1.

The amplification control signal input from the amplification control terminal E1 may be provided by an integrated circuit (integrated circuit, IC).

It should be understood that, since each row of the ambient light amplifying circuit 270 is connected to the same detection signal line, and the plurality of rows of the ambient light amplifying circuit 270 are electrically connected to the first-stage ambient light output end of the ambient light amplifying circuit 220, when the ambient light amplifying circuit 270 performs short integration on a row-by-row basis, the signals collected by each row can be sequentially transmitted to the ambient light amplifying circuit 270 row by row for accumulation, which is equivalent to performing long integration on the ambient light of the color, thereby improving the detection accuracy.

Based on the above, the embodiment of the application provides an ambient light amplifying circuit, which resets an integrating sub-circuit under the control of a second control end through an amplifying reset sub-circuit, then performs long integration on a signal provided by a primary ambient light output end of a multi-row ambient photon pixel circuit through the integrating sub-circuit, and outputs the signal under the control of the voltage of an amplifying control end through an amplifying output sub-circuit, thereby improving the detection accuracy.

Alternatively, as shown in fig. 22 and 25, the amplification reset sub-circuit 271 includes a fifteenth transistor T71.

The gate of the fifteenth transistor T71 is electrically connected to the second control terminal S2, the first pole of the fifteenth transistor T71 is electrically connected to the integrating sub-circuit 272, and the second pole of the fifteenth transistor T71 is electrically connected to the reset control terminal Vref.

In addition, the amplifying and resetting sub-circuit 271 may further include a plurality of transistors connected in parallel with the fifteenth transistor T71, the amplifying and resetting sub-circuit 271 is merely illustrated, and other structures having the same functions as those of the amplifying and resetting sub-circuit 271 are not described herein, but are also included in the protection scope of the present application.

Alternatively, as shown in fig. 22 and 25, the integrating sub-circuit 272 includes a third capacitor C3 and a sixteenth transistor T72.

The first end of the third capacitor C3 is electrically connected to the first power voltage terminal VDD and the first pole of the sixteenth transistor T72, the second end of the third capacitor C3 is electrically connected to the first-level ambient light output terminal Out1 of the ambient photon pixel circuit 220 in the plurality of rows of the same-color sub-pixels, and the first pole of the fifteenth transistor T71 is electrically connected to the gate of the sixteenth transistor T72.

The second pole of the sixteenth transistor T72 is electrically connected to the amplifying output sub-circuit.

In addition, the integrating sub-circuit 272 may further include a plurality of capacitors connected in parallel with the third capacitor C3, and/or a plurality of transistors connected in parallel with the fifteenth transistor T71, and/or a plurality of transistors connected in parallel with the sixteenth transistor T72, which are merely illustrative of the integrating sub-circuit 272, and other structures having the same functions as those of the integrating sub-circuit 272 will not be described herein, but should also fall within the scope of the present application.

It should be appreciated that the third capacitor C3 is a storage capacitor, and may store photo-charges generated by the ambient photon pixel circuit 220. After integrating the current for a certain period of time, the potential of the second end, i.e. the lower plate, of the third capacitor C3 changes (decreases), and at this time, vgs of the sixteenth transistor T72 changes, resulting in a change of the current flowing through T72. The magnitude of the change is related to the time of the current integration. At this time, the sixteenth transistor T72 corresponds to a photocurrent for amplifying the formation of the photo-charges.

Alternatively, as shown in fig. 22 and 25, the amplification output sub-circuit 273 includes a seventeenth transistor T73.

The gate of the seventeenth transistor T73 is electrically connected to the amplification control terminal E1, the first pole of the seventeenth transistor T73 is electrically connected to the second pole of the sixteenth transistor T72, and the second pole of the seventeenth transistor T73 is electrically connected to the second-stage ambient light output terminal Out 2.

In addition, the amplifying output sub-circuit 273 may further include a plurality of transistors connected in parallel to the seventeenth transistor T73, and the above is merely an example of the amplifying output sub-circuit 273, and other structures having the same functions as those of the amplifying output sub-circuit 273 are not described herein, but are also included in the protection scope of the present application.

In some embodiments, the fifteenth transistor T71 to the seventeenth transistor T73 are of the same type, and are both N-type or P-type; alternatively, the fifteenth transistor T71 to the seventeenth transistor T73 may be different in type, in which one transistor is N-type and the other transistor is P-type, which is not limited in any way by the embodiment of the present application.

In some embodiments, the fifteenth to seventeenth transistors T71 to T73 may have a first pole being a drain and a second pole being a source; alternatively, the first pole is the source and the second pole is the drain. The fifteenth to seventeenth transistors T71 to T73 may be enhancement transistors or depletion transistors according to the conduction mode of the transistors, and may be selected as needed, which is not limited in the embodiment of the present application.

Based on the above description of the ambient light amplifying circuit 270, the operation of the ambient light amplifying circuit 270 will be described below with reference to fig. 21 and 22.

Illustratively, the fifteenth transistor T71 through the seventeenth transistor T73 are all P-type.

As shown in fig. 26, in the i-1 stage, when the amplification control signal changes from the low level voltage to the high level voltage, it is explained that the last output of the ambient light amplification circuit is finished, and at this time, a reset may be performed before the next ambient light collection.

Then, the scan signal may be multiplexed while the 9 th row scan synchronization circuit supplies the scan signal to the first control terminal S1 of the 1 st row ambient photon pixel circuit, and supplied to the second control terminal S2 to which the ambient light amplifying circuit 270 is connected, so that the low level voltage is supplied to the second control terminal S2 through the 9 th row scan synchronization circuit, the fifteenth transistor T71 is turned on, and the reset control terminal Vref resets the second terminal of the third capacitor C3, that is, resets the ambient light amplifying circuit 270.

In the i-th to i+1-th phases, the 9 th row scanning synchronization circuit continues to provide the second control terminal S2 with the high level voltage, the fifteenth transistor T71 is turned off, and the reset is ended; the amplification control terminal E1 is at a high level voltage, and the seventeenth transistor T73 is turned off and does not output.

In the i+2 stage, the 2 nd row of the ambient light sub-pixel circuits 220 corresponding to the 10 th row of the OLED sub-pixel circuits 210 are turned on to collect ambient light, so that the third capacitor C3 starts to store photo charges, and the sixteenth transistor T72 amplifies photocurrent formed by the photo charges. At this stage, the second control terminal S2 continues to provide the high level voltage, the fifteenth transistor T71 is turned off, the amplifying control terminal E1 is the high level voltage, and the seventeenth transistor T73 is turned off and does not output.

In the i+3 stage, the 9 th row OLED sub-pixel circuit 210 emits light again, and the 2 nd row ambient sub-pixel circuit 220 is turned off, at which time the third capacitor C3 is charged. In this stage, the 9 th row scan synchronization circuit continues to provide the high level voltage to the second control terminal S2, the fifteenth transistor T71 is turned off, the amplifying control terminal E1 may still be the high level voltage, and the seventeenth transistor T73 is turned off and does not output.

After the i+3 stage, for example, the amplifying control signal E1 may provide the low level voltage after all the row environment sub-pixel circuits 220 are charged, or after all the row environment sub-pixel circuits 22 are cycled for a plurality of charging cycles. At this time, since the amplification control signal E1 is supplied with a low level voltage, the seventeenth transistor T73 will be turned on, so that a long-integrated secondary ambient light signal can be output from the secondary ambient light output terminal Out 2.

It should be understood that long integration refers to integration by all row ambient photon pixel circuits 22 cumulatively or by integration by all row ambient photon pixel circuits 220 after multiple charges. At this time, the secondary ambient light signal obtained by long integration refers to a signal obtained by integrating all the row ambient light sub-pixel circuits 220, or a signal obtained by integrating all the row ambient light sub-pixel circuits 220 after a plurality of charges.

As to the number of rounds of charging of all the row environment sub-pixel circuits 220, the present application is not limited in any way, and may be set and modified as necessary.

The embodiment of the application provides a driving method of an ambient light amplifying circuit, which resets an integrating sub-circuit under the control of a second control end through an amplifying resetting sub-circuit, then accumulates and amplifies signals provided by a primary ambient light output end of a multi-row ambient photon pixel circuit through the integrating sub-circuit, and then outputs the signals under the control of the voltage of an amplifying control end through an amplifying output sub-circuit, thereby improving the detection accuracy and adapting to high refresh rate.

As shown in fig. 23, the scan synchronization circuit 260 includes: a scan sync inverting sub-circuit 261 and a scan sync output sub-circuit 262 electrically connected.

The scan synchronization inverting sub-circuit 261 is further electrically connected to the amplification control terminal E1, the third power supply voltage terminal VGH, and the fourth power supply voltage terminal VGL, and the scan synchronization inverting sub-circuit 261 is configured to provide the third inverting sub-circuit 262, which is inverted with respect to the amplification control signal, to the scan synchronization output sub-circuit 262 under the control of the amplification control signal from the amplification control terminal E1.

The third inversion signal is a third voltage provided by the third power voltage terminal VGH or a fourth voltage provided by the fourth power voltage terminal VGL.

The scan-synchronous output sub-circuit 262 is further electrically connected to the scan-synchronous input terminal ScIn, the third power supply voltage terminal VGH, the fourth power supply voltage terminal VGL, and the scan-synchronous output terminal ScOut; the scan synchronous output sub-circuit 262 is configured to transmit the third voltage provided by the third power voltage terminal VGH or the fourth voltage provided by the fourth power voltage terminal VGL to the scan synchronous output terminal ScOut under control of the third phase inversion and the scan signal from the scan synchronous input terminal ScIn.

Optionally, as an implementation manner, the scan synchronization sub-circuit is configured to provide the fourth voltage provided by the fourth power voltage terminal VGL to the scan synchronization output terminal ScOut when the voltages received by the third inversion signal and the scan synchronization input terminal ScIn are both low-level voltages, and otherwise, provide the third voltage provided by the third power voltage terminal VGH to the scan synchronization output terminal ScOut.

It should be appreciated that when the third inverted signal is a low level voltage, the amplification control signal is illustrated as a high level voltage.

Note that, for the 2 nd row of the ambient light sub-pixel circuits 220 corresponding to the 10 th row of the ambient light sub-pixel circuits, when the 2 nd row of the ambient light sub-pixel circuits is not driven and the ambient light amplifying circuit 270 is not integrated and amplified, the 2 nd row of the ambient light sub-pixel circuits 220 can be reset, so that the scan signal provided by the scan output terminal SOut of the 9 th row of the scan circuit 250 and the amplifying control terminal E1 of the ambient light amplifying circuit 270 can be multiplexed, and whether the 2 nd row of the ambient light sub-pixel circuits 220 are reset is commonly controlled by the scan signal provided by the 9 th row of the scan circuit 250 and the amplifying control signal provided by the amplifying control terminal E1.

Based on the above, the embodiment of the application provides a scan synchronization circuit, which inverts an amplification control signal provided by an amplification control terminal through a scan synchronization inverting sub-circuit, and then uses the inverted voltage and a scan signal provided by a scan synchronization input terminal to jointly control the output of the scan synchronization output sub-circuit, so that a first control signal can be jointly controlled according to a previous line of scan signal and the amplification control signal provided by the amplification control terminal, thereby realizing the purpose that when an ambient light amplifying circuit does not work, the ambient light amplifying circuit is reset, and when the ambient light amplifying circuit works, the ambient light amplifying circuit is not reset.

Alternatively, as shown in fig. 24 and 25, the scan synchronization inverting sub-circuit 261 includes: a twelfth transistor T63 and a thirteenth transistor T64.

The gate of the thirteenth transistor T64 is electrically connected to the amplification control signal terminal E1, the first pole of the thirteenth transistor T64 is electrically connected to the third power supply voltage terminal VGH, and the second pole of the thirteenth transistor T64 is electrically connected to the first pole of the twelfth transistor T63.

The gate and the second pole of the twelfth transistor T63 are electrically connected to the fourth power supply voltage terminal VGL.

In addition, the scan synchronous inverting sub-circuit 261 may further include a plurality of transistors connected in parallel with the twelfth transistor T63 and/or the thirteenth transistor T64, and the above description is merely an example of the scan synchronous inverting sub-circuit 261, and other structures having the same functions as those of the scan synchronous inverting sub-circuit 261 are not described herein, but should also fall within the scope of the present application.

Alternatively, as shown in fig. 24 and 25, the scan synchronization output sub-circuit 262 includes: a tenth transistor T61, an eleventh transistor T62, and a fourteenth transistor T65.

The gate of the eleventh transistor T62 is electrically connected to the fourth power supply voltage terminal VGL, the first pole of the eleventh transistor T62 is electrically connected to the third power supply voltage terminal VGH, and the second pole of the eleventh transistor T62 is electrically connected to the scan synchronization output terminal ScOut.

The gate of the tenth transistor T61 is electrically connected to the scan synchronization input terminal ScIn, the first pole of the tenth transistor T61 is electrically connected to the scan synchronization output terminal ScOut, and the second pole of the tenth transistor T61 is electrically connected to the first pole of the fourteenth transistor T65.

The gate of the fourteenth transistor T65 is electrically connected to the second pole of the thirteenth transistor T64, and the second pole of the fourteenth transistor T65 is electrically connected to the fourth power supply voltage terminal VGL.

In addition, the scan synchronous output sub-circuit 262 may further include a plurality of transistors connected in parallel to the tenth transistor T61, and/or a plurality of transistors connected in parallel to the eleventh transistor T62, and/or a plurality of transistors connected in parallel to the twelfth transistor T63, which are merely illustrative of the scan synchronous output sub-circuit 262, and other structures having the same functions as the scan synchronous output sub-circuit 262 will not be described herein, but should also fall within the scope of the present application.

Based on the above description of the scan synchronization circuit 260, the specific operation of the scan circuit 250 and the scan synchronization circuit 260 will be described below with reference to fig. 23 to 26. The tenth transistor T61 to the fourteenth transistor T65 are each P-type, for example.

As shown in fig. 26, the 9 th row scan signal is supplied to the 9 th row OLED sub-pixel circuit 210 by the 9 th row scan circuit 250, the 10 th row scan signal is supplied to the 10 th row OLED sub-pixel circuit 210 by the 10 th row scan circuit 250, and the 11 th row scan signal is supplied to the 11 th row OLED sub-pixel circuit 210 by the 11 th row scan circuit 250.

The 10 th line scan synchronization circuit 260 receives the 9 th line scan signal outputted from the 9 th line scan circuit 250 by using the scan synchronization input terminal ScIn, and receives the amplification control signal by using the amplification control terminal E1.

In the i-th stage, since the 9-th row scan signal is a low-level voltage, the amplification control signal is a high-level voltage, the tenth transistor T61 is turned on, the thirteenth transistor T64 is turned off, and the twelfth transistor T63 is turned on, so that the fourth voltage supplied from the fourth power voltage terminal VGL, that is, the inverted voltage of the amplification control signal, can be transmitted to the gate of the fourteenth transistor T65, and the fourteenth transistor T65 is turned on, whereby the fourth voltage, that is, the low-level voltage can be outputted from the output terminal of the scan synchronization circuit 260.

In the i+1 to i+3 stages, since the 9 th row scanning signal is a high level voltage, the tenth transistor T61 is turned off, and the amplification control signal does not affect the output either at the high level voltage or at the low level voltage; and the gate of the eleventh transistor T62 is connected to the fourth power voltage terminal VGL, and the eleventh transistor T62 is turned on, so that the third voltage, i.e., the high-level voltage, of the third power voltage terminal VGH received by the first pole of the eleventh transistor T62 can be transmitted to the output terminal of the scan synchronization circuit 260 for output.

Based on the above, the embodiment of the application provides a driving method of a scan synchronization circuit, which inverts an amplification control signal provided by an amplification control terminal through a scan synchronization inverting sub-circuit, and then uses the inverted voltage and a scan signal provided by a scan synchronization input terminal to jointly control the output of the scan synchronization output sub-circuit, so that a first control signal can be jointly controlled according to a previous line of scan signal and the amplification control signal provided by the amplification control terminal, thereby realizing the purpose that when an ambient light amplifying circuit does not work, the ambient photon pixel circuit is reset, and when the ambient light amplifying circuit works, the ambient photon pixel circuit is not reset.

Based on the above description of the respective partial circuits, the driving process of the OLED circuit 200 shown in fig. 15 is described in its entirety below with reference to fig. 26.

Wherein the OLED circuit 200 includes: an OLED subpixel circuit 210, an ambient photon pixel circuit 220, a scanning circuit 250, a scanning synchronization circuit 260, an enabling circuit 230, an enabling synchronization circuit 240, an ambient light amplifying circuit 270, and an analog amplifying circuit 280.

The analog amplifying circuit 280 may include an amplifier for integrating the secondary ambient light signal output from the ambient light amplifying circuit 270, converting the integrated signal into a voltage value, and providing the voltage value to the analog-to-digital converter. The analog-to-digital converter then converts the analog voltage to a digital quantity. Of course, the analog amplifying circuit 280 may also include other devices, which are not limited in any way by the embodiment of the present application. The analog amplifying circuit 280 includes an amplifier and an analog-to-digital converter, which are not described in detail below.

Taking the row 10 OLED subpixel circuit 210 and the row 2 ambient subpixel circuit 220 as examples, in the OLED circuit 200:

the Scan output terminal SOut of the 10 th row Scan circuit 250 is electrically connected to the Scan terminal Scan10 of the 10 th row OLED sub-pixel circuit 210; the enable output Eout of the 10 th row enable circuit 230 is electrically connected to the enable terminal Emit10 of the 10 th row OLED subpixel circuit 210.

The scan output terminal SOut of the 9 th row scan circuit 250 is electrically connected to the scan synchronization input terminal scot of the 10 th row scan synchronization circuit 260, and the scan synchronization output terminal scot of the 10 th row scan synchronization circuit 260 is electrically connected to the first control terminal S1 of the 2 nd row ambient photon pixel circuit 220. The 10 th line scan synchronization circuit 260 is further electrically connected to the amplification control terminal E1.

The enable output Eout of the 9 th row enable circuit 230 is electrically connected to the first enable input EmIn1 of the 10 th row enable synchronization circuit 240, the enable output Eout of the 11 th row enable circuit 230 is electrically connected to the second enable input EmIn2 of the 10 th row enable synchronization circuit 240, and the enable synchronization output EmOut of the 10 th row enable synchronization circuit 240 is electrically connected to the third control terminal S3 of the 2 nd row ambient photon pixel circuit 220.

The first-stage ambient light output terminal Out1 of the 2 nd row ambient light sub-pixel circuit 220 is electrically connected to the second-stage ambient light input terminal In2 of the ambient light amplifying circuit 270, the ambient light amplifying circuit 270 is further electrically connected to the amplifying control terminal E1, and the second control terminal S2 of the ambient light amplifying circuit 270 is further electrically connected to the scan synchronization output terminal ScOut of the 9 th row scan synchronization circuit 260.

The second-stage ambient light output of the ambient light amplifying circuit 270 is electrically connected to the third-stage ambient light input In3 of the analog amplifying circuit 280, and the analog amplifying circuit 280 further includes a third-stage ambient light output Out3.

Accordingly, the driving process of the OLED circuit may include:

in the i-1 stage, while resetting the 1 st row of ambient light sub-pixel circuits corresponding to the 9 th row of OLED sub-pixel circuits, the scan synchronization output port SCout of the 9 th row of scan synchronization circuit provides a low-level voltage to the second control port S2 of the ambient light amplifying circuit 270, the fifteenth transistor T71 in the ambient light amplifying circuit 270 is turned on, and the reset control port Vref provides a voltage to reset the voltage of the third capacitor C3; at this time, the amplification control terminal E1 is at a high level voltage, the seventeenth transistor T73 is turned off, the secondary ambient light output terminal Out2 is not outputted, and the analog amplifying circuit 280 is not operated.

In the i-th stage, the Scan output terminal SOut of the 10 th row Scan circuit 250 supplies the Scan terminal Scan10 of the 10 th row OLED sub-pixel circuit 210 with a high level voltage; the enable output Eout of the 10 th row enable circuit 230 supplies a low level voltage to the enable terminal Emit10 of the 10 th row OLED sub-pixel circuit 210, while the enable output Eout of the 9 th row enable circuit 230 supplies a high level voltage to the enable terminal Emit9 of the 9 th row OLED sub-pixel circuit 210, and the enable output Eout of the 11 th row enable circuit 230 supplies a low level voltage to the enable terminal Emit11 of the 11 th row OLED sub-pixel circuit 210, at which time the 9 th row OLED sub-pixel circuit 210 is in a non-light emitting stage and the 10 th and 11 th row OLED sub-pixel circuits 210 are in a light emitting stage.

The scan output terminal SOut of the 9 th row scan circuit 250 supplies the low level voltage to the scan sync input terminal ScIn of the 10 th row scan sync circuit 260, and the amplification control terminal E1 supplies the high level voltage, and at this time, the fourteenth transistor T65 and the tenth transistor T61 in the 10 th row scan sync circuit 260 are turned on, so that the low level voltage supplied from the fourth power supply voltage terminal VGL can be supplied to the first control terminal S1 (10) of the 2 nd row ambient photon pixel circuit 220.

The first control terminal S1 (10) inputs a low level voltage, the first transistor T21 in the row 2 ambient light sub-pixel circuit 220 is turned on, and the reset control terminal Vref supplies a voltage to reset the photodiode D1 and the second capacitor C2.

The enable output Eout of the 9 th row enable circuit 230 supplies the high level voltage to the first enable input EmIn1 of the 10 th row enable synchronous circuit 240, the enable output Eout of the 11 th row enable circuit 230 supplies the low level voltage to the second enable input EmIn2 of the 10 th row enable synchronous circuit 240, at this time, the seventh transistor T45 of the 10 th row enable synchronous circuit 240 is turned on, the eighth transistor T46 is turned off, and the ninth transistor T47 is turned on, and the high level voltage supplied from the third power supply voltage terminal VGH is outputted from the enable synchronous output EmOut to the third control terminal S3 of the 2 nd row ambient light sub-pixel circuit 220.

The third control terminal S3 (10) inputs a high level voltage, and the second transistor T22 in the row 2 ambient light sub-pixel circuit 220 is turned off, so that the first level ambient light output terminal Out1 of the row 2 ambient light sub-pixel circuit 220 is not outputted.

Meanwhile, the scanning synchronization output end SCout of the 9 th line scanning synchronization circuit provides a high level voltage to the second control end S2 of the ambient light amplifying circuit 270, the fifteenth transistor T71 in the ambient light amplifying circuit 270 is turned off and cannot be reset, and the primary ambient light output end Out1 of the 2 nd line ambient light sub-pixel circuit is not output, so that integration is not generated; also, because the amplification control terminal E1 is at a high level voltage, the seventeenth transistor T73 is turned off, the second-stage ambient light output terminal Out2 is not outputted, and the analog amplifying circuit 280 does not operate.

In the i+1 stage, the Scan output terminal SOut of the 10 th row Scan circuit 250 supplies the Scan terminal Scan10 of the 10 th row OLED sub-pixel circuit 210 with a low level voltage; the enable output Eout of the 10 th row enable circuit 230 supplies a high level voltage to the enable terminal Emit10 of the 10 th row OLED sub-pixel circuit 210, while the enable output Eout of the 9 th row enable circuit 230 supplies a high level voltage to the enable terminal Emit9 of the 9 th row OLED sub-pixel circuit 210, and the enable output Eout of the 11 th row enable circuit 230 supplies a low level voltage to the enable terminal Emit11 of the 11 th row OLED sub-pixel circuit 210, that is, the 9 th and 10 th row OLED sub-pixel circuits 210 are in a non-light emitting stage and the 11 th row OLED sub-pixel circuit 210 is in a light emitting stage.

The scan output terminal SOut of the 9 th row scan circuit 250 supplies the high level voltage to the scan sync input terminal ScIn of the 10 th row scan sync circuit 260, and the amplification control terminal E1 supplies the high level voltage, at this time, the fourteenth transistor T65 and the tenth transistor T61 in the 10 th row scan sync circuit 260 are turned on and the eleventh transistor T62 is turned on, whereby the high level voltage supplied from the third power supply voltage terminal VGH can be supplied to the first control terminal S1 (10) of the 2 nd row ambient sub-pixel circuit 220.

The first control terminal S1 (10) inputs a high level voltage, and the first transistor T21 in the row 2 ambient light sub-pixel circuit 220 is turned off and does not reset.

The third control terminal S3 inputs a high level voltage, and the second transistor T22 in the row 2 ambient light sub-pixel circuit 220 is turned off, so that the first level ambient light output terminal Out1 of the row 2 ambient light sub-pixel circuit 220 is not output.

In the i+2 stage, the Scan output terminal SOut of the 10 th row Scan circuit 250 supplies a high level voltage to the Scan terminal Scan10 of the 10 th row OLED subpixel circuit 210; the enable output Eout of the 10 th row enable circuit 230 supplies a high level voltage to the enable terminal Emit10 of the 10 th row OLED sub-pixel circuit 210, while the enable output Eout of the 9 th row enable circuit 230 supplies a high level voltage to the enable terminal Emit9 of the 9 th row OLED sub-pixel circuit 210, and the enable output Eout of the 11 th row enable circuit 230 supplies a high level voltage to the enable terminal Emit11 of the 11 th row OLED sub-pixel circuit 210, that is, the 9 th, 10 th and 11 th row OLED sub-pixel circuits 210 are in a non-light emitting stage.

The enable output Eout of the 9 th row enable circuit 230 supplies the high level voltage to the first enable input EmIn1 of the 10 th row enable synchronous circuit 240, the enable output Eout of the 11 th row enable circuit 230 supplies the high level voltage to the second enable input EmIn2 of the 10 th row enable synchronous circuit 240, at this time, the seventh transistor T45 of the 10 th row enable synchronous circuit 240 is turned on, the eighth transistor T46 is turned on, and the low level voltage supplied from the fourth power voltage terminal VGL is outputted from the enable synchronous output EmOut and supplied to the third control terminal S3 of the 2 nd row ambient light sub-pixel circuit 220.

The third control terminal S3 inputs a low level voltage, and the second transistor T22 in the row 2 ambient light sub-pixel circuit 220 is turned on, so that the row 2 ambient light sub-pixel circuit 220 performs photoelectric conversion, and the generated photo-charges are output from the first-stage ambient light output terminal Out 1.

Meanwhile, the scanning synchronization output end SCout of the 9 th line scanning synchronization circuit provides a high level voltage to the second control end S2 of the ambient light amplifying circuit 270, the fifteenth transistor T71 in the ambient light amplifying circuit 270 is turned off and cannot be reset, and the output of the 2 nd line ambient light amplifying circuit 270 integrates the output of the 2 nd line ambient light sub-pixel circuit because the first-level ambient light output end Out1 of the 2 nd line ambient light sub-pixel circuit has an output; also, because the amplification control terminal E1 is at a high level voltage, the seventeenth transistor T73 is turned off, the second-stage ambient light output terminal Out2 is not outputted, and the analog amplifying circuit 280 does not operate.

In the i+3 stage, the Scan output terminal SOut of the 10 th row Scan circuit 250 supplies a high level voltage to the Scan terminal Scan10 of the 10 th row OLED subpixel circuit 210; the enable output Eout of the 10 th row enable circuit 230 supplies a high level voltage to the enable terminal Emit10 of the 10 th row OLED sub-pixel circuit 210, while the enable output Eout of the 9 th row enable circuit 230 supplies a low level voltage to the enable terminal Emit9 of the 9 th row OLED sub-pixel circuit 210, and the enable output Eout of the 11 th row enable circuit 230 supplies a high level voltage to the enable terminal Emit11 of the 11 th row OLED sub-pixel circuit 210, that is, the 9 th row OLED sub-pixel circuit 210 is in a light emitting stage and the 10 th and 11 th row OLED sub-pixel circuits 210 are in a non-light emitting stage.

The scan output terminal SOut of the 9 th row scan circuit 250 supplies the high level voltage to the scan sync input terminal ScIn of the 10 th row scan sync circuit 260, and the amplification control terminal E1 supplies the low level voltage, and at this time, the fourteenth transistor T65 and the tenth transistor T61 in the 10 th row scan sync circuit 260 are turned on and the eleventh transistor T62 is turned on, whereby the high level voltage supplied from the third power supply voltage terminal VGH can be supplied to the first control terminal S1 (10) of the 2 nd row ambient sub-pixel circuit 220.

The enable output Eout of the 9 th row enable circuit 230 supplies a low level voltage to the first enable input EmIn1 of the 10 th row enable synchronous circuit 240, the enable output Eout of the 11 th row enable circuit 230 supplies a high level voltage to the second enable input EmIn2 of the 10 th row enable synchronous circuit 240, at this time, the seventh transistor T45 of the 10 th row enable synchronous circuit 240 is turned off, the eighth transistor T46 is turned on, the ninth transistor T47 is turned on, and the high level voltage supplied from the third power supply voltage terminal VGH is outputted from the enable synchronous output EmOut to the third control terminal S3 of the 2 nd row ambient light sub-pixel circuit 220.

The third control terminal S3 inputs the high level voltage, and the second transistor T22 in the row 2 ambient light sub-pixel circuit 220 is turned off, so that the photoelectric conversion of the row 2 ambient light sub-pixel circuit 220 is finished, and the first-level ambient light output terminal Out1 no longer outputs.

Meanwhile, the scan synchronization output terminal SCout of the 9 th line scan synchronization circuit supplies a high level voltage to the second control terminal S2 of the ambient light amplifying circuit 270, and the fifteenth transistor T71 in the ambient light amplifying circuit 270 is turned off; also, because the amplification control terminal E1 is at a high level voltage, the seventeenth transistor T73 is turned off, the second-stage ambient light output terminal Out2 is not outputted, and the analog amplifying circuit 280 does not operate.

It should be understood that the driving process of performing the ambient light collection by only one row of ambient light sub-pixel circuits is similar to the driving process of performing the ambient light collection by other rows of ambient light sub-pixel circuits, and will not be described herein.

After the above-mentioned phase, for example, after all the row-ambient-light-emitting-pixel circuits are charged, or after all the row-ambient-light-emitting-pixel circuits are charged for a plurality of times, the amplifying control terminal E1 provides the low-level voltage again, so that the seventeenth transistor T73 is turned on, the transistor T72 outputs the charge stored in the third capacitor C3 from the second-stage ambient-light output terminal Out2, and the second control terminal S2 continues to input the high-level voltage at this time, and the fifteenth transistor T71 in the ambient-light amplifying circuit 270 is turned off and does not reset.

Finally, the three-stage ambient light input terminal In3 of the analog amplifying circuit 280 receives the amplified charge, integrates the charge into a voltage, converts the voltage into a data amount, generates ambient light data, and outputs the ambient light data from the three-stage ambient light output terminal Out 3.

The embodiment of the application provides a driving method of an OLED circuit, which multiplexes scanning signals provided by a scanning circuit on the last line through a scanning synchronous circuit; and then, the first control signal provided for the current row of environment photon pixel circuits is controlled together according to the first control signal and the amplification control signal provided by the amplification control terminal so as to reset the current row of environment photon pixel circuits.

The enabling synchronous circuit multiplexes the enabling signals provided by the enabling circuits of the upper and lower adjacent rows, so that the enabling circuits of the upper and lower adjacent rows can control the third control signals provided for the environmental photon pixel circuits of the row according to the two enabling signals while controlling the OLED sub-pixel circuits corresponding to the enabling circuits of the upper and lower adjacent rows to be in a non-luminous stage, and the environmental photon pixel circuits of the row can be controlled to collect and output environmental light.

The charge generated by the multi-row ambient photon pixel circuit is collected and integrated through the ambient light amplifying circuit and then output to the additionally arranged analog amplifying circuit to be converted into ambient light data.

The structure of the OLED circuit 200 and the sub-circuit structure of each part included in the OLED circuit 200 according to the embodiment of the present application and the driving process of the OLED circuit 200 are described in detail with reference to the accompanying drawings, and other related devices are described below.

The embodiment of the application also provides an OLED display panel, which comprises: the substrate is an OLED circuit as described above.

An OLED subpixel circuit in an OLED circuit includes: a light emitting element; an ambient photon pixel circuit in the OLED circuit is disposed between the substrate base and the light emitting element.

It should be appreciated that since the ambient photon pixel circuit is integrated in the OLED display panel, the ambient photon pixel circuit will not be affected by the light transmittance of the display screen when the external ambient light intensity is collected, and thus, the detection accuracy of the ambient light can be improved.

Optionally, as an implementation manner, the OLED subpixel circuit in the OLED display panel further includes: and a driving circuit for driving the light emitting element to emit light.

Wherein the driving circuit and the ambient photon pixel circuit are arranged on the same layer.

It will be appreciated that the process steps may be reduced and the manufacturing efficiency increased by the co-layer arrangement.

Optionally, as one implementable way, the photodiode in the ambient photon pixel circuit comprises: a first electrode, a photoelectric material layer and a second electrode which are stacked;

wherein the first electrode is positioned at one side close to the substrate and parallel to the substrate.

Optionally, as an achievable way, a second transistor in the ambient photon pixel circuit is electrically connected to the first electrode for transmitting a voltage on the first electrode.

It should be appreciated that the voltage of the first electrode is the first order ambient light signal collected.

The embodiment of the application also provides a display screen, which comprises the OLED display panel.

The embodiment of the application also provides electronic equipment comprising the display screen.

The electronic device and the display screen provided by the embodiments of the present application are used for executing the methods provided above, so that the beneficial effects that can be achieved by the electronic device and the display screen can refer to the beneficial effects corresponding to the methods provided above, and are not described herein.

When a user plays a game by using the mobile phone provided by the embodiment of the application, as the ambient photon pixel circuit included in the ambient light sensor provided by the application can be matched with the OLED sub-pixel circuit, the ambient photon pixel circuit performs photoelectric conversion only when the OLED sub-pixel circuit which is positioned in the same row or the same row and adjacent rows with the ambient photon pixel circuit is in a non-luminous stage, so that the influence of the pixel luminescence of the display screen on the ambient light sensor to the ambient light collection can be reduced, and further, the accurate detection of the external ambient intensity can be achieved, therefore, when the user walks from a dark area to a light bright area under a street lamp, the ambient light sensor in the display screen can quickly and accurately detect the change of ambient light, and the brightness of the display screen can be adjusted in time, for example, the brightness of the display screen of the mobile phone is enhanced along with the place where the user is closest to the street lamp under the street lamp, and the enough clarity is ensured.

In addition, the ambient light detection mode is suitable for the electronic equipment with high refresh rate, so that even if a user plays a game, the ambient light can be accurately measured, the brightness of the display screen can be timely adjusted, and the visual experience of the user is met.

It should be understood that the above description is only intended to assist those skilled in the art in better understanding the embodiments of the present application, and is not intended to limit the scope of the embodiments of the present application. It will be apparent to those skilled in the art from the foregoing examples that various equivalent modifications or variations can be made, for example, certain steps may not be necessary in the various embodiments of the detection methods described above, or certain steps may be newly added, etc. Or a combination of any two or more of the above. Such modifications, variations, or combinations are also within the scope of embodiments of the present application.

It should also be understood that the foregoing description of embodiments of the present application focuses on highlighting differences between the various embodiments and that the same or similar elements not mentioned may be referred to each other and are not repeated herein for brevity.

It should be further understood that the sequence numbers of the above processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic of the processes, and should not be construed as limiting the implementation process of the embodiments of the present application.

It should be further understood that, in the embodiments of the present application, the "preset" and "predefined" may be implemented by pre-storing corresponding codes, tables, or other manners that may be used to indicate relevant information in a device (including, for example, an electronic device), and the present application is not limited to the specific implementation manner thereof.

It should also be understood that the manner, the case, the category, and the division of the embodiments in the embodiments of the present application are merely for convenience of description, should not be construed as a particular limitation, and the features in the various manners, the categories, the cases, and the embodiments may be combined without contradiction.

It is also to be understood that in the various embodiments of the application, where no special description or logic conflict exists, the terms and/or descriptions between the various embodiments are consistent and may reference each other, and features of the various embodiments may be combined to form new embodiments in accordance with their inherent logic relationships.

Finally, it should be noted that: the foregoing is merely illustrative of specific embodiments of the present application, and the scope of the present application is not limited thereto, but any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The organic light-emitting diode (OLED) circuit is characterized by being applied to an OLED display panel, wherein the OLED display panel comprises a plurality of sub-pixels which are arranged in an array; the OLED circuit includes: a multi-line scanning synchronization circuit and a multi-line enabling synchronization circuit;

the OLED circuit further includes:

2. The OLED circuit of claim 1, further comprising: a multi-line scanning circuit and a multi-line enabling circuit;

3. The OLED circuit of claim 2 wherein the subpixels comprise subpixels of F colors, the OLED circuit further comprising: f ambient light amplifying circuits and analog amplifying circuits, wherein F is an integer greater than or equal to 3;

The first-stage ambient light output ends of the ambient light sub-pixel circuits in the same color sub-pixel are electrically connected with 1 ambient light amplifying circuit, and the ambient light amplifying circuit is used for integrating the first-stage ambient light signals acquired once or for many times by the ambient light sub-pixel circuits in the same color sub-pixel to generate a second-stage ambient light signal;

4. An OLED circuit as claimed in any one of claims 1 to 3 wherein the ambient photon pixel circuit in row M comprises: the device comprises an ambient light resetting sub-circuit, a photoelectric conversion sub-circuit and a switch control sub-circuit, wherein the ambient light resetting sub-circuit, the photoelectric conversion sub-circuit and the switch control sub-circuit are electrically connected with a first node;

The ambient light resetting sub-circuit is further electrically connected with the first control end and the resetting control end, and is used for inputting the voltage of the resetting control end to the first node under the control of the voltage from the first control end;

the switch control sub-circuit is further electrically connected with the third control end and the first-stage ambient light output end, and the switch control sub-circuit is used for outputting the voltage at the first node as the first-stage ambient light signal by the first-stage ambient light output end under the control of the third control signal provided by the third control end when the N-1 row OLED sub-pixel circuit, the N row OLED sub-pixel circuit and the (n+1) row OLED sub-pixel circuit do not emit light.

5. The OLED circuit of claim 4, wherein the ambient light resetting sub-circuit includes a first transistor;

6. The OLED circuit according to claim 4 or 5, wherein the photoelectric conversion sub-circuit includes a photodiode and a first capacitance;

7. The OLED circuit according to any one of claims 4-6, wherein the switch control sub-circuit includes a second transistor;

8. The OLED circuit according to any one of claims 2 to 7, wherein the nth row enable synchronization circuit includes: a first inverting sub-circuit, a second inverting sub-circuit, and an enable synchronous output sub-circuit;

9. The OLED circuit of claim 8, wherein the first inverting subcircuit includes a third transistor and a fourth transistor;

10. The OLED circuit of claim 9, wherein the second inverting subcircuit includes a fifth transistor and a sixth transistor;

the grid electrode and the second electrode of the sixth transistor are electrically connected with the fourth power supply voltage end, and the first electrode of the sixth transistor is electrically connected with the third node.

11. The OLED circuit of claim 10, wherein the enable synchronous output sub-circuit includes a seventh transistor, an eighth transistor, and a ninth transistor;

12. The OLED circuit according to any one of claims 2 to 11, wherein the nth row scan synchronization circuit includes: the scanning synchronous inverting sub-circuit and the scanning synchronous output sub-circuit are electrically connected;

the scanning synchronous inverting sub-circuit is further electrically connected with an amplification control end, a third power supply voltage end and a fourth power supply voltage end, and is used for providing a third inverting signal which is in phase opposition with the amplification control signal to the scanning synchronous output sub-circuit under the control of the amplification control signal from the amplification control end, wherein the third inverting signal is a third voltage provided by the third power supply voltage end or a fourth voltage provided by the fourth power supply voltage end;

13. The OLED circuit of claim 12, wherein the scan-synchronized inverting sub-circuit includes: a twelfth transistor and a thirteenth transistor;

14. The OLED circuit of claim 13, wherein the scan sync output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fourteenth transistor;

15. The OLED circuit according to any one of claims 3-14, wherein the ambient light amplifying circuit comprises: an amplifying reset sub-circuit, an integrating sub-circuit and an amplifying output sub-circuit;

the amplifying reset sub-circuit is electrically connected with the second control end, the reset control end and the integrating sub-circuit, and is used for providing the voltage from the reset control end for the integrating sub-circuit under the control of the second control signal from the second control end so as to reset the integrating sub-circuit;

16. The OLED circuit of claim 15, wherein the amplification reset sub-circuit includes: a fifteenth transistor;

17. The OLED circuit of claim 16, wherein the integrating sub-circuit includes: a third capacitor and a sixteenth transistor;

a first end of the third capacitor is electrically connected with the first power supply voltage end and a first pole of the sixteenth transistor, a second end of the third capacitor is electrically connected with the first-stage ambient light output end of the ambient photon pixel circuit in the plurality of rows of the same-color sub-pixels, and a first pole of the fifteenth transistor is electrically connected with a grid electrode of the sixteenth transistor;

18. The OLED circuit of claim 17, wherein the amplified output sub-circuit includes: a seventeenth transistor;

19. An OLED display panel, wherein the OLED display panel includes: a substrate base and an OLED circuit as claimed in any one of claims 1 to 18;

20. The OLED display panel of claim 19, wherein the OLED subpixel circuits in the OLED display panel further comprise: the OLED sub-pixel driving circuit is used for driving the light-emitting element to emit light;

21. A display screen comprising an OLED display panel as claimed in claim 19 or 20.

22. An electronic device comprising the display screen of claim 21.