CN116933720A - Method and circuit compatible with different voltage chip designs packaged in same way - Google Patents
Method and circuit compatible with different voltage chip designs packaged in same way Download PDFInfo
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- CN116933720A CN116933720A CN202311196638.2A CN202311196638A CN116933720A CN 116933720 A CN116933720 A CN 116933720A CN 202311196638 A CN202311196638 A CN 202311196638A CN 116933720 A CN116933720 A CN 116933720A
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- 238000013461 design Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000012545 processing Methods 0.000 claims abstract description 13
- 239000000725 suspension Substances 0.000 claims abstract description 5
- 239000003990 capacitor Substances 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 16
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 238000012423 maintenance Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2113/00—Details relating to the application field
- G06F2113/18—Chip packaging
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Abstract
The invention provides a method and a circuit compatible with different voltage chip designs packaged in the same way, wherein the method comprises the following steps: finding unused suspension PIN in the replaced chip on the PCB; when designing the replaced chip, forcibly pulling down the package inside at the same position as the unused suspended PIN in the replaced chip to be the grounding PIN; when the PCB is applied, external resistor pull-up processing is carried out on the same position of unused suspended PIN in the replaced chip or the position of the replaced chip which is pulled down to be the grounding PIN, so that the PIN of the replaced chip or the replaced chip presents high level or low level to the outside; the chip is identified as being replaced or a chip is replaced according to the high level or the low level, so that corresponding voltages are output according to different voltage division ratios. According to the invention, the automatic identification of the substituted chip and the substituted chip is realized through the design scheme of the redundant PIN in the substituted chip, so that PIN2PIN compatibility is achieved.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a method and a circuit compatible with chip design of different voltages packaged in the same way.
Background
Chips of different manufacturers with the same function are required to achieve forward substitution (before the manufacturer who enters later performs seamless substitution), so that the chip design needs to achieve PIN2PIN compatibility (PIN 2PIN compatibility refers to the fact that the chips can be interchanged with the same function PINs of the chip), but the PIN2PIN compatibility cannot be achieved due to various limitations such as different IP (Intellectual Property ), different process and procedure differences, and the like, so that the later-entering manufacturer is difficult to achieve chip substitution and share breakthrough at the customer.
The existing solutions generally require the customer to modify the PCB (Printed Circuit Board ) and circuit diagram design, and two sets Of BOMs (Bill Of materials; one BOM for each Of the substituted chip and the substituted chip needs to be newly developed to replace the corresponding PCB Of the chip) are used to implement compatibility with two suppliers, which results in splitting the PCB code and the single board code into two sets, and then introducing a series Of changing risks such as cost for changing the board, maintenance cost for one set Of single board and PCB code, inventory and fund occupation Of the single board chip, spare parts, and design problems possibly introduced by board change.
Disclosure of Invention
The invention aims to provide a method and a circuit for designing and compatible with different packaged voltage chips, so as to realize that the replaced chip PIN2PIN is compatible with the replaced chip PIN2PIN without modifying the customer design, and solve the problems of a series of changing risks such as PCB board changing cost, a set of single board and PCB coding maintenance cost, single board chip inventory and fund occupation, spare parts, and design problems possibly introduced by board changing in the prior art.
The invention provides a method for designing and compatibility with different packaged voltage chips, which comprises the following steps:
finding unused suspension PIN in the replaced chip on the PCB;
when designing the replaced chip, forcibly pulling down the package inside at the same position as the unused suspended PIN in the replaced chip to be the grounding PIN;
when the PCB board is applied, external resistor pull-up processing is performed on the same position of unused suspended PIN in the replaced chip or the replaced chip pulled down to be the grounding PIN, so that:
if the unused suspended PIN in the replaced chip is used, the external resistor is pulled up to be at a high level;
if the chip is replaced by the ground PIN, the external resistor is in a low level after being pulled up;
the chip is identified as being replaced or a chip is replaced according to the high level or the low level, so that corresponding voltages are output according to different voltage division ratios.
In one embodiment, the outputting the respective voltages at different voltage division ratios includes:
feeding high level or low level back to the BUCK power supply and the voltage dividing circuit;
the BUCK power supply and the voltage dividing circuit output corresponding voltages according to different voltage dividing ratios.
In one embodiment, the high level or the low level is isolated by the isolation circuit and then fed back to the BUCK power supply and the voltage division circuit.
In one embodiment of the invention, a circuit compatible with different voltage chip designs is provided, comprising:
the capacitor comprises a BUCK power supply, a voltage dividing circuit, an inductor L1, a capacitor C1 and a resistor R4; the voltage dividing circuit comprises a resistor R1 and a resistor R2;
after the output end of the BUCK power supply passes through the inductor L1, the output end is connected with a power supply end VCC of a replaced chip or a replaced chip, is grounded through a capacitor C1, and is grounded through a resistor R1 and a resistor R2 in sequence;
the feedback end fb of the BUCK power supply is grounded through an isolation circuit and a resistor R4 in sequence, and is connected with an electrical connection point between a resistor R1 and a resistor R2;
the electrical connection point between the resistor R4 and the isolation circuit is connected with the unused hanging PIN in the replaced chip or the grounding PIN pulled down by the replaced chip, and is used for carrying out external resistor pull-up processing on the same position of the unused hanging PIN in the replaced chip or the grounding PIN pulled down by the replaced chip.
In one embodiment, the isolation circuit includes a resistor R3 and a MOS transistor Q2;
the feedback end fb of the BUCK power supply is connected with the drain electrode of the MOS tube Q2 through a resistor R3, the source electrode of the MOS tube Q2 is grounded, and the grid electrode of the MOS tube Q2 is grounded through a resistor R4.
In another embodiment of the present invention, a method for designing compatibility with different voltage chips packaged in a same package is provided, including:
finding out the grounding PIN of the replaced chip on the PCB;
when designing the substituted chip, the package inside at the same position as the grounding PIN in the substituted chip is realized as an unused suspended PIN;
when the PCB is applied, external resistor pull-up processing is performed on the same position of the grounding PIN in the replaced chip or the unused hanging PIN in the replaced chip, so that the chip is enabled to be in a state of being in contact with the ground PIN:
if the grounding PIN of the replaced chip is the grounding PIN, the external resistor is in a low level after being pulled up;
if the unused suspended PIN in the chip is replaced, the external resistor is pulled up to be at a high level;
the chip is identified as being replaced or a chip is replaced according to the high level or the low level, so that corresponding voltages are output according to different voltage division ratios.
In another embodiment of the present invention, the outputting the corresponding voltages according to the different voltage division ratios includes:
feeding high level or low level back to the BUCK power supply and the voltage dividing circuit;
the BUCK power supply and the voltage dividing circuit output corresponding voltages according to different voltage dividing ratios.
In another embodiment of the invention, the high level or the low level is isolated by the MOS tube and then fed back to the BUCK power supply and the voltage dividing circuit.
In another embodiment of the present invention, a circuit compatible with packaging different voltage chip designs is provided, comprising:
the capacitor comprises a BUCK power supply, a voltage dividing circuit, an inductor L1, a capacitor C1, a resistor R3, a resistor R4 and a MOS tube Q2; the voltage dividing circuit comprises a resistor R1 and a resistor R2;
after the output end of the BUCK power supply passes through the inductor L1, the output end is connected with a power supply end VCC of a replaced chip or a replaced chip, is grounded through a capacitor C1, and is grounded through a resistor R1 and a resistor R2 in sequence;
the feedback end fb of the BUCK power supply is connected with the drain electrode of the MOS tube Q2 through a resistor R3 on one hand, and is connected with an electrical connection point between the resistor R1 and the resistor R2 on the other hand;
the source electrode of the MOS tube Q2 is grounded, and the grid electrode of the MOS tube Q2 is grounded through a resistor R4;
the electrical connection point between the resistor R4 and the grid electrode of the MOS tube Q2 is connected with the grounding PIN in the replaced chip or the unused hanging PIN in the replaced chip, and is used for carrying out external resistor pull-up processing on the same position of the grounding PIN in the replaced chip or the unused hanging PIN in the replaced chip.
In another embodiment, the isolation circuit includes a resistor R3 and a MOS transistor Q2;
the feedback end fb of the BUCK power supply is connected with the drain electrode of the MOS tube Q2 through a resistor R3, the source electrode of the MOS tube Q2 is grounded, and the grid electrode of the MOS tube Q2 is grounded through a resistor R4.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
the invention realizes the automatic identification of the replaced chip and the replaced chip through the redundant PIN design scheme in the replaced chip, completely does not need manual intervention or software identification, does not need any distinction by an external BOM, achieves PIN2PIN compatibility when being applied to a PCB for customers, does not newly increase the cost of changing the PCB, does not introduce the problems of board changing or design changing, does not have the coding and maintenance cost of the newly increased single board, does not occupy the stock funds of the newly increased single board and the chip, and does not have the spare parts of the newly increased single board, and the like.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly describe the drawings in the embodiments, it being understood that the following drawings only illustrate some embodiments of the present invention and should not be considered as limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for designing compatibility with different voltage chips packaged in the same package in embodiment 1 of the present invention.
Fig. 2 is a block diagram of a compatible circuit for designing a chip with different voltages packaged in accordance with embodiment 1 of the present invention.
Fig. 3 is a flowchart of a method for designing compatibility with different voltage chips packaged in the same package in embodiment 2 of the present invention.
Fig. 4 is a block diagram of a compatible circuit for designing a chip with different voltages packaged in accordance with embodiment 2 of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The root reason that the existing scheme can not realize BOM normalization (chips of different suppliers are normalized under the same code) is that: the board cannot automatically obtain from which vendor the chip currently attached to the PCB comes, for example, the power supply voltage requirement of a certain power plane of the a manufacturer (the replaced chip) chip is 1.2V, and the power supply voltage requirement of the same plane of the B manufacturer (the replaced chip) is 1.0V. In this regard, the examples of the present invention provide the following embodiments.
Example 1
As shown in fig. 1, the present embodiment proposes a method for designing and compatibility with different voltage chips packaged in a same package, including:
finding unused dangling PIN (NC PIN) in the replaced chip on the PCB;
when designing the replaced chip, forcibly pulling down the package inside at the same position as the unused suspended PIN in the replaced chip to be the grounding PIN;
when the PCB board is applied, external resistor pull-up processing is performed on the same position of unused suspended PIN in the replaced chip or the replaced chip pulled down to be the grounding PIN, so that:
if the unused suspended PIN in the replaced chip is used, the external resistor is pulled up to be at a high level;
if the chip is replaced by the ground PIN, the external resistor is in a low level after being pulled up;
the chip is identified as being replaced or a chip is replaced according to the high level or the low level, so that the corresponding voltage (1.2V or 1.0V) is output according to different voltage division ratios. Wherein: the outputting the corresponding voltages according to the different voltage division ratios includes:
feeding high level or low level (which can be isolated by an isolating circuit) back to the BUCK power supply and the voltage dividing circuit;
the BUCK power supply and the voltage dividing circuit output corresponding voltages according to different voltage dividing ratios.
It can be seen from the above that, the scheme of the embodiment of the invention realizes the automatic identification of the substituted chip and the substituted chip through the redundant PIN design scheme in the substituted chip, completely does not need manual intervention or software identification, does not need any distinction by external BOM, achieves PIN2PIN compatibility when the PCB board is applied to clients, does not newly increase the cost of changing the PCB board, does not introduce the problems of board changing or design changing, does not have the coding maintenance cost of the newly increased single board, does not occupy the stock funds of the newly increased single board and the chip, and does not have the spare parts of the newly increased single board.
As shown in fig. 2, a circuit compatible with different voltage chip designs for implementing the method for compatible with different voltage chip designs for different packages includes:
the capacitor comprises a BUCK power supply, a voltage dividing circuit, an inductor L1, a capacitor C1 and a resistor R4; the voltage dividing circuit comprises a resistor R1 and a resistor R2;
after the output end of the BUCK power supply passes through the inductor L1, the output end is connected with a power supply end VCC of a replaced chip or a replaced chip, is grounded through a capacitor C1, and is grounded through a resistor R1 and a resistor R2 in sequence;
the feedback end fb of the BUCK power supply is grounded through an isolation circuit and a resistor R4 in sequence, and is connected with an electrical connection point between a resistor R1 and a resistor R2;
the electrical connection point between the resistor R4 and the isolation circuit is connected with the unused hanging PIN in the replaced chip or the grounding PIN pulled down by the replaced chip, and is used for carrying out external resistor pull-up processing on the same position of the unused hanging PIN in the replaced chip or the grounding PIN pulled down by the replaced chip.
The isolation circuit can be implemented in various manners, and in one preferred implementation scheme in this embodiment, the isolation circuit includes a resistor R3 and a MOS transistor Q2;
the feedback end fb of the BUCK power supply is connected with the drain electrode of the MOS tube Q2 through a resistor R3, the source electrode of the MOS tube Q2 is grounded, and the grid electrode of the MOS tube Q2 is grounded through a resistor R4.
Example 2
If the replaced chip cannot find the unused suspension PIN (NC PIN), the scheme can be realized by using the redundant grounding PIN (GND PIN), the corresponding replaced chip is realized as the unused suspension PIN (NC PIN) inside the package, and the difference of high or low level is still presented under the action of an external pull-up resistor, so that the replaced chip and the replaced chip are distinguished.
As shown in fig. 3, the method for designing and compatibility of chips with different voltages packaged in the same package according to this embodiment includes:
finding out the grounding PIN of the replaced chip on the PCB;
when designing the substituted chip, the package inside at the same position as the grounding PIN in the substituted chip is realized as an unused suspended PIN;
when the PCB is applied, external resistor pull-up processing is performed on the same position of the grounding PIN in the replaced chip or the unused hanging PIN in the replaced chip, so that the chip is enabled to be in a state of being in contact with the ground PIN:
if the grounding PIN of the replaced chip is the grounding PIN, the external resistor is in a low level after being pulled up;
if the unused suspended PIN in the chip is replaced, the external resistor is pulled up to be at a high level;
the chip is identified as being replaced or a chip is replaced according to the high level or the low level, so that the corresponding voltage (1.2V or 1.0V) is output according to different voltage division ratios. Wherein: the outputting the corresponding voltages according to the different voltage division ratios includes:
feeding high level or low level (which can be isolated by an isolating circuit) back to the BUCK power supply and the voltage dividing circuit;
the BUCK power supply and the voltage dividing circuit output corresponding voltages according to different voltage dividing ratios.
Similarly, the scheme of the embodiment of the invention realizes the automatic identification of the replaced chip and the replaced chip through the redundant PIN design scheme in the replaced chip, does not need manual intervention or software identification at all, does not need any distinction by external BOM, achieves PIN2PIN compatibility when the PCB is applied to clients, does not increase the cost of changing the PCB, does not introduce the problems of board changing or design changing, does not increase the encoding maintenance cost of a single board, does not occupy the inventory funds of the newly added single board and the chip, and does not have newly added single board spare parts.
As shown in fig. 4, a circuit compatible with different voltage chip designs for implementing the method for compatible with different voltage chip designs for different packages includes:
the capacitor comprises a BUCK power supply, a voltage dividing circuit, an inductor L1, a capacitor C1, a resistor R3, a resistor R4 and a MOS tube Q2; the voltage dividing circuit comprises a resistor R1 and a resistor R2;
after the output end of the BUCK power supply passes through the inductor L1, the output end is connected with a power supply end VCC of a replaced chip or a replaced chip, is grounded through a capacitor C1, and is grounded through a resistor R1 and a resistor R2 in sequence;
the feedback end fb of the BUCK power supply is connected with the drain electrode of the MOS tube Q2 through a resistor R3 on one hand, and is connected with an electrical connection point between the resistor R1 and the resistor R2 on the other hand;
the source electrode of the MOS tube Q2 is grounded, and the grid electrode of the MOS tube Q2 is grounded through a resistor R4;
the electrical connection point between the resistor R4 and the grid electrode of the MOS tube Q2 is connected with the grounding PIN in the replaced chip or the unused hanging PIN in the replaced chip, and is used for carrying out external resistor pull-up processing on the same position of the grounding PIN in the replaced chip or the unused hanging PIN in the replaced chip.
The isolation circuit can be implemented in various manners, and in one preferred implementation scheme in this embodiment, the isolation circuit includes a resistor R3 and a MOS transistor Q2;
the feedback end fb of the BUCK power supply is connected with the drain electrode of the MOS tube Q2 through a resistor R3, the source electrode of the MOS tube Q2 is grounded, and the grid electrode of the MOS tube Q2 is grounded through a resistor R4.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for compatibility with different voltage chip designs packaged in a same package, comprising:
finding unused suspension PIN in the replaced chip on the PCB;
when designing the replaced chip, forcibly pulling down the package inside at the same position as the unused suspended PIN in the replaced chip to be the grounding PIN;
when the PCB board is applied, external resistor pull-up processing is performed on the same position of unused suspended PIN in the replaced chip or the replaced chip pulled down to be the grounding PIN, so that:
if the unused suspended PIN in the replaced chip is used, the external resistor is pulled up to be at a high level;
if the chip is replaced by the ground PIN, the external resistor is in a low level after being pulled up;
the chip is identified as being replaced or a chip is replaced according to the high level or the low level, so that corresponding voltages are output according to different voltage division ratios.
2. The method of claim 1, wherein outputting the respective voltages at different voltage division ratios comprises:
feeding high level or low level back to the BUCK power supply and the voltage dividing circuit;
the BUCK power supply and the voltage dividing circuit output corresponding voltages according to different voltage dividing ratios.
3. The method of claim 2, wherein the high level or the low level is isolated by an isolation circuit and fed back to the BUCK power supply and the voltage divider.
4. A circuit compatible with packaging different voltage chip designs, comprising:
the capacitor comprises a BUCK power supply, a voltage dividing circuit, an inductor L1, a capacitor C1 and a resistor R4; the voltage dividing circuit comprises a resistor R1 and a resistor R2;
after the output end of the BUCK power supply passes through the inductor L1, the output end is connected with a power supply end VCC of a replaced chip or a replaced chip, is grounded through a capacitor C1, and is grounded through a resistor R1 and a resistor R2 in sequence;
the feedback end fb of the BUCK power supply is grounded through an isolation circuit and a resistor R4 in sequence, and is connected with an electrical connection point between a resistor R1 and a resistor R2;
the electrical connection point between the resistor R4 and the isolation circuit is connected with the unused hanging PIN in the replaced chip or the grounding PIN pulled down by the replaced chip, and is used for carrying out external resistor pull-up processing on the same position of the unused hanging PIN in the replaced chip or the grounding PIN pulled down by the replaced chip.
5. The co-packaged different voltage chip design compatible circuit according to claim 4, wherein the isolation circuit comprises a resistor R3 and a MOS transistor Q2;
the feedback end fb of the BUCK power supply is connected with the drain electrode of the MOS tube Q2 through a resistor R3, the source electrode of the MOS tube Q2 is grounded, and the grid electrode of the MOS tube Q2 is grounded through a resistor R4.
6. A method for compatibility with different voltage chip designs packaged in a same package, comprising:
finding out the grounding PIN of the replaced chip on the PCB;
when designing the substituted chip, the package inside at the same position as the grounding PIN in the substituted chip is realized as an unused suspended PIN;
when the PCB is applied, external resistor pull-up processing is performed on the same position of the grounding PIN in the replaced chip or the unused hanging PIN in the replaced chip, so that the chip is enabled to be in a state of being in contact with the ground PIN:
if the grounding PIN of the replaced chip is the grounding PIN, the external resistor is in a low level after being pulled up;
if the unused suspended PIN in the chip is replaced, the external resistor is pulled up to be at a high level;
the chip is identified as being replaced or a chip is replaced according to the high level or the low level, so that corresponding voltages are output according to different voltage division ratios.
7. The method of claim 6, wherein outputting the respective voltages at different voltage division ratios comprises:
feeding high level or low level back to the BUCK power supply and the voltage dividing circuit;
the BUCK power supply and the voltage dividing circuit output corresponding voltages according to different voltage dividing ratios.
8. The method of claim 7, wherein the high level or the low level is isolated by the MOS transistor and fed back to the BUCK power supply and the voltage divider circuit.
9. A circuit compatible with packaging different voltage chip designs, comprising:
the capacitor comprises a BUCK power supply, a voltage dividing circuit, an inductor L1, a capacitor C1, a resistor R3, a resistor R4 and a MOS tube Q2; the voltage dividing circuit comprises a resistor R1 and a resistor R2;
after the output end of the BUCK power supply passes through the inductor L1, the output end is connected with a power supply end VCC of a replaced chip or a replaced chip, is grounded through a capacitor C1, and is grounded through a resistor R1 and a resistor R2 in sequence;
the feedback end fb of the BUCK power supply is connected with the drain electrode of the MOS tube Q2 through a resistor R3 on one hand, and is connected with an electrical connection point between the resistor R1 and the resistor R2 on the other hand;
the source electrode of the MOS tube Q2 is grounded, and the grid electrode of the MOS tube Q2 is grounded through a resistor R4;
the electrical connection point between the resistor R4 and the grid electrode of the MOS tube Q2 is connected with the grounding PIN in the replaced chip or the unused hanging PIN in the replaced chip, and is used for carrying out external resistor pull-up processing on the same position of the grounding PIN in the replaced chip or the unused hanging PIN in the replaced chip.
10. The co-packaged different voltage chip design compatible circuit according to claim 9, wherein the isolation circuit comprises a resistor R3 and a MOS transistor Q2;
the feedback end fb of the BUCK power supply is connected with the drain electrode of the MOS tube Q2 through a resistor R3, the source electrode of the MOS tube Q2 is grounded, and the grid electrode of the MOS tube Q2 is grounded through a resistor R4.
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| CN202311196638.2A CN116933720B (en) | 2023-09-18 | 2023-09-18 | Method and circuit compatible with different voltage chip designs packaged in same way |
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