CN116932175A - Heterogeneous chip task scheduling method and device based on sequence generation - Google Patents
Heterogeneous chip task scheduling method and device based on sequence generation Download PDFInfo
- Publication number
- CN116932175A CN116932175A CN202311208268.XA CN202311208268A CN116932175A CN 116932175 A CN116932175 A CN 116932175A CN 202311208268 A CN202311208268 A CN 202311208268A CN 116932175 A CN116932175 A CN 116932175A
- Authority
- CN
- China
- Prior art keywords
- task
- scheduled
- chip
- scheduling
- determining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 83
- 230000008569 process Effects 0.000 claims description 34
- 238000004590 computer program Methods 0.000 claims description 17
- 238000012804 iterative process Methods 0.000 claims description 8
- 238000012163 sequencing technique Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 13
- 238000012545 processing Methods 0.000 description 11
- 230000006870 function Effects 0.000 description 9
- 230000006872 improvement Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000001514 detection method Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000003902 lesion Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000010979 ruby Substances 0.000 description 1
- 229910001750 ruby Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
The specification discloses a heterogeneous chip task scheduling method and device based on sequence generation, which are used for determining the execution time of each task to be scheduled on each chip according to each task to be scheduled, determining the idle time of each chip, and generating a scheduling sequence according to the idle time of each chip and the execution time of each task to be scheduled on each chip, so as to schedule each chip to execute each task to be scheduled according to the scheduling sequence. Under the condition that the chips in the idle state exist in the computing cluster containing heterogeneous chips, tasks matched with the chips in the idle state are distributed as far as possible, and task execution efficiency is guaranteed.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a heterogeneous chip task scheduling method and apparatus based on sequence generation.
Background
At present, with the rapid development of computer technology, heterogeneous chips are increasingly widely applied in people's life. The heterogeneous chips can be different chips of different types in the same electronic equipment, or can be chips of the same type but different types in the same electronic equipment.
In the prior art, a common heterogeneous chip scheduling method is to consider chips in the same electronic device as chips of the same type, manually allocate priorities to tasks to be scheduled, and when the chips are idle, select tasks to be scheduled with highest priorities from the tasks to be scheduled according to priorities respectively corresponding to the tasks to be scheduled which are not allocated to the chips. The chip may execute the task to be scheduled assigned to itself.
However, in the case that the types, models, and processing capacities of the chips are different, a task that is allocated to a chip and is not matched with the chip may occur, so that it takes a long time for the chip to perform the task, which results in a low utilization rate of the computing cluster.
Based on the above, the specification provides a heterogeneous chip task scheduling method based on sequence generation.
Disclosure of Invention
The specification provides a heterogeneous chip task scheduling method and device based on sequence generation, so as to partially solve the problems existing in the prior art.
The technical scheme adopted in the specification is as follows:
the specification provides a heterogeneous chip task scheduling method based on sequence generation, which is applied to scheduling nodes in a computing cluster, wherein the computing cluster comprises the scheduling nodes and a plurality of chips, and the computing resources of the chips are not identical; the method comprises the following steps:
For each task to be scheduled, determining the execution time of the task to be scheduled on each chip in the computing cluster, and determining the task information of the task to be scheduled according to each execution time;
determining idle time corresponding to each chip in the computing cluster;
responding to a scheduling request, and generating a scheduling sequence according to idle time corresponding to each chip and task information corresponding to each task to be scheduled, wherein the scheduling sequence comprises a designated number of tasks to be scheduled, and the scheduling sequence comprises a scheduling sequence corresponding to each task to be scheduled and a chip corresponding to each task to be scheduled;
and scheduling the chips to execute the specified number of tasks to be scheduled according to the scheduling sequence.
Optionally, determining the execution time of the task to be scheduled on each chip in the computing cluster, which corresponds to the task to be scheduled, specifically includes:
determining at least one of overtime time and priority of the task to be scheduled as task information of the task to be scheduled;
and combining chip information of each chip and task information of the task to be scheduled in the computing cluster, and inputting a combined result into a pre-trained prediction model to obtain execution time output by the prediction model, wherein the execution time is the time required by the chip to execute the task to be scheduled.
Optionally, determining task information of the task to be scheduled according to each execution time specifically includes:
and determining task information of each task to be scheduled according to at least one of execution time of the task to be scheduled, overtime time of the task to be scheduled and priority of the task to be scheduled.
Optionally, generating a scheduling sequence according to the idle time corresponding to each chip and the task information corresponding to each task to be scheduled, which specifically includes:
determining a first designated attribute and a second designated attribute from the task information of each task to be scheduled, wherein the task information at least comprises attribute data of the first designated attribute and the second designated attribute;
determining an initial chip according to idle time corresponding to each chip in the computing cluster;
according to the first appointed attribute and the second appointed attribute which correspond to the tasks to be scheduled respectively, determining the correlation degree of the tasks to be scheduled and the initial chip, determining the target task executed by the initial chip according to the correlation degree, and updating the idle time of the initial chip;
According to the updated idle time of the initial chip and the idle time corresponding to other chips in the computing cluster, the initial chip is redetermined, and target tasks are redetermined until the number of tasks allocated to each chip in the computing cluster reaches the designated number;
and generating a scheduling sequence according to the determined target tasks.
Optionally, determining, according to each correlation degree, a target task executed by the initial chip specifically includes:
judging whether the current iterative process is a first iterative process or not;
if so, sequencing the tasks to be scheduled according to the relevance, determining a specific number of tasks to be scheduled from the sequencing result, taking the specific number of tasks to be scheduled as target tasks, and taking the target tasks as initial tasks of candidate sequences corresponding to the target tasks for each target task;
if not, determining the task to be scheduled with the highest correlation degree with the initial chip determined in the current iteration process from the tasks to be scheduled according to the correlation degrees, and taking the task to be scheduled as a target task.
Generating a scheduling sequence according to each determined target task, which specifically comprises the following steps:
and determining a scheduling sequence from candidate sequences respectively corresponding to the target tasks determined in the initial iteration process.
Optionally, determining a scheduling sequence from candidate sequences corresponding to each target task determined in the initial iteration process, which specifically includes:
determining each candidate sequence which does not contain the overtime task from candidate sequences which are determined in the initial iteration process and respectively correspond to each target task, and determining the candidate sequence with the shortest execution time from each candidate sequence which does not contain the overtime task as the target sequence;
and taking the target sequence as a scheduling sequence corresponding to the scheduling request.
Optionally, the scheduling node comprises a cluster state sensing unit, a task information storage unit, a scheduling sequence generating unit and a task distributing unit; the cluster state sensing unit is used for determining idle time corresponding to each chip in the computing cluster; the task information storage unit is used for determining and storing task information corresponding to each task to be scheduled respectively; the scheduling sequence generating unit is used for generating a scheduling sequence; the task allocation unit is used for allocating each task to be scheduled in the scheduling sequence to each chip in the computing cluster.
The specification provides a heterogeneous chip task scheduling device based on sequence generation, which is applied to scheduling nodes in a computing cluster, wherein the computing cluster comprises the scheduling nodes and a plurality of chips, and the computing resources of the chips are not identical; the device comprises:
The task information determining module is used for determining the execution time of each task to be scheduled on each chip in the computing cluster according to each task to be scheduled, and determining the task information of the task to be scheduled according to each execution time;
the chip state determining module is used for determining idle time corresponding to each chip in the computing cluster;
the sequence generation module is used for responding to the scheduling request, generating a scheduling sequence according to idle time corresponding to each chip and task information corresponding to each task to be scheduled, wherein the scheduling sequence comprises a designated number of tasks to be scheduled, and the scheduling sequence comprises a scheduling sequence corresponding to each task to be scheduled and a chip corresponding to each task to be scheduled;
and the scheduling module is used for scheduling the chips to execute the specified number of tasks to be scheduled according to the scheduling sequence.
The present specification provides a computer readable storage medium storing a computer program which when executed by a processor implements a heterogeneous chip task scheduling method based on sequence generation as described above.
The present specification provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the above-described heterogeneous chip task scheduling method based on sequence generation when executing the program.
The above-mentioned at least one technical scheme that this specification adopted can reach following beneficial effect:
and determining the execution time of each task to be scheduled on each chip according to each task to be scheduled, determining the idle time of each chip, and generating a scheduling sequence according to the idle time of each chip and the execution time of each task to be scheduled on each chip, so as to schedule each chip to execute each task to be scheduled according to the scheduling sequence. Under the condition that the chips in the idle state exist in the computing cluster containing heterogeneous chips, tasks matched with the chips in the idle state are distributed as far as possible, and task execution efficiency is guaranteed.
Drawings
The accompanying drawings, which are included to provide a further understanding of the specification, illustrate and explain the exemplary embodiments of the present specification and their description, are not intended to limit the specification unduly. In the drawings:
Fig. 1 is a schematic flow chart of a heterogeneous chip task scheduling method based on sequence generation provided in the present specification;
FIG. 2 is a schematic flow chart of determining a target task provided in the present specification;
FIG. 3 is a flow chart of a certain scheduling sequence provided in the present specification;
FIG. 4 is a schematic diagram of a scheduling node provided in the present specification;
fig. 5 is a schematic structural diagram of a heterogeneous chip task scheduling device based on sequence generation provided in the present specification;
fig. 6 is a schematic view of the electronic device corresponding to fig. 1 provided in the present specification.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present specification more apparent, the technical solutions of the present specification will be clearly and completely described below with reference to specific embodiments of the present specification and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present specification. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.
The following describes in detail the technical solutions provided by the embodiments of the present specification with reference to the accompanying drawings.
At present, with the rapid development of computer technology, heterogeneous chips are increasingly widely applied in people's life. Among them, heterogeneous chips are different chips of different types in the same electronic device, such as a central processor (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), a tensor processor (Tensor Processing Unit, TPU) and the like in the same server. Or chips belonging to the same type but different types in the same electronic device, such as CPUs of different types in the same electronic device, and the like.
Different chips require different execution times when processing the same task. Taking the task to be scheduled as a convolution task as an example, the execution time required by the image processor is generally smaller than that required by the central processor. Therefore, how to process each task to be scheduled based on each chip in the computing cluster after receiving the task to be scheduled and ensure high utilization rate of each chip in the processing process has become one of the technical problems to be solved at present.
One common scheduling method is to consider the chips in the same electronic device or the same computing cluster as chips of the same type, manually allocate priorities to the tasks to be scheduled, and when the chips are idle, select the task to be scheduled with the highest priority from the tasks to be scheduled according to the priorities corresponding to the tasks to be scheduled which are not allocated to the chips. The chip may execute the task to be scheduled assigned to itself.
However, in the case that the types, models, and processing capacities of the chips are different, a task that is allocated to a chip and is not matched with the chip may occur, so that it takes a long time for the chip to perform the task, which results in a low utilization rate of the computing cluster.
Based on the above, the present specification provides a heterogeneous chip task scheduling method based on sequence generation, which generates a scheduling sequence based on execution time of each scheduling task on each chip and idle time corresponding to each chip, and schedules each chip based on the scheduling sequence to execute the task to be scheduled. Therefore, tasks matched with the chips are distributed for the chips as much as possible, and task execution efficiency is guaranteed.
Fig. 1 is a schematic diagram of a heterogeneous chip task scheduling method based on sequence generation, where:
s100: and determining the execution time of each task to be scheduled on each chip in the computing cluster, and determining the task information of the task to be scheduled according to each execution time.
Different from the prior art that tasks are distributed to all chips in a computing cluster only based on the priority of each task to be scheduled, the processing efficiency of the computing cluster is low. The specification provides a chip task scheduling method, which is used for determining the execution time of each to-be-scheduled task on each chip according to each to-be-scheduled task, determining the idle time of each to-be-scheduled task on each chip, and generating a scheduling sequence according to the idle time of each to-be-scheduled task on each chip and the execution time of each to-be-scheduled task on each chip, so as to schedule each chip to execute each to-be-scheduled task according to the scheduling sequence. Under the condition that the chip is idle, tasks matched with the chip are distributed to the chip as much as possible, and task execution efficiency is guaranteed.
Based on the above brief description of the heterogeneous chip task scheduling method based on sequence generation provided in the present specification, the heterogeneous chip task scheduling method based on sequence generation provided in the present specification may be executed by a scheduling node in a computing cluster, and the scheduling node may be a server, a terminal, or an intelligent device. Wherein the computing cluster comprises a scheduling node and each chip. That is, the chip task scheduling method provided in the present specification is essentially a method for calling each chip to process each task to be scheduled. The computing cluster can be electronic equipment with a plurality of chips and a scheduling unit for scheduling each task deployed inside, or can be a cluster formed by a scheduling node and a plurality of computing nodes with chips deployed.
Specifically, for each task to be scheduled, the execution time of the task to be scheduled on each chip is not identical. Therefore, the scheduling node can determine the task information of each task to be scheduled according to each task to be scheduled, and input the task information into a pre-trained prediction model as input to obtain the execution time of the task to be scheduled, which is output by the prediction model, corresponding to each chip. The task information of each task to be scheduled may be at least one of a remaining time of the task to be scheduled, a priority of the task to be scheduled, a data length of task data of the task to be scheduled, and a task type of the task to be scheduled.
After determining the execution time of the task to be scheduled on each chip, the scheduling node can directly take each execution time as the task information of the task to be scheduled.
Of course, in order to distinguish the chips corresponding to the execution times conveniently, when determining the execution times, the scheduling node may further combine, for each chip, chip information of the chip and task information of the task to be scheduled, and use the combined result as input data of the prediction model. And obtaining the execution time of the output of the prediction model. The execution time is used for indicating the time required by the chip to execute the task to be scheduled.
Furthermore, the scheduling node can also determine a plurality of tasks to be scheduled which are executed historically as each historical task, and determine a chip corresponding to each historical task and execution time corresponding to each historical task. For each historical task, the chip corresponding to the historical task may be the chip executing the historical task.
Then, the scheduling node may determine, for each task to be scheduled, a similarity corresponding to each historical task, and for each historical task, use the similarity between the task to be scheduled and the historical task as a weight of the historical task.
And finally, determining the execution time of the scheduling node corresponding to each chip according to the chip corresponding to each historical task, the execution time corresponding to each historical task and the weight corresponding to each historical task.
The above two ways are merely examples of determining the execution time of each task to be scheduled, and specifically how to determine the execution time of each task to be scheduled may be set according to needs, which is not limited in this specification.
S102: and determining the idle time corresponding to each chip in the computing cluster.
In one or more embodiments provided in the present disclosure, for each task to be scheduled, the task to be scheduled may be executed only when the chip is idle, so the scheduling node may further determine an idle time corresponding to each chip, so as to determine the task to be scheduled allocated to each chip according to the idle time of each chip.
Specifically, the scheduling node may determine, for each chip, a task being executed by the chip and a remaining execution time corresponding to the task executed by the chip.
Then, the scheduling node may determine the idle time of the chip according to the remaining execution time corresponding to the task. The idle time is used for indicating that the chip is in an idle state when the idle time is reached.
The idle time may be a specific time, or may be text such as "the remaining execution time is 10s" for describing a gap between the idle time and the current time.
Of course, the idle time corresponding to each chip may be determined after the task is allocated to each chip, or may be determined according to a preset time interval, or may be determined when the scheduling request is received. The idle time corresponding to each chip can be set according to the needs when the chips are determined, and the specification does not limit the idle time.
S104: responding to a scheduling request, and generating a scheduling sequence according to idle time corresponding to each chip and task information corresponding to each task to be scheduled, wherein the scheduling sequence comprises a designated number of tasks to be scheduled, and the scheduling sequence comprises a scheduling sequence corresponding to each task to be scheduled and a chip corresponding to each task to be scheduled.
In one or more embodiments provided in the present disclosure, as described above, the scheduling node may allocate, for each chip, a task matching the idle time and task information corresponding to each task to be scheduled, as far as possible, so as to generate a scheduling sequence.
Specifically, the scheduling node may receive a scheduling request, where the scheduling request is used to generate a scheduling sequence, and the scheduling request carries a specified number.
The scheduling node may then parse the scheduling request to determine a specified number in the scheduling request.
Then, the scheduling node can determine the appointed number of tasks to be scheduled from the tasks to be scheduled according to the appointed number, the idle time corresponding to each chip and the task information corresponding to each task to be scheduled.
Finally, the scheduling node can generate a scheduling sequence according to the generated specified number of tasks to be scheduled.
Taking task information corresponding to each task to be scheduled as overtime time, the scheduling node can sort each task to be scheduled according to the overtime time corresponding to each task to be scheduled, and determine the appointed number of tasks to be scheduled with earlier overtime time as the appointed number of tasks to be scheduled according to the determined sorting. And then, the scheduling node can determine the task to be scheduled with the earliest overtime from the tasks to be scheduled, and allocate the task to be scheduled according to the execution time corresponding to the task to be scheduled and the idle time corresponding to each chip. And repeating the allocation process until the assigned number of tasks to be scheduled are allocated to each chip. Finally, the scheduling node can generate a scheduling sequence according to the chip corresponding to each task to be scheduled and the execution sequence corresponding to each task to be scheduled.
S106: and scheduling the chips to execute the specified number of tasks to be scheduled according to the scheduling sequence.
In one or more embodiments provided herein, after determining a scheduling sequence, the scheduling node may schedule each chip to perform tasks in the scheduling sequence.
Specifically, the scheduling sequence includes chips corresponding to each task to be scheduled and scheduling sequences corresponding to each task to be scheduled.
Therefore, the scheduling node can allocate, for each chip, a task to be scheduled corresponding to the chip in the scheduling sequence to the chip when the chip is in an idle state according to the scheduling sequence.
The chip can receive the task to be scheduled sent by the scheduling node, process the task to be scheduled and submit the processing result.
Further, the tasks to be scheduled corresponding to the chip may be multiple. Therefore, the scheduling node can determine the scheduling sequence corresponding to each task to be scheduled corresponding to the chip according to the scheduling sequence corresponding to each task to be scheduled in the scheduling sequence. And according to the scheduling sequence corresponding to each task to be scheduled corresponding to the chip, each task to be scheduled corresponding to the chip is sequentially sent to the chip, and the chip processes the tasks to be scheduled.
Based on the heterogeneous chip task scheduling method based on sequence generation shown in fig. 1, for each task to be scheduled, determining the execution time of the task to be scheduled on each chip, which corresponds to each chip, determining the idle time of each chip, and generating a scheduling sequence according to the idle time of each chip, which corresponds to each chip, and the execution time of each task to be scheduled on each chip, so as to schedule each chip to execute each task to be scheduled according to the scheduling sequence. Under the condition that the chips in the idle state exist in the computing cluster containing heterogeneous chips, tasks matched with the chips in the idle state are distributed as far as possible, and task execution efficiency is guaranteed.
Further, for each task to be scheduled, the execution time of the task to be scheduled on each chip corresponding to the task to be scheduled may be used to describe the task to be scheduled. But in addition to the execution time, the time-out time and priority can also be used to describe the task to be scheduled. Then, for each task to be scheduled, the scheduling node may determine at least one of execution time of the task to be scheduled, timeout time of the task to be scheduled, and priority of the task to be scheduled as task information of the task to be scheduled;
Furthermore, for each task to be scheduled, the task information of the task to be scheduled may include data corresponding to various task attributes. Therefore, the scheduling node can also determine the designated number of tasks to be scheduled according to the task information corresponding to each task to be scheduled.
Specifically, the scheduling node may determine a first specified attribute and a second specified attribute from task information of each task to be scheduled, where the task information at least includes attribute data of the first specified attribute and the second specified attribute.
Then, the scheduling node can determine the earliest idle chip from the chips according to the idle time corresponding to each chip in the computing cluster, namely, the chip which can be used for executing the task to be scheduled corresponding to the current scheduling process as the initial chip.
Then, the scheduling node can determine the correlation degree of each task to be scheduled and the initial chip according to the first designated attribute and the second designated attribute corresponding to each task to be scheduled, and determine the target task executed by the initial chip and update the idle time of the initial chip according to each correlation degree.
And then, the scheduling node can redetermine the initial chip and redetermine the target task according to the updated idle time of the initial chip and the idle time corresponding to other chips in the computing cluster respectively until the number of tasks allocated to each chip in the computing cluster reaches the designated number.
Finally, after determining the specified number of target tasks, the scheduling node may generate a scheduling sequence according to each determined target task. As shown in fig. 2.
Fig. 2 is a schematic flow chart of determining a target task provided in the present specification. In the figure, the right-angle matrix characterizes the task to be distributed to the execution of the x chip, the small-round-angle rectangle guarantees the task to be distributed to the execution of the y chip, and the large-round-angle rectangle guarantees the task to be distributed to the execution of the z chip. It is assumed that the execution times of different tasks on different chips and the remaining times corresponding to the tasks are shown in table 1.
TABLE 1
As shown in table 1, the computing cluster includes three chips, i.e., an x chip, a y chip and a z chip, and the task to be scheduled stored in the scheduling node has A, B, C, D, E five tasks, the execution time is the time required for each chip to execute each task, and the remaining time is used for representing how long the current time is from the timeout time of the task.
Assuming that the x chip is currently in an idle state, after the idle time of the y chip is 3s, the idle time of the z chip is 5 s. The scheduling node may determine that the initial chip is an x-chip according to the idle time corresponding to each chip.
Then, the scheduling node can determine the correlation degree between each task to be scheduled and the initial chip according to the first designated attribute and the second designated attribute of each task to be scheduled. Taking the first designated attribute as the remaining time and the second designated attribute as the execution time as an example. The scheduling node can determine a plurality of tasks to be scheduled with shortest remaining time according to first designated attributes respectively corresponding to the tasks to be scheduled. Assuming that the number of tasks to be scheduled, which is determined by the scheduling node and has the shortest remaining time, is two, the node to be scheduled can determine that the task a and the task C are two scheduling tasks with the shortest remaining events.
Then, the scheduling node can determine, according to the execution events of the two tasks to be scheduled with the shortest remaining time, the idle time corresponding to the initial chip after the tasks to be scheduled are allocated to the initial chip from the two tasks to be scheduled with the shortest remaining time: after 9s and after 8 s. And then determining a target task according to the idle time corresponding to the initial chip after the task to be scheduled is distributed to the initial chip. The scheduling node may determine that the C-task is the target task.
And then, the scheduling node can redetermine the initial chip according to the idle time corresponding to each chip, and redetermine the target task according to the task information corresponding to each task to be scheduled. And repeating the process until the determined number of the target tasks reaches the designated number of positions. In the figure, the scheduling node may determine that the task a and the task D may be candidate tasks according to the first specified attribute, and determine that the task a is a target task according to the second specified attribute. And in the next iteration process, determining the D task and the B task as candidate tasks according to the first designated attribute, and determining the D task as the candidate task according to the second designated attribute. In the next iteration process, the current B task and the current E task are determined to be candidate tasks, and the current E task is determined to be the candidate task according to the second designated attribute. And finally, in the last iteration process, determining the task B as a candidate task.
It should be noted that, in the figure, only five tasks to be scheduled are stored in the scheduling node, and the number of the tasks to be scheduled included in the scheduling sequence is not less than five. And then, when the initial chip corresponding to the B task is finally determined, determining the initial chip corresponding to the B task as a z chip according to the chip currently in idle state and the execution time of the B task on each chip respectively. How to determine each initial chip and each initial task can be set according to the needs, and the specification does not limit the initial chips and the initial tasks.
In addition, in order to avoid that the determined sequence is locally optimal, the scheduling node may further determine a number of candidate sequences, and determine a scheduling sequence from the candidate sequences.
Specifically, the scheduling node may determine whether the current iteration process is a first iteration process.
If so, the scheduling node can order the tasks to be scheduled according to the relevance, determine a specific number of tasks to be scheduled from the ordering result, serve as target tasks, and serve as initial tasks of candidate sequences corresponding to the target tasks for each target task.
If not, the scheduling node can determine the task to be scheduled with the highest correlation with the initial chip determined in the current iteration process from the tasks to be scheduled according to the correlations, and the task to be scheduled is used as a target task.
And finally, the scheduling node can determine a scheduling sequence from candidate sequences respectively corresponding to the target tasks determined in the initial iteration process. As shown in fig. 3.
Fig. 3 is a schematic flow chart of a determining scheduling sequence provided in the present specification. Similar to fig. 2, the right angle matrix characterizes the assignment of tasks to x-chip execution, the small rounded rectangle guarantees the assignment of tasks to y-chip execution, and the large rounded rectangle guarantees the assignment of tasks to z-chip execution. The dispatching node is stored with three chips including an x chip, a y chip and a z chip, the tasks to be dispatched stored in the dispatching node have A, B, C, D, E five tasks, the execution time is the time required by each chip to execute each task, and the remaining time is used for representing how long the current time is from the overtime time of the task. Assuming that the x chip is currently in an idle state, after the idle time of the y chip is 3s, the idle time of the z chip is 5 s. The scheduling node may determine that the initial chip is an x-chip according to the idle time corresponding to each chip.
When the scheduling node determines the target task for the first time, the scheduling node can take both the task A and the task C as target tasks and generate candidate sequences taking the target task as an initial task for each target task.
And then, for each candidate sequence, the scheduling node can redetermine the idle time of each chip in the computing cluster according to each determined task to be scheduled in the candidate sequence and the initial chip corresponding to each task to be scheduled. And determining an initial chip according to the idle time of each chip, and distributing a corresponding target task for the initial chip.
Finally, when the number of target tasks included in each candidate sequence reaches a specified number, the scheduling node may determine a scheduling sequence from each candidate sequence.
The sequence with the C task as the initial task is illustrated in fig. 2. In the sequence taking the task A as the initial task, the scheduling node can determine that the task C and the task D can be taken as candidate tasks according to the first appointed attribute, and determine that the task D is taken as a target task according to the second appointed attribute. And in the next iteration process, determining the C task and the B task as candidate tasks according to the first designated attribute, and determining the C task as the candidate task according to the second designated attribute. In the next iteration process, the current B task and the current E task are determined to be candidate tasks, and the current E task is determined to be the candidate task according to the second designated attribute. And finally, in the last iteration process, determining the task B as a candidate task.
Further, for a computing cluster, the number of tasks that time out is one of the more important evaluation indicators. It is therefore becoming increasingly important to execute a task before it times out. Thus, the scheduling node may determine the target sequence from among candidate sequences that do not contain timeout tasks.
Specifically, the scheduling node may determine each candidate sequence that does not include the timeout task from the candidate sequences corresponding to each target task determined in the initial iteration process.
Next, each candidate sequence that does not include the timeout task is determined as the target sequence, and the candidate sequence that has the shortest execution time is determined.
Finally, the scheduling node may use the target sequence as a scheduling sequence corresponding to the scheduling request.
Based on the same thought, the present disclosure provides a schematic structural diagram of a scheduling node, as shown in fig. 3.
Fig. 4 is a schematic structural diagram of a scheduling node provided in the present specification, where the scheduling node includes a cluster state sensing unit, a task information storage unit, a scheduling sequence generating unit and a task allocation unit.
The cluster state sensing unit is used for determining idle time corresponding to each chip in the computing cluster. The task information storage unit is used for determining and storing task information corresponding to each task to be scheduled. The scheduling sequence generating unit is used for generating a scheduling sequence. The task allocation unit is used for allocating each task to be scheduled in the scheduling sequence to each chip in the computing cluster.
It should be noted that, for each task to be scheduled stored in the scheduling node, the task to be scheduled may be that the scheduling node has not scheduled in the previous scheduling process, that is, the receiving time of the task to be scheduled is before the scheduling node receives the scheduling request last time. The time period between the time when the scheduling node receives the scheduling request and the time corresponding to the scheduling request received last time can also be the time period between the time when the scheduling node receives the scheduling request to be scheduled this time and the time corresponding to the scheduling request received last time. The scheduling node can be set as required when receiving the task to be scheduled, which is not limited in this specification. Of course, for each task to be scheduled, the task to be scheduled has a corresponding overtime time, and when the current time reaches the overtime time of the task to be scheduled but the task to be scheduled is not yet executed, the scheduling center can take the task to be scheduled as the overtime task and send prompt information to the user sending the overtime task according to the identifier of the overtime task. The prompt information can be used for reminding a user that the task has timed out.
Based on the same thought, the specification also provides a heterogeneous chip task scheduling device based on sequence generation, as shown in fig. 5.
FIG. 5 is a schematic diagram of a heterogeneous chip task scheduling device based on sequence generation, which is provided in the present disclosure, the device is applied to a scheduling node in a computing cluster, the computing cluster includes the scheduling node and a plurality of chips, and computing resources of the chips are not identical; wherein:
the task information determining module 200 is configured to determine, for each task to be scheduled, execution time of the task to be scheduled on each chip in the computing cluster, where the execution time corresponds to each chip, and determine task information of the task to be scheduled according to each execution time.
The chip state determining module 202 is configured to determine idle time corresponding to each chip in the computing cluster.
The sequence generating module 204 is configured to generate a scheduling sequence according to the idle time respectively corresponding to each chip and task information respectively corresponding to each task to be scheduled, where the scheduling sequence includes a specified number of tasks to be scheduled, and the scheduling sequence includes a scheduling sequence respectively corresponding to each task to be scheduled and a chip respectively corresponding to each task to be scheduled.
And the scheduling module 206 is configured to schedule each chip to execute the specified number of tasks to be scheduled according to the scheduling sequence.
Optionally, the task information determining module 200 is configured to determine at least one of a timeout time of the task to be scheduled and a priority of the task to be scheduled, as task information of the task to be scheduled, combine, for each chip included in the computing cluster, chip information of the chip and task information of the task to be scheduled, and input a combination result into a pre-trained prediction model, so as to obtain an execution time output by the prediction model, where the execution time is a time required by the chip to execute the task to be scheduled;
optionally, the task information determining module 200 is configured to determine, for each task to be scheduled, task information of the task to be scheduled according to at least one of execution time of the task to be scheduled, timeout time of the task to be scheduled, and priority of the task to be scheduled.
Optionally, the sequence generating module 204 is configured to determine a first designated attribute and a second designated attribute from task information of each task to be scheduled, where the task information at least includes attribute data of the first designated attribute and the second designated attribute, determine an initial chip according to idle moments corresponding to each chip in the computing cluster, determine a correlation degree corresponding to each task to be scheduled and each initial chip according to the first designated attribute and the second designated attribute corresponding to each task to be scheduled, determine a target task executed by each initial chip according to each correlation degree, update idle moments of the initial chip, redetermine the initial chip according to the updated idle moments of the initial chip and idle moments corresponding to other chips in the computing cluster, redetermine the target task until the number of tasks allocated to each chip in the computing cluster reaches the designated number, and generate the scheduling sequence according to the determined target tasks.
Optionally, the sequence generating module 204 is configured to determine whether the current iterative process is a first iterative process, if yes, sort the tasks to be scheduled according to each relevance, determine a specific number of tasks to be scheduled from the sorting result, as each target task, and regarding each target task as an initial task of a candidate sequence corresponding to the target task, if no, determine, from the tasks to be scheduled, a task to be scheduled with the highest relevance to the initial chip determined in the current iterative process, as a target task; and determining a scheduling sequence from candidate sequences respectively corresponding to the target tasks determined in the initial iteration process.
Optionally, the sequence generating module 204 is configured to determine, from candidate sequences corresponding to each target task determined in the initial iteration process, each candidate sequence that does not include the overtime task, determine, from each candidate sequence that does not include the overtime task, a candidate sequence with the shortest execution time, and use the target sequence as a scheduling sequence corresponding to the scheduling request.
Optionally, the scheduling node comprises a cluster state sensing unit, a task information storage unit, a scheduling sequence generating unit and a task distributing unit; the cluster state sensing unit is used for determining idle time corresponding to each chip in the computing cluster; the task information storage unit is used for determining and storing task information corresponding to each task to be scheduled respectively; the scheduling sequence generating unit is used for generating a scheduling sequence; the task allocation unit is used for allocating each task to be scheduled in the scheduling sequence to each chip in the computing cluster.
The present specification also provides a computer readable storage medium storing a computer program operable to perform a heterogeneous chip task scheduling method based on sequence generation as provided in fig. 1 above.
The present specification also provides a schematic structural diagram of the electronic device shown in fig. 6. At the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile storage, as illustrated in fig. 6, although other hardware required by other services may be included. The processor reads the corresponding computer program from the nonvolatile memory into the memory and then runs the computer program to realize the heterogeneous chip task scheduling method based on the sequence generation as shown in the above-mentioned figure 1. Of course, other implementations, such as logic devices or combinations of hardware and software, are not excluded from the present description, that is, the execution subject of the following processing flows is not limited to each logic unit, but may be hardware or logic devices.
In the 90 s of the 20 th century, improvements to one technology could clearly be distinguished as improvements in hardware (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) or software (improvements to the process flow). However, with the development of technology, many improvements of the current method flows can be regarded as direct improvements of hardware circuit structures. Designers almost always obtain corresponding hardware circuit structures by programming improved method flows into hardware circuits. Therefore, an improvement of a method flow cannot be said to be realized by a hardware entity module. For example, a programmable logic device (Programmable Logic Device, PLD) (e.g., field programmable gate array (Field Programmable Gate Array, FPGA)) is an integrated circuit whose logic function is determined by the programming of the device by a user. A designer programs to "integrate" a digital system onto a PLD without requiring the chip manufacturer to design and fabricate application-specific integrated circuit chips. Moreover, nowadays, instead of manually manufacturing integrated circuit chips, such programming is mostly implemented by using "logic compiler" software, which is similar to the software compiler used in program development and writing, and the original code before the compiling is also written in a specific programming language, which is called hardware description language (Hardware Description Language, HDL), but not just one of the hdds, but a plurality of kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), lava, lola, myHDL, PALASM, RHDL (Ruby Hardware Description Language), etc., VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog are currently most commonly used. It will also be apparent to those skilled in the art that a hardware circuit implementing the logic method flow can be readily obtained by merely slightly programming the method flow into an integrated circuit using several of the hardware description languages described above.
The controller may be implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic controllers, and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic of the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller may thus be regarded as a kind of hardware component, and means for performing various functions included therein may also be regarded as structures within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.
The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being functionally divided into various units, respectively. Of course, the functions of each element may be implemented in one or more software and/or hardware elements when implemented in the present specification.
It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
The present description is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the specification. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable lesion detection device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable lesion detection device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable lesion detection device to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
The description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing is merely exemplary of the present disclosure and is not intended to limit the disclosure. Various modifications and alterations to this specification will become apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, or the like, which are within the spirit and principles of the present description, are intended to be included within the scope of the claims of the present description.
Claims (10)
1. The heterogeneous chip task scheduling method based on sequence generation is characterized by being applied to scheduling nodes in a computing cluster, wherein the computing cluster comprises the scheduling nodes and a plurality of chips, and the computing resources of the chips are not identical; the method comprises the following steps:
for each task to be scheduled, determining the execution time of the task to be scheduled on each chip in the computing cluster, and determining the task information of the task to be scheduled according to each execution time;
determining idle time corresponding to each chip in the computing cluster;
responding to a scheduling request, and generating a scheduling sequence according to idle time corresponding to each chip and task information corresponding to each task to be scheduled, wherein the scheduling sequence comprises a designated number of tasks to be scheduled, and the scheduling sequence comprises a scheduling sequence corresponding to each task to be scheduled and a chip corresponding to each task to be scheduled;
and scheduling the chips to execute the specified number of tasks to be scheduled according to the scheduling sequence.
2. The method of claim 1, wherein determining the execution time of the task to be scheduled on each chip in the computing cluster, respectively, specifically comprises:
Determining at least one of overtime time and priority of the task to be scheduled as task information of the task to be scheduled;
and combining chip information of each chip and task information of the task to be scheduled in the computing cluster, and inputting a combined result into a pre-trained prediction model to obtain execution time output by the prediction model, wherein the execution time is the time required by the chip to execute the task to be scheduled.
3. The method of claim 1, wherein determining task information for the task to be scheduled based on each execution time, specifically comprises:
and determining task information of each task to be scheduled according to at least one of execution time of the task to be scheduled, overtime time of the task to be scheduled and priority of the task to be scheduled.
4. The method of claim 1, wherein generating a scheduling sequence according to the idle time corresponding to each chip and the task information corresponding to each task to be scheduled, specifically comprises:
determining a first designated attribute and a second designated attribute from the task information of each task to be scheduled, wherein the task information at least comprises attribute data of the first designated attribute and the second designated attribute;
Determining an initial chip according to idle time corresponding to each chip in the computing cluster;
according to the first appointed attribute and the second appointed attribute which correspond to the tasks to be scheduled respectively, determining the correlation degree of the tasks to be scheduled and the initial chip, determining the target task executed by the initial chip according to the correlation degree, and updating the idle time of the initial chip;
according to the updated idle time of the initial chip and the idle time corresponding to other chips in the computing cluster, the initial chip is redetermined, and target tasks are redetermined until the number of tasks allocated to each chip in the computing cluster reaches the designated number;
and generating a scheduling sequence according to the determined target tasks.
5. The method of claim 4, wherein determining the target task performed by the initial chip based on each correlation comprises:
judging whether the current iterative process is a first iterative process or not;
if so, sequencing the tasks to be scheduled according to the relevance, determining a specific number of tasks to be scheduled from the sequencing result, taking the specific number of tasks to be scheduled as target tasks, and taking the target tasks as initial tasks of candidate sequences corresponding to the target tasks for each target task;
If not, determining a task to be scheduled with the highest correlation degree with the initial chip determined in the current iteration process from the tasks to be scheduled according to the correlation degrees, and taking the task to be scheduled as a target task;
generating a scheduling sequence according to each determined target task, which specifically comprises the following steps:
and determining a scheduling sequence from candidate sequences respectively corresponding to the target tasks determined in the initial iteration process.
6. The method of claim 5, wherein determining a scheduling sequence from candidate sequences corresponding to each target task determined in the initial iterative process, comprises:
determining each candidate sequence which does not contain the overtime task from candidate sequences which are determined in the initial iteration process and respectively correspond to each target task, and determining the candidate sequence with the shortest execution time from each candidate sequence which does not contain the overtime task as the target sequence;
and taking the target sequence as a scheduling sequence corresponding to the scheduling request.
7. The method of claim 1, wherein the scheduling node comprises a cluster state sensing unit, a task information storage unit, a scheduling sequence generating unit, and a task allocation unit; the cluster state sensing unit is used for determining idle time corresponding to each chip in the computing cluster; the task information storage unit is used for determining and storing task information corresponding to each task to be scheduled respectively; the scheduling sequence generating unit is used for generating a scheduling sequence; the task allocation unit is used for allocating each task to be scheduled in the scheduling sequence to each chip in the computing cluster.
8. The heterogeneous chip task scheduling device based on sequence generation is characterized in that the device is applied to scheduling nodes in a computing cluster, the computing cluster comprises the scheduling nodes and a plurality of chips, and the computing resources of the chips are not identical; the device comprises:
the task information determining module is used for determining the execution time of each task to be scheduled on each chip in the computing cluster according to each task to be scheduled, and determining the task information of the task to be scheduled according to each execution time;
the chip state determining module is used for determining idle time corresponding to each chip in the computing cluster;
the sequence generation module is used for responding to the scheduling request, generating a scheduling sequence according to idle time corresponding to each chip and task information corresponding to each task to be scheduled, wherein the scheduling sequence comprises a designated number of tasks to be scheduled, and the scheduling sequence comprises a scheduling sequence corresponding to each task to be scheduled and a chip corresponding to each task to be scheduled;
and the scheduling module is used for scheduling the chips to execute the specified number of tasks to be scheduled according to the scheduling sequence.
9. A computer readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the method of any of the preceding claims 1-7.
10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any of the preceding claims 1-7 when executing the program.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311208268.XA CN116932175B (en) | 2023-09-19 | 2023-09-19 | Heterogeneous chip task scheduling method and device based on sequence generation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311208268.XA CN116932175B (en) | 2023-09-19 | 2023-09-19 | Heterogeneous chip task scheduling method and device based on sequence generation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116932175A true CN116932175A (en) | 2023-10-24 |
| CN116932175B CN116932175B (en) | 2024-01-09 |
Family
ID=88390143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311208268.XA Active CN116932175B (en) | 2023-09-19 | 2023-09-19 | Heterogeneous chip task scheduling method and device based on sequence generation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116932175B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117271100A (en) * | 2023-11-21 | 2023-12-22 | 北京国科天迅科技股份有限公司 | Algorithm chip cluster scheduling method, device, computer equipment and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113127173A (en) * | 2021-04-21 | 2021-07-16 | 浙江大学 | Heterogeneous sensing cluster scheduling method and device |
| CN114864069A (en) * | 2022-04-14 | 2022-08-05 | 深圳大学 | Method and device for scheduling tasks |
| US20230048833A1 (en) * | 2020-05-29 | 2023-02-16 | Alibaba Group Holding Limited | Method, apparatus, and storage medium for scheduling tasks |
| CN115756793A (en) * | 2022-11-17 | 2023-03-07 | 南京地平线集成电路有限公司 | Processing method and device for task scheduling, electronic equipment and storage medium |
| CN116185596A (en) * | 2023-04-24 | 2023-05-30 | 之江实验室 | Method and device for improving task execution efficiency of wide-area multi-cluster distributed system |
| WO2023159568A1 (en) * | 2022-02-28 | 2023-08-31 | 华为技术有限公司 | Task scheduling method, npu, chip, electronic device and readable medium |
-
2023
- 2023-09-19 CN CN202311208268.XA patent/CN116932175B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20230048833A1 (en) * | 2020-05-29 | 2023-02-16 | Alibaba Group Holding Limited | Method, apparatus, and storage medium for scheduling tasks |
| CN113127173A (en) * | 2021-04-21 | 2021-07-16 | 浙江大学 | Heterogeneous sensing cluster scheduling method and device |
| WO2023159568A1 (en) * | 2022-02-28 | 2023-08-31 | 华为技术有限公司 | Task scheduling method, npu, chip, electronic device and readable medium |
| CN114864069A (en) * | 2022-04-14 | 2022-08-05 | 深圳大学 | Method and device for scheduling tasks |
| CN115756793A (en) * | 2022-11-17 | 2023-03-07 | 南京地平线集成电路有限公司 | Processing method and device for task scheduling, electronic equipment and storage medium |
| CN116185596A (en) * | 2023-04-24 | 2023-05-30 | 之江实验室 | Method and device for improving task execution efficiency of wide-area multi-cluster distributed system |
Non-Patent Citations (1)
| Title |
|---|
| 许巾一;陈仪香;李凯旋;: "异构分布式嵌入式系统的优化设计方法", 微纳电子与智能制造, no. 01 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117271100A (en) * | 2023-11-21 | 2023-12-22 | 北京国科天迅科技股份有限公司 | Algorithm chip cluster scheduling method, device, computer equipment and storage medium |
| CN117271100B (en) * | 2023-11-21 | 2024-02-06 | 北京国科天迅科技股份有限公司 | Algorithm chip cluster scheduling method, device, computer equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116932175B (en) | 2024-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6716149B2 (en) | Blockchain-based data processing method and apparatus | |
| CN113282659B (en) | Data processing method and device based on block chain | |
| CN116225669B (en) | Task execution method and device, storage medium and electronic equipment | |
| CN116932175B (en) | Heterogeneous chip task scheduling method and device based on sequence generation | |
| CN116306856B (en) | Deep learning model deployment method and device based on search | |
| CN117421129B (en) | Service execution method and device based on heterogeneous storage cluster and electronic equipment | |
| CN116467061A (en) | Task execution method and device, storage medium and electronic equipment | |
| CN116347623B (en) | Task scheduling method and device, storage medium and electronic equipment | |
| CN116107728B (en) | Task execution method and device, storage medium and electronic equipment | |
| CN117493015A (en) | Capacity expansion and contraction method, device, medium and equipment of container management system | |
| CN111400032B (en) | Resource allocation method and device | |
| CN113344248A (en) | Order allocation method, device, storage medium and electronic equipment | |
| CN113032119A (en) | Task scheduling method and device, storage medium and electronic equipment | |
| CN117032999A (en) | CPU-GPU cooperative scheduling method and device based on asynchronous running | |
| CN116204324A (en) | Task execution method and device, storage medium and electronic equipment | |
| CN116384505A (en) | Data processing method and device, storage medium and electronic equipment | |
| CN110032433B (en) | Task execution method, device, equipment and medium | |
| CN112862228A (en) | Order distribution method and device, computer readable storage medium and electronic equipment | |
| CN111880922A (en) | Processing method, device and equipment for concurrent tasks | |
| CN116167437B (en) | Chip management system, method, device and storage medium | |
| CN116501474B (en) | System, method and device for processing batch homogeneous tasks | |
| CN116954954B (en) | Method and device for processing multi-task queues, storage medium and electronic equipment | |
| CN115098271B (en) | Multithreading data processing method, device, equipment and medium | |
| CN116089434B (en) | Data storage method and device, storage medium and electronic equipment | |
| CN114118798B (en) | Task processing method and device of industrial internet platform and industrial internet platform |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |