CN116931707A

CN116931707A - System-on-chip, dynamic adjustment method and chip system

Info

Publication number: CN116931707A
Application number: CN202210333289.3A
Authority: CN
Inventors: 樊小波; 刁君强
Original assignee: Beijing Simm Computing Technology Co ltd
Current assignee: Beijing Simm Computing Technology Co ltd
Priority date: 2022-03-31
Filing date: 2022-03-31
Publication date: 2023-10-24

Abstract

The invention discloses a system-on-chip, a dynamic adjustment method and a chip system, wherein the system-on-chip of an embodiment comprises the following steps: at least one chip, the chip comprising: a single wafer comprising a plurality of partitions, each of the partitions comprising a partition sensor; the power chip is used for providing output voltage for the single chip; and the dynamic adjustment unit is used for adjusting the output voltage of the power supply chip according to the monitoring data of each partition sensor. Dynamic. The embodiment of the invention can dynamically adjust the voltage of the corresponding partition according to the monitoring data of each partition, and effectively improve the performance of the system on chip.

Description

System-on-chip, dynamic adjustment method and chip system

Technical Field

The present invention relates to the field of computer control technologies, and in particular, to a system on a chip, a dynamic adjustment method, and a chip system.

Background

At present, research and application of a dynamic voltage frequency adjustment (DVFS) technology at home and abroad are very wide and mature, a traditional DVFS mode is realized by adopting open loop control, after chip design is finished, the corresponding relation between voltage and frequency is set in a lookup table mode, and then corresponding working frequency and voltage are searched and selected according to the actual working state of the chip.

In the prior art, the use of Dynamic Voltage Frequency Scaling (DVFS) technology in consumer chips enables normal, stable operation of the chip, but there are also cases of instability in arithmetic chips with large arithmetic forces.

Disclosure of Invention

To solve at least one of the above problems, a first embodiment of the present invention provides a system on a chip including at least one chip including: a single wafer comprising a plurality of partitions, each of the partitions comprising a partition sensor; the power chip is used for providing output voltage for the single chip; and the dynamic adjustment unit is used for adjusting the output voltage of the power supply chip according to the monitoring data of each partition sensor.

According to the embodiment, the hardware architecture of the dynamic adjustment unit and the power chip which are matched with the single chip is adopted, the monitoring data of each partition of the single chip is collected through the dynamic adjustment unit, the power chip matched with the single chip is adjusted according to the monitoring data, and the on-chip system for dynamically adjusting the voltage according to the monitoring data of each partition on the basis that a plurality of partitions of one single chip share one power chip is formed, so that the dynamic adjustment of the voltage can be rapidly, flexibly and conveniently carried out, the fluctuation of the power voltage caused by IR voltage drop is relieved, and the operation performance of the on-chip system is effectively improved.

In an alternative embodiment, the dynamic adjustment unit comprises: a configuration unit, and an adjustment controller corresponding to each partition one by one, the adjustment controller configured to: and generating an adjustment instruction according to a dynamic adjustment table in the configuration unit in response to the monitoring data of the partition sensor of the corresponding partition not meeting the preset monitoring threshold requirement, wherein the adjustment instruction comprises a first instruction for adjusting the output voltage of the power chip.

According to the embodiment, the dynamic adjustment flow is realized through the adjustment controllers corresponding to the partitions, specifically, according to the monitoring data of the partition sensors of the partitions, the adjustment instruction is determined through the dynamic adjustment table of the configuration unit in the dynamic adjustment unit, and the output voltage of the power supply chip is adjusted in the form of outputting the first instruction, so that the dynamic adjustment is triggered by the fact that the monitoring data of the partitions does not meet the monitoring threshold requirement, and the method has the characteristics of being rapid, flexible and convenient.

In an alternative embodiment, the monitoring data includes voltage acquisition data and temperature acquisition data, and the monitoring threshold includes a first threshold corresponding to the voltage acquisition data and a second threshold corresponding to the temperature acquisition data; the adjustment controller is configured to: comparing the voltage acquisition data in the monitoring data with the first threshold value, and determining a voltage value to be adjusted in the dynamic adjustment table and generating the first instruction in response to the voltage acquisition data being smaller than the first threshold value; or alternatively

Comparing the temperature acquisition data in the monitoring data with the second threshold value, and responding to the fact that the temperature acquisition data is larger than the second threshold value, determining the voltage value to be adjusted in the dynamic adjustment table and generating the first instruction.

According to the embodiment, the dynamic adjustment flow is triggered according to the comparison result of the voltage acquisition data and the first threshold value of each partition and the comparison result of the temperature acquisition data and the second threshold value, the adjustment instruction is determined through the dynamic adjustment table, the output voltage of the power supply chip is adjusted in a mode of outputting the first instruction, and therefore the purpose that the dynamic adjustment is triggered when the monitoring data of each partition does not meet the monitoring threshold value requirement is achieved, and the method has the advantages of being rapid, flexible and convenient.

In an alternative embodiment, the chip further comprises: the power management unit is used for outputting clock frequency to the single chip; and the dynamic adjustment unit is also used for adjusting the clock frequency output by the power management unit according to the monitoring data of each partition sensor.

The embodiment further dynamically adjusts the power management unit according to the monitoring data of the partition sensors of each partition through the power management unit matched with the single chip, thereby realizing the dynamic adjustment of the clock frequency of each partition.

In an alternative embodiment, the adjustment instructions further comprise second instructions to adjust the clock frequency of the power management unit, the adjustment controller further configured to: and generating the second instruction for adjusting clock frequency trend according to a dynamic adjustment table in the configuration unit in response to the temperature acquisition data being greater than the second threshold.

According to the embodiment, a dynamic adjustment flow of the clock frequency is further realized through the adjustment controllers corresponding to the partitions, specifically, according to the temperature acquisition data of the partition sensors of the partitions, an adjustment instruction is determined through the dynamic adjustment table of the configuration unit in the dynamic adjustment unit, and the clock frequency trend of the power management unit is adjusted in a form of outputting a second instruction, so that the dynamic adjustment of triggering the clock frequency in a mode that the temperature acquisition data of the partitions does not meet the monitoring threshold requirement is realized, and the method has the characteristics of being rapid, flexible and convenient.

In an alternative embodiment, the power management unit is further configured to: and determining the clock frequency of the partition adjusted corresponding to the second instruction according to the second instruction.

The embodiment further outputs the clock frequency to the corresponding partition by the power management unit according to the second instruction of each partition, thereby realizing the dynamic adjustment of the clock frequency of the corresponding partition according to the temperature acquisition data of each partition.

In an alternative embodiment, the dynamic adjustment table includes a plurality of adjustment tables corresponding to each partition one to one; the adjustment controller is further configured to: and generating the first instruction of the partition according to the adjustment form corresponding to the partition in response to the monitoring data of the partition sensor of the corresponding partition not meeting the preset monitoring threshold requirement.

The embodiment further limits that the dynamic adjustment table respectively comprises an adjustment table of each partition, and in the dynamic adjustment process, each partition triggers dynamic adjustment according to the fact that the monitoring data of the partition sensor does not meet the monitoring threshold requirement, and adjusts according to the respective adjustment table, so that the voltage of each partition is adjusted more flexibly.

In an alternative embodiment, the dynamic adjustment unit comprises: an adaptive voltage regulating unit is provided for regulating the voltage of the power supply,

the adaptive voltage regulating unit is configured to: and determining the output voltage output by the power chip according to a first instruction generated by at least one adjustment controller.

In the dynamic adjustment process triggered by the monitoring data of one partition, the adaptive voltage adjustment unit of the embodiment generates a first instruction for adjusting the power supply chip according to the monitoring data of the partition, and generates a first instruction transmitted to the power supply chip together according to the first instructions generated by the monitoring data of other partitions, so that the dynamic adjustment of the voltage is realized under the condition that each partition shares one power supply chip.

In an alternative embodiment, the system on chip further comprises a droop control unit connected to the dynamic adjustment unit, the droop control unit being configured to: generating a droop signal based on the dynamic adjustment unit according to the adjustment of the monitoring data to the power chip, and sending a droop interrupt to the dynamic adjustment unit in response to the droop signal not meeting a preset droop threshold value requirement; the dynamic adjustment unit is further configured to: receiving a droop interrupt sent by the droop control unit; adjusting the output voltage of the power chip.

In this embodiment, in combination with the droop control unit of the on-chip system, after the dynamic adjustment unit adjusts the power supply chip, the droop control unit generates a droop signal, and uses the droop threshold to determine the droop signal, if the droop signal does not meet the droop threshold, the droop control unit generates a transmission interrupt to the dynamic adjustment unit to trigger the dynamic adjustment unit to adjust the voltage of each partition, thereby further improving the accuracy of adjusting the voltage frequency of each partition of each single-chip of the on-chip system, alleviating the power supply voltage fluctuation caused by the IR drop, and effectively improving the operation performance of the on-chip system.

A second embodiment of the present invention provides a dynamic adjustment method applied to a system on a chip, the system on a chip including at least one chip, the chip including: a single wafer comprising a plurality of partitions, each of the partitions comprising a partition sensor; the power chip is used for providing output voltage for the single chip;

the method comprises the following steps: acquiring monitoring data acquired by the partition sensors of each partition of the chip; and adjusting the output voltage of the power supply chip according to the monitoring data.

According to the hardware architecture of the system on chip, the monitoring data of each partition of the single chip is collected through the dynamic adjusting unit, the power supply chip matched with the single chip is adjusted according to the monitoring data, and the system on chip with the voltage dynamically adjusted according to the monitoring data of each partition on the basis that a plurality of partitions of one single chip share one power supply chip is formed, so that the dynamic adjustment of the voltage can be quickly, flexibly and conveniently carried out, the fluctuation of the power supply voltage caused by IR voltage drop is relieved, and the operation performance of the system on chip is effectively improved.

In an alternative embodiment, said adjusting said output voltage of said power supply chip according to said monitoring data further comprises: and generating an adjustment instruction of the partition according to a dynamic adjustment table in response to the monitoring data of the partition sensor of the partition not meeting the preset monitoring threshold requirement, wherein the adjustment instruction comprises a first instruction for adjusting the output voltage of the power supply chip.

In an alternative embodiment, the monitoring data includes voltage acquisition data and temperature acquisition data, and the monitoring threshold includes a first threshold corresponding to the voltage acquisition data and a second threshold corresponding to the temperature acquisition data; and generating an adjustment instruction of the partition according to a dynamic adjustment table in response to the monitoring data of the partition sensor of the partition not meeting the preset monitoring threshold requirement, and further comprising:

comparing the voltage acquisition data in the monitoring data with the first threshold value, and determining a voltage value to be adjusted in the dynamic adjustment table and generating the first instruction in response to the voltage acquisition data being smaller than the first threshold value; or alternatively

In an alternative embodiment, the chip further comprises: the power management unit is used for outputting clock frequency to the single chip; the determining the voltage value to be adjusted in the dynamic adjustment table and generating the first instruction in response to the temperature acquisition data being greater than the second threshold value, further comprises: and generating a second instruction for adjusting clock frequency trend in response to the temperature acquisition data being greater than the second threshold value, so that the power management unit determines the partition adjusted clock frequency corresponding to the second instruction according to the second instruction.

In an alternative embodiment, the dynamic adjustment table includes a plurality of adjustment levels; the determining, in the dynamic adjustment table, a voltage value to be adjusted and generating the first instruction in response to the temperature acquisition data being greater than the second threshold value, further comprises: responsive to the temperature acquisition data being greater than the second threshold; and determining a target adjustment level based on a first condition, wherein the first condition comprises an adjustment level of the partition at which the partition is currently located, determining a voltage value to be adjusted of the partition according to the target adjustment level, and generating a first instruction of the partition.

In this embodiment, based on the temperature acquisition data, the second threshold value and the dynamic adjustment table, a first instruction for adjusting the power supply chip is generated according to the current state of the partition, so that the voltage and the frequency of each partition can be dynamically adjusted rapidly, flexibly and conveniently.

In an alternative embodiment, the dynamic adjustment table further includes a first threshold value corresponding to each of the adjustment levels in the plurality of adjustment levels, and at least two voltage adjustment values corresponding to each adjustment level,

The comparing the voltage acquisition data in the monitoring data with the first threshold value, and in response to the voltage acquisition data being smaller than the first threshold value, determining a voltage value to be adjusted in the dynamic adjustment table and generating the first instruction, further comprises: determining a current first threshold corresponding to the current adjustment level based on the current adjustment level of the partition; comparing the voltage acquisition data with the current first threshold; and responding to the voltage acquisition data being smaller than the current first threshold value, determining a voltage value to be adjusted of the partition based on a current voltage adjustment value corresponding to the current adjustment level, and generating the first instruction of the partition.

In this embodiment, according to the voltage acquisition data of the partitions, and the adjustment level in the dynamic adjustment table, the first threshold value of each adjustment level, and at least two voltage adjustment values, an adjustment frame and an adjustment basis for the voltage of each partition are formed, so that the dynamic adjustment unit determines the first instruction according to the acquired monitoring data and the dynamic adjustment table in a table look-up manner, thereby realizing rapid, flexible and convenient dynamic adjustment of the voltage of each partition.

In an alternative embodiment, the dynamic adjustment table includes a plurality of adjustment tables corresponding to each partition one to one; and generating an adjustment instruction of the partition according to a dynamic adjustment table in response to the monitoring data of the partition sensor of the partition not meeting the preset monitoring threshold requirement, and further comprising: and generating the first instruction in the adjustment instructions of the partition according to the adjustment form corresponding to the partition in response to the monitoring data of the partition sensor of the partition not meeting the preset monitoring threshold requirement.

In an alternative embodiment, the method further comprises: the output voltage of the power chip is determined according to a first instruction of at least one partition.

In the dynamic adjustment process triggered by the monitoring data of one partition, the embodiment generates the first instruction for adjusting the power chip according to the monitoring data of the partition, and generates the first instruction transmitted to the power chip according to the first instructions generated by the monitoring data of other partitions, so that the dynamic adjustment of the voltage is realized under the condition that each partition shares one power chip.

In an alternative embodiment, said determining said output voltage of said power supply chip according to a first instruction of at least one of said partitions further comprises: determining at least one voltage value to be adjusted, wherein the at least one voltage value to be adjusted corresponds to a first instruction of the at least one partition; determining a maximum voltage value of the at least one voltage value to be adjusted, and determining the maximum voltage value as the output voltage of the power supply chip.

According to the embodiment, the first instruction is generated according to the voltage acquisition data of the partitions, and the maximum voltage value is selected and used as the output voltage of the power chip according to the first instructions generated by other partitions, so that the power chip is adjusted under the condition that each partition of the single chip can be ensured to be in a normal working voltage, namely, the power chip can supply voltage signals to each partition simultaneously by selecting the maximum voltage value, and each partition can be ensured to be in a normal working state.

In an alternative embodiment, the method further comprises: receiving a droop interrupt, wherein the droop interrupt is generated when a droop signal generated according to the adjustment of the monitoring data to the power chip does not meet the preset droop threshold value requirement; and adjusting the output voltage of the power supply chip according to a dynamic adjustment table based on the droop interrupt.

In an alternative embodiment, the monitoring threshold further includes a third threshold corresponding to the voltage acquisition data and a fourth threshold corresponding to the temperature acquisition data, the method further comprising: comparing the voltage acquisition data in the monitoring data with the third threshold value, determining a preset voltage value as the voltage value to be adjusted of the partition and generating the first instruction in response to the voltage acquisition data being larger than the third threshold value; and/or the number of the groups of groups,

comparing the temperature acquisition data in the monitoring data with the fourth threshold, determining a preset clock frequency trend as the frequency trend to be adjusted of the partition and generating the second instruction, and determining the preset voltage value as the voltage value to be adjusted of the partition and generating the first instruction in response to the temperature acquisition data being larger than the fourth threshold.

In this embodiment, in order to further avoid the influence of the IR drop on the operation performance of each partition of each single-chip of the on-chip system, fuse protection is set in the adjustment process of the dynamic adjustment unit, specifically, the fuse detection is performed on the collected voltage collection data and the temperature collection data through the third threshold and the fourth threshold serving as fuse thresholds, when any one of the temperature collection data and the voltage collection data of one partition exceeds the fuse threshold, the power management chip is adjusted to set the frequency of the partition to a frequency protection value through the preset clock frequency trend, or the power chip is adjusted to set the voltage of the partition to a voltage protection value through the preset voltage value, so that each partition of each single-chip of the on-chip system is protected, the hardware operation unit is ensured to be in a safe working environment, and the service life of the on-chip system is effectively improved.

A third embodiment of the present invention provides a system-on-chip comprising the system-on-chip of the first embodiment.

The chip of the embodiment comprises the system on chip, based on the hardware architecture of the system on chip, the monitoring data of each partition of the single chip is collected through the dynamic adjusting unit, the power supply chip matched with the single chip is adjusted according to the monitoring data, and the system on chip which dynamically adjusts the voltage according to the monitoring data of each partition on the basis that a plurality of partitions of one single chip share one power supply chip is formed, so that the dynamic adjustment of the voltage frequency can be rapidly, flexibly and conveniently carried out, the fluctuation of the power supply voltage caused by IR voltage drop is relieved, and the operation performance of the system on chip is effectively improved.

A fourth embodiment of the invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method as described in the second embodiment.

A fifth embodiment of the invention provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method according to the second embodiment when executing the program.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a block diagram of a system on a chip according to an embodiment of the invention;

FIG. 2 shows a block diagram of a system on a chip according to another embodiment of the invention;

FIG. 3 shows a flow chart of a dynamic adjustment method according to an embodiment of the invention;

FIG. 4 shows a block diagram of a system on a chip according to another embodiment of the invention;

FIG. 5 shows a flow chart of a dynamic adjustment method according to another embodiment of the invention;

FIG. 6 shows a block diagram of a system on a chip according to another embodiment of the invention;

fig. 7 is a schematic structural diagram of a computer device according to another embodiment of the present invention.

Detailed Description

In order to more clearly illustrate the present invention, the present invention will be further described with reference to preferred embodiments and the accompanying drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.

In view of the above, the inventors have proposed through a great deal of research and experiments that the reason why the operation chip is unstable using the dynamic voltage frequency adjustment (DVFS) technique is that: with the increasing integration of the operation chip, the fluctuation of the power supply voltage is larger and larger, and the fluctuation of the power supply voltage is mainly caused by the IR drop (IR drop) caused by the parasitic resistance of the current flowing through the power supply network, namely, the IR drop of the operation chip easily affects the operation performance of the chip, so that the stability performance of the chip is greatly reduced. In other words, the operation chip has more stringent requirements for the dynamic voltage frequency adjustment technology due to the influence of the IR drop.

In accordance with the above-described problems and the causes thereof, as shown in fig. 1, an embodiment of the present application provides a system on a chip, comprising: at least one chip, the chip comprising: a single wafer comprising a plurality of partitions, each of the partitions comprising a partition sensor; the power chip is used for providing output voltage for the single chip; and the dynamic adjustment unit is used for adjusting the output voltage of the power supply chip according to the monitoring data of each partition sensor.

In a specific embodiment, each single chip includes a dynamic adjustment unit, where the dynamic adjustment unit includes a configuration unit storing a dynamic adjustment table and an adjustment controller corresponding to each partition one by one, where the dynamic adjustment table may be an independent adjustment table, or may include a plurality of adjustment tables corresponding to each partition one by one, and the plurality of adjustment tables may be the same table or different tables.

In this embodiment, the monitoring data of the present partition is collected by the adjustment controller of each partition, and the power supply chip matched with the single chip is adjusted according to the monitoring data and the dynamic adjustment table, so that on the basis that a plurality of partitions of a single chip share one power supply chip, when the monitoring data of each partition does not meet the preset monitoring threshold requirement, dynamic adjustment of the voltage is performed, specifically, the adjusted voltage value is obtained from the dynamic adjustment table according to the monitoring data which does not meet the monitoring threshold and the power supply chip is adjusted, so that the power supply voltage to each partition is adjusted by the power supply chip. The power supply chip is dynamically adjusted to supply voltage to the single chip according to the adjustment requirements of different partitions by triggering the adjustment of the power supply chip through the monitoring data of each partition, so that the fluctuation of the power supply voltage caused by IR voltage drop is relieved, and the operation performance of the system on chip is effectively improved.

In this embodiment, as shown in fig. 1, the system on a chip includes a single chip, a dynamic adjustment unit and a power chip that are matched with the single chip.

Wherein the single die (die) is a block of semiconductor material formed by dicing a wafer, integrated circuits formed on Electronic Grade Silicon (EGS) or other semiconductor (e.g., gaAs) material by a process such as photolithography. The integrated circuits on the single chip are further partitioned according to functional requirements or circuit design requirements, for example, one single chip comprises 4 partitions, each partition comprises partition sensors for detecting the working state of the corresponding partition, for example, each partition comprises 8 processing cores, each processing core comprises sensors for detecting temperature and voltage, and each partition determines the working state of the partition according to the detected temperature and the detected voltage of each processing core. For example, a maximum value of a detected temperature output from a sensor for detecting a temperature of each processing core in each partition is used as temperature sampling data of the partition, a minimum value of a detected voltage output from a sensor for detecting a voltage of each processing core in each partition is used as voltage sampling data of the partition, and the temperature sampling data and the voltage sampling data of the partition are transmitted to the dynamic adjustment unit.

The power chip supplies power to the single chip, specifically, the power chip provides voltage signals for each partition of the single chip, in this embodiment, one single chip corresponds to one power chip, that is, the 4 partitions of one single chip all supply power through one power chip, so the voltage signals of each partition of the single chip are the same.

The dynamic adjustment unit uses dynamic adjustment technology to dynamically adjust the working voltage of the chip according to the real-time load demand of the single chip. In this embodiment, the dynamic adjustment unit includes a configuration unit storing a dynamic adjustment table and an adjustment controller corresponding to each partition one by one. And the adjustment controller of the dynamic adjustment unit performs data processing based on the temperature sampling data and the voltage sampling data of the partition, determines an adjustment value of the voltage according to the dynamic adjustment table, and adjusts the voltage of the partition by sending an instruction to the power chip.

In an alternative embodiment, the monitoring data comprises voltage acquisition data, and the monitoring threshold comprises a first threshold corresponding to the voltage acquisition data; the adjustment controller is configured to: comparing the voltage acquisition data in the monitoring data with the first threshold value, and responding to the fact that the voltage acquisition data is smaller than the first threshold value, determining a voltage value to be adjusted in the dynamic adjustment table and generating the first instruction.

In this embodiment, when the voltage acquisition data is smaller than the corresponding first threshold value, the adjustment controller performs dynamic adjustment, obtains a voltage value to be modified according to the dynamic adjustment table, and generates a first instruction transmitted to the voltage chip through the voltage value, so that the power supply voltage to each partition of the single chip is modified through the voltage chip. In other words, the embodiment triggers the dynamic adjustment flow according to the comparison result of the voltage acquisition data of each partition and the first threshold value, determines the adjustment instruction through the dynamic adjustment table and adjusts the output voltage of the power supply chip in the form of outputting the first instruction, so that the dynamic adjustment is triggered by the fact that the monitoring data of each partition does not meet the monitoring threshold value requirement, and the method has the characteristics of being rapid, flexible and convenient.

In another alternative embodiment, the monitoring data includes temperature acquisition data, and the monitoring threshold includes a second threshold corresponding to the temperature acquisition data; the adjustment controller is configured to: comparing the temperature acquisition data in the monitoring data with the second threshold value, and responding to the fact that the temperature acquisition data is larger than the second threshold value, determining the voltage value to be adjusted in the dynamic adjustment table and generating the first instruction. In an implementation embodiment, the same second threshold may be set for multiple partitions of the single wafer, or a corresponding second threshold may be set for each partition separately.

In this embodiment, when the temperature acquisition data is greater than the corresponding second threshold value, the adjustment controller performs dynamic adjustment, obtains a voltage value to be modified according to the dynamic adjustment table, and generates a first instruction transmitted to the voltage chip through the voltage value, thereby modifying the power supply voltage to each partition of the single chip through the voltage chip. In other words, the embodiment triggers the dynamic adjustment flow according to the comparison result of the temperature acquisition data of each partition and the second threshold value, determines the adjustment instruction through the dynamic adjustment table and adjusts the output voltage of the power supply chip in the form of outputting the first instruction, so that the dynamic adjustment is triggered by the fact that the monitoring data of each partition does not meet the monitoring threshold value requirement, and the method has the characteristics of being rapid, flexible and convenient.

In an alternative embodiment, considering the frequency adjustment requirements for each partition, as shown in fig. 2, the chip further comprises: the power management unit is used for outputting clock frequency to the single chip; and the dynamic adjustment unit is also used for adjusting the clock frequency output by the power management unit according to the monitoring data of each partition sensor. In this embodiment, the power management unit provides a frequency for a single chip, and specifically, the power management unit provides clock signals for each partition of the single chip.

The dynamic adjustment unit realizes dynamic voltage frequency adjustment (Dynamic Voltage Frequency Scaling, DVFS) of the system on chip through the power chip and the power management unit, thereby dynamically adjusting the operating frequency and operating voltage of the chip according to the real-time load demand of the single chip. Specifically, the dynamic voltage frequency adjustment unit comprises a configuration unit storing a dynamic adjustment table and adjustment controllers corresponding to all the partitions one by one. The adjusting controller of the dynamic voltage frequency adjusting unit performs data processing based on the temperature sampling data and the voltage sampling data of the partition, and determines adjusting values of voltage and frequency according to an adjusting form to adjust the power chip and the power management unit, so that the voltage and the frequency of the partition are adjusted.

Further, the power management unit is further configured to: and determining the clock frequency of the partition adjusted corresponding to the second instruction according to the second instruction.

In this embodiment, when the temperature acquisition data is greater than the corresponding second threshold, the adjustment controller performs dynamic adjustment, obtains the clock frequency trend to be modified according to the dynamic adjustment table, and generates the second instruction transmitted to the power management unit through the clock frequency trend, so that the clock frequency of each partition of the single chip is modified through the power management unit. It is worth to describe that the power management unit adjusts the clock frequency of each partition according to the temperature acquisition data of each partition. The embodiment further determines the adjusting instruction through the dynamic adjusting table and adjusts the clock frequency trend of the power management unit in a form of outputting the second instruction through the power management unit matched with the single chip, and the power management unit can determine the adjusted clock frequency according to the received clock frequency trend and the configured frequency adjusting strategy, outputs the adjusted clock frequency to the partition corresponding to the second instruction, dynamically adjusts the power management unit according to the monitoring data of the partition sensor of each partition, and accordingly dynamically adjusts the clock frequency of each partition.

In this embodiment, the dynamic adjustment table includes a plurality of adjustment tables corresponding to each partition one by one, where the plurality of adjustment tables may be the same table or different tables, and when each adjustment table is the same table, each partition dynamically adjusts the working voltage and the working frequency according to the same adjustment table; when each adjustment form is different forms, each partition can dynamically adjust the working voltage and the working frequency more flexibly according to the corresponding adjustment form.

In an alternative embodiment, the dynamic adjustment unit comprises: an adaptive voltage regulating unit configured to: and determining the output voltage output by the power chip according to a first instruction generated by at least one adjustment controller.

In one specific example, as shown in fig. 3, the description is given of performing one dynamic voltage frequency adjustment:

the first step is to acquire the monitoring data collected by the partition sensors of each partition of the chip.

In this embodiment, the adjustment controller of each partition of the single-chip obtains the monitoring data of the corresponding partition according to a preset time interval, as shown in fig. 1 and fig. 2, and the adjustment controller of the first partition of the single-chip obtains the monitoring data of the partition sensor of the first partition. Specifically, the adjustment controller acquires voltage acquisition data and temperature acquisition data of the first partition through a partition sensor of the first partition.

For example, a maximum value (for example, 65 ℃) of the detected temperatures of the respective processors of the first partition is taken as temperature acquisition data, and a minimum value (for example, 0.53V) of the detected voltages of the respective processors of the first partition is taken as voltage acquisition data. The partition sensor of the first partition outputs the sensing value to the corresponding adjustment controller in the dynamic adjustment unit, and the specific transmission mode is not limited in the application.

In order to ensure that each partition of the single crystal wafer works in a suitable voltage and frequency environment, the embodiment controls the dynamic adjustment unit to automatically adjust the voltage and frequency at fixed time through a preset time interval, that is, the adjustment controller corresponding to each partition in the dynamic adjustment unit repeatedly adjusts the voltage and frequency according to the preset time interval. The preset time interval is not particularly limited in the present application, and a person skilled in the art should select an appropriate time interval according to actual application requirements, which is not described herein.

And step two, according to the monitoring data, adjusting the output voltage of the power supply chip to each partition, and adjusting the clock frequency of the power supply management unit respectively output to each partition.

In this embodiment, first, the adjustment controller compares the monitoring data with the monitoring threshold value, and generates a comparison result. Specifically, the voltage acquisition data is compared with a first threshold value, the temperature acquisition data is compared with a second threshold value, and a comparison result is generated.

To ensure the operational performance of the processors of the first partition, an adjustment is made when any of the monitored data does not meet a threshold. For example, when the temperature acquisition data of the first partition is greater than the second threshold value, or when the voltage acquisition data of the first partition is smaller than the first threshold value, the working state and the calculation performance of each partition of each single crystal plate can be further improved by limiting the adjustment time.

In this embodiment, as shown in table 1, the dynamic adjustment table may be an independent adjustment table of a single chip; the system may include a plurality of adjustment forms corresponding to each partition, each of the adjustment forms being the same form; i.e. each partition uses the same adjustment table as the adjustment basis. Each adjustment form stores configuration items including 11 adjustment levels (levels) from Level0 to Level10 and each Level, the configuration items of each Level including: the minimum voltage threshold value Min Volt (i.e. the first threshold value) of the level, the clock frequency PP, the multi-stage voltage adjustment values voltage0, voltage1, voltage2, different levels represent the minimum voltage value Min Volt corresponding to the same or different voltage values (voltage 0-2) output to each partition under different clock frequencies PP, and the adjustment form further comprises a plurality of reserved settings (Reserve) so as to facilitate expansion application.

It should be noted that, when determining the adjustment level, the adjustment device further includes a preset adjustment range, and if the adjustment step is adjusted up or down to exceed the adjustment range, the boundary value of the adjustment range is used as the adjustment level, that is, the adjustment level cannot exceed the adjustment range. For example, when the adjustment level is adjusted up, the adjustment level is the highest adjustment level of the adjustment range when the adjustment level exceeds the highest adjustment level of the adjustment range, whereas when the adjustment level is adjusted down, the adjustment level is the lowest adjustment level of the adjustment range when the adjustment level exceeds the lowest adjustment level of the adjustment range. When the voltage acquisition data is smaller than the minimum voltage value, the voltage adjustment value is set to be a multi-stage voltage adjustment value, and if the voltage is still required to be adjusted upwards when the dynamic adjustment of the voltage frequency is performed again, the voltage adjustment value is set to be a voltage adjustment value of a higher stage.

In this embodiment, the current adjustment levels of the 4 partitions are the same and are all Level7, and the voltage adjustment values are all voltage0, at this time, the output voltage of the power supply chip to the 4 partitions is 0.68V, and the clock frequency of the voltage management unit to the 4 partitions is 3.2.

TABLE 1 adjustment form

In the normal working process, the dynamic adjustment unit controls the power supply chip to output working voltage to each partition of the single chip and controls the power supply management unit to output clock frequency to each partition respectively according to real-time voltage acquisition data or temperature acquisition data acquired by the partition sensors of each partition.

Specifically, the adjustment controller 2 corresponding to the second partition acquires that the temperature acquisition data acquired by the partition sensor is 65 ℃, and the adjustment controller judges that the acquired 65 ℃ is greater than the second threshold 60 ℃, namely, the acquired 65 ℃ does not meet the preset monitoring threshold requirement.

And secondly, the adjustment controller monotonically adjusts the output voltage of the power supply chip according to the comparison result, the monitoring data and the corresponding adjustment table, and outputs clock frequency trend to the power supply management unit.

In this embodiment, according to the current adjustment step distance of the adjustment form being 1, it is determined that the second partition is adjusted downward from level7 to level6, that is, the clock frequency trend of the second partition is adjusted downward, that is, 3.1 needs to be adjusted, and a second instruction is generated according to the clock frequency trend and sent to the power management unit (the power management unit may determine that the adjusted clock frequency is 3.1 according to the clock frequency trend) to adjust the clock frequency of the second partition. It should be noted that, at this time, the clock frequencies of the first partition, the third partition and the fourth partition are unchanged and still 3.2, and the power management unit provides the clock frequencies of 3.2 to the first partition, the third partition and the fourth partition.

And then, according to the regulation form, the voltage regulation value is regulated from 0.68V of voltage0 of level7 to 0.65V of voltage0 of level 6. Based on the adaptive voltage regulating unit, the regulating controller of the second partition sends the voltage value of 0.65V to the adaptive voltage regulating unit; considering that each partition of the single chip shares one power chip, and each processor of each partition needs to obtain an operating voltage running in a normal operating state, at this time, according to a voltage adjustment value that the first partition once transmits to the adaptive voltage adjustment unit according to the collected voltage collection data, and a voltage adjustment value that the third partition once transmits to the adaptive voltage adjustment unit according to the collected voltage collection data, and a voltage adjustment value that the fourth partition once transmits to the adaptive voltage adjustment unit according to the collected voltage collection data, the adaptive voltage adjustment unit determines a final voltage adjustment value and generates a first instruction to adjust the power chip. Specifically, the voltage adjustment values of the historical first instructions sent to the adaptive voltage adjustment unit by the first partition, the third partition and the fourth partition are all 0.68V; in consideration of the need to meet the power supply requirements of each partition, the adaptive voltage regulating unit takes the maximum voltage regulating value in the four partitions as a final voltage regulating value and generates a first instruction to transmit to the power supply chip.

It should be noted that, in this embodiment, in order to further improve the working state and the operation performance of each partition of the single-chip, when the voltage and the frequency are adjusted upwards, the voltage is adjusted first and then the frequency is adjusted, so as to ensure that the voltage signal received by each processor of the second partition when the frequency is adjusted can support the adjusted frequency, thereby avoiding that each processor cannot normally operate under the adjusted frequency due to lower voltage signal; similarly, when the voltage and the frequency are adjusted downwards, the frequency is adjusted first and then the voltage is adjusted, so that each processor of the second partition is ensured to reduce the voltage signal after the frequency is adjusted, and each processor can always normally operate under different frequencies in the adjustment process.

At this time, the current adjustment level of the first partition, the third partition and the fourth partition is level7, the clock frequency is 3.2, the voltage adjustment value is 0.68V of voltage0, and the power supply of the obtained power supply chip is 0.68V; the current regulation level of the second partition is level6, the clock frequency is 3.1, the voltage regulation value is voltage0, but the obtained power supply of the power supply chip is 0.68V. That is, each partition can be configured with different adjustment levels, clock frequencies and voltage adjustment values according to different calculation power demands, but a plurality of partitions based on a single chip share one power chip, and the working voltages obtained by the partitions are the same.

Thus, one-time dynamic adjustment is completed. According to the hardware architecture of the system on chip, the monitoring data of each partition of the single chip is collected through the dynamic adjusting unit, the voltage adjusting value of the partition and the historical voltage adjusting values of other partitions are decided and the final voltage adjusting value is determined through the self-adaptive voltage adjusting unit included in the dynamic adjusting unit, and then the power chip is adjusted according to the final voltage adjusting value in a mode of sending instructions to the power chip to update the voltage of each partition, so that the dynamic adjustment of the voltage is carried out under the condition that each partition shares one power chip; the frequency adjustment value of the partition is obtained according to the temperature acquisition data acquired by the partition and the corresponding dynamic adjustment form, and the power management unit is adjusted according to the frequency adjustment value in a mode of sending instructions to the power management unit so as to update the frequency of the corresponding partition; thus realizing dynamic adjustment of the voltage frequency of each partition of each chip. In other words, the on-chip system of the embodiment can dynamically adjust the voltage according to the monitoring data of each partition on the basis that a plurality of partitions of a single chip share one power chip, and can quickly, flexibly and conveniently dynamically adjust the voltage frequency, thereby relieving the power voltage fluctuation caused by IR voltage drop and effectively improving the operation performance of the on-chip system.

In an alternative embodiment, as shown in fig. 4, the system on chip further comprises a droop control unit connected to the dynamic adjustment unit, the droop control unit being configured to: generating a droop signal based on the dynamic adjustment unit according to the adjustment of the monitoring data to the power chip, and sending a droop interrupt to the dynamic adjustment unit in response to the droop signal not meeting a preset droop threshold value requirement;

the dynamic adjustment unit is further configured to: receiving a droop interrupt sent by the droop control unit; adjusting the output voltage of the power chip.

In this embodiment, in combination with the adaptive clock distribution unit of the system on chip, after the dynamic adjustment unit dynamically adjusts the voltage and the frequency of each partition of the single chip, the droop control unit simulates and generates a droop signal of the working voltage of each partition, compares the droop signal by using the droop threshold value, and sends a droop interrupt to the dynamic adjustment unit to trigger the dynamic adjustment of the working voltage and the working frequency when the droop signal is smaller than the droop threshold value.

In a specific example, as shown in fig. 4 and 5, the dynamic adjustment of the voltage frequency by the second partition is still illustrated as an example.

S10: the adjustment controller is calibrated using an adaptive clock distribution unit.

In this embodiment, before the dynamic adjustment of the voltage frequency is performed, the existing adaptive clock distribution unit of the system on chip is used to perform calibration, that is, the adaptive clock distribution unit is used to verify the dynamic adjustment table stored in the configuration unit of the dynamic adjustment unit, so as to improve the operation performance of the system on chip.

It should be noted that the adaptive clock distribution unit is not particularly limited in the present application, and a person skilled in the art should select an appropriate adaptive clock distribution unit according to the actual application requirement, which is not described herein.

S20: and the adjustment controller acquires monitoring data acquired by the partition sensors of each partition of the chip.

In this embodiment, the adjustment controller acquires the monitoring data of the partition, as shown in fig. 4, and the adjustment controller corresponding to the second partition of the single-chip acquires the monitoring data of the partition sensor of the second partition. In this embodiment, as shown in table 2-table 5, the dynamic adjustment table includes a plurality of adjustment tables corresponding to each partition, and each adjustment table is a different table; that is, each partition uses an adjustment table conforming to the voltage frequency adjustment rule of the partition as an adjustment basis. The specific form structure is the same as that of the foregoing embodiment, and will not be described in detail herein.

TABLE 2 adjustment form for first partition

Level	Min Volt	PP	Voltage2	Voltage1	Voltage0
						level0	0.50	BOOT	0.57	0.56	0.55
level1	0.50	1.0	0.57	0.56	0.55
						level2	0.53	2.0	0.62	0.61	0.60
level3	0.54	2.1	0.63	0.62	0.61
						level4	0.55	2.2	0.64	0.63	0.62
level5	0.58	3.0	0.66	0.64	0.63

TABLE 3 adjustment form for second partition

Level	Min Volt	PP	Voltage2	Voltage1	Voltage0
						level0	0.50	BOOT	0.57	0.56	0.55
level1	0.50	1.0	0.57	0.56	0.55
						level2	0.52	2.0	0.63	0.62	0.61
level3	0.54	2.1	0.64	0.63	0.62
						level4	0.56	2.2	0.66	0.64	0.63
level5	0.59	3.0	0.67	0.66	0.64

TABLE 4 adjustment form for third partition

Level	Min Volt	PP	Voltage2	Voltage1	Voltage0
						level0	0.51	BOOT	0.58	0.57	0.56
level1	0.51	1.0	0.58	0.57	0.56
						level2	0.52	2.0	0.63	0.62	0.61
level3	0.54	2.1	0.64	0.63	0.62
						level4	0.55	2.2	0.65	0.64	0.63
level5	0.58	3.0	0.66	0.64	0.62

TABLE 5 adjustment form for fourth partition

Level	Min Volt	PP	Voltage2	Voltage1	Voltage0
						level0	0.50	BOOT	0.57	0.56	0.55
level1	0.50	1.0	0.57	0.56	0.55
						level2	0.52	2.0	0.61	0.60	0.59
level3	0.53	2.1	0.62	0.61	0.60
						level4	0.54	2.2	0.65	0.64	0.62
level5	0.55	3.0	0.67	0.65	0.63

In this embodiment, the current adjustment levels of the 4 partitions are different, where the current adjustment level of the first partition is level3, the Voltage adjustment value is Voltage1, the current adjustment level of the second partition is level2, the Voltage adjustment value is Voltage0, the current adjustment level of the third partition is level3, the Voltage adjustment value is Voltage0, and the current adjustment level of the fourth partition is level4, the Voltage adjustment value is Voltage1. Since the 4 partitions share one power chip, the output voltage of the power chip output to the 4 partitions is 0.62V, and the clock frequencies of the power management unit output to the first partition to the fourth partition are 2.1, 2.0, 2.1 and 2.2 in sequence.

S30: the adjustment controller compares the monitoring data with a preset monitoring threshold value, adjusts the output voltage of the power supply chip according to a comparison result, the monitoring data and a corresponding adjustment form, and performs handshake communication with the self-adaptive clock distribution unit.

In the actual operation process, the adjustment controller of the second partition acquires that the Voltage acquisition data acquired by the partition sensor is 0.5V, the first threshold value of the level2 of the current adjustment level of the second partition is 0.52V, and the adjustment controller judges that the acquired 0.5V is smaller than the first threshold value of 0.52V, that is, does not meet the preset monitoring threshold requirement, and then the Voltage of the second partition is adjusted to be Voltage1 of the level2, that is, the adjustment Voltage value is 0.62V according to the adjustment form of the second partition in table 3.

Based on the adaptive voltage regulating unit, the second partition sends the voltage value of 0.63V to the adaptive voltage regulating unit; considering that each partition of the single chip shares one power chip, and each processor of each partition needs to obtain an operating voltage running in a normal operating state, at this time, according to a voltage adjustment value that the first partition once transmits to the adaptive voltage adjustment unit according to the collected voltage collection data, and a voltage adjustment value that the third partition once transmits to the adaptive voltage adjustment unit according to the collected voltage collection data, and a voltage adjustment value that the fourth partition once transmits to the adaptive voltage adjustment unit according to the collected voltage collection data, the adaptive voltage adjustment unit determines a final voltage adjustment value and generates a first instruction to adjust the power chip. Specifically, the voltage adjustment values of the historical first instructions sent to the adaptive voltage adjustment unit by the first partition, the third partition and the fourth partition are respectively 0.62V, 0.62V and 0.64V; in consideration of the need to meet the power supply requirements of each partition, the adaptive voltage regulating unit takes the maximum voltage regulating value of 0.64V in the four partitions as a final voltage regulating value and generates a first instruction to transmit to the power supply chip.

At this time, the current adjustment levels of the first partition, the second partition, the third partition and the fourth partition are unchanged, the Voltage adjustment values of the first partition, the third partition and the fourth partition are unchanged, the Voltage adjustment value of the second partition becomes Voltage2, and the output Voltage output by the power chip to each partition is 0.64V.

S40: the droop control unit simulates and generates a droop signal of the working voltage of each partition after the dynamic adjustment unit dynamically adjusts the voltage and the frequency of each partition of the single crystal plate through the droop control unit of the self-adaptive clock distribution unit, judges the droop signal by utilizing a droop threshold value, and sends a droop interrupt to the dynamic adjustment unit to trigger the dynamic adjustment of the working voltage and the working frequency under the condition that the droop signal is smaller than the droop threshold value.

When the dynamic adjustment unit completes the voltage adjustment on the second partition, the droop control unit of the adaptive clock distribution unit simulates the working voltage of the second partition, in this embodiment, the droop signal generated by the droop control unit is 0.51V, the droop threshold is 0.52V, the droop signal 0.51V is less than the droop threshold 0.52V, and the droop control unit sends a droop interrupt to the dynamic adjustment unit. The dynamic adjustment unit dynamically adjusts the Voltage of the second partition to be Voltage2 of level2 according to the received sagging interrupt, namely, adjusts the Voltage value to be 0.63V. In consideration of the need to meet the power supply requirements of each partition, the adaptive voltage adjustment unit takes the maximum voltage adjustment value 0.64V of the voltage adjustment values (0.62V, 0.63V, 0.62V, 0.64V) of the four partitions as a final voltage adjustment value and generates a first instruction to transmit to the power supply chip so that the output voltage of the power supply chip to each partition is 0.64V.

When the dynamic adjusting unit completes the voltage adjustment of the second partition, the droop control unit of the adaptive clock distribution unit simulates the working voltage of the second partition, at this time, the droop signal generated by the droop control unit is 0.60V and is greater than the droop threshold value of 0.52V, and the droop control unit does not act any more.

In this embodiment, in combination with the droop control unit of the adaptive clock distribution unit of the system on chip, after the dynamic adjustment unit adjusts the power supply chip, the droop control unit generates a droop signal, and uses the droop threshold to determine the droop signal, if not, the droop control unit generates a transmission interrupt to the dynamic adjustment unit and jumps to S30 to trigger the dynamic adjustment unit to adjust the voltage of each partition and adjust the frequency of each partition, thereby further improving the accuracy of adjusting the voltage frequency of each partition of each single-crystal chip of the system on chip, alleviating the power supply voltage fluctuation caused by IR drop, and effectively improving the operation performance of the system on chip.

Finally, S50: and the adjustment controller judges whether the frequency and/or the voltage of the partition are updated, and if the frequency and/or the voltage of the partition are updated, the step is skipped to S10.

In this embodiment, based on handshake communication between the adjustment controller and the adaptive clock distribution unit, after the adjustment controller completes dynamic adjustment of the voltage and the frequency of the second partition, the adaptive clock distribution unit is used again to perform calibration after the frequency update, or after the voltage update, or after both the frequency and the voltage update, by updating and judging any one of the frequency and the voltage in the partition, so as to further improve the accuracy of adjusting the voltage frequency of each partition of each single chip of the system on chip.

Specifically, as shown in fig. 5, after the second partition completes the dynamic update of the voltage frequency, if there is an updated voltage or frequency or an updated voltage and frequency in the second partition, the adaptive clock distribution unit is used for calibration; and if the voltage and the frequency of the second partition are not updated, dynamically adjusting the voltage and the frequency at the next moment according to a preset time interval.

So far, based on the self-adaptive clock distribution unit and the droop control unit thereof, one-time dynamic adjustment is completed. The embodiment combines the self-adaptive clock distribution unit of the system on chip, performs calibration by utilizing the self-adaptive clock distribution unit before dynamically adjusting the voltage frequency, performs handshake communication with the self-adaptive clock distribution unit in the process of dynamically adjusting the voltage frequency, performs re-judgment by using the sagging signal generated by the sagging control unit and a preset sagging threshold value after dynamically adjusting the voltage frequency, starts dynamic adjustment again if the sagging threshold value is not met, and performs calibration again by utilizing the self-adaptive clock distribution unit finally, thereby further improving the adjustment accuracy of the voltage frequency of each partition of each single chip of the system on chip, relieving the power voltage fluctuation caused by IR voltage drop and effectively improving the operation performance of the system on chip.

To further enhance the normal operation of the individual single-chip chips of the system-on-chip, in an alternative embodiment, the monitoring threshold further comprises a third threshold value corresponding to the voltage acquisition data and a fourth threshold value corresponding to the temperature acquisition data, the method further comprising: comparing the voltage acquisition data in the monitoring data with the third threshold value, determining a preset voltage value as the voltage value to be adjusted of the partition and generating the first instruction in response to the voltage acquisition data being larger than the third threshold value; and/or comparing the temperature acquisition data in the monitoring data with the fourth threshold value, determining a preset clock frequency trend as the frequency trend to be adjusted of the partition and generating the second instruction, and determining the preset voltage value as the voltage value to be adjusted of the partition and generating the first instruction in response to the temperature acquisition data being larger than the fourth threshold value.

In this embodiment, in order to further avoid the influence of the IR drop on the operation performance of each partition of each single chip of the system on chip, a fuse protection is set during the adjustment of the dynamic adjustment unit. Specifically, the collected temperature collection data and voltage collection data are subjected to fusing detection through a fusing threshold, when any one of the temperature collection data and the voltage collection data of one partition exceeds the fusing threshold, for example, when the temperature collection data of a first partition is larger than a fourth threshold of the temperature fusing threshold, or when the voltage collection data is larger than a third threshold of the voltage fusing threshold, or when the temperature collection data is larger than the fourth threshold and the voltage collection data is larger than the third threshold, a second instruction is directly sent to a power management unit to reduce the frequency of the first partition to a preset clock frequency. When the temperature acquisition data is larger than a fourth threshold value, a first instruction is sent to the power chip to reduce the voltage of each partition of the single chip to a preset voltage value, so that each partition of each single chip of the system on chip is protected, the hardware operation unit is ensured to be in a safe working environment, and the service life of the system on chip is effectively prolonged.

In an alternative embodiment, as shown in fig. 6, the system on a chip includes two single chips, and a dynamic adjustment unit, a power management unit, and a power chip are associated with each single chip.

In this embodiment, the single-chip 1 includes 4 partitions, and a dynamic adjustment unit 1, a power management unit 1 and a power chip 1 corresponding to the single-chip 1, where the dynamic adjustment unit 1 compares the collected monitoring data of each partition of the single-chip 1 with a monitoring threshold value to generate a comparison result, and generates a first instruction sent to the power chip 1 and a second instruction sent to the power management unit 1 according to the comparison result, the monitoring data and the dynamic adjustment form corresponding to the first partition of the dynamic adjustment unit 1, and finally sends the instructions to the power chip 1 and the power management unit 1, respectively, so as to implement frequency adjustment of each partition of the single-chip 1 by the power management unit 1, and unified adjustment of voltages of each partition of the single-chip 1 by the power chip 1 to implement voltage adjustment of each partition of the single-chip 1 sharing the power chip 1. The specific implementation manner of this embodiment is the same as that of the foregoing embodiment, and will not be described herein.

Similarly, the single chip 2 includes 4 partitions, and a dynamic adjustment unit 2, a power management unit 2, and a power chip 2 corresponding to the single chip 2. The dynamic adjustment unit 2 compares the collected monitoring data of each partition of the single crystal wafer 2 with a monitoring threshold value to generate a comparison result, generates a first instruction sent to the power chip 2 and a second instruction sent to the power management unit 2 according to the comparison result, the monitoring data and a dynamic adjustment form corresponding to the first partition of the dynamic adjustment unit 2, and finally sends the instructions to the power chip 2 and the power management unit 2 respectively, so that frequency adjustment of each partition of the single crystal wafer 2 by the power management unit 2 is realized, and voltage adjustment of each partition of the single crystal wafer 2 by the power chip 2 is uniformly adjusted to realize voltage adjustment of each partition of the single crystal wafer 2 sharing the power chip 2. The specific implementation manner of this embodiment is the same as that of the foregoing embodiment, and will not be described herein.

It should be noted that, in this embodiment, the description is made with the embodiment including two single chips and the matched dynamic adjustment unit, the power management unit and the power chip, but the number of the single chips is not limited in this embodiment, and those skilled in the art should set single chip data of the system on chip according to actual application requirements, which is not described herein.

Corresponding to the system on chip provided by the above embodiments, an embodiment of the present application further provides a dynamic adjustment method applied to the system on chip, and since the dynamic adjustment method provided by the embodiment of the present application corresponds to the system on chip provided by the above embodiments, the previous embodiment is also applicable to the dynamic adjustment method provided by the present embodiment, which is not described in detail in the present embodiment.

As shown in fig. 3, one embodiment of the present application also provides a dynamic adjustment method applied to the system-on-chip,

the system on a chip comprises at least one chip,

the chip comprises:

a single wafer comprising a plurality of partitions, each of the partitions comprising a partition sensor;

the power chip is used for providing output voltage for the single chip;

the method comprises the following steps:

Acquiring monitoring data acquired by the partition sensors of each partition of the chip;

and adjusting the output voltage of the power supply chip according to the monitoring data.

In another optional embodiment, the adjusting the output voltage of the power supply chip according to the monitoring data further includes:

and generating an adjustment instruction of the partition according to a dynamic adjustment table in response to the monitoring data of the partition sensor of the partition not meeting the preset monitoring threshold requirement, wherein the adjustment instruction comprises a first instruction for adjusting the output voltage of the power supply chip.

In an alternative embodiment, the chip further comprises: the power management unit is used for outputting clock frequency to the single chip;

the determining the voltage value to be adjusted in the dynamic adjustment table and generating the first instruction in response to the temperature acquisition data being greater than the second threshold value, further comprises:

and generating a second instruction for adjusting clock frequency trend in response to the temperature acquisition data being greater than the second threshold value, so that the power management unit determines the partition adjusted clock frequency corresponding to the second instruction according to the second instruction.

In an alternative embodiment, the dynamic adjustment table includes a plurality of adjustment levels;

the determining, in the dynamic adjustment table, a voltage value to be adjusted and generating the first instruction in response to the temperature acquisition data being greater than the second threshold value, further comprises:

responsive to the temperature acquisition data being greater than the second threshold;

And determining a target adjustment level based on a first condition, wherein the first condition comprises an adjustment level of the partition at which the partition is currently located, determining a voltage value to be adjusted of the partition according to the target adjustment level, and generating a first instruction of the partition.

the comparing the voltage acquisition data in the monitoring data with the first threshold value, and in response to the voltage acquisition data being smaller than the first threshold value, determining a voltage value to be adjusted in the dynamic adjustment table and generating the first instruction, further comprises:

determining a current first threshold corresponding to the current adjustment level based on the current adjustment level of the partition;

comparing the voltage acquisition data with the current first threshold;

And responding to the voltage acquisition data being smaller than the current first threshold value, determining a voltage value to be adjusted of the partition based on a current voltage adjustment value corresponding to the current adjustment level, and generating the first instruction of the partition.

In an alternative embodiment, the dynamic adjustment table includes a plurality of adjustment tables corresponding to each partition one to one;

and generating an adjustment instruction of the partition according to a dynamic adjustment table in response to the monitoring data of the partition sensor of the partition not meeting the preset monitoring threshold requirement, and further comprising:

and generating the first instruction in the adjustment instructions of the partition according to the adjustment form corresponding to the partition in response to the monitoring data of the partition sensor of the partition not meeting the preset monitoring threshold requirement.

In an alternative embodiment, the method further comprises:

the output voltage of the power chip is determined according to a first instruction of at least one partition.

In an alternative embodiment, said determining said output voltage of said power supply chip according to a first instruction of at least one of said partitions further comprises:

determining at least one voltage value to be adjusted, wherein the at least one voltage value to be adjusted corresponds to a first instruction of the at least one partition;

Determining a maximum voltage value of the at least one voltage value to be adjusted, and determining the maximum voltage value as the output voltage of the power supply chip.

In an alternative embodiment, the method further comprises:

receiving a droop interrupt, wherein the droop interrupt is generated when a droop signal generated according to the adjustment of the monitoring data to the power chip does not meet the preset droop threshold value requirement;

and adjusting the output voltage of the power supply chip according to a dynamic adjustment table based on the droop interrupt.

In an alternative embodiment, the monitoring threshold further includes a third threshold corresponding to the voltage acquisition data and a fourth threshold corresponding to the temperature acquisition data, the method further comprising:

comparing the voltage acquisition data in the monitoring data with the third threshold value, and comparing the temperature acquisition data in the monitoring data with the fourth threshold value,

in response to the voltage acquisition data being greater than the third threshold and/or in response to the temperature acquisition data being greater than the fourth threshold, determining a preset clock frequency trend as the frequency trend of the partition to be adjusted and generating the second instruction, determining a preset voltage value as the voltage value of the partition to be adjusted and generating the first instruction.

In this embodiment, in order to further avoid the influence of the IR drop on the operation performance of each partition of each single-chip of the on-chip system, fuse protection is set in the adjustment process of the dynamic adjustment unit, specifically, the fusing detection is performed on the collected temperature collection data and the collected voltage collection data through the third threshold and the fourth threshold which are the fusing threshold, when any one of the temperature collection data and the voltage collection data of one partition exceeds the fusing threshold, the power management chip is adjusted to set the frequency of the partition to be a frequency protection value through the preset clock frequency trend, and the power chip is adjusted to set the voltage of the partition to be a voltage protection value through the preset voltage value, so that each partition of each single-chip of the on-chip system is protected, the hardware operation unit is ensured to be in a safe working environment, and the service life of the on-chip system is effectively improved.

The foregoing embodiments refer to the foregoing embodiments, and are not repeated herein.

Based on the above system-on-chip, an embodiment of the present application further provides a chip system, including the above system-on-chip.

Another embodiment of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements: acquiring monitoring data acquired by the partition sensors of each partition of the chip; and adjusting the output voltage of the power supply chip according to the monitoring data.

In practical applications, the computer-readable storage medium may take the form of any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this embodiment, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

As shown in fig. 7, another embodiment of the present invention provides a schematic structural diagram of a computer device. The computer device 12 shown in fig. 7 is only an example and should not be construed as limiting the functionality and scope of use of embodiments of the invention.

As shown in fig. 7, the computer device 12 is in the form of a general purpose computing device. Components of computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, a bus 18 that connects the various system components, including the system memory 28 and the processing units 16.

Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, and a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, micro channel architecture (MAC) bus, enhanced ISA bus, video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

Computer device 12 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by computer device 12 and includes both volatile and nonvolatile media, removable and non-removable media.

The system memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 30 and/or cache memory 32. The computer device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 7, commonly referred to as a "hard disk drive"). Although not shown in fig. 7, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In such cases, each drive may be coupled to bus 18 through one or more data medium interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of embodiments of the invention.

A program/utility 40 having a set (at least one) of program modules 42 may be stored in, for example, memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 42 generally perform the functions and/or methods of the embodiments described herein.

The computer device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), one or more devices that enable a user to interact with the computer device 12, and/or any devices (e.g., network card, modem, etc.) that enable the computer device 12 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 22. Moreover, computer device 12 may also communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through network adapter 20. As shown in fig. 7, the network adapter 20 communicates with other modules of the computer device 12 via the bus 18. It should be appreciated that although not shown in fig. 7, other hardware and/or software modules may be used in connection with computer device 12, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

The processor unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, for example, implementing a dynamic adjustment method for a system on a chip provided by an embodiment of the present invention.

It should be understood that the foregoing examples of the present invention are provided merely for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention, and that various other changes and modifications may be made therein by one skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A system on a chip, comprising, at least one chip,

the chip comprises:

the power chip is used for providing output voltage for the single chip;

the method comprises the steps of,

and the dynamic adjustment unit is used for adjusting the output voltage of the power supply chip according to the monitoring data of each partition sensor.

2. The system on a chip of claim 1, wherein the dynamic adjustment unit comprises: the configuration unit and the adjusting controller are in one-to-one correspondence with each partition,

the adjustment controller is configured to: and generating an adjustment instruction according to a dynamic adjustment table in the configuration unit in response to the monitoring data of the partition sensor of the corresponding partition not meeting the preset monitoring threshold requirement, wherein the adjustment instruction comprises a first instruction for adjusting the output voltage of the power chip.

3. The system on a chip of claim 2, wherein the monitoring data comprises voltage acquisition data and temperature acquisition data, the monitoring threshold comprising a first threshold corresponding to the voltage acquisition data and a second threshold corresponding to the temperature acquisition data;

the adjustment controller is configured to: comparing the voltage acquisition data in the monitoring data with the first threshold value, and determining a voltage value to be adjusted in the dynamic adjustment table and generating the first instruction in response to the voltage acquisition data being smaller than the first threshold value; or alternatively

4. The system on a chip of claim 3, wherein the chip further comprises: the power management unit is used for outputting clock frequency to the single chip; the method comprises the steps of,

the dynamic adjustment unit is further configured to adjust the clock frequency output by the power management unit according to the monitoring data of each partition sensor.

5. The system on a chip of claim 4, wherein the adjustment instructions further comprise second instructions to adjust the clock frequency of the power management unit,

the adjustment controller is further configured to: and generating the second instruction for adjusting clock frequency trend according to a dynamic adjustment table in the configuration unit in response to the temperature acquisition data being greater than the second threshold.

6. The system on a chip of claim 5, wherein the power management unit is further configured to: and determining the clock frequency of the partition adjusted corresponding to the second instruction according to the second instruction.

7. The system on a chip of any of claims 2-6, wherein the dynamic adjustment table comprises a plurality of adjustment tables in one-to-one correspondence with each partition;

the adjustment controller is further configured to: and generating the first instruction of the partition according to the adjustment form corresponding to the partition in response to the monitoring data of the partition sensor of the corresponding partition not meeting the preset monitoring threshold requirement.

8. The system on a chip of any of claims 2-7, wherein the dynamic adjustment unit comprises: an adaptive voltage regulating unit is provided for regulating the voltage of the power supply,

9. The system on a chip of any of claims 1-8, further comprising a droop control unit coupled to the dynamic adjustment unit, the droop control unit configured to: generating a droop signal based on the dynamic adjustment unit according to the adjustment of the monitoring data to the power chip, and sending a droop interrupt to the dynamic adjustment unit in response to the droop signal not meeting a preset droop threshold value requirement;

10. A dynamic adjustment method is characterized by being applied to a system on a chip, wherein the system on a chip comprises at least one chip,

the chip comprises:

the power chip is used for providing output voltage for the single chip;

the method comprises the following steps:

11. The method of claim 10, wherein said adjusting said output voltage of said power chip based on said monitoring data further comprises:

12. The method of claim 11, wherein the monitoring data comprises voltage acquisition data and temperature acquisition data, the monitoring threshold comprising a first threshold corresponding to the voltage acquisition data and a second threshold corresponding to the temperature acquisition data;

13. The method of claim 12, wherein the chip further comprises: the power management unit is used for outputting clock frequency to the single chip;

14. The method of claim 12, wherein the dynamic adjustment table includes a plurality of adjustment levels therein;

15. The method of claim 14, wherein the dynamic adjustment table further includes a first threshold value for each of the adjustment levels of the plurality of adjustment levels and at least two voltage adjustment values for each adjustment level,

comparing the voltage acquisition data with the current first threshold;

16. The method of any of claims 11-15, wherein the dynamic adjustment table comprises a plurality of adjustment tables in one-to-one correspondence with each partition;

17. The method according to any one of claims 11-16, further comprising:

18. The method of claim 17, wherein said determining said output voltage of said power chip according to a first instruction of at least one of said partitions further comprises:

19. The method according to any one of claims 11-18, further comprising:

20. The method of claim 12, wherein the monitoring threshold further comprises a third threshold corresponding to the voltage acquisition data and a fourth threshold corresponding to the temperature acquisition data, the method further comprising:

comparing the voltage acquisition data in the monitoring data with the third threshold value, determining a preset voltage value as the voltage value to be adjusted of the partition and generating the first instruction in response to the voltage acquisition data being larger than the third threshold value; and/or the number of the groups of groups,