CN116918075A

CN116918075A - Semiconductor device and equipment

Info

Publication number: CN116918075A
Application number: CN202280019241.3A
Authority: CN
Inventors: 小林广明
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2021-03-08
Filing date: 2022-03-02
Publication date: 2023-10-20

Abstract

In the present invention, the first element included in the semiconductor layer 11 is different from the second element included in the semiconductor layer 21, and the third element included in the source electrode 13 is the same as the fourth element included in the gate electrode 22.

Description

Semiconductor device and equipment

Technical Field

The present invention relates to a semiconductor device.

Background

There has been a technique of changing constituent elements of semiconductor layers of transistors disposed on the same substrate. Patent literature (PTL) 1 discusses a semiconductor device using a Thin Film Transistor (TFT) including polysilicon and another TFT including an oxide semiconductor layer. Patent document (PTL) 2 discusses a semiconductor device including a first top gate thin film transistor using a polysilicon layer as a channel and a second top gate thin film transistor using an oxide semiconductor layer as another channel. In the semiconductor device discussed in (PTL) 2, the common metal layer is used as the source and drain of the first top-gate thin film transistor and the gate of the second top-gate thin film transistor.

CITATION LIST

Patent literature

PTL 1: japanese patent laid-open No.2020-202223

PTL 2: japanese patent laid-open No.2018-50030

Disclosure of Invention

Technical problem

In the technique discussed in PTL 1, consideration of cost reduction is not yet sufficient. The effects obtainable with the technique discussed in PTL 2 are applicable to only limited structures. Accordingly, the present invention relates to a technique that is advantageous in reducing the cost of a semiconductor device.

Solution to the problem

In a first aspect of the semiconductor device according to the present invention, the semiconductor device includes a substrate, a first semiconductor layer which is a first transistor and disposed over the substrate, a first semiconductor layer which is disposed over the substrate and overlaps the first semiconductor layer, a second semiconductor layer which is a second transistor and disposed over the substrate, and a second semiconductor layer which is disposed over the substrate and overlaps the second semiconductor layer, wherein a first element having a highest concentration in the first semiconductor layer among elements of groups 12 to 16 included in the first semiconductor layer is different from a second element having a highest concentration in the second semiconductor layer among elements of groups 12 to 16 included in the second semiconductor layer, wherein a second element having a highest concentration in the first semiconductor layer among metal elements or metalloid elements included in the first semiconductor layer is the same as a first element having a highest concentration in the second semiconductor layer among metal elements or metalloid elements included in the second semiconductor layer, wherein the first semiconductor layer is in contact with the second semiconductor layer, and wherein the second semiconductor layer is disposed between the second semiconductor layer and the second semiconductor layer.

In the semiconductor device according to the second aspect of the present invention, the second conductor layer is disposed between the second semiconductor layer and the substrate. The third aspect is that a third conductor layer disposed over the substrate and overlapping the second conductor layer is not in contact with the second semiconductor layer and is insulated from the second conductor layer. The fourth aspect is that the first transistor is P-type and the second transistor is N-type.

Advantageous effects of the invention

According to the present invention, a technique advantageous in reducing the cost of a semiconductor device can be provided.

Drawings

Fig. 1A is a schematic diagram illustrating a semiconductor device.

Fig. 1B is a schematic diagram illustrating a semiconductor device.

Fig. 1C is a schematic diagram illustrating a semiconductor device.

Fig. 1D is a schematic diagram illustrating a semiconductor device.

Fig. 2A is a schematic diagram illustrating the type of transistor.

Fig. 2B is a schematic diagram illustrating the type of transistor.

Fig. 2C is a schematic diagram illustrating the type of transistor.

Fig. 2D is a schematic diagram illustrating the type of transistor.

Fig. 3A is a schematic diagram illustrating a semiconductor device.

Fig. 3B is a schematic diagram illustrating a semiconductor device.

Fig. 4A is a schematic diagram illustrating a semiconductor device.

Fig. 4B is a schematic diagram illustrating a semiconductor device.

Fig. 5A is a schematic diagram illustrating a semiconductor device.

Fig. 5B is a schematic diagram illustrating the semiconductor device.

Fig. 6A is a schematic diagram illustrating a semiconductor device.

Fig. 6B is a schematic diagram illustrating the semiconductor device.

Fig. 7A is a schematic diagram illustrating a manufacturing method of the semiconductor device.

Fig. 7B is a schematic diagram illustrating a manufacturing method of the semiconductor device.

Fig. 7C is a schematic diagram illustrating a manufacturing method of the semiconductor device.

Fig. 7D is a schematic diagram illustrating a manufacturing method of the semiconductor device.

Fig. 8 is a schematic diagram illustrating a semiconductor device.

Fig. 9A is a schematic diagram illustrating a semiconductor device.

Fig. 9B is a schematic diagram illustrating the semiconductor device.

Fig. 10A is a schematic diagram illustrating an apparatus.

Fig. 10B is a schematic diagram illustrating the apparatus.

Detailed Description

Hereinafter, modes for carrying out the present invention will be described with reference to the accompanying drawings. In the following description and drawings, configurations illustrated in common among a plurality of drawings are given the same reference numerals. Common configurations will sometimes be described with reference to a plurality of drawings without further notification. In addition, a description of a configuration given the same reference numerals is sometimes omitted. Different components having the same name may be distinguished from each other by assigning an "nth" (n is a number) as the first component and the second component. In this specification, the case where a and B correspond to either C or D means any one of the case where a and B correspond to C, the case where a and B correspond to D, the case where a corresponds to C and B corresponds to D, and the case where a corresponds to D and B corresponds to C.

Fig. 1A is a schematic plan view of the semiconductor device AP. The semiconductor device AP applicable to the present exemplary embodiment may include a pixel region 2 in which a plurality of pixel circuits PX are arranged, and a peripheral region 3 disposed around the pixel region 2. In fig. 1A, the pixel region 2 is a region surrounded by a chain line, and the peripheral region 3 is a region between the chain line and a two-dot chain line. The semiconductor device AP including the pixel region 2 may be used as a display device or an imaging device. The present exemplary embodiment is also applicable to a semiconductor device AP that does not include the pixel region 2 and the peripheral region 3, and is applicable to, for example, a computing device, a storage device, or a communication device.

Fig. 1B is a schematic cross-sectional view of the semiconductor device AP. The semiconductor device AP includes a substrate 1, a transistor 10 disposed above the substrate 1, and a transistor 20 disposed above the substrate 1. Fig. 2A to 2D are schematic cross-sectional views each illustrating the configuration of the transistor 10 and the transistor 20. The transistor 10 includes a semiconductor layer 11 disposed over the substrate 1, and the transistor 20 includes a semiconductor layer 21 disposed over the substrate 1. The semiconductor layers 11 and 21 each include one or more elements of groups 12 to 16. Each of the semiconductor layers 11 and 21 may include an element other than elements of groups 12 to 16 (for example, hydrogen), or the like.

The transistor 10 is disposed in at least the pixel region 2 or the peripheral region 3. The transistor 20 is disposed in at least the pixel region 2 or the peripheral region 3. Here, an example in which the transistor 10 is disposed in the pixel region 2 and the peripheral region 3 and the transistor 20 is disposed in the pixel region 2 is illustrated. Further, the transistor 30 is disposed in the peripheral region 3 together with the transistor 10. The transistor 10 in the peripheral region 3 and the transistor 30 in the peripheral region 3 may together form a complementary integrated circuit, such as a Complementary Metal Oxide Semiconductor (CMOS) circuit. In a complementary integrated circuit, transistor 10 may be a P-type transistor and transistor 30 may be an N-type transistor. Alternatively, in a complementary integrated circuit, transistor 10 may be an N-type transistor and transistor 30 may be a P-type transistor. Although the transistor 10 may be any one of an N-type transistor and a P-type transistor, it is desirable that the transistor 10 be an N-type transistor because electron mobility is generally higher than hole mobility. Although the transistor 20 may be any one of an N-type transistor and a P-type transistor, it is desirable that the transistor 20 be an N-type transistor because electron mobility is generally higher than hole mobility.

In the pixel region 2, the functional element 200 is disposed above the transistor 20 (and the transistor 10). The functional element 200 is an element generally included in a pixel, such as a liquid crystal element, a light emitting element, or a photoelectric conversion element. The functional element 200 is connected to a transistor included in the pixel circuit PX, and the transistor to which the functional element 200 is connected is, for example, the transistor 20 or the transistor 10.

As shown in fig. 1B, an insulator 40 is disposed on the substrate 1. The insulator 40 is a stacked member of insulator films having various functions, such as an interlayer insulating film, a planarizing film, an anti-diffusion film, a protective film, and a sealing film, which are present around the transistors 10, 20, and 30, in addition to the gate insulating films of the transistors 10, 20, and 30.

Fig. 1C illustrates one of the pixel circuits PX in the case where the semiconductor device AP is an imaging device. The pixel circuit PX includes a functional element 200 serving as a photoelectric conversion element, and an amplifier transistor 104 that amplifies a signal generated in the functional element 200. The functional element 200 serving as a photoelectric conversion element includes a first electrode 201, a second electrode 209, a functional layer 205 disposed between the first electrode 201 and the second electrode 209, and an insulating layer 207 disposed between the functional layer 205 and the second electrode 209. The functional layer 205 is a photoelectric conversion layer made of an organic material, an inorganic material, or a mixed material of an organic material and an inorganic material. The hybrid material may be a quantum dot material. The functional element 200 serving as a photoelectric conversion element may include a barrier layer 203 disposed between a functional layer 205 and a first electrode 201. The blocking layer 203 is disposed to prevent charges of the same conductivity type as the signal charges accumulated in the functional layer 205 from being injected from the first electrode 201 to the functional layer 205. The barrier layer 203 and the insulating layer 207 may be omitted. With this configuration, the photoelectric conversion unit can accumulate charges generated in accordance with incident light as signal charges. Then, the voltage to be supplied to the pixel circuit PX is controlled, whereby the photoelectric conversion unit reads out a signal from the photoelectric conversion element (functional element 200).

The pixel PX includes a reset transistor 102, a capacitor 103, an amplifier transistor 104, and a selection transistor 105. The drain of the reset transistor 102 is connected to a node to which a reset voltage Vres is supplied. The source voltage Vs is supplied to the node a including the first electrode 201 of the functional element 200. The source of the reset transistor 102 is connected to the second electrode 209 of the functional element 200 and to the gate of the amplifier transistor 104. In this configuration, the reset transistor 102 resets the voltage at node B to a reset voltage Vres. That is, the reset transistor 102 is a reset unit that supplies a reset voltage Vres to the second electrode 209. When the reset transistor 102 is turned off, the node B including the second electrode 209 of the functional element 200 (photoelectric conversion element) enters an electrically floating state. Node C is capacitively coupled to node B via capacitor 103. A first terminal of capacitor 103 is connected to node B. The voltage Vd from the voltage supply unit 410 is supplied to the node C to which the second terminal of the capacitor 103 is connected. Node B includes the gate of amplifier transistor 104. The amplifier transistor 104 is an amplifying unit, and the gate of the amplifier transistor 104 is an input node of the amplifying unit. That is, the second electrode 209 of the functional element 200 is electrically connected to the amplifying unit. In this configuration, the amplifying unit amplifies a signal generated in the functional element 200 (photoelectric conversion element), and outputs the amplified signal. The drain of the amplifier transistor 104 is connected to a node to which a source voltage is supplied. The source of the amplifier transistor 104 is connected to an output line 130 via a selection transistor 105. A current source 160 is connected to the output line 130. The amplifier transistor 104 and the current source 160 form a source follower circuit, and output a signal based on the charge generated in the functional element 200 to the output line 130. The column circuit 140 is further connected to the output line 130. A signal output from the pixel circuit PX to the output line 130 is input to the column circuit 140.

Fig. 1D illustrates one of the pixel circuits PX in the case where the semiconductor device AP is a display device. The pixel PX includes a functional element 200 serving as an organic Electroluminescence (EL) element, and the functional element 200 may include a first electrode 201, a second electrode 209, and a functional layer 205 disposed between the first electrode 201 and the second electrode 209. The functional layer 205 is a light emitting layer made of an organic material or an inorganic material. The first electrode 201 is, for example, a cathode, and the second electrode 209 is, for example, an anode. The light emission color of the light emitting layer of the functional element 200 serving as an organic EL element may be changed to red, green, or blue for each sub-pixel, or the light emission color of each sub-pixel may be set to white and light may be dispersed using a color filter.

The pixel circuit PX includes a selection transistor 107, a driving transistor 106, and a capacitor 108. The source voltage Vd is supplied from the power supply line PL to the driving transistor 106, and the source voltage Vs is supplied to the first electrode 201. The source voltage Vs may be a voltage lower than the source voltage Vd. In response to the scan signal applied to the scan line GL, the selection transistor 107 outputs the applied data signal to the data line DL. The capacitor 108 is charged with a voltage corresponding to the data signal received via the selection transistor 107. The source or drain of the selection transistor 107 is connected to the node D. The gate of the driving transistor 106 is connected to the node D. The driving transistor 106 is connected to the node E. The drive transistor 106 is connected to the second electrode 209 of the functional element 200. One of a source and a drain of the driving transistor 106 is connected to the node E, and the other of the source and the drain of the driving transistor 106 is connected to the second electrode 209. The voltage Vd is supplied from the voltage supply unit to the node E. A first terminal of capacitor 108 is connected to node D. In this example, the second terminal of capacitor 108 is connected to node E, and node E is capacitively coupled to node D via capacitor 108. Alternatively, the capacitor 108 may be connected to a node to which the second electrode 209 is connected, instead of the node E. The driving transistor 106 controls the driving current flowing through the functional element 200 according to the amount of charge stored in the capacitor. In this configuration, the functional element 200 serving as a light emitting element emits light at a luminance corresponding to the data level of the data signal.

The pixel circuit PX described with reference to fig. 1C or 1D is merely an example, and the configuration is not limited thereto. The pixel PX may further include a plurality of transistors, and may include a greater number of capacitors. The capacitor 103 and the capacitor 108 may be of a metal-insulator-semiconductor (MIS) type in which a dielectric layer is located between a conductor layer and a semiconductor layer, may be of a metal-insulator-metal (MIM) type in which a dielectric layer is located between a conductor layer and a conductor layer, or may have a structure in which a dielectric layer is located between a semiconductor layer and a semiconductor layer.

In the above-described pixel circuit PX, for example, the selection transistor 105, the reset transistor 102, and the selection transistor 107 may be switching transistors. These switching transistors may correspond to the transistor 20 described above. In the pixel circuit PX described above, for example, the amplifier transistor 104 and the driving transistor 106 are different from the switching transistor in that the amplifier transistor 104 and the driving transistor 106 output a potential related to a potential input to the gate thereof, and these transistors may correspond to the transistor 10. The capacitor 103 and the capacitor 108 have a common function, that is, the capacitor 103 and the capacitor 108 hold an amount of charge corresponding to a signal level of the pixel. The reset transistor 102 and the selection transistor 107, which are directly connected to the capacitor 103 and the capacitor 108, respectively, are expected to correspond to the transistor 10. The amplifier transistor 104 and the driving transistor 106 directly connected to the capacitor 103 and the capacitor 108, respectively, may correspond to the transistor 20.

Fig. 2A to 2D are schematic cross-sectional views illustrating the configuration of the transistor 10 and the transistor 20. Fig. 2A to 2D illustrate four different configurations of the transistor 10 and the transistor 20. First, the commonality of these configurations will be described.

The transistor 10 includes a semiconductor layer 11, a gate electrode 12, a source electrode 13, a drain electrode 14, and a gate insulating film 15 disposed over the substrate 1. The gate electrode 12, the source electrode 13, and the drain electrode 14 overlap with the semiconductor layer 11. The gate electrode 12 is insulated from the semiconductor layer 11 by a gate insulating film 15, and the source electrode 13 and the drain electrode 14 are in contact with the semiconductor layer 11. In the transistor 10, a gate electrode 12 is disposed on a channel of the semiconductor layer 11, and a gate insulating film 15 is disposed between the semiconductor layer 11 and the gate electrode 12. In the transistor 10, a source electrode 13 is disposed on the source of the semiconductor layer 11, and a drain electrode 14 is disposed on the drain of the semiconductor layer 11.

The transistor 20 includes a semiconductor layer 21, a gate electrode 22, a source electrode 23, a drain electrode 24, and a gate insulating film 25 disposed over the substrate 1. The gate electrode 22, the source electrode 23, and the drain electrode 24 overlap with the semiconductor layer 21. The gate electrode 22 is insulated from the semiconductor layer 21 by a gate insulating film 25, and the source electrode 23 and the drain electrode 24 are in contact with the semiconductor layer 21. In the transistor 20, a gate electrode 22 is disposed above the semiconductor layer 21, and a gate insulating film 25 is disposed between the semiconductor layer 21 and the gate electrode 22. In the transistor 20, a source electrode 23 is disposed on the source of the semiconductor layer 21, and a drain electrode 24 is disposed on the drain of the semiconductor layer 21.

Among the elements of groups 12 to 16 included in the semiconductor layer 11, the element having the highest concentration in the semiconductor layer 11 will be described as the element S1. Among the elements of groups 12 to 16 included in the semiconductor layer 21, the element having the highest concentration in the semiconductor layer 21 will be described as the element S2. In the present exemplary embodiment, the element S1 is different from the element S2.

The semiconductor layers 11 and 21 may be group IV semiconductors such as silicon (Si), germanium (Ge), fullerenes, and carbon nanotubes. In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be elements of group 14. The semiconductor layers 11 and 21 may be II-VI compound semiconductors such as zinc selenide (ZnSe), cadmium sulfide (CdS), and zinc oxide (ZnO). In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be elements of group 12 or 16. The semiconductor layers 11 and 21 may be oxide semiconductors such as indium gallium zinc oxide (InGaZnO) and indium tin zinc oxide (InSnZnO). In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be oxygen (elements of group 16) or elements of groups 12 to 14. The concentration of oxygen in the oxide semiconductor is, for example, 50 atomic percent (at%) or more, 70at% or less, 67at% or less, or 60at% or less. The semiconductor layers 11 and 21 may be group III-V compound semiconductors such as gallium arsenide (GaAs), indium phosphide (InP), and gallium nitride (GaN). In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be elements of group 13 or 15. The semiconductor layers 11 and 21 may be group IV compound semiconductors such as silicon carbide (SiC) and silicon germanium (SiGe). In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be elements of group 14. The semiconductor layers 11 and 21 may be organic semiconductors. In this case, the elements S1 and S2 in the semiconductor layers 11 and 21 may be carbon (group 14 element).

The semiconductor layers 11 and 21 are at least any one of a single crystal layer, a polycrystalline layer, and an amorphous layer. The semiconductor layers 11 and 21 may be a multi-layered member including various types of layers including a single crystal layer, a polycrystalline layer, and an amorphous layer. In order to realize a large area of the semiconductor device AP, the semiconductor layers 11 and 21 are desirably Thin Film Transistors (TFTs) using a polycrystalline layer or an amorphous layer.

The gate electrodes 12 and 22, the source electrodes 13 and 23, and the drain electrodes 14 and 24 each include at least one conductor layer. In the case where the gate electrodes 12 and 22 have a multilayer structure including a plurality of conductor layers, the lowermost or uppermost conductor layer of the gate electrodes 12 and 22 is in contact with the gate insulating films 15 and 25. In the case where the source electrodes 13 and 23 and the drain electrodes 14 and 24 have a multilayer structure including a plurality of conductor layers, the lowermost or uppermost conductor layers of the source electrodes 13 and 23 and the drain electrodes 14 and 24 are in contact with the semiconductor layers 11 and 21. In the following description of the conductor layers of the gate electrodes 12 and 22, the source electrodes 13 and 23, and the drain electrodes 14 and 24, the conductor layers may be the conductor layers closest to the semiconductor layers 11 and 21.

A conductor member overlapping with the semiconductor layer 11 and insulated from the semiconductor layer 11 may be disposed above the substrate 1 except for the gate electrode 12. A conductor member 28 (to be described below) overlapping with the semiconductor layer 21 and insulated from the semiconductor layer 21 may be disposed above the substrate 1 in addition to the gate electrode 22. The conductor member 28 can be used as an auxiliary electrode, a wire, a light shielding member, a level difference adjustment member, or the like for the transistor 20. Although another conductor layer may be present between the conductor member 28 and the semiconductor layer 21, another conductor layer need not be present between the conductor member 28 and the semiconductor layer 21.

The conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14 are each made of one or more types of metal elements or metalloid elements. Among the metal elements or metalloid elements included in the conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14, the element having the highest concentration in the source electrode 13 or the drain electrode 14 will be described as the element M1.

The conductor layer of the gate electrode 22 is made of one or more types of metal elements or metalloid elements. Among the metal elements or metalloid elements included in the gate electrode 22, the element having the highest concentration in the gate electrode 22 will be described as the element M2.

The conductor layer of the gate electrode 12 is made of one or more types of metal elements or metalloid elements. Among the metal elements or metalloid elements included in the conductor layer of the gate electrode 12, the element having the highest concentration in the conductor layer of the gate electrode 12 will be described as the element M3.

The conductor layer of the source electrode 23 and the conductor layer of the drain electrode 24 are made of one or more types of metal elements or metalloid elements. Among the metal elements or metalloid elements included in the conductor layer of the source electrode 23 and the conductor layer of the drain electrode 24, the element having the highest concentration in the gate electrode 22 will be described as the element M4.

The element M3, which is a metal element or a metalloid element included in the gate electrode 12, may be different from the element S2 included in the semiconductor layer 21. The element M4, which is a metal element or a metalloid element included in the gate electrode 22, may be different from the element S1 included in the semiconductor layer 11.

The conductor layer of the conductor member 28 overlaps with the semiconductor layer 21 and is insulated from the semiconductor layer 21. The conductor layer of the conductor member 28 is made of one or more types of metal elements or metalloid elements other than the gate electrode 22. Among the metal elements or metalloid elements included in the conductor layer of the conductor member 28, the element having the highest concentration in the conductor member 28 will be described as the element M5.

The element M1, which is a metal element or a metalloid element included in the source electrode 13 or the drain electrode 14, may be different from the element S2 included in the semiconductor layer 21.

The element M2 as a metal element or a metalloid element included in the gate electrode 22 may be different from the element S1 included in the semiconductor layer 11.

The element M3, which is a metal element or a metalloid element included in the gate electrode 12, may be different from the element S2 included in the semiconductor layer 21.

The element M4, which is a metal element or a metalloid element included in the gate electrode 22, may be different from the element S1 included in the semiconductor layer 11.

The element M5 as a metal element or a metalloid element included in the conductor member 28 may be different from the element S1 included in the semiconductor layer 11.

The difference in main constituent elements between the gate electrode of the transistor 10 or the transistor 20 and the semiconductor layer of the other of the transistor 10 and the transistor 20 is advantageous in realizing the characteristics of the electrodes of the transistor 10 and the transistor 20.

For example, the elements M1 to M4 are elements of groups 3 to 13, and may be elements of groups 3 to 9. In general, the elements M1 to M4 may be any one of gold (Au), silver (Ag), copper (Cu), platinum (Pt), molybdenum (Mo), tungsten (W), tantalum (Ta), and titanium (Ti). In particular, the elements M1 to M4 are desirably any one of Cu, mo, W, and Ti.

In the present exemplary embodiment, the element M1 and the element M2 may be the same. The same element means that the atomic numbers of the elements are the same. The use of the same elements in the source electrode 13, the drain electrode 14, and the gate electrode 22 allows design, procurement, and manufacturing costs to be reduced.

In the present exemplary embodiment, the element M1 and the element M5 may be the same. The same element means that the atomic numbers of the elements are the same. The use of the same elements in the source electrode 13, the drain electrode 14, and the conductor member 28 allows design, procurement, and manufacturing costs to be reduced.

Although illustration of the insulator 40 on the substrate 1 shown in fig. 1B is omitted in fig. 2A to 2D, an insulator film such as a gate insulating film or an interlayer insulating film may be disposed around the semiconductor layers 11 and 21 as at least a part of the insulator 40.

In the T-type transistor 10 shown in fig. 2A and 2D, the semiconductor layer 11 is disposed between the substrate 1 and the gate electrode 12. Further, in the T-type transistor 20, the semiconductor layer 21 is disposed between the substrate 1 and the gate electrode 22.

In the C-type transistor 10 shown in fig. 1A and 1B, the gate electrode 12, the source electrode 13, and the drain electrode 14 of the transistor 10 are disposed on one of a side facing the substrate 1 and an opposite side of the side facing the substrate 1 with respect to the semiconductor layer 11. In the example shown in fig. 2A, the gate electrode 12, the source electrode 13, and the drain electrode 14 are disposed on opposite sides of the side facing the substrate 1 with respect to the semiconductor layer 11. In the example shown in fig. 2B, the gate electrode 12, the source electrode 13, and the drain electrode 14 are disposed on a side facing the substrate 1 with respect to the semiconductor layer 11. In the C-type transistor 10, the gate electrode 12 may be disposed between the source electrode 13 and the drain electrode 14.

In the C-type transistor 20 shown in fig. 1A and 1B, the gate electrode 22, the source electrode 23, and the drain electrode 24 of the transistor 20 are disposed on one of a side facing the substrate 1 and an opposite side of the side facing the substrate 1 with respect to the semiconductor layer 21. In the example shown in fig. 2A, the gate electrode 22, the source electrode 23, and the drain electrode 24 are disposed on opposite sides of the side facing the substrate 1 with respect to the semiconductor layer 11. In the example shown in fig. 2B, the gate electrode 22, the source electrode 23, and the drain electrode 24 are disposed on a side facing the substrate 1 with respect to the semiconductor layer 21. In the C-type transistor 20, a gate electrode 22 may be disposed between a source electrode 23 and a drain electrode 24.

In the B-type transistor 10 shown in fig. 2B and 2C, the gate electrode 12 is disposed between the substrate 1 and the semiconductor layer 11. In addition, in the B-type transistor 20, a gate electrode 22 is disposed between the substrate 1 and the semiconductor layer 21.

In the S-type transistor 10 shown in fig. 2C and 2D, the semiconductor layer 11 is disposed between the gate electrode 12 and the source electrode 13. Further, in the S-type transistor 10, the semiconductor layer 11 is disposed between the gate electrode 12 and the drain electrode 14. Further, in the S-type transistor 20, the semiconductor layer 21 is disposed between the gate electrode 22 and the source electrode 23. Further, in the S-type transistor 20, the semiconductor layer 21 is disposed between the gate electrode 22 and the drain electrode 24.

In the second exemplary embodiment, both the transistor 10 and the transistor 20 disposed over a single substrate, i.e., the substrate 1, are T-shaped. In this case, it is desirable that both the transistor 10 and the transistor 20 are C-shaped, and it is also desirable that both the transistor 10 and the transistor 20 are S-shaped. Alternatively, the type of the transistor 10 may be one of a C-type and an S-type, and the type of the transistor 20 may be the other of the C-type and the S-type.

In the third exemplary embodiment, both the transistor 10 and the transistor 20 disposed over a single substrate, i.e., the substrate 1, are B-type transistors. In this case, it is desirable that both the transistor 10 and the transistor 20 are C-shaped, and it is also desirable that both the transistor 10 and the transistor 20 are S-shaped. Alternatively, the type of the transistor 10 may be one of a C-type and an S-type, and the type of the transistor 20 may be the other of the C-type and the S-type.

In the fourth exemplary embodiment, both the transistor 10 and the transistor 20 disposed over a single substrate, i.e., the substrate 1, are C-type transistors. In this case, it is desirable that both the transistor 10 and the transistor 20 are T-type, and it is also desirable that both the transistor 10 and the transistor 20 are B-type. Alternatively, the type of the transistor 10 may be one of a T-type and a B-type, and the type of the transistor 20 may be the other of the T-type and the B-type.

In the fifth exemplary embodiment, the transistor 10 and the transistor 20 disposed over a single substrate, i.e., the substrate 1, are both S-type transistors. In this case, it is desirable that both the transistor 10 and the transistor 20 are T-type, and it is also desirable that both the transistor 10 and the transistor 20 are B-type. Alternatively, the type of the transistor 10 may be one of a T-type and a B-type, and the type of the transistor 20 may be the other of the T-type and the B-type.

As in the second to fifth exemplary embodiments, using the same type of transistor as both the transistor 10 and the transistor 20 disposed over the single substrate, i.e., the substrate 1, results in simplification of the configuration of the semiconductor device AP and cost reduction in design and manufacture of the semiconductor device AP.

In the sixth exemplary embodiment, the element M2 included in the gate electrode 22 is the same as the element M4 included in the source electrode 23 and the drain electrode 24. The use of the same elements in the three electrodes of transistor 20 results in a cost reduction.

In the seventh exemplary embodiment, the element M3 included in the gate electrode 12 is the same as the element M1 included in the source electrode 13 and the drain electrode 14. The use of the same elements in the three electrodes of the transistor 10 results in a cost reduction.

In the eighth exemplary embodiment, the gate electrode 22 has a conductor layer including the element M4, and the element M4 is the same as the element M1 included in the source electrode 13 and the drain electrode 14. The conductor layer of the gate electrode 22 may be continuous with the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14. The conductor layer of the gate electrode 22 including the element M4 may be discontinuous with the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14 including the element M1.

In the ninth exemplary embodiment, the conductor member 28 has a conductor layer including the element M5, and the element M5 is the same as the element M1 included in the source electrode 13 and the drain electrode 14. The semiconductor layer 21 is disposed between the gate electrode 22 and the conductor member 28 (conductor layer including the element M5). In the ninth exemplary embodiment, the conductor layer including the same element M5 as the element M1 is the conductor member 28. The conductor layer of the conductor member 28 including the element M5 may be continuous with the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14 including the element M1. The conductor layer of the conductor member 28 may be discontinuous with the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14 including the element M1.

The potential of the conductor member 28 (the conductor layer including the element M5) may be the same as the potential of any one of the gate electrode 12, the source electrode 13, the drain electrode 14, the gate electrode 22, the source electrode 23, and the drain electrode 24. In particular, the potential of the conductor member 28 (the conductor layer including the element M5) may be the same as the potential of the gate electrode 22. To achieve this, the gate electrode 22 and the conductor member 28 may be electrically connected to each other. The conductor layer of the gate electrode 22 including the element M2 and the conductor layer of the conductor member 28 including the element M5 may be in contact with each other, or the two conductor layers may be electrically connected via another conductor layer (e.g., a via). The electric field to be added to the semiconductor layer 21 is controlled by the gate electrode 22 and the conductor member 28 disposed on both sides of the semiconductor layer 21. The potential of the conductor member 28 (the conductor layer including the element M5) may be different from any one of the potentials of the gate electrode 12, the source electrode 13, the drain electrode 14, the gate electrode 22, the source electrode 23, and the drain electrode 24, or may be a floating potential.

The element M3 as a metal element or a metalloid element included in the gate electrode 12 may be different from the element M2 as a metal element or a metalloid element included in the gate electrode 22. The difference in the main metal element or metalloid element included in the gate electrodes 12 and 22 is advantageous in achieving the characteristics of the transistors 10 and 20.

Among the elements of groups 12 to 16 included in the semiconductor layer 11, an element having the second highest concentration in the semiconductor layer 11 after the element S1 will be described as an element S3. In the case where the semiconductor layer 11 is a binary compound semiconductor, the semiconductor layer 11 is a compound of the element S1 and the element S3. Among the elements of groups 12 to 16 included in the semiconductor layer 21, an element having the second highest concentration in the semiconductor layer 21 after the element S2 will be described as an element S4. When the semiconductor layer 21 is a binary compound semiconductor, the semiconductor layer 21 is a compound of the element S2 and the element S4. The element S3 included in the semiconductor layer 21 may be different from the element S4 included in the semiconductor layer 21.

In the case where the elements S1 and S2 are oxygen (O) in an oxide semiconductor such as InGaZnO or insnnzno, the elements S3 and S4 may be zinc (Zn). In an oxide semiconductor such as InGaZnO or insnzzno, the concentration of zinc may be, for example, 10at% to 30at% or 10at% to 20at%, or 16at%. In the case where the elements S1 and S2 are oxygen (O) In an oxide semiconductor such as InGaZnO or insnnzno, the elements S3 and S4 may be indium (In). For example, the concentration of indium may be 5at% to 20at%, or 14at%. In an oxide semiconductor such as InGaZnO or insnnzno, the concentration of gallium (Ga) and tin (Sn) may be lower than the concentration of zinc (Zn). In an oxide semiconductor such as InGaZnO or insnnzno, the concentration of gallium (Ga) and tin (Sn) may be lower than the concentration of indium (In). In an oxide semiconductor such as InGaZnO or insnnzno, the concentration of gallium (Ga) and tin (Sn) may be, for example, 5at% to 20at%, or 10at%. For example, in InGaZnO, in: ga: zn: o=16:10:14:60 is obtained.

In the tenth exemplary embodiment, the conductor layer including the same element (e.g., the element M2 or the element M5) as the element M1 included in the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14 may be the same layer as the conductor layer of the source electrode 13 or the conductor layer of the drain electrode 14. The conductor layers being the same layer means that the conductor layers are layers formed of a single film. Even if the conductor layers are the same layer, the heights of the two layers from the substrate 1 may be different from each other due to the base height difference generated during film formation. Furthermore, in the case where the conductor layers are the same layer, the two layers may have substantially the same thickness. Here, the two layers having substantially the same thickness means that the thickness of one layer falls within a range of 90 to 110 percent (%) of the thickness of the other layer.

A combination of the types of transistors 10 and 20 will be described with reference to table 1.

TABLE 1

In table 1, 32 modes of combinations of the types of transistors 10 and 20 are listed. In table 1, "T" is described on the TB column when the transistors 10 and 20 are of the T type, and "B" is described on the TB column when the transistors 10 and 20 are of the B type. When the transistors 10 and 20 are of the C type, "C" is described on the CS column, and when the transistors 10 and 20 are of the S type, "S" is described on the CS column. In table 1, "G" is described on M columns when the component including the same element as the element M1 included in the source electrode 13 and the drain electrode 14 is the gate electrode 22. Further, when the component including the same element as the element M1 included in the source electrode 13 and the drain electrode 14 is the conductor member 28 other than the gate electrode 22, "N" is described on the M columns.

No.01 to 04 and No.09 to 12 correspond to the second exemplary embodiment. No.21 to 24 and No.29 to 32 correspond to the third exemplary embodiment. No.01, 02, 05, and 06, and No.17, 18, 21, and 22 correspond to the fourth exemplary embodiment. No.11, 12, 15, and 16, and No.27, 28, 31, and 32 correspond to the fifth exemplary embodiment. An odd example describing "G" on the M column corresponds to the eighth exemplary embodiment. An odd example describing "N" on the M column corresponds to the ninth exemplary embodiment.

Fig. 3A illustrates an example of a cross-sectional view of the semiconductor device AP having the configuration of No.01 in table 1 using a combination of dot-dash lines. The dash-dot line in fig. 3A indicates that members connected by the dash-dot line are the same layer. More specifically, the dot-dash line indicates that the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are located in the same layer.

Fig. 3B illustrates an example of a cross-sectional view of the semiconductor device AP having the configuration of No.31 in table 1 using a combination of dot-dash lines. The dash-dot line in fig. 3B indicates that the members connected by the dash-dot line are the same layer. More specifically, the dot-dash line indicates that the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are located in the same layer.

Fig. 4A illustrates an example of a cross-sectional view of the semiconductor device AP having the configuration of No.02 in table 1 using a combination of dot-dash lines. The dash-dot line in fig. 4A indicates a case where members connected by the dash-dot line are the same layer. More specifically, the dash-dot line indicates a case where the source electrode 13 (and the drain electrode 14) and the conductor member 28 are located in the same layer.

Fig. 4A illustrates an example of a cross-sectional view of a semiconductor device AP having the configuration of No.01 in table 1 using a two-dot chain line combination. The two-dot chain line in fig. 4A indicates a case where members connected by the two-dot chain line are the same layer. More specifically, the two-dot chain line indicates a case where the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are located in the same layer.

Fig. 4B illustrates an example of a cross-sectional view of the semiconductor device AP having the configuration of No.32 in table 1 using a combination of dot-dash lines. The dash-dot line in fig. 4B indicates that the members connected by the dash-dot line are the same layer. More specifically, the dash-dot line indicates a case where the source electrode 13 (and the drain electrode 14) and the conductor member 28 are located in the same layer.

Fig. 4B illustrates an example of a cross-sectional view of the semiconductor device AP having the configuration of No.31 in table 1 using a two-dot chain line combination. The two-dot chain line in fig. 4B indicates a case where members connected by the two-dot chain line are the same layer. More specifically, the two-dot chain line indicates a case where the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are located in the same layer.

Fig. 5A illustrates an example of a cross-sectional view of a semiconductor device AP having the configuration of No.08 in table 1 using a combination of dot-dash lines. The dash-dot line in fig. 5A indicates that members connected by the dash-dot line are the same layer. More specifically, the dot-dash line indicates that the source electrode 13 (and the drain electrode 14) and the conductor member 28 are located in the same layer.

Fig. 5A illustrates an example of a cross-sectional view of a semiconductor device AP having the configuration of No.07 in table 1 using two-dot chain line combinations. The two-dot chain line in fig. 5A indicates a case where members connected by the two-dot chain line are the same layer. More specifically, the two-dot chain line indicates a case where the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are located in the same layer.

Fig. 5B illustrates an example of a cross-sectional view of the semiconductor device AP having the configuration of No.27 in table 1 using a combination of dot-dash lines. The dash-dot line in fig. 5B indicates that the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are located in the same layer.

Fig. 6A illustrates an example of a cross-sectional view of the T/C type transistor shown in fig. 2A. Fig. 6A illustrates the dimensional relationship of thickness and distance of the layers. For example, in the transistor 20, the gate electrode 22, the source electrode 23, and the drain electrode 24 have a thickness T1. The thickness T2 of the semiconductor layer 21 is smaller than the thickness T1 (T1 > T2). The thickness T3 of the gate insulating film 25 is smaller than the thickness T1 (T1 > T3). As shown in fig. 6A, thickness T3 may be less than thickness T2 (T3 < T2), but thickness T3 may be greater than thickness T2 (T2 > T3). The distance between the conductor member 28 and the semiconductor layer 21 is larger than the distance between the gate electrode 22 and the semiconductor layer 21 (the thickness of the gate insulating film 25). An interlayer insulating film 26 is disposed between the conductor member 28 and the semiconductor layer 21. An interlayer insulating film 27 is disposed between the semiconductor layer 21 and the source electrode 23. The interlayer insulating film 27 is located in the same layer as the gate insulating film 25. An interlayer insulating film 29 is disposed and covers the transistor 20. The gate insulating film 25 has a portion extending outward from a region between the gate electrode 22 and the semiconductor layer 21 (a portion not overlapping the gate electrode 22), and the interlayer insulating film 25 has a protruding portion reflecting the extending portion (a portion not overlapping the gate electrode 22).

This structure of the transistor 20 shown in fig. 6A can also be applied to the transistor 10. For example, in the transistor 10, the interlayer insulating film 16 is disposed below the semiconductor layer 11, the interlayer insulating film 17 is disposed on the semiconductor layer 11, and the semiconductor layer 11 is disposed between the interlayer insulating film 16 and the interlayer insulating layer 17. Then, an interlayer insulating film 19 is disposed and covers the transistor 10. The conductor member 28 does not need to extend between the semiconductor layer 11 and the substrate 1. Any one of the interlayer insulating films 16, 17, and 19 overlapping the transistor 10 and any one of the interlayer insulating films 26, 27, and 29 overlapping the transistor 20 may be the same layer. For example, the interlayer insulating film 19 and the interlayer insulating film 26 may be the same layer. The interlayer insulating film 17 may correspond to the same layer as the gate insulating film 15. Although the conductor member 28 is disposed between the semiconductor layer 21 and the substrate 1, an interlayer insulating film disposed between the conductor member 28 and the substrate 1 may be in the same layer as at least one of the interlayer insulating film 17 and the gate insulating film 15.

Fig. 6B illustrates an example of a cross-sectional view of the B/S type transistor shown in fig. 2A. Fig. 6B illustrates the dimensional relationship of thickness and distance of the layers. This example is different from that in fig. 6B in that the gate insulating film 25 has a thickness T4 greater than the thickness T2 (T4 > T2). Further, in the transistor 10, the interlayer insulating film 16 is disposed below the semiconductor layer 11, and the interlayer insulating film 17 is disposed on the semiconductor layer 11, and the semiconductor layer 11 is disposed between the interlayer insulating film 16 and the interlayer insulating layer 17.

A method of manufacturing the semiconductor device AP will be described with reference to fig. 7A to 7D.

Fig. 7A illustrates a first example of a manufacturing method. In the first example, in a process S11, a semiconductor layer 11 is formed on a substrate 1. In the process S12, the conductor film 18 covering the semiconductor layer 11 is formed on the substrate 1. In this process, the conductor film 18 is in contact with the semiconductor layer 11. In the process S13, patterning of the conductor film 18 is performed. Although both wet etching and dry etching may be used for patterning, it is desirable to use wet etching to reduce damage to the semiconductor layer 11. In patterning, the source electrode 13 and the drain electrode 14 are formed from the conductor film 18. Further, in patterning, the gate electrode 22 or the conductor member 28 is formed from the conductor film 18. In the process S14, the semiconductor layer 21 insulated from the gate electrode 22 or the conductor member 28 is formed over the gate electrode 22 or the conductor member 28. In this way, the gate electrode 22 or the conductor member 28 is formed in the same layer as the source electrode 13 and the drain electrode 14.

Fig. 7B illustrates a second example of a manufacturing method. In the second example, in the process S21, the conductor film 18 is formed on the substrate 1. In the process S22, patterning of the conductor film 18 is performed. Both wet and dry etches may be used for patterning. In patterning, the source electrode 13 and the drain electrode 14 are formed from the conductor film 18. Further, in patterning, the gate electrode 22 or the conductor member 28 is formed from the conductor film 18. In the process S23, the semiconductor layer 11 covering the source electrode 13 and the drain electrode 14 is formed. In this process, the semiconductor layer 11 is in contact with the source electrode 13 and the drain electrode 14. In the process S14, the semiconductor layer 21 insulated from the gate electrode 22 or the conductor member 28 is formed over the gate electrode 22 or the conductor member 28. In this way, the gate electrode 22 or the conductor member 28 is formed in the same layer as the source electrode 13 and the drain electrode 14.

Fig. 7C illustrates a third example of the manufacturing method. In the second example, in the process S31, the semiconductor layer 11 is formed on the substrate 1. In the process S32, the semiconductor layer 21 is formed on the substrate 1. In the process S33, the conductor film 18 covering the semiconductor layer 11 and the semiconductor layer 21 is formed on the substrate 1. In this process, the conductor film 18 is in contact with the semiconductor layer 11, and an insulating film is formed between a part of the conductor film 18 and the semiconductor layer 21. In the process S34, patterning of the conductor film 18 is performed. Although both wet etching and dry etching may be used for patterning, it is desirable to use wet etching to reduce damage to the semiconductor layers 11 and 21. In patterning, the source electrode 13 and the drain electrode 14 are formed from the conductor film 18. Further, by patterning, the gate electrode 22 or the conductor member 28 is formed from the conductor film 18. With the insulating film formed in the process S34, the gate electrode 22 or the conductor member 28 is insulated from the semiconductor layer 21. In this way, the gate electrode 22 or the conductor member 28 is formed in the same layer as the source electrode 13 and the drain electrode 14.

Fig. 7D illustrates a fourth example of the manufacturing method. In the second example, in the process S41, the semiconductor layer 21 is formed on the substrate 1. In process S42, the semiconductor layer 11 is formed on the substrate 1. In the process S43, the conductor film 18 covering the semiconductor layer 11 and the semiconductor layer 21 is formed on the substrate 1. In this process, the conductor film 18 is in contact with the semiconductor layer 11, and an insulating film is formed between a part of the conductor film 18 and the semiconductor layer 21. In process S44, patterning of the conductor film 18 is performed. Although both wet etching and dry etching may be used for patterning, it is desirable to use wet etching to reduce damage to the semiconductor layers 11 and 21. In patterning, the source electrode 13 and the drain electrode 14 are formed from the conductor film 18. Further, in patterning, the gate electrode 22 or the conductor member 28 is formed from the conductor film 18. With the insulating film formed in the process S44, the gate electrode 22 or the conductor member 28 is insulated from the semiconductor layer 21. In this way, the gate electrode 22 or the conductor member 28 is formed in the same layer as the source electrode 13 and the drain electrode 14.

In the first example shown in fig. 7A and the second example shown in fig. 7B, since the conductor film 18 is formed before the formation of the semiconductor layer 21, unevenness generated in the conductor film 18 can be reduced as compared with the third example shown in fig. 7C and the fourth example shown in fig. 7D in which the conductor film 18 is formed after the formation of the semiconductor layer 21. Therefore, in the first example shown in fig. 7A and the second example shown in fig. 7B, patterning of the conductor film 18 can be performed better than in the third example shown in fig. 7C and the fourth example shown in fig. 7D.

In fig. 7A to 7D, the semiconductor layer 11 may be formed using a Chemical Vapor Deposition (CVD) method, the semiconductor layer 21 may be formed using a Physical Vapor Deposition (PVD) method, the conductor film 18 may be formed using a PVD method, and the insulator film may be formed using a CVD method.

In the eleventh exemplary embodiment, the distance D1 between the semiconductor layer 11 and the substrate 1 may be different from the distance D2 between the semiconductor layer 21 and the substrate 1. The difference between the distance D1 and the distance D2 in the transistors 10 and 20 achieves more suitable characteristics of the transistors 10 and 20 than in the case where the distance D1 and the distance D2 are equal to each other. The influence is applied from the substrate 1 to the semiconductor layers 11 and 21, and the influence is applied to the semiconductor layers 11 and 21 from members present on the opposite side to the side facing the substrate 1 with respect to the semiconductor layers 11 and 21. The difference between the distance D1 and the distance D2 in the transistors 10 and 20 achieves more suitable characteristics of the transistors 10 and 20.

In the twelfth exemplary embodiment, the distance D3 between the substrate 1 and the gate electrode 12 may be different from the distance D4 between the substrate 1 and the gate electrode 22. More specifically, the influence is applied to the gate electrodes 12 and 22 from the substrate 1, the influence is applied to the gate electrodes 12 and 22 from members present on the opposite side to the side facing the substrate 1 with respect to the gate electrodes 12 and 22, and the characteristics of the transistors 10 and 20 can be optimized.

The distance D3 between the substrate 1 and the gate electrode 12 may be different from the distance D2 between the substrate 1 and the semiconductor layer 21. Further, the distance D4 between the substrate 1 and the gate electrode 22 may be different from the distance D1 between the substrate 1 and the semiconductor layer 11.

In the thirteenth exemplary embodiment, the distance D5 between the semiconductor layer 11 and the gate electrode 12 may be different from the distance D6 between the semiconductor layer 21 and the gate electrode 22. The distance D5 between the semiconductor layer 11 and the gate electrode 12 corresponds to the thickness of the gate insulating film 15, and the distance D6 between the semiconductor layer 21 and the gate electrode 22 corresponds to the thickness of the gate insulating film 25. The difference between the distance D5 and the distance D6 in the transistors 10 and 20 achieves more suitable characteristics of the transistors 10 and 20 than in the case where the distance D5 and the distance D6 are equal to each other.

As in the eleventh to thirteenth exemplary embodiments, in the case where the positional relationship among the substrate 1, the semiconductor layers 11 and 21, and the gate electrodes 12 and 22 is changed in the transistors 10 and 20, unevenness is easily generated between the transistor 10 and the transistor 20. If the conductor layers of the same layer between the transistor 10 and the transistor 20 are continuous with each other, unexpected disconnection between the conductor layers may occur due to non-uniformity between the transistor 10 and the transistor 20. Accordingly, it is desirable that the conductor layers of the same layer be discontinuous with each other between the transistor 10 and the transistor 20. The conductor layer may be connected via another conductor layer in order to electrically connect the discontinuous conductor layers of the same layer. For example, in the case where the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are electrically connected in the same layer and in a discontinuous manner, these electrodes may be connected via a conductor layer included in at least one of the gate electrode 12 and the source electrode 23 (drain electrode 24).

In the fourteenth exemplary embodiment, the element S1 included in the semiconductor layer 11 may be a group 14 element, and the element S2 included in the semiconductor layer 21 may be a group 12, group 13, group 15, or group 16 element. For example, the element S1 included in the semiconductor layer 11 may be silicon (Si), and the element S2 included in the semiconductor layer 21 may be oxygen (O). The semiconductor layer 11 may be a polycrystalline layer or an amorphous layer, and the semiconductor layer 21 may be an oxide semiconductor layer. The semiconductor layer 11 may be a polysilicon layer. In the semiconductor layer 21, the element S4 may be indium (In). The use of indium (In) as the element S4 allows the mobility of the semiconductor layer 21 to be increased. The semiconductor layer 21 may include gallium (Ga). The semiconductor layer 21 may include tin (Sn). In the case where the semiconductor layer 21 includes tin (Sn), mobility of the semiconductor layer 21 increases.

The substrate 1 may be an insulator substrate made of glass, resin, or the like, but may be a semiconductor substrate made of silicon or the like, or may be a conductor substrate made of metal or the like. In the case where the substrate 1 is a resin substrate, a base member in which a resin film made of polyimide or the like is formed on a base material such as glass is prepared, and the transistors 10 and 20 are formed on the resin film of the base member. After that, the base material is separated from the resin film using a laser or the like to use the resin film as the substrate 1 (resin substrate). The resin substrate may be a flexible substrate. In the case where the substrate 1 is a semiconductor substrate, at least either one of the semiconductor layers 11 or 21 may be a single crystal semiconductor layer epitaxially grown on the substrate 1 as a single crystal semiconductor, depending on the crystal structure of the substrate 1. Alternatively, in the case where the substrate 1 is a semiconductor substrate, at least either one of the semiconductor layers 11 or 21 may have a structure (a semiconductor-on-insulator (SOI) structure) formed on the substrate 1 as a single crystal semiconductor with an insulator layer interposed therebetween. In the case where the substrate 1 is a conductor substrate, an insulator layer may be disposed between the semiconductor layer 11 or 21 and the substrate 1. Transistor 10 may be a P-type transistor or may be an N-type transistor. Transistor 10 is intended to form a CMOS circuit with transistor 30, and transistor 10 is intended to be a P-type transistor and transistor 30 is an N-type transistor. Transistor 10 may be an N-type transistor and transistor 30 may be a P-type transistor. Among the elements of groups 12 to 16 included in the semiconductor layer 31 of the transistor 30, the element having the highest concentration in the semiconductor layer 31 will be described as the element S5. The element S5 may be the same as the element S1 included in the semiconductor layer 11. Among the elements of groups 12 to 16 included in the semiconductor layer 31 of the transistor 30, an element having a second highest concentration in the semiconductor layer 31 after the element S5 will be described as an element S6. The element S6 may be different from the element S3 included in the semiconductor layer 11. For example, the element S1 and the element S5 may be silicon (Si), the element S3 may be boron (B), and the element S6 may be phosphorus (P).

In the case where the transistor 10 is an N-type transistor and the transistor 30 is a P-type transistor, the element S3 may be phosphorus (P) and the element S6 may be boron (B). In the case where the semiconductor layer 11 of the transistor 10 and the semiconductor layer 31 of the transistor 30 are polycrystalline semiconductor layers, carrier mobility increases, which is desirable for realizing high-speed switching. In the case where the semiconductor layer 11 of the transistor 10 and the semiconductor layer 31 of the transistor 30 are polycrystalline semiconductor layers, carrier mobility increases, and thus gate voltage decreases, which is desirable for achieving reduction in power consumption as compared with the case of an amorphous semiconductor.

Transistor 20 may be a P-type transistor or may be an N-type transistor. Because electron mobility is generally higher than hole mobility, it is desirable that transistor 20 be an N-type transistor. It is also desirable that the transistor 20 be a switching transistor. If transistor 20 is an N-type switching transistor, high speed switching may be performed. In the case where the semiconductor layer 21 of the transistor 20 is an oxide semiconductor, the band gap becomes wider, and thus the leakage current of the switching transistor is reduced due to the wide band gap, which is desirable for achieving reduction of the leakage current of the switching transistor.

The substrate 1 may have various sizes, but it is desirable that the diagonal length is greater than or equal to 1 centimeter (cm), and it is also desirable that the diagonal length is greater than or equal to 2.5cm. In the case where the diagonal length is less than 2.5cm, the semiconductor layer 11 of the transistor 10 may be a single crystal layer. For example, the transistor 10 may be formed over the substrate 1 made of single crystal silicon, and the transistor 20 as a thin film transistor may be formed over the substrate 1. The diagonal length of the substrate 1 may be greater than or equal to 5cm. In the case where the diagonal length of the substrate 1 is greater than or equal to 5cm, it is desirable that the transistor 10 be a thin film transistor, and the semiconductor layer 11 may be a polycrystalline layer or an amorphous layer. In the case where the semiconductor layer 11 is a polycrystalline layer or an amorphous layer, sufficient uniformity for the characteristics of the transistor 10 is ensured even if the diagonal length of the substrate 1 is 5cm or more. In the case where the diagonal length of the substrate 1 is less than 75cm, the semiconductor layer 11 of the transistor 10 is desirably a polycrystalline layer. In the case where the semiconductor layer 11 of the transistor 10 is a polycrystalline layer, the diagonal length of the substrate 1 may be greater than or equal to 20cm, may be greater than or equal to 25cm, and may be greater than or equal to 30cm. In the case where the diagonal length of the substrate 1 is 20cm or more, it is desirable to dispose the transistor 10 using a polycrystalline layer as the semiconductor layer 11 in the pixel circuit PX. In the case of using a polycrystalline layer having high charge mobility for the amplifier transistor 104 and the driving transistor 106 of the pixel circuit PX, power consumption of the power supply line PL connected to the pixel circuit PX is reduced even in the substrate 1 having a large diagonal length. In the case where the transistor 10 is disposed in the pixel circuit PX, from the viewpoint of improving the image quality, the diagonal length of the substrate 1 is desirably less than 50cm. In the case where the diagonal length of the substrate 1 is less than 50cm, sufficient uniformity for the characteristics of the transistor 10 is ensured. In the case where the diagonal length of the substrate 1 is 75cm or more, it is desirable that the semiconductor layer 11 of the transistor 10 be an amorphous layer. The semiconductor layer 21 of the transistor 20 is desirably an oxide semiconductor layer regardless of which diagonal length the substrate 1 has.

Although the diagonal length of the substrate 1 has been described, the same applies to the diagonal length of the pixel region 2, and the diagonal length of the substrate 1 may be interpreted as the diagonal length of the pixel region 2. For example, it is desirable that the diagonal length of the pixel region 2 is greater than or equal to 1cm, it is also desirable that the diagonal length of the pixel region 2 is greater than or equal to 2.5cm, it is also desirable that the diagonal length of the pixel region 2 is greater than or equal to 5cm, and the diagonal length of the pixel region 2 may be greater than or equal to 20cm, greater than or equal to 25cm, greater than or equal to 30cm, or may be less than 75cm.

The fifteenth exemplary embodiment is an exemplary embodiment obtained by combining the eleventh exemplary embodiment and the fourteenth exemplary embodiment, and it is desirable that the distance D1 between the semiconductor layer 11 and the substrate 1 is smaller than the distance D2 between the semiconductor layer 21 and the substrate 1. In the case where the semiconductor layer 11 is a polycrystalline layer, crystallinity control is important. In the case where the semiconductor layer 11 is disposed closer to the substrate 1 than the semiconductor layer 21, the flatness of the semiconductor layer 11 is improved, which improves uniformity of crystallinity. Further, in the case where the semiconductor layer 11 is formed earlier than the semiconductor layer 21, the influence of the heat treatment for forming the semiconductor layer 11 is prevented from being exerted on the semiconductor layer 21. That is, before forming the semiconductor layer 21, an appropriate heat treatment can be performed on the semiconductor layer 11. Therefore, crystallinity of the semiconductor layer 11 is more easily controlled.

The sixteenth exemplary embodiment is an exemplary embodiment obtained by combining the twelfth exemplary embodiment and the fourteenth exemplary embodiment, and it is desirable that the distance D3 between the substrate 1 and the gate electrode 12 is smaller than the distance D4 between the substrate 1 and the gate electrode 22.

The seventeenth exemplary embodiment is an exemplary embodiment obtained by combining the twelfth exemplary embodiment and the fifteenth exemplary embodiment, and it is desirable that the distance D5 between the semiconductor layer 11 and the gate electrode 12 is smaller than the distance D6 between the semiconductor layer 21 and the gate electrode 22. The distance D5 between the semiconductor layer 11 and the gate electrode 12 corresponds to the thickness of the gate insulating film 15, and the distance D6 between the semiconductor layer 21 and the gate electrode 22 corresponds to the thickness of the gate insulating film 25. For example, distance D5 may be 200 to 400 nanometers (nm) and distance D6 may be 50 to 200nm. Thinning the gate insulating film 15 improves the response characteristics of the transistor 10, which realizes a good driving force. In addition, thickening the gate insulating film 25 further reduces the leakage current of the transistor 20.

The eighteenth exemplary embodiment relates to the capacitor C disposed on the substrate 1. Although the capacitor C can be applied to, for example, the capacitors 103 and 108 shown in fig. 1C and 1D, respectively, the capacitor C is not limited to the capacitor in the pixel circuit PX, and may also be used in the integrated circuit of the peripheral area 3. As shown in fig. 8, at least one of the lower gate electrode 221 and the upper gate electrode 222 is disposed above the substrate 1 as the gate electrode 22 overlapping with the semiconductor layer 21. For convenience of description, fig. 8 illustrates both the lower gate electrode 221 and the upper gate electrode 222, but one of the gate electrodes may be omitted.

The lower gate electrode 221 is disposed on the substrate 1 side with respect to the semiconductor layer 21, and the lower gate electrode 221 is located between the semiconductor layer 21 and the substrate 1. The lower gate electrode 221 corresponds to the gate electrode 22 in the B-type transistor 20 shown in fig. 2B, 2C, 3B, 4B, 5B, and 6B.

The upper gate electrode 222 is disposed on a side opposite to the substrate 1 side with respect to the semiconductor layer 21, and the semiconductor layer 21 is located between the upper gate electrode 222 and the substrate 1. The upper gate electrode 222 corresponds to the gate electrode 22 in the T-type transistor 20 shown in fig. 2A, 2D, 3A, 4A, 5A, and 6A. The lower gate electrode 221 and/or the upper gate electrode 222 overlap the semiconductor layer 21, and the gate insulating film 25 is disposed between the lower gate electrode 221 and the semiconductor layer 21 and/or between the upper gate electrode 222 and the semiconductor layer 21.

The lower gate electrode 221 may overlap the source electrode 23 or the drain electrode 24. Thus, the lower gate electrode 221 forms a capacitor Ce together with the source electrode 23 or the drain electrode 24. The upper gate electrode 222 may overlap with the source electrode 23 or the drain electrode 24. Thus, the lower gate electrode 221 forms a capacitor Ch together with the source electrode 23 or the drain electrode 24. In this way, each of the capacitors Ce and Ch is a MIM type capacitor in which a dielectric layer is located between a conductor layer and another conductor layer.

Especially in the case where both the lower gate electrode 221 and the upper gate electrode 222 are disposed, the potential of the lower gate electrode 221 may be the same as the potential of the upper gate electrode 222. To achieve this, the lower gate electrode 221 and the upper gate electrode 222 may be electrically connected to each other. The conductor layer of the lower gate electrode 221 and the conductor layer of the upper gate electrode 222 may be in contact with each other, or the two conductor layers may be electrically connected to each other via another conductor layer (e.g., a via).

It is desirable that the element M2 in at least one of the conductor layer of the lower gate electrode 221 and the conductor layer of the upper gate electrode 222 is the same as the element M1 in at least one of the conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14. Further, it is also desirable that the conductor layer of the lower gate electrode 221 or the conductor layer of the upper gate electrode 222 including the element M2 be the same layer as at least one of the conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14 including the element M1.

The nineteenth exemplary embodiment also relates to a capacitor C disposed on the substrate 1. Although, for example, the capacitor C is applicable to the capacitors 103 and 108 shown in fig. 1C and 1D, respectively, the capacitor is not limited to the capacitor in the pixel circuit PX, and can also be used in the integrated circuit of the peripheral area 3. A description of points similar to those in the eighteenth exemplary embodiment will be omitted. As shown in fig. 8, at least one of the lower capacitor electrode 281 and the upper capacitor electrode 282 is disposed above the substrate 1 as a conductor member 28. For convenience of description, fig. 8 illustrates both the lower capacitor electrode 281 and the upper capacitor electrode 282, but one of the capacitor electrodes may be omitted, or both the lower capacitor electrode 281 and the upper capacitor electrode 282 may be omitted.

The lower capacitor electrode 281 overlaps at least any one of the lower gate electrode 221, the source electrode 23, the drain electrode 24, the upper gate electrode 222, and the upper capacitor electrode 282. The lower capacitor electrode 281 is disposed between an electrode overlapping with the lower capacitor electrode 281 and the substrate 1.

At least any one of the lower capacitor electrode 281 and an electrode overlapping with the lower capacitor electrode 281 forms a MIM type capacitor in which a dielectric layer is located between a conductor layer and another conductor layer. In this example, the dielectric layer of the capacitor is an interlayer insulating film 26. For example, the lower capacitor electrode 281 forms a capacitor Cf together with the lower gate electrode 221. For example, the lower capacitor electrode 281 forms a capacitor Ci together with the source electrode 23 or the drain electrode 24. For example, the lower capacitor electrode 281 forms a capacitor Cj together with the upper gate electrode 222. For example, the lower capacitor electrode 281 forms a capacitor Ca together with the upper capacitor electrode 282.

The upper capacitor electrode 282 overlaps at least any one of the lower capacitor electrode 281, the lower gate electrode 221, the source electrode 23, the drain electrode 24, and the upper gate electrode 222. An electrode overlapping the upper capacitor electrode 282 is located between the upper capacitor electrode 282 and the substrate 1.

At least any one of the upper capacitor electrode 282 and an electrode overlapping the upper capacitor electrode 282 forms a MIM type capacitor in which a dielectric layer is located between a conductor layer and another conductor layer. In this example, the dielectric layer of the capacitor is an interlayer insulating film 26. For example, the upper capacitor electrode 282 forms a capacitor Ca together with the lower capacitor electrode 281. For example, the upper capacitor electrode 282 forms a capacitor Cb together with the lower gate electrode 221. For example, the upper capacitor electrode 282 forms a capacitor Cd together with the source electrode 23 or the drain electrode 24. For example, the upper capacitor electrode 282 forms a capacitor Cg together with the upper gate electrode 222.

In the example shown in fig. 8, it has been described that the lower capacitor electrode 281 and the upper capacitor electrode 282 overlap with the semiconductor layer 21. The lower capacitor electrode 281 is located between the semiconductor layer 21 and the substrate 1. Further, the semiconductor layer 21 is located between the upper capacitor electrode 282 and the substrate 1. As long as the lower capacitor electrode 281 and the upper capacitor electrode 282 overlap with the counter electrode forming the capacitor, a configuration may be adopted in which the lower capacitor electrode 281 and the upper capacitor electrode 282 do not overlap with the semiconductor layer 21.

It is desirable that the element M5 in at least one of the conductor layer of the lower capacitor electrode 281 and the conductor layer of the upper capacitor electrode 282 is the same as the element M1 in at least one of the conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14. Further, it is desirable that the conductor layer of the lower capacitor electrode 281 or the conductor layer of the upper capacitor electrode 282 including the element M5 be the same layer as at least one of the conductor layer of the source electrode 13 and the conductor layer of the drain electrode 14 including the element M1.

In the eighteenth and nineteenth exemplary embodiments, at least one of the two electrodes forming the capacitor C is the gate electrode 22 or the conductor member 28 (capacitor electrode) that is not in contact with the semiconductor layer 21. The other of the two electrodes forming the capacitor C is the gate electrode 22 or the conductor member 28 (capacitor electrode) which is not in contact with the semiconductor layer 21, or the source electrode 13 or the drain electrode 14 which is in contact with the semiconductor layer 21. Then, among the two electrodes forming the capacitor C, an electrode that is not in contact with the semiconductor layer 21 (the gate electrode 22 or the conductor member 28 (capacitor electrode)) is insulated from the other electrode of the two electrodes forming the capacitor C by a dielectric layer (the interlayer insulating film 26).

The capacitors 103 and 108 shown in fig. 1C and 1D are connected to the source or drain of the reset transistor 102 serving as the transistor 20, the source or drain of the selection transistor 107, and the source or drain of the drive transistor 106, respectively. When connected, the electrodes of the capacitor electrically connected to the semiconductor layers 11 and 21 of the transistors 10 and 20 may be indirectly connected to the semiconductor layers 11 and 21 via another conductor layer (via hole or the like) in such a manner as not to be in contact with the semiconductor layers 11 and 21. In this configuration, metal contamination of the semiconductor layers 11 and 21 can be prevented. Especially in the case where the elements M1 to M5 are easily diffused copper (Cu), it is desirable to prevent the conductor layer (copper layer) made of copper from coming into contact with the semiconductor layers 11 and 21.

In the example shown in fig. 4A, 5A, and 6A, the gate electrode 22 may correspond to the upper gate electrode 222 shown in fig. 8, and the conductor member 28 may correspond to the lower capacitor electrode 281 shown in fig. 8. Then, the gate electrode 22 and the conductor member 28 may form a capacitor Cj shown in fig. 8. For example, the capacitor Cj may be used as the capacitors 103 and 108 shown in fig. 1C or 1D.

In the example shown in fig. 4B, the gate electrode 22 may correspond to the lower gate electrode 221 shown in fig. 8, and the conductor member 28 may correspond to the upper capacitor electrode 282 shown in fig. 8. Then, the gate electrode 22 and the conductor member 28 may form a capacitor Cb shown in fig. 8. For example, the capacitor Cb may be used as the capacitors 103 and 108 shown in fig. 1C or 1D.

Fig. 9A illustrates an example of a cross-sectional view of a semiconductor device AP having the configuration of No.01 in table 1 using a combination of dot-dash lines. The dash-dot line in fig. 9A indicates that members connected by the dash-dot line are the same layer. More specifically, the dot-dash line indicates that the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are located in the same layer.

Fig. 9A illustrates an example of a cross-sectional view of a semiconductor device AP having the configuration of No.02 in table 1 using a two-dot chain line combination. The two-dot chain line in fig. 9A indicates a case where members connected by the two-dot chain line are the same layer. More specifically, the two-dot chain line indicates a case where the source electrode 13 (and the drain electrode 14) and the conductor member 28 are located in the same layer.

In the example shown in fig. 9A, the gate electrode 22 corresponds to the upper gate electrode 222 shown in fig. 8, and the conductor member 28 corresponds to the upper capacitor electrode 282 shown in fig. 8. Then, the gate electrode 22 and the conductor member 28 form a capacitor Cg shown in fig. 8. For example, the capacitor Cg may be used as the capacitors 103 and 108 shown in fig. 1C or 1D.

Fig. 9B illustrates an example of a cross-sectional view of the semiconductor device AP having the configuration of No.17 in table 1 using a combination of dot-dash lines. The dash-dot line in fig. 9B indicates that the members connected by the dash-dot line are the same layer. More specifically, the dot-dash line indicates that the source electrode 13 (and the drain electrode 14) and the gate electrode 22 are located in the same layer.

Fig. 9B illustrates an example of a cross-sectional view of the semiconductor device AP having the configuration of No.18 in table 1 using a two-dot chain line combination. The two-dot chain line in fig. 9B indicates a case where members connected by the two-dot chain line are the same layer. More specifically, the two-dot chain line indicates a case where the source electrode 13 (and the drain electrode 14) and the conductor member 28 are located in the same layer.

In the example shown in fig. 9B, the gate electrode 22 corresponds to the lower gate electrode 221 shown in fig. 8, and the conductor member 28 corresponds to the lower capacitor electrode 281 shown in fig. 8. Then, the gate electrode 22 and the conductor member 28 form a capacitor Cf shown in fig. 8. For example, the capacitor Cf may be used as the capacitors 103 and 108 shown in fig. 1C or 1D.

Also, in fig. 3A to 9B, an insulator 40 as shown in fig. 1B is disposed on the substrate 1, and an insulator film such as an interlayer insulating film or a gate insulating film included in the insulator 40 is disposed around the semiconductor layer 11 or 21. In fig. 3A to 9B, at least a part of these insulators 40 is omitted from illustration.

Fig. 10A illustrates an equipment EQP including a semiconductor device AP. The equipment EQP may include at least any one of a display device DSPL, an imaging device IS, an AUDIO device AUDIO, a control device CTRL, and a communication device IF. In general, the display device DSPL or the imaging device IS has the above-described structure of the semiconductor device AP. The AUDIO device AUDIO, the control device CTRL and the communication device IF may have the above-described structure of the semiconductor device AP. The AUDIO device AUDIO includes a microphone and a speaker. The communication device IF performs cable communication or wireless communication. The communication apparatus IF may perform communication in a frequency band of 3.5 to 5.0 gigahertz (GHz), and may perform communication in a frequency band of 24 to 53 GHz. The communication device IF may perform communication using terahertz waves in addition to microwaves and millimeter waves. The control device CTRL may comprise a wiring board and a plurality of components mounted on the wiring board. The control means CTRL may comprise a semiconductor device manufactured in a 65 to 5nm process or may comprise a semiconductor device manufactured in a 1 to 4nm process. In the manufacture of these semiconductor devices, it is sufficient to use an Extreme Ultraviolet (EUV) exposure apparatus, an electron beam exposure apparatus, a nanoimprint lithography apparatus, or the like.

The control means CTRL are connected to the display means DSPL. In the case where the display device DSPL includes a driving circuit for driving the pixel circuits in the peripheral region 3, the control device CTRL may supply power and signals to the driving circuit. In the case where the display device DSPL does not include a driving circuit for driving the pixel circuits in the peripheral region 3, the control device CTRL includes a driving circuit for driving the pixel circuits.

The control means CTRL are connected to the imaging means IS. The control means CTRL controls the image capturing mode of the imaging means IS and processes the signal output from the imaging means IS. The imaging means IS may be an image sensor or may be an infrared sensor or a distance measuring sensor.

The equipment EQP may include an optical member OPT disposed above a display device DSPL as the semiconductor device AP. The optical member OPT is a lens, a cover, or a filter. In the case where the semiconductor device AP is the top emission type display device DSPL, the semiconductor layer 21 may be disposed between the substrate 1 of the semiconductor device AP and the optical member OPT. In the case where the semiconductor device AP is the bottom emission type display device DSPL, the substrate 1 may be disposed between the semiconductor layer 21 of the semiconductor device AP and the optical member OPT.

The setup EQP may include an imaging device IS and a display device DSPL. The image captured by the imaging device IS may be displayed on the display device DPSL.

The display device DSPL may be capable of switching a frame rate at which the display device DSPL performs display between a low frame rate and a high frame rate higher than the low frame rate. For example, the low frame rate is less than or equal to 10 frames per second (fps), or less than or equal to 5fps, or for example 1fps. For example, the high frame rate is greater than or equal to 100fps, or greater than or equal to 200fps, or for example 240fps. The display device DSPL may be capable of switching a refresh rate at which the display device DSPL performs display between a low refresh rate and a high refresh rate higher than the low refresh rate. For example, the low refresh rate is less than or equal to 10 hertz (Hz), or less than or equal to 5Hz, or for example 1Hz. For example, the high refresh rate is less than or equal to 100Hz, or greater than or equal to 200Hz, or for example 240Hz. Both frame rate units (fps) and refresh rate units (Hz) may be expressed as "frames per second" or "times per second". The display device DSPL may be capable of switching the frame rate at which the display device DSPL performs display to a medium frame rate between a low frame rate and a high frame rate. For example, the medium frame rate is 20 to 80fps. The display device DSPL may be capable of switching a refresh rate at which the display device DSPL performs display to a medium refresh rate between a low refresh rate and a high refresh rate. For example, the medium refresh rate is 20 to 80Hz. Since the oxide semiconductor layer has a small leakage current, in the case where the oxide semiconductor layer is used in the selection transistor 107, leakage of charge from the capacitor 108 is suppressed, whereby driving at a low frame rate is easily performed. Further, since the polycrystalline semiconductor layer has higher mobility than the amorphous semiconductor layer, in the case where the polycrystalline semiconductor layer is used in the selection transistor 107, the selection speed increases, whereby driving at a high frame rate and refresh rate is easily performed. Further, since the mobility of the polycrystalline semiconductor layer is higher than that of the amorphous semiconductor layer, in the case where the polycrystalline semiconductor layer is used in the driving transistor 106, reduction in gate voltage is achieved, whereby driving with low power consumption is easily performed.

The imaging device IS may perform image capturing at the above-described intermediate frame rate between the low frame rate and the high frame rate. The imaging device IS can perform image capturing at the above-described intermediate frame rate between the low refresh rate and the high refresh rate. For example, the imaging device IS may perform image capturing at a frame rate of 20 to 80 fps. The image capturing here is not limited to the stored image, but also includes image capturing for performing only temporary display, such as live view. It IS desirable that the frame rate of the display device DSPL to be set when an image captured by the imaging device IS at a medium frame rate IS to be displayed IS a medium frame rate or a high frame rate. It IS desirable that the refresh rate of the display device DSPL to be set when an image captured by the imaging device IS at a medium frame rate IS to be displayed IS a medium refresh rate or a high refresh rate. For example, it IS desirable that the refresh rate of the display device DSPL to be set when an image captured by the imaging device IS at a frame rate of 30 frames per second IS to be displayed IS 60 frames per second or 120 frames per second.

The equipment EQP may be an electronic equipment such as a smart phone, tablet terminal, laptop personal computer, digital camera, or wearable terminal. Arming EQP may include a battery, such as a lithium ion battery, a solid state battery, or a fuel cell. Since the power consumed by the imaging device IS and the display device DSPL can be reduced, a long driving time using a battery IS realized. Fig. 10B illustrates a head mounted display HMD serving as a wearable terminal. The main body including the display device DSPL and the imaging device IS may be attached to the head using the wearing unit WR. In addition to the above-described electronic equipment, the present invention can also be applied to various equipment such as transportation equipment, industrial equipment, medical equipment, and analysis equipment.

The above-described exemplary embodiments may be appropriately changed without departing from the technical idea. For example, a plurality of exemplary embodiments may be combined. Further, portions of the configuration described in at least one example embodiment may be deleted or replaced. Furthermore, new configurations may be added to at least one example embodiment.

The disclosure of the present specification is not limited to the matters explicitly described in the present specification, and includes all matters recognizable from the present specification and the accompanying drawings of the present specification. The disclosure of this specification includes a complementary set of concepts described in this specification. More specifically, for example, if "a is greater than B" is described in the present specification, the present specification can be said to disclose "a is not greater than B" even if the description of "a is not greater than B" is omitted. This is because, in the case where "a is greater than B" is described, a case where "a is not greater than B" is considered.

The present application is not limited to the above-described exemplary embodiments, and various changes and modifications may be made without departing from the spirit and scope of the present application. Accordingly, to disclose the scope of the present application, the appended claims are attached.

The present application claims the benefit of Japanese patent application No.2021-036296 filed on 3/8/2021 and Japanese patent application No.2021-109341 filed on 6/30/2021, which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device, comprising:

a substrate;

a first semiconductor layer serving as a first transistor and disposed over the substrate;

a first conductor layer disposed over the substrate and overlapping the first semiconductor layer;

a second semiconductor layer serving as a second transistor and disposed over the substrate; and

a second conductor layer disposed over the substrate and overlapping the second semiconductor layer,

wherein a first element having the highest concentration in the first semiconductor layer among elements of groups 12 to 16 included in the first semiconductor layer is different from a second element having the highest concentration in the second semiconductor layer among elements of groups 12 to 16 included in the second semiconductor layer,

wherein a third element having the highest concentration in the first conductor layer among the metal elements or metalloid elements included in the first conductor layer is the same as a fourth element having the highest concentration in the second conductor layer among the metal elements or metalloid elements included in the second conductor layer,

wherein the first conductor layer is in contact with the first semiconductor layer,

wherein the second conductor layer is insulated from the second semiconductor layer, and

wherein the second conductor layer is disposed between the second semiconductor layer and the substrate.

2. A semiconductor device, comprising:

a substrate;

a second semiconductor layer serving as a second transistor and disposed over the substrate;

a second conductor layer disposed over the substrate and overlapping the second semiconductor layer; and

a third conductor layer disposed over the substrate and overlapping the second conductor layer,

wherein the second conductor layer is insulated from the second semiconductor layer,

Wherein the third conductor layer is not in contact with the second semiconductor layer, and

wherein the third conductor layer is insulated from the second conductor layer.

3. A semiconductor device, comprising:

a substrate;

a first semiconductor layer serving as a P-type first transistor and disposed over the substrate;

a second semiconductor layer serving as an N-type second transistor and disposed over the substrate; and

wherein the first conductor layer is in contact with the first semiconductor layer, and

Wherein the second conductor layer is insulated from the second semiconductor layer.

4. A semiconductor device according to any one of claims 1 to 3, wherein the first conductor layer and the second conductor layer are the same layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the second semiconductor layer is disposed between the substrate and a gate electrode of the second transistor.

6. The semiconductor device according to any one of claims 1 to 4, wherein a gate electrode of the second transistor is disposed between the substrate and the second semiconductor layer.

7. The semiconductor device according to claim 5 or 6, wherein a gate electrode of the second transistor comprises the second conductor layer.

8. The semiconductor device according to claim 5 or 6, wherein the second semiconductor layer is disposed between the gate electrode of the second transistor and the second conductor layer.

9. The semiconductor device according to any one of claim 6 to 8,

wherein the source electrode of the first transistor comprises a first conductor layer, and

wherein the source electrode of the second transistor and the gate electrode of the second transistor are disposed on one of a side facing the substrate and an opposite side of the side facing the substrate with respect to the second semiconductor layer.

10. The semiconductor device according to any one of claim 2 to 5,

wherein the second semiconductor layer is disposed between the gate electrode of the second transistor and the source electrode of the second transistor.

11. The semiconductor device according to any one of claims 5 to 10, wherein the second semiconductor layer is thinner than a gate electrode of the second transistor.

12. The semiconductor device according to any one of claims 1 to 6, wherein the third element and the fourth element are copper (Cu) or titanium (Ti).

13. The semiconductor device according to any one of claims 1 to 12, wherein a drain electrode of the second transistor includes the same element as the fourth element.

14. The semiconductor device according to any one of claims 1 to 13, wherein a gate electrode of the first transistor comprises the same element as the third element.

15. The semiconductor device according to any one of claim 1 to 14,

wherein the distance between the first semiconductor layer and the substrate is different from the distance between the second semiconductor layer and the substrate,

wherein a distance between the first semiconductor layer and the first gate electrode is different from a distance between the second semiconductor layer and the second gate electrode,

Wherein a distance between the substrate and the first gate electrode is different from a distance between the substrate and the second gate electrode, and

wherein the second conductor layer is discontinuous with the first conductor layer.

16. The semiconductor device according to any one of claims 1 to 15, wherein the first transistor and the second transistor are electrically connected.

17. The semiconductor device according to claim 16, wherein the first transistor and the second transistor are connected to a first node, the second node is coupled to the first node via a capacitor, and the capacitor has a structure in which a dielectric layer is disposed between the second conductor layer and the semiconductor layer or the conductor layer.

18. The semiconductor device according to any one of claims 1 to 17, further comprising an organic Electroluminescent (EL) element disposed over the substrate,

wherein the first element is a group 14 element, and

wherein the second element is a group 12, 13, 15 or 16 element.

19. The semiconductor device according to any one of claim 1 to 18,

wherein the diagonal length of the substrate is greater than or equal to 5 centimeters (cm),

wherein the first semiconductor layer is a polycrystalline layer or an amorphous layer, and

wherein the second semiconductor layer is an oxide semiconductor layer.

20. The semiconductor device according to any one of claims 1 to 19, wherein the second semiconductor layer comprises tin (Sn).

21. The semiconductor device according to any one of claims 1 to 20, wherein a third element is different from the second element, and wherein a fourth element is different from the first element.

22. A semiconductor device, comprising:

a substrate;

wherein the semiconductor of the first semiconductor layer is silicon (Si),

wherein the semiconductor of the second semiconductor layer is indium tin zinc oxide (InSnZnO), and

wherein the first conductor layer and the second conductor layer are the same layer.

23. The semiconductor device according to claim 22, wherein the first conductor layer is included in an electrode of the first transistor.

24. The semiconductor device according to any one of claims 1 to 23, wherein a distance between the first semiconductor layer and the substrate is smaller than a distance between the second semiconductor layer and the substrate.

25. An apparatus, comprising:

the semiconductor device according to any one of claims 1 to 24; and

a control device connected to the semiconductor device.

26. An apparatus, comprising:

the semiconductor device according to any one of claims 1 to 24; and

an optical member disposed over the semiconductor device,

wherein the second semiconductor layer is disposed between the substrate and the optical member.

27. An apparatus, comprising:

an imaging device; and

the display device comprises a display device, a display device and a display control unit,

wherein the display device comprises the semiconductor device according to any one of claims 1 to 24,

wherein the display device is capable of switching a rate at which display is performed between a first rate and a second rate higher than the first rate, and

wherein the imaging device performs image capturing at a third rate between the first rate and the second rate.

28. The apparatus of claim 27, wherein the first rate is less than or equal to 10 frames per second fps and the second rate is greater than or equal to 100fps.

29. The apparatus of claim 27, wherein the first rate is less than or equal to 5 hertz (Hz), and the third rate is from 20 to 80fps.

30. An apparatus comprising the semiconductor device of any one of claims 1 to 24, the apparatus comprising at least any one of:

Semiconductor devices fabricated in a 1 to 4 nanometer (nm) process;

a communication device configured to perform communication using terahertz waves; and

a solid-state battery.