CN116915749A

CN116915749A - Method, device and storage medium for automatically distributing addresses by BMS parallel operation

Info

Publication number: CN116915749A
Application number: CN202310782651.XA
Authority: CN
Inventors: 刘军; 陈志勇
Original assignee: Guangdong Mic Power New Energy Co Ltd
Current assignee: Guangdong Mic Power New Energy Co Ltd
Priority date: 2023-06-29
Filing date: 2023-06-29
Publication date: 2023-10-20

Abstract

The application provides a method, a device and a storage medium for automatically allocating addresses by a BMS parallel operation, wherein the method mainly comprises the following steps: the BMSs are sequentially connected in parallel through the power wire harness, wherein the positive electrode and the negative electrode of a power supply of any BMS are respectively connected with the positive electrode and the negative electrode of the power supply of the previous BMS and the negative electrode of the power supply of the next BMS in a one-to-one correspondence manner through the power wire harness; acquiring level signals of pin input IO ports and pin output IO ports of the BMS to identify an end BMS and an intermediate BMS; choose arbitrary tip BMS regard as BMS host computer, another tip BMS with middle BMS is as BMS slave unit, by the BMS host computer is through serial communication protocol to the input of later BMS preset address, just later BMS also passes through serial communication protocol is according to the ordering mode of parallel connection in proper order transmission distribution between slave unit BMS preset address. The application realizes that a plurality of BMSs can automatically allocate the addresses of the slaves in parallel, has high success rate of address allocation and improves the efficiency of address allocation.

Description

Method, device and storage medium for automatically distributing addresses by BMS parallel operation

Technical Field

The application belongs to the technical field of battery parallel operation control, and particularly relates to a method, a device and a storage medium for automatically distributing addresses by a BMS parallel operation.

Background

The existing multi-battery parallel operation automatic address allocation technology is mainly of the following two types: 1. address 2 is assigned via a dial switch, controlled via a key and external hard-wire signal. The first type of dial switch needs to manually dial each device, if not a professional, a dial error exists to cause the system to be inoperable, and in addition, the situation that the number of parallel machines (such as 32 or more) is large is time-consuming and labor-consuming. The second method of controlling by key and external hard wire signal can be called semi-automatic control, this method does not need each machine to press key, only need to press button on the first machine of parallel machine to determine host, but it is easy to make mistakes in the course of address transmission and distribution, the success rate of address distribution is lower and the efficiency of address distribution is also not high. In addition, when addresses are allocated in the parallel connection of a plurality of BMSs, the speed and efficiency of the allocation of addresses to the whole BMS parallel system are easily hindered because of the non-parallel connection state in the plurality of BMSs.

Disclosure of Invention

Aiming at the defects of the prior art, the application provides a method, a device and a storage medium for automatically allocating addresses by parallel operation of a BMS, wherein the method realizes that a plurality of BMSs are connected in sequence in parallel operation, automatically identifies end BMSs when the BMSs are connected in parallel operation, takes any one end BMS as a BMS host, and sequentially transmits and allocates the preset addresses between other BMSs according to a sequencing mode of parallel operation connection through an RS485 communication protocol, and has high success rate of address allocation.

In order to achieve the above object, the present application provides a method for automatically allocating addresses by a BMS parallel operation, comprising:

s1: and a plurality of BMSs are sequentially connected in parallel through the power wire harness, wherein the power anode of any BMS is correspondingly connected with the power anodes of the former BMS and the latter BMS through the power wire harness, and the power cathode of any BMS is correspondingly connected with the power cathodes of the former BMS and the latter BMS through the power wire harness.

S2: and acquiring level signals of the pin input IO ports and the pin output IO ports of the BMS so as to identify the end BMS and the middle BMS.

S3: choose arbitrary tip BMS regard as BMS host computer, another tip BMS with middle BMS regard as BMS slave machine, all pass through between the arbitrary BMS serial communication protocol connects, by the BMS host computer is through serial communication protocol to the input of later BMS preset address, just later BMS also passes through serial communication protocol is according to the ordering mode of parallel connection between slave machine BMS in proper order the transmission distributes preset address.

When the power wire harness is connected to any BMS, the wire end copper sheet in the power wire harness is contacted with the contact pin with the elastic sheet at the end of the BMS, so that two elastic sheets in the BMS connector are connected, and the other elastic sheet in the BMS connector is grounded.

In the application, the BMS connector in each BMS further comprises a power anode P1+ and a power cathode P1-at the pin input end of the BMS, and a power anode P2+ and a power cathode P2-at the pin output end of the BMS, wherein the two spring plates in the BMS connector are connected through the contact of the wire end copper sheet in the power wire harness with the contact pin with the spring plate at the BMS end, and the other spring plate in the BMS connector is grounded, so that the electrical level signal testing loop is formed.

In the application, a pin input IO port is arranged at a pin input end of the BMS, a pin output IO port is arranged at a pin output end of the BMS, and a level signal is obtained by detecting the levels of the pin input IO port and the pin output IO port in each BMS.

Further, the level signal includes a high level and a low level;

the identification of the end BMS and the middle BMS is specifically as follows:

when the pin input IO mouth of BMS is high level, just the pin output IO mouth of BMS is low level, perhaps, when the pin input IO mouth of BMS is low level, just the pin output IO mouth of BMS is high level, BMS is tip BMS.

When the pin input IO port of the BMS is at a low level, and the pin output IO port of the BMS is at a low level, the BMS is an intermediate BMS.

Further, the intermediate BMS further includes: when the pin input IO port of the BMS is at a high level and the pin output IO port of the BMS is at a high level, judging that the BMS is in an uncombined state or the BMS connector is in an uncoupling state.

In the application, the BMS with the uncombined state possibly exists in the BMS parallel operation connection or the BMS connector in the BMS is in the uncoupling state, and the BMS with the abnormal connection state can be judged and positioned according to the level signal so as to conveniently and quickly find out the fault source.

In the application, the serial communication protocol at least comprises RS485 communication; any BMS comprises RS485 communication and MCU; the RS485 communication comprises an RS485 communication input end and an RS485 communication output end.

In the application, the serial communication protocol CAN also comprise CAN communication and IIC communication, and the BMS parallel operation automatic address allocation CAN be realized through a communication connection mode of the CAN communication and the IIC communication.

Further, in any BMS, the RS485 communication output end is respectively connected with one end of a bus 485A and one end of a bus 485B, the other end of the bus 485A is connected with the anode of the MCU, and the other end of the bus 485B is connected with the cathode of the MCU;

and the RS485 communication output end in any BMS is connected with the RS485 communication input end in the subsequent BMS.

In the application, in any BMS, an analog switch module is further arranged between one end of the bus 485A and the MCU, and the analog switch module at least comprises a MOS tube Q1.

In any BMS, still be equipped with analog switch module between bus 485B's one end with MCU, analog switch module includes MOS pipe Q2 at least.

The analog switch module can also comprise a relay, and the opening and closing of the line connection can be realized by controlling the relay through the MCU.

Further, when the BMS host computer and the BMS slave computers are in a parallel operation state, and the slave computers BMS are sequentially transmitted and distributed according to a parallel operation connection ordering mode, any BMS is closed by an MCU detection signal to the MOS tube Q1 and the MOS tube Q2, and the MCU records the preset addresses.

When at least any non-parallel operation state BMS exists between the BMS host computer and the BMS slave computers, and preset addresses are sequentially transferred and distributed between the slave computers BMS according to a sequencing mode of parallel operation connection, the preset addresses are transferred and distributed to the later parallel operation state BMS through the RS485 communication input end and the RS485 communication output end of the non-parallel operation state BMS, and the non-parallel operation state BMS is skipped.

In order to achieve the above object, the present application further provides a device for automatically allocating addresses by a BMS parallel operation, including:

and the BMSs are sequentially connected in parallel through the power wire harness.

Wherein, the power positive pole of arbitrary BMS passes through power pencil and the positive pole of the power of preceding and the follow-up BMS corresponds to be connected, and the power negative pole of arbitrary BMS passes through power pencil and the power negative pole of preceding and follow-up BMS corresponds to be connected.

The judging unit is used for acquiring level signals of the pin input IO ports and the pin output IO ports of the BMS according to the power connector to judge the end BMS and the middle BMS identified by the power connector so as to judge a BMS host and a BMS slave; the BMS master is any end BMS, and the BMS slaves are an intermediate BMS and another end BMS.

The judging unit is further used for judging whether the non-parallel operation state BMS exists.

The address allocation unit is connected between any BMSs through the serial communication protocol, the BMS host sends allocation addresses to the following BMS through the serial communication protocol, and the following BMS also sequentially transmits the allocation addresses between the slave BMSs through the serial communication protocol according to a parallel connection ordering mode.

The serial communication protocol at least comprises RS485 communication; and any BMS comprises RS485 communication and MCU.

To achieve the above object, the present application also provides a storage medium for automatically assigning addresses by parallel operation of a BMS, which is one of computer-readable storage media, having a computer program stored thereon, which when executed by a processor, implements the method for automatically assigning addresses by parallel operation of a BMS as described above.

Compared with the prior art, the application has the beneficial effects that:

the application provides a method, a device and a storage medium for automatically allocating addresses by a BMS parallel operation, wherein the method realizes the following steps:

1. according to the method for automatically allocating addresses by parallel operation of the BMS, a plurality of BMSs are connected in sequence and simultaneously the end BMS and the middle BMS are identified by acquiring the level signals of the pin input IO ports and the pin output IO ports of the plurality of BMSs. The method can identify the end BMS by detecting the high-low level signal, is simple and quick, and is not easy to make mistakes in the detection process.

2. According to the method for automatically allocating addresses by the BMS parallel operation, any end BMS is selected as the BMS host, the BMS host inputs the preset address to the first BMS slave through the RS485 communication protocol, and then the first BMS slave sequentially transmits and allocates the preset address according to the ordering mode of parallel operation connection through the RS485 communication protocol.

3. According to the method for automatically allocating addresses by the parallel operation of the BMS, when at least any non-parallel operation state BMS exists between the BMS master machine and the BMS slave machines, and preset addresses are sequentially transmitted and allocated between the slave machines BMS according to the ordering mode of parallel operation connection, the preset addresses are transmitted and allocated to the later parallel operation state BMS through the RS485 communication input end and the RS485 communication output end of the non-parallel operation state BMS, and the non-parallel operation state BMS is skipped. According to the application, if the abnormal BMS exists in the multiple BMSs, such as the BMS in the non-parallel operation connection state, the BMS in the non-parallel operation state does not need to be removed, but the BMS in the non-parallel operation state skillfully skips, so that the multiple BMSs can complete the flow of transmitting and distributing the address integrally and rapidly, and then the BMS in the non-parallel operation state is detected and positioned by the MCU.

Drawings

Fig. 1 is a flowchart of a method for automatically allocating addresses by a BMS parallel operation according to an embodiment of the present application.

Fig. 2 is a flowchart of a method for automatically allocating addresses by a BMS parallel operation according to an embodiment of the present application.

Fig. 3 is a schematic diagram illustrating a parallel operation structure of a plurality of BMS according to an embodiment of the present application.

Fig. 4 is a schematic diagram of an automatic address allocation structure of a plurality of BMS parallel operation in an embodiment of the present application.

Fig. 5 is a schematic diagram of an apparatus for automatically assigning addresses by parallel operation of a BMS according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions will be clearly and completely described below in connection with the embodiments of the present application. It will be apparent that the described embodiments are some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Embodiment one:

as shown in fig. 1 and 2, in order to solve the above technical problems, the present application provides a method for automatically allocating addresses by a BMS parallel machine, including:

As shown in fig. 3, when the power harness is connected to any BMS, the copper sheet at the end of the wire in the power harness is contacted with the contact pin with the spring sheet at the end of the BMS, so that two spring sheets in the BMS connector are connected, and the other spring sheet in the BMS connector is grounded.

Further, the level signal includes a high level and a low level.

Preferably, it is assumed that there are 5 BMS parallel connections, BMS1, BMS2, BMS3, BMS4, BMS5, and the pin input and output IO ports of their BMS are as follows:

	pin input IO port level of BMS	Pin output IO port level of BMS
			BMS1	0	0
BMS2	1	0
			BMS3	0	0
BMS4	1	1
			BMS5	0	1

TABLE 1

It can be seen from the above table 1 that BMS2 and BMS5 are two end BMSs, and BMS1, BMS3, BMS4 are middle BMSs, wherein BMS4 is in an un-connected state in 5 BMS parallel operation devices, or BMS connectors of BMS4 are in an un-connected state, which is not limited thereto.

In the application, in the BMS parallel operation connection, the BMS in an unconnected state possibly exists or the BMS connector in the BMS is in the unconnected state, and the MCU can judge and locate the BMS in the abnormal connection state according to the level signal so as to conveniently and quickly find a fault source.

As shown in fig. 4, in the present application, the serial communication protocol at least includes RS485 communication; any BMS comprises RS485 communication and MCU; the RS485 communication comprises an RS485 communication input end and an RS485 communication output end.

Preferably, the serial communication protocol may further include CAN communication and IIC communication, and the BMS parallel operation automatic address allocation CAN also be realized through a communication connection mode of CAN communication and IIC communication, which is not limited thereto.

Preferably, the analog switch module may further include a relay, and the circuit connection can be opened and closed by controlling the relay through the MCU, which is not limited thereto.

In summary, an embodiment of the application makes detailed analysis and illustration on a method for automatically allocating addresses by parallel operation of a BMS, the application can identify an end BMS by detecting a low-level signal, is simple and rapid, and is not easy to make errors in the detection process, meanwhile, a preset allocation address is written into a first BMS slave by a BMS host by using an RS485 communication protocol, then the preset allocation address is sequentially transferred and allocated in the BMS slave, thereby greatly improving the efficiency of address allocation and managing the BMS host and the BMS slave more orderly.

Embodiment two:

as shown in fig. 5, in order to solve the above technical problems, the present application further provides a device for automatically allocating addresses by a BMS parallel machine, which includes the following steps:

As shown in fig. 5, if there are N BMS connected in parallel, each BMS has a determining unit and an address allocating unit, and when the determining unit determines that the end BMS and the middle BMS are connected, then 1 BMS master and N-1 BMS slaves are confirmed, then the BMS slaves N-1 are connected in parallel according to the BMS master, the BMS slaves 1, and the BMS slaves 2.

When the judging unit in the BMS slave 1 judges that the BMS slave 1 is in a parallel connection state, the BMS host writes the preset address into the BMS slave 1 through the address distributing unit, but if the judging unit in the BMS slave 1 judges that the BMS slave 1 is in a non-parallel connection state, the preset address can be transmitted and distributed to the BMS in a later parallel state through the RS485 communication input end and the RS485 communication output end of the BMS slave 1 in the non-parallel state, and the BMS1 in the current non-parallel state is skipped;

at this time, if the judging unit in the BMS slave 2 judges that the BMS slave 2 is in the parallel connection state, the preset address is transferred and allocated to the BMS slave 2 until all BMS in the parallel connection state in the N BMS parallel connection devices write and store the preset address, and then the automatic allocation of the address is completed.

In summary, the second embodiment makes detailed analysis and illustration for the device for automatically allocating addresses by parallel operation of the BMS provided by the application, which is convenient for intuitively understanding the structure and connection of each unit in the whole device, and the scheme of the application can be more clearly represented by combining the method for automatically allocating addresses by parallel operation of the BMS.

Embodiment III:

in order to solve the above technical problems, the present application further provides a storage medium for automatically allocating addresses for a BMS parallel operation, which is one of computer readable storage media, comprising:

the computer program is stored, and when the computer program is executed by a processor, the method for automatically allocating addresses by the BMS parallel operation is realized.

In the present application, when the computer program is executed by the processor, the processes of the above embodiments of the interface display method are implemented, and the same technical effects can be achieved, so that repetition is avoided, and no detailed description is given here. Wherein the computer readable storage medium is selected from Read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims

1. A method for automatically allocating addresses by a parallel operation of a BMS, comprising:

s1: the plurality of BMSs are sequentially connected in parallel through a power wire harness, wherein the power anode of any BMS is correspondingly connected with the power anodes of the former BMS and the latter BMS through the power wire harness, and the power cathode of any BMS is correspondingly connected with the power cathodes of the former BMS and the latter BMS through the power wire harness;

s2: acquiring level signals of pin input IO ports and pin output IO ports of the BMS to identify an end BMS and an intermediate BMS;

s3: choose arbitrary tip BMS regard as BMS host computer, another tip BMS with middle BMS regard as BMS slave machine, all connect through serial communication protocol between arbitrary BMS, by the BMS host computer is through serial communication protocol is to the input of later BMS predetermine the address, just later BMS also passes through serial communication protocol is according to the ordering mode of parallel connection between slave machine BMS in proper order the transmission distributes predetermine the address.

2. The method for automatically assigning addresses by parallel operation of a BMS according to claim 1, wherein,

when the power wire harness is connected to any BMS, the copper sheet at the wire end in the power wire harness is contacted with the contact pin with the spring sheet at the BMS end, so that two spring sheets in the BMS connector are connected, and the other spring sheet in the BMS connector is grounded.

3. The method for automatically assigning addresses in parallel to BMS according to claim 2, wherein the level signal comprises a high level and a low level;

when the pin input IO port of the BMS is at a high level and the pin output IO port of the BMS is at a low level,

or when the pin input IO port of the BMS is at a low level and the pin output IO port of the BMS is at a high level, the BMS is an end BMS;

4. The method for automatically assigning addresses by parallel operation of a BMS according to claim 3,

the intermediate BMS further includes: when the pin input IO port of the BMS is at a high level and the pin output IO port of the BMS is at a high level, judging that the BMS is in an uncombined state or the BMS connector is in an uncoupling state.

5. The method for automatically assigning addresses in parallel to BMS according to claim 4, wherein said serial communication protocol comprises at least RS485 communication; any BMS comprises RS485 communication and MCU;

the RS485 communication comprises an RS485 communication input end and an RS485 communication output end;

in any BMS, the RS485 communication output end is respectively connected with one end of a bus 485A and one end of a bus 485B, the other end of the bus 485A is connected with the anode of the MCU, and the other end of the bus 485B is connected with the cathode of the MCU;

6. The method for automatically assigning addresses in parallel to BMS according to claim 5, wherein,

in any BMS, an analog switch module is further arranged between one end of the bus 485A and the MCU, and the analog switch module at least comprises a MOS tube Q1;

7. The method for automatically assigning addresses in parallel to BMS according to claim 6, wherein,

when the BMS host computer and the BMS slave computers are in a parallel operation state, and the slave computers BMS are sequentially transmitted and distributed according to a parallel operation connection ordering mode, any BMS is closed by an MCU detection signal to the MOS tube Q1 and the MOS tube Q2, and the MCU records the preset addresses.

8. The method for automatically assigning addresses in parallel to BMS according to claim 7, wherein,

9. A device for automatically assigning addresses by a BMS parallel operation, comprising:

the BMS is sequentially connected in parallel through a power wire harness;

the judging unit is used for acquiring level signals of the pin input IO ports and the pin output IO ports of the BMS according to the power connector to judge the end BMS and the middle BMS identified by the power connector so as to judge a BMS host and a BMS slave; the BMS master is any end BMS, and the BMS slaves are an intermediate BMS and another end BMS; the judging unit is also used for judging whether the non-parallel operation state BMS exists or not;

the address allocation unit is connected between any BMSs through a serial communication protocol, the BMS host sends an allocation address to the next BMS through the serial communication protocol, and the next BMS sequentially transmits the allocation address between the slave BMSs through the serial communication protocol according to a parallel connection ordering mode;

10. A storage medium, being one of computer readable storage media, characterized in that it has stored thereon a computer program, which when being executed by a processor, implements the method for automatically assigning addresses in parallel to BMS according to claims 1-8.