CN116915556A - Pulse amplitude modulation transmitter and receiver and method for limiting transition level thereof - Google Patents

Abstract

A Pulse Amplitude Modulation (PAM) transmitter comprising: a transceiver; and at least one processor connected to the transceiver and configured to identify a symbol exceeding a designated transition level from among symbols included in the input signal, obtain a frame buffer including at least one bit among bits constituting the identified symbol when the symbol exceeding the transition level is identified, encode the input data by inverting the at least one bit among the bits constituting the identified symbol, and transmit the frame buffer and the encoded input data.

Description

Pulse amplitude modulation transmitter and receiver and method for limiting transition level thereof

Cross reference to related applications

The present application is based on and claims priority from korean patent application No. 10-2022-0048694 filed on the korean intellectual property office on day 4 and 20 of 2022, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to a pulse amplitude modulation transmitter and receiver, and a method of limiting a transition level thereof, and more particularly, to a technique for increasing reliability at a receiving end by limiting a transition level when transmitting data. This work was supported by the three-star technology foundation [ SRFC-IT2001-02 ].

Background

With the increase in processing power of digital computing engines and the development of technologies using interconnection networks, ultra-high-speed, high-capacity data transmission technologies are demanded, and for this reason, high-speed serial link circuit structures are being used.

In order to increase the data rate of a communication system under the condition of a limited channel bandwidth, a 4-level pulse amplitude modulation (PAM-4) method of transmitting 2 bits of data per symbol by using four voltage levels has emerged instead of a conventional method of transmitting 1 bit per symbol called non-return-to-zero (NRZ).

Furthermore, as computing technology continues to evolve, wired communication circuits and systems that enable higher data rates are needed, and it is expected that higher level PAM schemes, such as PAM-8 and PAM-16, will be used in the future.

In a general PAM system, the magnitude of inter-symbol interference (ISI) caused by channel loss is greater than that of the existing NRZ system due to the presence of various signal levels. ISI refers to a phenomenon in which pulses spread and affect adjacent symbols when a channel bandwidth is smaller than a signal bandwidth, and the quality of a signal is degraded when ISI occurs during signal transmission and reception.

Therefore, when the modulation level of the signal is excessively increased to increase the data transmission rate, the influence of ISI becomes very large, resulting in a decrease in the eye opening of the signal and an increase in the Bit Error Rate (BER), and thus, it is difficult to establish a practical communication system.

Recently, a technique of preventing a complete transition (e.g., 11- >00 or 00- >11 in PAM-4) by using a mapping table has emerged to solve the above-described problems, however, in a method of using such a mapping table according to the related art, a data rate is lowered and a slice level is determined according to a predetermined digital circuit, and thus, there is still a problem in that the slice level can be adaptively changed in various ways.

Disclosure of Invention

A pulse amplitude modulation transmitter and receiver having a limited transition level and a high data rate, and a method of limiting the transition level thereof, are provided.

A pulse amplitude modulation transmitter and receiver capable of adaptively limiting a level by encoding without using a separate digital circuit are provided.

Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

According to an aspect of the present disclosure, a Pulse Amplitude Modulation (PAM) transmitter includes: a transceiver; and at least one processor connected to the transceiver and configured to: identifying a symbol exceeding a specified transition level from among symbols included in an input signal, obtaining a frame buffer including at least one bit among bits constituting the identified symbol when the symbol exceeding the transition level is identified, encoding input data by inverting the at least one bit among bits constituting the identified symbol, and transmitting the frame buffer and the encoded input data.

In the PAM transmitter according to an embodiment, at least one bit among bits constituting the identified symbol may be a Most Significant Bit (MSB).

In the PAM transmitter according to an embodiment, the at least one processor may be further configured to identify whether an i-th symbol among symbols included in the input signal exceeds the transition level by comparing the i-1-th symbol with the i-th symbol.

In the PAM transmitter according to an embodiment, the at least one processor may be further configured to obtain a symbol in which the MSB of the i-th symbol is inverted after comparing the i-1-th symbol with the i-th symbol, and to identify a difference between the MSB inverted symbol and the i-1-th symbol.

In the PAM transmitter according to an embodiment, the at least one processor may be further configured to fill the frame buffer with dummy bits having a value equal to the bits included in the frame buffer until a transition level of a symbol generated by combining the first bits included in the frame buffer and the bits corresponding to the first bits included in the frame buffer among symbols of the input signal does not exceed a designated transition level.

In the PAM transmitter according to an embodiment, the at least one processor may be further configured to: when a symbol exceeding the transition level is detected based on the result of inverting the MSB of the ith symbol, the input data is encoded without inverting at least one bit.

According to another aspect of the present disclosure, a PAM receiver includes: a transceiver; and at least one processor connected to the transceiver and configured to receive the frame buffer and the encoded input data, identify a symbol exceeding a specified transition level from among symbols included in the encoded input data, and recover the identified symbol by inverting at least one bit among bits constituting the identified symbol based on bits included in the frame buffer when the symbol exceeding the specified transition level is identified.

In the PAM receiver according to an embodiment, at least one bit among bits constituting the identified symbol may be the MSB.

In the PAM receiver according to an embodiment, the at least one processor may be further configured to identify whether the i-th symbol exceeds the transition level by comparing the i-1-th symbol among the symbols with the i-th symbol.

In the PAM receiver according to an embodiment, the at least one processor may be further configured to obtain a symbol in which the MSB of the i-th symbol is inverted after comparing the i-1-th symbol with the i-th symbol, and to identify a difference between the MSB inverted symbol and the i-1-th symbol.

According to another aspect of the present disclosure, a method of limiting a transition level and transmitting PAM data includes: identifying a symbol exceeding a specified transition level from among symbols included in an input signal; when a symbol exceeding the transition level is identified, obtaining a frame buffer including at least one bit among bits constituting the identified symbol; encoding input data by inverting at least one bit among bits constituting the identified symbol; and transmitting the frame buffer and the encoded input data.

In the method of limiting the transition level and transmitting PAM data according to the embodiment, at least one bit among bits constituting the identified symbol may be the MSB.

In the method of limiting a transition level and transmitting PAM data according to an embodiment, identifying a symbol exceeding a designated transition level may include identifying whether the i-th symbol exceeds the transition level by comparing the i-1-th symbol among symbols included in an input signal with the i-th symbol.

In a method of limiting a transition level and transmitting PAM data according to an embodiment, encoding input data may include: after comparing the i-1 symbol with the i symbol, obtaining a symbol in which the MSB of the i symbol is inverted; and identifying a difference between the MSB inverted symbol and the i-1 th symbol.

In a method of limiting a transition level and transmitting PAM data according to an embodiment, obtaining a frame buffer may include: the frame buffer is filled with dummy bits having a value equal to the bits included in the frame buffer until a transition level of a symbol generated by combining the first bits included in the frame buffer and the bits corresponding to the first bits included in the frame buffer among symbols of the input signal does not exceed a specified transition level.

In a method of limiting a transition level and transmitting PAM data according to an embodiment, encoding input data may include: when a symbol exceeding the transition level is detected based on the result of inverting the MSB of the ith symbol, the input data is encoded without inverting at least one bit.

According to another aspect of the present disclosure, a method of limiting a transition level and receiving PAM data includes: receiving a frame buffer and encoded input data; identifying a symbol exceeding a specified transition level from among symbols included in the encoded input data; and recovering the identified symbol by inverting at least one bit among bits constituting the identified symbol based on the bits included in the frame buffer when the symbol exceeding the specified transition level is identified.

In the method of limiting a transition level and receiving PAM data according to an embodiment, at least one bit among bits constituting an identified symbol is an MSB.

In the method of limiting a transition level and receiving PAM data according to an embodiment, identifying a symbol exceeding a designated transition level may include identifying whether the i-th symbol exceeds the transition level by comparing the i-1-th symbol among the symbols with the i-th symbol.

In a method of limiting a transition level and receiving PAM data according to an embodiment, recovering an identified symbol may include: after comparing the i-1 th symbol with the i-th symbol, a symbol in which the MSB of the i-th symbol is inverted is obtained, and a difference between the MSB inverted symbol and the i-1 th symbol is identified.

Drawings

The foregoing and other aspects, features, and advantages of certain embodiments of the disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings in which:

for a more complete understanding of the drawings referred to herein, a brief description of each figure is provided.

FIG. 1 is a conceptual diagram of a high-speed interconnect system according to various embodiments;

fig. 2 is a block diagram showing a transmitting apparatus according to an embodiment;

fig. 3 is a flowchart illustrating a method of limiting a transition level and transmitting data performed by a transmitting device according to an embodiment;

fig. 4 is a flowchart for describing in more detail a method of limiting a transition level and transmitting data performed by a transmitting apparatus according to an embodiment;

fig. 5A and 5B are diagrams illustrating a method of limiting a transition level by using a 4-level pulse amplitude modulation (PAM-4) data block according to an embodiment;

fig. 6A and 6B are diagrams illustrating a method of limiting a transition level by using PAM-8 data blocks according to an embodiment;

Fig. 7 is an eye diagram in a case of limiting a transition level in PAM-4 communication according to an embodiment;

fig. 8 is an eye diagram in the case of limiting a transition level in PAM-8 communication according to an embodiment;

fig. 9 is a block diagram showing a receiving apparatus according to an embodiment; and

fig. 10 is a flowchart illustrating a method of limiting transfer and receiving data performed by a receiving device according to an embodiment.

Detailed Description

Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. In this regard, the present embodiments may take various forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below merely by referring to the drawings to explain aspects of the present description. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. An expression such as "at least one of … …" modifies the entire list of elements when following the list of elements, rather than modifying individual elements in the list.

Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same elements are assigned the same reference numerals although they are shown in different drawings. In addition, in describing the embodiments, when it is determined that detailed descriptions of known functions and configurations incorporated herein may make the embodiments rather unclear, the descriptions will be omitted. In addition, the embodiments will be described below, but the technical spirit of the present disclosure is not limited thereto, and may be modified and implemented in various ways by those skilled in the art.

In addition, the terminology used herein is used to describe embodiments and is not intended to limit the scope of the present disclosure. Singular expressions may include plural expressions unless they are clearly different in context.

As used herein, terms such as "comprises," "comprising," or "having" specify the presence of stated features, integers, stages, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, stages, operations, elements, components, or groups thereof.

In addition, throughout this specification, when an element is referred to as being "connected to" another element, it can be "directly connected to" the other element or be indirectly connected to "the other element through intervening elements, and although terms such as" first "or" second "may be used herein to describe various elements, these elements are not limited by these terms.

As used herein, the expression "configured to" may be used interchangeably with, for example, "adapted to", "having the ability of … …", "designed to", "adapted to", "manufactured to" or "capable of" as appropriate. The expression "configured to" does not merely imply "specifically designed to be in hardware". Conversely, in some cases, the expression "a system configured as … …" may indicate that the system is "capable" with another device or component. For example, "a processor configured (or arranged) to perform A, B and C" may mean a dedicated processor (e.g., an embedded processor) for performing the corresponding operations or a general-purpose processor (e.g., a Central Processing Unit (CPU) or an application processor) capable of performing the corresponding operations by executing one or more software programs stored in a memory.

It will be understood that each block of the process flow diagrams and flowchart combinations of flow diagrams can be implemented by computer program instructions. These computer program instructions may be loaded onto a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the instructions which execute by the processor of the computer or other programmable data processing apparatus create means for implementing the functions specified in the flowchart block(s). These computer program instructions may also be stored in a computer-usable or computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-usable or computer-readable memory produce an article of manufacture including instruction means that implement the function specified in the flowchart block(s). The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block(s).

Additionally, each block may indicate a module, segment, or portion of code, which comprises one or more executable instructions for performing a particular logical function(s). Furthermore, in several alternative embodiments, the functions described in the blocks may be performed out of order. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings to allow those skilled in the art to easily perform the embodiments. In addition, in order to clearly describe the embodiments with reference to the drawings, portions irrelevant to the description will be omitted.

Fig. 1 is a conceptual diagram of a high-speed interconnect system 100 according to various embodiments.

Referring to fig. 1, a typical high-speed interconnect system 100 may include a transmitter 110, at least one channel (e.g., 121), and a receiver 130.

According to various embodiments, the at least one channel (e.g., 121) includes a coaxial cable, a back-plate, a Printed Circuit Board (PCB), a package, or an on-chip wire, and the length of the at least one channel (e.g., 121) may be in the range of several centimeters to several tens of meters.

At least one channel (e.g., 121) has the characteristics of a Low Pass Filter (LPF) when the data rate is in the range of several Gb/s to several tens of Gb/s. Thus, when a signal passes through at least one channel (e.g., 121), intersymbol interference (ISI) may occur.

In the case where signal loss due to a channel at the nyquist frequency is large, ISI severely impedes communication. For example, it is known that ISI is relatively small when the signal loss is 0dB to 10dB, that ISI is large when the signal loss is 10dB to 20dB, and that ISI is very large when the signal loss is 20dB to 30 dB.

Meanwhile, in the case of transmitting or receiving a signal to which Pulse Amplitude Modulation (PAM) is applied to increase a data rate in the high-speed interconnect system 100, ISI caused by a channel may cause serious performance degradation due to the presence of various signal levels. The embodiments described herein provide a method of limiting the transition level of a signal in order to prevent degradation of signal quality due to ISI while increasing the data rate.

Fig. 2 is a block diagram illustrating a transmitting apparatus 200 according to an embodiment.

Referring to fig. 2, the transmitting apparatus 200 may include a bit separator 210, an invalid symbol detector 220, a frame buffer encoder 230, an input data encoder 240, and a communication unit 250. Here, the bit separator 210, the invalid symbol detector 220, the frame buffer encoder 230, the input data encoder 240, and the communication unit 250 may be modules included in respective programs executed by different processors or one processor. Each component may be omitted or modified according to various embodiments. The transmitting device 200 may correspond to the transmitter 110 in the high-speed interconnect system 100 described above with reference to fig. 1.

In addition, in fig. 2, the frame buffer encoder 230 and the input data encoder 240 may be configured in one processor. In this case, the processor may combine bits encoded by the frame buffer encoder 230 and the input data encoder 240 with each other and transmit the combined bits to the communication unit 250.

The bit separator 210 according to the embodiment may sequentially separate symbols included in the input signal from the highest level into a first bit, a second bit, and an nth bit based on a specified criterion.

In detail, the bit separator 210 may separate a first bit as a Most Significant Bit (MSB) and separate a second bit and an n-th bit as a first Least Significant Bit (LSB) and an n-1LSB, respectively.

For example, in case the output signal is a PAM-4 signal matching two bits with one symbol as shown in table 1, the bit separator 210 may group bits included in the input signal into groups each including two bits. Then, the bit separator 210 may separate a first bit of the two bits in each group into MSBs and separate a second bit into LSBs.

TABLE 1

For example, in case the output signal is a PAM-8 signal matching three bits with one symbol as shown in table 2, the bit separator 210 may group bits included in the input signal into groups each including three bits. In addition, the bit separator 210 may separate a first bit from among the three bits into MSBs, separate a second bit into first LSBs, and separate a third bit into second LSBs.

TABLE 2

PAM-8 symbol	MSB	First LSB	Second LSB
				7	1	1	1
6	1	1	0
				5	1	0	1
4	1	0	0
				3	0	1	1
2	0	1	0
				1	0	0	1
0	0	0	0

In addition, the invalid symbol detector 220 may identify, for example, a symbol of the input signal exceeding a specified transition level. The transition level may be specified by the user or system based on the state of the channel or system requirements.

For example, in PAM-4, the transition level may be specified as a value of 3 or less, and in PAM-8, the transition level may be specified as a value of 7 or less. Hereinafter, an example in which the transition level is designated as 2 in PAM-4 and the transition level is designated as 5 in PAM-8 will be described.

In addition, the invalid symbol detector 220 may sequentially compare the i-1 th symbol with the i-th symbol and check whether the i-th symbol exceeds the transition level. For example, when the difference between the i-1 st symbol and the i-th symbol in PAM-4 is "3", the invalid symbol detector 220 may determine that the i-th symbol exceeds a designated transition level ("2"). As another example, when the difference between the i-1 st symbol and the i-th symbol in PAM-8 is "6" or "7", the invalid symbol detector 220 may determine that the i-th symbol exceeds a designated transition level ("5").

After comparing the i-1 th symbol with the i-th symbol, the invalid symbol detector 220 may invert the MSB of the i-th symbol and again compare the i-th symbol with the i-1 th symbol. For example, in PAM-4, when the i-1 symbol is "0" and the i-1 symbol is "1", the invalid symbol detector 220, which has determined that the transition level is not exceeded, may invert the MSB of the i-1 symbol. The value of the i-th symbol whose MSB is inverted may be "3", and the invalid symbol detector 220 may determine that the inverted i-th symbol exceeds a designated transition level ("2").

The invalid symbol detector 220 according to the embodiment may invert the MSB only when the i-1 symbol exceeds a designated transition level as a result of comparing the i-1 symbol with the i-th symbol. When the result of comparing the i-1 symbol with the i-th symbol whose MSB is inverted also exceeds the inversion level, the invalid symbol detector 220 may determine that the i-th symbol is not inverted.

Meanwhile, the above-described embodiment is merely an example, and when the i-th symbol exceeds a designated transition level as a result of comparing the i-1-th symbol with the i-th symbol, the invalid symbol detector 220 may invert at least one bit other than the MSB according to a setting.

When a symbol exceeding the transition level is detected, the frame buffer encoder 230 according to an embodiment may register at least one bit constituting a corresponding symbol in the frame buffer.

For example, based on determining that the ith symbol exceeds a specified transition level, frame buffer encoder 230 may register the MSB of the ith symbol in the frame buffer.

For example, the frame buffer encoder 230 may register "0" in the frame buffer when the MSB of the i-th symbol exceeding the designated transition level is "0", and may register "1" in the buffer frame when the MSB of the i-th symbol exceeding the designated transition level is "1".

In addition, the frame buffer encoder 230 may check whether a symbol obtained by combining a bit registered in the frame buffer with the LSB exceeds a designated transition level, and fill the frame buffer with the same bit as the registered bit (i.e., dummy bit) until the symbol obtained by combining the bit registered in the frame buffer with the LSB does not exceed the transition level. For example, the frame buffer encoder 230, which has registered "1" in the first bit of the frame buffer, may continuously register "1" until the transition level of the symbol obtained by combining the second bit, which is a bit next to the first bit, and the LSB corresponding to the second bit does not exceed a specified level.

The input data encoder 240 according to an embodiment may encode input data by inverting at least one bit constituting a corresponding symbol.

For example, based on determining that the i-th symbol exceeds a specified transition level, the input data encoder 240 may invert the MSB of the i-th symbol and then encode the input data.

For example, when the MSB of the i-th symbol exceeding the designated transition level is "0", the input data encoder 240 may invert the MSB to "1", and when the MSB of the i-th symbol exceeding the designated transition level is "1", the input data encoder 240 may invert the MSB to "0".

For example, when the invalid symbol detector 220 again determines that the inverted symbol exceeds the inversion level, the input data encoder 240 does not invert at least one bit constituting the corresponding symbol.

For example, when the invalid symbol detector 220, which has inverted the MSB of the i-th symbol, determines that the i-th symbol exceeds a designated transition level, the input data encoder 240 encodes input data while maintaining the MSB of the i-th symbol.

The communication unit 250 according to the embodiment may combine the frame buffer encoded by the frame buffer encoder 230 with the input data encoded by the input data encoder 240 and transmit the resultant data to the receiver 130.

For example, the communication unit 250 may support establishment of a direct (e.g., wired) communication channel or a wireless communication channel between external electronic devices supporting PAM communication, and communication through the established communication channel.

Fig. 3 is a flowchart illustrating a method of limiting a transition level and transmitting data performed by a transmitting apparatus according to an embodiment.

Referring to fig. 3, in operation 310, the transmitting device may identify a symbol exceeding a designated transition level from among at least one symbol included in an input signal. The transmitting apparatus may sequentially compare the i-1 th symbol included in the input signal with the i-th symbol, and recognize whether the i-th symbol exceeds a designated transition level based on a result of the comparison. For example, when the difference between the result of converting the i-1 th symbol into the decimal number and the result of converting the i-th symbol into the decimal number exceeds a specified transition level (e.g., 5), the transmitting device may recognize the i-th symbol as a symbol exceeding the specified transition level.

In operation 320, the transmitting device may obtain a frame buffer including at least one bit among bits constituting the recognized symbol based on the recognized symbol exceeding the transition level. For example, based on determining that the i-th symbol exceeds a specified transition level, the transmitting device may register the MSB of the i-th symbol in the frame buffer.

In operation 330, the transmitting device may encode the input data by inverting at least one bit among bits constituting the identified symbol. For example, based on determining that the i-th symbol exceeds a specified transition level, the transmitting apparatus may encode a symbol obtained by inverting the MSB of the i-th symbol as input data.

In operation 340, the transmitting device may transmit the frame buffer and the encoded input data. For example, the transmitting device may combine the frame buffer with the encoded input data into a signal and transmit the signal to the receiving device. However, this is merely an example, and according to another example, the transmitting device may transmit the frame buffer and the encoded input data as separate signals to the receiving device.

Fig. 4 is a flowchart for describing in more detail a method of limiting a transition level and transmitting data performed by a transmitting apparatus according to an embodiment.

Referring to fig. 4, in operation 410, a transmitting device may separate at least one symbol included in an input signal into bits.

For example, the transmitting apparatus may sequentially separate symbols included in the input signal from the highest level into a first bit, a second bit, and an nth bit based on a predetermined criterion. For example, the transmitting device may separate the first bit into MSBs and separate the second bit and the n-th bit into the first LSB and the n-1LSB, respectively.

In operation 420, the transmitting device may identify a symbol exceeding a designated transition level from among at least one symbol. For example, the transmitting apparatus may sequentially compare the i-1 th symbol with the i-th symbol and check whether the i-th symbol exceeds the transition level. After comparing the i-1 th symbol with the i-1 th symbol, the transmitting apparatus according to the embodiment may invert the MSB of the i-th symbol and compare the i-th symbol with the i-1 th symbol again.

In operation 430, the transmitting device may register at least one bit constituting a corresponding symbol in the frame buffer based on the recognition that the symbol exceeds the transition level.

For example, based on determining that the i-th symbol exceeds a specified transition level, the transmitting device may sequentially register the MSBs of the i-th symbol in the frame buffer. The transmitting device according to the embodiment may check whether the symbol combined with the LSB exceeds a designated transition level based on the frame buffer after the registration, and fill the frame buffer with the same bits as the registered bits (i.e., dummy bits) until the symbol does not exceed the transition level.

In operation 440, the transmitting device may encode the input data by inverting at least one bit constituting a corresponding symbol.

For example, based on determining that the ith symbol exceeds a specified transition level, the transmitting device may invert the MSB of the ith symbol and then encode the input data.

In operation 450, the transmitting device may combine the frame buffer with the encoded input data and transmit the resultant data to the receiving device.

Fig. 5A and 5B are diagrams illustrating a method of limiting a transition level by using a PAM-4 data block according to an embodiment.

Fig. 5A shows an example of generating a data block by dividing symbols of an input signal into bits. In the case of PAM-4 signals, the transmitting device may group bits included in the input signal into groups each including two bits. Then, the transmitting device may separate a first bit of the two bits in each group into MSBs and separate a second bit into LSBs.

The PAM-4 data block according to an embodiment may include input data and frame buffer data. For example, frame buffer data may be written by allocating a portion of the data blocks constituting the MSB to the frame buffer data block 520. According to an embodiment, the length of the frame buffer data block 520 may be flexibly changed, and the length of the MSB input data block 510 may be determined based on the length of the frame buffer data block 520.

Fig. 5A and 5B show PAM-4 data blocks with a total length of 100. In case that the length of the frame buffer data block 520 is set to 20, the length of the MSB input data block 510 may be determined to be 80. In this case, since the LSB input data block 530 is not affected by the frame buffer data block 520, the input data can be allocated using the entire length of 100.

The transmitting apparatus according to the embodiment can recognize the sign of the input signal exceeding the specified transition level. For example, the transmitting apparatus may sequentially compare the i-1 th symbol with the i-th symbol and check whether the i-th symbol exceeds the transition level.

Referring to fig. 5A, it can be seen that by combining bit 511 with bit 531, the first symbol has a value of "0". By combining bit 512 with bit 532, the second symbol has a symbol of "3", and the transmitting device can identify that the second symbol exceeds a specified transition level ("2") by comparing the second symbol to the first symbol.

As another example, it can be seen that by combining bit 513 with bit 533, the kth-1 symbol has a value of "0", and by combining bit 514 with bit 534, the kth symbol has a value of "1". The transmitter 110 may again determine whether the designated transition level is exceeded by inverting the bit 514 which is the MSB of the kth symbol. In this case, by combining the inverted bit 514 with the bit 534, a value of "3" is obtained, and the transmitter 110 can determine that the kth symbol exceeds the designated transition level ("2").

Fig. 5B shows an example of encoding MSB input data block 510 and frame buffer data block 520. For example, "1" of MSB 512, which is a second symbol exceeding a specified transition level ("2"), may be registered in frame buffer data block 520. Fig. 5B shows an example in which "1" of MSB 512, which is the second symbol, is registered in bit 521, bit 521 being the first bit of frame buffer data block 520.

The transmitting device according to the embodiment can check whether the transition level of the frame buffer data block 520 is exceeded due to the data registration. For example, by combining bit 521 and bit 535, the first symbol of frame buffer data block 520 where the data is registered has a value of "3".

The second symbol, in which no data is registered, has a symbol "0" by combining bit 522 with bit 536, and the transmitting device can determine that the second symbol exceeds a specified transition level ("2") by comparing the second symbol with the first symbol.

In this case, the transmitting apparatus may also limit the transition level by registering "1" as dummy data in the second symbol of the frame buffer data block 520.

The transmitting device may continuously check whether the transition level of the frame buffer data block 520 is exceeded due to data registration. For example, by combining bit 522 and bit 536, the second symbol of frame buffer data block 520 where dummy data is registered has a value of "2".

By combining the bit 523 with the bit 537, the third symbol in which no data is registered has the symbol "1", and the specified transition level is satisfied. The transmitting device may invert the MSB of the third symbol and again determine whether the transition level is exceeded.

For example, the transmitting apparatus stops registering dummy data based on identifying that the second symbol has a value of "3" by combining the inverted bit 523 with the bit 537 and thereby satisfying a specified transition level.

Thereafter, the transmitting device may encode the input data by inverting the MSB of the data register in its completed frame buffer data block 520. For example, the specified transition level may be satisfied by inverting ("1" to "0") the bit 512 for which the data registration in the first bit 521 of the frame buffer data block 520 is completed.

Sequentially, the transmitting device may register "0" as the k-th symbol MSB 514 in the third MSB 523 of the frame buffer data block 520. The transmitting device may check whether the transition level of the frame buffer data block 520 is exceeded due to data registration. However, because the kth symbol has satisfied the specified transition level, the transmitting device does not invert the MSB 514 of the kth symbol.

Fig. 6A and 6B are diagrams illustrating a method of limiting a transition level by using a PAM-8 data block according to an embodiment.

Fig. 6A shows an example of generating a data block by separating symbols of an input signal into bits. In the case of PAM-8 signals, the transmitting device may group bits included in the input signal into groups each including three bits.

In addition, the transmitting apparatus may separate a first bit of the three bits in each group into MSBs, a second bit into first LSBs, and a third bit into second LSBs.

PAM-8 data blocks according to various embodiments may include input data and frame buffer data. For example, the frame buffer data may be written by allocating a portion of the data blocks constituting the MSB to the frame buffer data block 620. According to an embodiment, the length of the frame buffer data block 620 may be flexibly changed, and the length of the MSB input data block 610 may be determined based on the length of the frame buffer data block 620.

Fig. 6A and 6B show PAM-8 data blocks with a total length of 10000. In case that the length of the frame buffer data block 620 is set to 2000, the length of the MSB input data block 610 may be determined to be 8000.

In this case, since the first and second LSB input data blocks 630 are not affected by the frame buffer data block 620, the entire length of 10000 can be used to allocate input data.

A transmitting device according to various embodiments may identify symbols in an input signal that exceed a specified transition level.

For example, the transmitting apparatus may sequentially compare the i-1 th symbol with the i-th symbol and check whether the i-th symbol exceeds the transition level. Referring to fig. 6A, it can be seen that the first symbol has a value of "0" by combining the bit 611, the bit 631a, and the bit 631b with each other.

By combining bit 612, bit 632a, and bit 632b with each other, the second symbol has a symbol of "6", and the transmitting device can determine that the second symbol exceeds the specified transition level ("5") by comparing the second symbol with the first symbol.

As another example, the kth-1 symbol may have a value of "1" by combining bit 613, bit 633a, and bit 633b with each other, and the kth symbol may have a value of "3" by combining bit 614, bit 634a, and bit 634b with each other. The transmitting device may again determine whether the designated transition level is exceeded by inverting the bit 614 which is the MSB of the kth symbol.

In this case, by combining the inverted bit 614, the bit 634a, and the bit 634b with each other, the kth symbol has a value of "7", and the transmitting apparatus can recognize that the kth symbol exceeds the designated transition level ("5").

Fig. 6B shows an example of encoding MSB input data block 610 and frame buffer data block 620.

For example, "1" of MSB 612, which is the second symbol exceeding the specified transition level ("5"), may be registered in frame buffer data block 620. Fig. 6B shows an example in which "1" of the MSB 612 as the second symbol is registered in the bit 621, and the bit 621 is the first bit of the frame buffer data block 620.

The transmitting device according to the embodiment may check whether the transition level of the frame buffer data block 620 is exceeded due to the data registration. For example, by combining bit 621, bit 635a, and bit 635b with each other, the first symbol of the frame buffer data block 620 where the data is registered has a value of "7".

The second symbol in which no data is registered has a symbol "1" obtained by combining the bit 622, the bit 636a, and the bit 636b with each other, and the transmitting apparatus can determine that the second symbol exceeds a designated transition level ("5") by comparing the second symbol with the first symbol.

In this case, the transmitting apparatus may also limit the transition level by registering "1" as dummy data in the second symbol of the frame buffer data block 620.

The transmitting device may continuously check whether the transition level of the frame buffer data block 620 is exceeded due to data registration.

For example, by combining bit 622, bit 636a, and bit 636b with each other, the second symbol of the frame buffer data block 620 where dummy data is registered has a value of "5". By combining the bit 623, the bit 637a, and the bit 637b with each other, the third symbol in which no data is registered has the symbol "2", and the specified transition level is satisfied.

The transmitting device may invert the MSB of the third symbol and determine again whether the transition level is exceeded based on the inverted MSB. For example, the transmitting apparatus determines that the second symbol has a value of "6" by combining the inverted bits 623, 637a, and 637b with each other, and thus satisfies a specified transition level, and stops registering dummy data.

Thereafter, the transmitting device may encode the input data by inverting the MSB of the data register in its completed frame buffer data block 620. For example, the specified transition level may be satisfied by inverting the bits 612 that register the data in its done bits 621 ("1" to "0").

Sequentially, the transmitting device may register "0" as the MSB 614 of the kth symbol in the third MSB 623 of the frame buffer data block 620. The transmitting device may check whether the transition level of the frame buffer data block 620 is exceeded due to data registration. However, because the kth symbol has satisfied the specified transition level, the transmitting device does not invert the MSB 614 of the kth symbol.

Fig. 7 is an eye diagram in a case of limiting a transition level in PAM-4 communication according to an embodiment.

The first eye diagram 710 of fig. 7 shows a case where the transition level limit is set to 1 in PAM-4 communication having a total of 4 levels. In the case where the transition level limit is designated as 1 in PAM-4 communication, since the eye opening (eye-opening) is very large, the bit error rate becomes almost zero. However, in this case, the data rate may become very low.

The second eye diagram 720 of fig. 7 shows a case where the transition level limit is set to 2 in PAM-4 communication having a total of 4 levels. In the case where the transition level is limited to 2 in PAM-4 communication, an actual communication environment having a relatively large eye opening and a very small bit error rate can be provided.

The third eye diagram 730 of fig. 7 shows a case where the transition level limit is set to 3 in PAM-4 communication having a total of 4 levels. Designating the transition level limit as 3 in PAM-4 communication corresponds to a case where there is substantially no transition level limit in practice, and the bit error rate may become very high depending on the channel environment.

Fig. 8 is an eye diagram in a case of limiting a transition level in PAM-8 communication according to an embodiment.

The first eye diagram 810 of fig. 8 shows a case where the transition level limit is set to 1 in PAM-8 communication having a total of 8 levels. In the case where the transition level limit is specified as 1 in PAM-8 communication, the bit error rate is very low because the eye opening is very large. However, in this case, there is a problem in that the data rate becomes very low.

The second eye diagram 820 of fig. 8 shows a case where the transition level limit is set to 3 in PAM-8 communication having a total of 8 levels. In the case where the transition level is limited to 3 in PAM-8 communication, an actual communication environment having a relatively large eye opening and a very small bit error rate can be provided.

The third eye diagram 830 of fig. 8 shows a case where the transition level limit is set to 4 in PAM-8 communication having a total of 8 levels. In the case where the transition level is limited to 4 in PAM-8 communication, an actual communication environment having a relatively large eye opening and a very small bit error rate can be provided.

The fourth eye diagram 840 of fig. 8 shows a case where the transition level limit is set to 7 in PAM-8 communication having a total of 8 levels. Designating the transition level limit as 7 in PAM-8 communication corresponds to a case where there is substantially no transition level limit, and the bit error rate may become very high depending on the channel environment.

Fig. 9 is a block diagram illustrating a receiving apparatus 900 according to an embodiment.

Referring to fig. 9, the reception apparatus 900 may include a communication unit 910, a bit separator 920, an invalid symbol detector 930, and a decoder 940. In this case, the communication unit 910, the bit separator 920, the invalid symbol detector 930, and the decoder 940 may be modules included in respective programs executed by different processors or one processor. Each component may be omitted or modified according to various embodiments. The receiving device 900 may correspond to the receiver 130 in the high-speed interconnect system 100 described above with reference to fig. 1.

According to various embodiments, the communication unit 910 may receive data transmitted from a transmitting device. For example, the communication unit 910 may support establishment of a direct (e.g., wired) communication channel or a wireless communication channel between external electronic devices supporting PAM communication, and communication through the established communication channel.

The bit separator 920 according to the embodiment may sequentially separate symbols included in the input signal from the highest level into a first bit, a second bit, and an nth bit based on a specified criterion. The bit separator 920 may separate the first bit into MSBs and separate the second bit and the n-th bit into a first LSB and an n-1LSB, respectively.

An invalid symbol detector 930 according to various embodiments may identify symbols of an input signal that exceed a specified transition level, for example. The transition level may be specified by a user or system based on the state of the channel.

For example, in PAM-4, the transition level may be specified as a value of 3 or less, and in PAM-8, the transition level may be specified as a value of 7 or less. Hereinafter, an example in which the transition level is designated as 2 in PAM-4 and the transition level is designated as 5 in PAM-8 will be described.

The invalid symbol detector 930 according to various embodiments may sequentially compare the i-1 th symbol with the i-th symbol and check whether the i-th symbol exceeds the transition level. For example, when the difference between the i-1 st symbol and the i-th symbol in PAM-4 is "3", the invalid symbol detector 930 may determine that the i-th symbol exceeds a designated transition level ("2"). As another example, when the difference between the i-1 st symbol and the i-th symbol in PAM-8 is "6" or "7", the invalid symbol detector 930 may determine that the i-th symbol exceeds a designated transition level ("5").

After comparing the i-1 th symbol with the i-1 th symbol, the invalid symbol detector 930 according to various embodiments may invert the MSB of the i-th symbol and compare the i-th symbol with the i-1 th symbol again.

For example, in PAM-4, when the i-1 symbol is "0" and the i-1 symbol is "1", the invalid symbol detector 930, which has determined that the transition level is not exceeded, may invert the MSB of the i-1 symbol. The value of the i-th symbol whose MSB is inverted may be "3", and the invalid symbol detector 930 may determine that the i-th symbol exceeds a designated transition level ("2").

When a symbol exceeding the transition level is detected, the decoder 940 according to various embodiments may recover the input data based on the data registered in the frame buffer.

For example, when a symbol exceeding a transition level is detected, the decoder 940 may extract at least one bit registered in the frame buffer and restore a corresponding symbol based on the extracted at least one bit. For example, based on determining that the i-th symbol exceeds a specified transition level, the decoder 940 may recover the MSB of the i-th symbol based on the bits registered in the frame buffer.

For example, when the i-th symbol exceeds a designated transition level and "0" is registered in the frame buffer, the decoder 940 may restore the MSB of the i-th symbol to "0". As another example, when the i-th symbol exceeds a designated transition level and a "1" is registered in the frame buffer, the decoder 940 may restore the MSB of the i-th symbol to "1".

Fig. 10 is a flowchart illustrating a method of limiting a transition level and receiving data performed by a receiving apparatus according to an embodiment.

Referring to fig. 10, in operation 1010, a receiving device may receive data from a transmitting device. The receiving device according to the embodiment may receive data in which the frame buffer and the encoded input data are combined with each other from the transmitting device.

In operation 1020, the receiving device may separate symbols of the input signal into bits. For example, the reception apparatus may sequentially separate symbols included in the input signal from the highest level into a first bit, a second bit, and an nth bit based on a predetermined criterion. For example, the receiving device may separate the first bit into MSBs and separate the second bit and the n-th bit into the first LSB and the n-1LSB, respectively.

In operation 1030, the reception apparatus may identify a symbol exceeding a designated transition level from among symbols of the input signal. For example, the reception apparatus may sequentially compare the i-1 th symbol with the i-th symbol and check whether the i-th symbol exceeds the transition level. After comparing the i-1 th symbol with the i-1 th symbol, the reception apparatus according to the embodiment may invert the MSB of the i-th symbol and compare the i-th symbol with the i-1 th symbol again.

In operation 1040, when a symbol exceeding the transition level is detected, the reception apparatus may restore the input data based on the data registered in the frame buffer. For example, when a symbol exceeding the transition level is detected, the receiving device may extract at least one bit registered in the frame buffer and recover the corresponding symbol. For example, based on determining that the ith symbol exceeds a specified transition level, the receiving device may recover the MSB of the ith symbol based on the bits registered in the frame buffer.

The configuration and operation principle of the PAM transmitter and receiver according to the embodiment have been described in detail with reference to the accompanying drawings.

The PAM transmitter and receiver according to the embodiment have an effect of providing PAM communication with a high data rate and a low data error rate, and can adaptively set a slice level without applying an additional digital circuit.

The above-described devices may be implemented as hardware components, software components, and/or a combination of hardware and software components. For example, the devices and components described in the embodiments may be implemented using one or more general purpose or special purpose computers, such as a processor, controller, arithmetic Logic Unit (ALU), digital signal processor, microcomputer, field Programmable Gate Array (FPGA), programmable Logic Unit (PLU), microprocessor, or any other device configured to execute and respond to instructions. The processor may execute an Operating System (OS) and one or more software applications running on the OS. The processor may also access, store, modify, process, and generate information in response to execution of the software. Although some embodiments are described with reference to an example using a single processor for ease of understanding, those skilled in the art will appreciate that a processor may include multiple processing elements and/or multiple types of processing elements. For example, a processor may include one or more processors and a controller. In addition, other processing configurations are possible, such as parallel processors.

The software may include a computer program, code, instructions, or a combination of one or more thereof, and may configure the processor to operate as desired or may instruct the processor individually or collectively. The software and/or information may be permanently or temporarily embodied in any type of machine, component, physical or virtual device, computer storage medium, or device for providing instructions or information to or for interpretation by a processor. The software may be distributed over networked computer systems and stored or executed in a distributed fashion. The software and information may be stored in one or more computer-readable recording media.

The method according to the embodiment may be embodied as program commands executable by various computer devices and recorded on a computer readable medium. Examples of the computer readable recording medium include magnetic media such as a hard disk, a floppy disk, or a magnetic tape, optical media such as a compact disk ROM (CD-ROM) or a Digital Video Disk (DVD), magneto-optical media such as a magneto-optical floppy disk, and hardware devices such as a ROM, a RAM, and a flash memory, which are specially configured to store and execute program instructions. Examples of program instructions include not only machine code, such as produced by a compiler, but also high-level language code that may be executed by the computer using an interpreter or the like.

While the embodiments have been described with respect to limited embodiments and drawings, those skilled in the art will appreciate numerous modifications and variations from the foregoing description. For example, the described techniques may be performed in a different order than the described methods, and/or components of the described systems, structures, devices, circuits, etc. may be combined or integrated in a different form than the described methods, or may be replaced or substituted with other components or equivalents to achieve suitable results. Therefore, other implementations or embodiments of the appended claims, as well as equivalents thereof, are within the scope of the claims.

The PAM transmitter and receiver according to the embodiment can perform PAM communication at a high data rate and a low data error rate, and adaptively set a slice level without applying an additional digital circuit.

The effects of the present disclosure are not limited to the foregoing, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

It should be understood that the embodiments described herein should be considered in descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered as available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims (20)

1. A Pulse Amplitude Modulation (PAM) transmitter comprising:

a transceiver; and

at least one processor connected to the transceiver and configured to:

identifying a symbol exceeding a specified transition level from among symbols included in an input signal;

when a symbol exceeding a transition level is identified, obtaining a frame buffer including at least one bit among bits constituting the identified symbol;

encoding input data by inverting at least one bit of bits constituting the identified symbol; and

the frame buffer and the encoded input data are transmitted.

2. The PAM transmitter of claim 1, wherein at least one bit among bits constituting the identified symbol is a Most Significant Bit (MSB).

3. The PAM transmitter of claim 1, wherein the at least one processor is further configured to: whether an i-th symbol among symbols included in the input signal exceeds a transition level is recognized by comparing the i-1-th symbol with the i-th symbol.

4. The PAM transmitter of claim 3, wherein the at least one processor is further configured to: after comparing the i-1 symbol with the i symbol, obtaining a symbol in which the MSB of the i symbol is inverted; and identifies the difference between the sign of the MSB inverted and the i-1 symbol.

5. The PAM transmitter of claim 1, wherein the at least one processor is further configured to: the frame buffer is filled with dummy bits having a value equal to the bits included in the frame buffer until a transition level of a symbol generated by combining the first bits included in the frame buffer and the bits corresponding to the first bits included in the frame buffer among the symbols of the input signal does not exceed a specified transition level.

6. The PAM transmitter of claim 4, wherein the at least one processor is further configured to: when a symbol exceeding the transition level is detected based on the result of inverting the MSB of the i-th symbol, the input data is encoded without inverting the at least one bit.

7. A Pulse Amplitude Modulation (PAM) receiver comprising:

a transceiver; and

at least one processor connected to the transceiver and configured to:

receiving a frame buffer and encoded input data;

identifying a symbol exceeding a specified transition level from among symbols included in the encoded input data; and

when a symbol exceeding a specified transition level is identified, the identified symbol is restored by inverting at least one bit among bits constituting the identified symbol based on the bits included in the frame buffer.

8. The PAM receiver of claim 7, wherein at least one bit among bits constituting the identified symbol is a Most Significant Bit (MSB).

9. The PAM receiver of claim 7, wherein the at least one processor is further configured to: whether the i-th symbol exceeds the transition level is identified by comparing the i-1-th symbol among the symbols with the i-th symbol.

10. The PAM receiver of claim 8, wherein the at least one processor is further configured to: after comparing the i-1 th symbol with the i-th symbol, a symbol in which the MSB of the i-th symbol is inverted is obtained, and a difference between the MSB inverted symbol and the i-1 th symbol is identified.

11. A method of limiting transition levels and transmitting Pulse Amplitude Modulation (PAM) data, the method comprising:

identifying a symbol exceeding a specified transition level from among symbols included in an input signal;

when a symbol exceeding a transition level is identified, obtaining a frame buffer including at least one bit among bits constituting the identified symbol;

encoding input data by inverting at least one bit among bits constituting the identified symbol; and

the frame buffer and the encoded input data are transmitted.

12. The method of claim 11, wherein at least one bit among bits constituting the identified symbol is a Most Significant Bit (MSB).

13. The method of claim 11, wherein identifying symbols that exceed a specified transition level comprises: whether the ith symbol exceeds the transition level is identified by comparing the ith-1 symbol among symbols included in the input signal with the ith symbol.

14. The method of claim 13, wherein encoding the input data comprises:

after comparing the i-1 symbol with the i symbol, obtaining a symbol in which the MSB of the i symbol is inverted; and

the difference between the inverted symbol of the MSB and the i-1 symbol is identified.

15. The method of claim 11, wherein obtaining a frame buffer comprises: the frame buffer is filled with dummy bits having a value equal to the bits included in the frame buffer until a transition level of a symbol generated by combining the first bits included in the frame buffer and the bits corresponding to the first bits included in the frame buffer among the symbols of the input signal does not exceed a specified transition level.

16. The method of claim 14, wherein encoding the input data comprises: when a symbol exceeding the transition level is detected based on the result of inverting the MSB of the i-th symbol, the input data is encoded without inverting the at least one bit.

17. A method of limiting transition levels and receiving Pulse Amplitude Modulation (PAM) data, the method comprising:

receiving a frame buffer and encoded input data;

identifying a symbol exceeding a specified transition level from among symbols included in the encoded input data; and

when a symbol exceeding a specified transition level is identified, the identified symbol is restored by inverting at least one bit among bits constituting the identified symbol based on the bits included in the frame buffer.

18. The method of claim 17, wherein at least one bit among bits constituting the identified symbol is a Most Significant Bit (MSB).

19. The method of claim 17, wherein identifying the symbol exceeding the specified transition level comprises identifying whether the i-th symbol exceeds the transition level by comparing the i-1 th symbol among the symbols to the i-th symbol.

20. The method of claim 18, wherein recovering the identified symbol comprises:

after comparing the i-1 symbol with the i symbol, obtaining a symbol in which the MSB of the i symbol is inverted; and

the difference between the inverted symbol of the MSB and the i-1 symbol is identified.