CN116915197A - Power amplifier bias adjusting circuit and power amplifier chip - Google Patents
Power amplifier bias adjusting circuit and power amplifier chip Download PDFInfo
- Publication number
- CN116915197A CN116915197A CN202311139583.1A CN202311139583A CN116915197A CN 116915197 A CN116915197 A CN 116915197A CN 202311139583 A CN202311139583 A CN 202311139583A CN 116915197 A CN116915197 A CN 116915197A
- Authority
- CN
- China
- Prior art keywords
- bias
- circuit
- class
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims abstract description 81
- 230000008878 coupling Effects 0.000 claims description 33
- 238000010168 coupling process Methods 0.000 claims description 33
- 238000005859 coupling reaction Methods 0.000 claims description 33
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 15
- 102100032937 CD40 ligand Human genes 0.000 description 13
- 101000868215 Homo sapiens CD40 ligand Proteins 0.000 description 13
- 238000000034 method Methods 0.000 description 13
- 230000003321 amplification Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 230000003044 adaptive effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 241001125929 Trisopterus luscus Species 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003121 nonmonotonic effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
Abstract
The application belongs to the technical field of microelectronics, and particularly discloses a power amplifier bias adjustment circuit and a power amplifier chip. The adjusting circuit comprises a power detection circuit, which detects the power of the output signal on the output end and outputs a detection signal; the comparison circuit is used for comparing the detection signal with a set threshold value, outputting a first comparison signal when the detection signal is smaller than the threshold value, and outputting a second comparison signal when the detection signal is larger than the threshold value; the first bias adjustment circuit comprises a first class A bias circuit, a first class AB bias circuit and a first switch circuit, wherein the first switch circuit receives a comparison signal, when receiving the first comparison signal, the first switch circuit controls the first class AB bias circuit to work to input bias to the power amplifier, and when receiving the second comparison signal, the first switch circuit controls the first class A bias circuit to work to input bias to the power amplifier. The application has the advantage that the linearity of the power amplifier is ensured in a large dynamic power range.
Description
Technical Field
The present application relates to the field of microelectronics technologies, and in particular, to a power amplifier bias adjustment circuit and a power amplifier chip.
Background
In 5G millimeter wave applications, there are two typical scenarios of emission states: high bandwidth (-1 GHz) low output power (high back-off) and low bandwidth (-400 MHz) high output power (low back-off).
In a small bandwidth scenario, the output Power requirement is higher, and the requirement on the rollback efficiency is also met, so that a Power Amplifier (PA) generally adopts an AB bias to provide higher rollback efficiency and linearity; in a large bandwidth scenario, the output power requirement is typically low, so the PA output power back-off will be large. But for class AB PAs, a large backoff may result in deteriorated linearity (ACLR) and in a large bandwidth scenario, the Digital Predistortion (DPD) method cannot be used to compensate for the nonlinearity.
Disclosure of Invention
In order to solve the above-mentioned drawbacks, the present application proposes a power amplifier bias adjustment circuit, which is applied to a circuit including a power amplifier, and includes:
the power detection circuit is arranged at the output end of the power amplifier, and is used for detecting the power of the output signal at the output end and outputting a detection signal;
the comparison circuit receives the detection signal, compares the detection signal with a set threshold value to output a comparison signal, outputs a first comparison signal when the detection signal is smaller than the threshold value, and outputs a second comparison signal when the detection signal is larger than the threshold value;
the first bias adjustment circuit comprises a first class A bias circuit, a first class AB bias circuit and a first switch circuit, wherein the first switch circuit receives the comparison signal, when receiving the first comparison signal, the first switch circuit controls the first class AB bias circuit to work to bias the power amplifier input, and when receiving the second comparison signal, the first switch circuit controls the first class A bias circuit to work to bias the power amplifier input.
In the bias adjustment circuit, the power amplifier comprises a driving stage and an output stage which are sequentially connected in series; the first bias adjustment circuit is electrically connected with the control end of the driving stage; the bias adjustment circuit further comprises a second bias adjustment circuit electrically connected with the control end of the output stage, the second bias adjustment circuit comprises a second class A bias circuit, a second class AB bias circuit and a second switch circuit, the second switch circuit receives the comparison signal, when receiving the first comparison signal, the second switch circuit controls the second class A bias circuit to work so as to input bias to the output stage of the power amplifier, and when receiving the second comparison signal, the second switch circuit controls the second class AB bias circuit to work so as to input bias to the output stage of the power amplifier.
In the bias adjustment circuit, the power detection circuit comprises a coupling structure, one end of the coupling structure is connected with the output end, the other end of the coupling structure outputs a coupling signal, and the coupling signal is used for power detection.
In the above bias adjustment circuit, the power detection circuit further includes: and the detection structure is connected with the coupling structure and outputs the detection signal.
In the bias adjustment circuit, the detection structure includes a detector, or the detection structure includes a mixer and a low-pass filter connected to the mixer.
In the above bias adjustment circuit, the comparison circuit includes: and one path of input end of the voltage comparator is electrically connected with the power detection circuit, the set threshold value is a voltage threshold value, and the other path of input end of the voltage comparator is input.
In the above bias adjustment circuit, the comparison circuit includes: and the digital signal processor is used for comparing the set threshold value with the detection signal and outputting a comparison signal.
In the above bias adjustment circuit, the first class a bias circuit and the second class a bias circuit include a first voltage source; the first and second class AB bias circuits include a second voltage source, the first switch circuit operating the second voltage source in the first class AB bias circuit to output bias to the driver stage when the first comparison signal is received, the second switch circuit operating the first voltage source in the second class a bias circuit to output bias to the output stage; when the second comparison signal is received, the first switching circuit causes the first voltage source in the first class A bias circuit to operate to output a bias to the driver stage, and the second switching circuit causes the second voltage source in the second class AB bias circuit to operate to output a bias to the output stage.
In the above bias adjustment circuit, the first class a bias circuit and the second class a bias circuit include a first current source and a second current source, the first class AB bias circuit and the second class AB bias circuit include the first current source, when the first comparison signal is received, the first switch circuit makes the first current source in the first class AB bias circuit operate to output bias to the driving stage, and the second switch circuit makes the first current source and the second current source in the second class a bias circuit operate to output bias to the output stage; when the second comparison signal is received, the first switch circuit causes the first current source and the second current source in the first class A bias circuit to operate to output a bias to the driver stage, and the second switch circuit causes the first current source in the second class AB bias circuit to operate to output a bias to the output stage.
The application also provides a power amplifier chip, which comprises the power amplifier bias adjusting circuit.
Compared with the prior art, the application obtains the information of the power of the output signal by arranging the power detection circuit, and sets the threshold value, compares the information of the power of the output signal with the threshold value by the comparison circuit, thereby obtaining the comparison signal, and then controls the bias voltage/current output by the first bias adjustment circuit according to the comparison signal. Therefore, the power amplifier always works under relatively good linearity, so that no or less signal deformation occurs after the output signal passes through the power amplifier, and the reliability of the power amplifier is improved.
Further, for a power amplifier including a driving stage and an output stage, the bias of each stage of the amplifier is adjusted by providing first and second bias adjustment circuits, respectively. The bias types of the first bias adjusting circuit and the second bias adjusting circuit are always different, so that complementation can be formed in the aspects of gain and linearity, and the total gain and the business of the power amplifier are ensured to be maintained at relatively stable levels.
Drawings
Fig. 1 shows a schematic diagram of the internal structure of a power amplifier;
FIG. 2 shows third order intermodulation distortion (IMD 3) with output power (P) for class A and class AB biases out ) Is a schematic of the relationship;
FIG. 3 illustrates a block diagram of a power amplifier adaptive bias circuit according to some embodiments of the application;
FIG. 4 shows third order intermodulation distortion (IMD 3) and output power (P) of the bias circuit of FIG. 3 out ) Is a schematic of the relationship;
FIG. 5 shows a gain effect versus graph of the bias circuit of FIG. 3;
FIG. 6 illustrates a schematic block diagram of a bias adjustment circuit according to some embodiments of the application;
FIG. 7 illustrates a schematic block diagram of yet another bias adjustment circuit in accordance with some embodiments of the application;
FIG. 8 shows a practical application circuit of the bias adjustment circuit shown in FIG. 7;
FIG. 9 shows a practical application circuit of the bias adjustment circuit shown in FIG. 6;
FIG. 10 illustrates a functional block diagram of a power detection circuit according to some embodiments of the application;
fig. 11 illustrates a functional block diagram of yet another power detection circuit according to some embodiments of the application.
Detailed Description
Further advantages and effects of the present application will become apparent to those skilled in the art from the disclosure of the present specification, by describing the embodiments of the present application with specific examples. While the description of the application will be described in connection with the preferred embodiments, it is not intended to limit the inventive features to the implementation. Rather, the purpose of the application described in connection with the embodiments is to cover other alternatives or modifications, which may be extended by the claims based on the application. The following description contains many specific details for the purpose of providing a thorough understanding of the present application. The application may be practiced without these specific details. Furthermore, some specific details are omitted from the description in order to avoid obscuring the application. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
It should be noted that in this specification, like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, it need not be further defined and explained in the following figures, defaults to the same definition.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of the internal structure of a power amplifier 10 to which the present application is directed. A radio frequency power amplifier is shown. In the front-end circuit of the transmitter, the power of the radio frequency signal generated by the modulation oscillation circuit is very small, and the radio frequency signal can be fed to the antenna to radiate into space after a series of amplification-buffering, intermediate amplification (i.e. the driving stage shown in the figure), final power amplification (i.e. the output stage shown in the figure) and the like are required to obtain enough radio frequency power.
In the figure, the power amplifier 10 includes a driving stage and an output stage in series. The driver stage is arranged to receive an input signal, such as the radio frequency input shown in the figure, which is often small, which is required to be amplified by the driver stage to the input power required by the output stage of the final stage. The output stage is for outputting a relatively powerful output signal, such as the radio frequency output shown in the figures, which is for remote transmission in space, and requires sufficient energy for the output stage to supply it with sufficient energy.
As an amplifier, the above-described driving stage and output stage each need to be configured with a bias circuit so that the above-described driving stage and output stage operate in a desired state.
Class a biasing is one of the most common amplifier biasing techniques commonly used in radio frequency power amplifiers. The class a bias sets the operating point of the transistor (i.e., the average value of the sine wave signal) on the centerline of its I-V characteristic. This biasing causes the transistor to remain on for the entire period of each signal cycle.
Class AB biasing is also a common power amplifier biasing technique that uses a combination of both class a and class B biasing techniques, with the class AB biased transistor operating point being set below the center of the I-V characteristic, so that the transistor is off when no input signal is present and on only when the input signal exceeds a set threshold.
An important performance indicator of an assessment amplifier is linearity. Linearity is the proportional relationship between the frequency components of the output signal and the input signal components that remain the same after the frequency components contained in the input signal are amplified by the amplifier. If the output signal of the amplifier does not maintain such a proportional relationship when it contains the frequency component of the input signal, distortion occurs, resulting in the output signal being different from the input signal. The distortion of an amplifier is generally classified into linear distortion and nonlinear distortion. The linear distortion refers to deviation of a linear proportional relation between an output signal and an input signal component of the amplifier, such as gain reduction, phase shift, and the like.
As described in the background, if both the driving stage and the output stage in the power amplifier 10 are set to the class AB bias, it is possible to have higher backoff efficiency and linearity in a small bandwidth high power scenario, but linearity will deteriorate in a large bandwidth low power scenario.
There is therefore a need to find a power amplifier that can be adapted to both small bandwidth high power scenarios and large bandwidth low power wide scenarios of operation.
Fig. 2 shows a schematic diagram of the third order intermodulation distortion (IMD 3, third Order Intermodulation), i.e. linearity, versus output power (Pout), under class a and class AB bias. As can be seen from the illustration, in the case of class a bias, the amplifier IMD3 deteriorates (or "monotonic") with increasing output power. However, in the case of class AB bias, the linearity of the amplifier is non-monotonic with power, at lower powers, IMD3 increases and decreases with increasing amplifier power, but overall IMD3 is maintained within a relatively small range of fluctuations. Then at point Z, IMD3 has a linear monotonic rising trend, and the value of IMD3 rises rapidly, i.e. the linearity of the amplifier deteriorates rapidly, which is not desirable in current usage scenarios.
However, the inventor notes that the class a bias curve and the class AB bias curve have an intersection point P, at the left side of which the linearity of the class a bias is significantly better than that of the class AB bias, and the value of IMD3 increases monotonically; to the right of the intersection point P, the linearity of the class AB bias is in most cases significantly better than that of the class a bias. Therefore, the present application proposes that the sectional bias adjustment is performed for the magnitude of the amplifier power, i.e. the class a bias is performed on the amplifier under the low power condition, and the class AB bias is performed on the amplifier under the high power condition, so as to control the IMD3 on a lower level (i.e. the condition of better linearity) as a whole.
Fig. 3 illustrates a block diagram of a power amplifier adaptive bias circuit according to some embodiments of the application. As shown in the figure, the present application proposes a solution of adding a power detection circuit 20, a comparison circuit 40 and a bias adjustment circuit 30 on the basis of the power amplifier 10 shown in fig. 1.
The power detection circuit 20 is disposed at an output end (i.e. radio frequency output) of the power amplifier 10, and is configured to detect a power of an output signal (i.e. radio frequency output) at the output end, and generate a detection signal according to the power of the output signal, where the detection signal is used to indicate a magnitude of the output signal power.
The comparison circuit 40 receives the detection signal and compares the detection signal with a preset threshold value P TH The comparison is performed and then a comparison signal is output. The comparison signals include a first comparison signal for indicating that the output signal is a small signal of less power and a second comparison signal for indicating that the output signal is a large signal of greater power. For example, when the power detection circuit 10 detects that the power of the output signal is greater than the preset threshold value P TH When the comparison signal is a second comparison signal indicating that the output signal is a large signal (e.g., indicated by logic "1"), the power detection circuit 10 detects that the power of the output signal is less than the threshold value P TH The comparison signal is a first comparison signal indicating that the output signal is a small signal (e.g., indicated by a logic "0").
Further, the power detection circuit 20 may include a coupling structure and a detection structure. The coupling structure is used to couple the output signal from the output of the power amplifier into the power detection circuit 20. Specifically, one end of the coupling structure may be connected to the output end of the power amplifier to sense the radio frequency signal at the output end, and the other end is connected to the detection structure to output the coupling signal. The detection structure receives the coupled signal and processes the signal to output a detection signal reflecting the power level of the coupled signal (corresponding to the power level of the radio frequency signal). The comparison circuit 40 receives the detection signal and compares it with a predetermined threshold value P TH The comparison is performed and then a comparison signal, i.e., a power detection logic signal (refer to fig. 6 and 7) is output. The subsequent bias adjustment circuit 30 adjusts the bias of the power amplifier 10 based on the comparison signal.
The bias adjustment circuit 30 receives the power detection logic signal, and adjusts the bias of the power amplifier 10 to a small signal bias state if the power detection logic signal indicates that the current output signal is a small signal (i.e., a first comparison signal), and adjusts the bias of the power amplifier to a large signal bias state if the comparison signal indicates that the current output signal is a large signal (i.e., a second comparison signal).
Specifically, the bias adjustment circuit 30 includes a first bias adjustment circuit 31 and a second bias adjustment circuit 32. The first bias adjustment circuit 31 is used to adjust the bias of the driving stage, and the second bias adjustment circuit 32 is used to adjust the bias of the output stage. The first bias adjustment circuit 31 and the second bias adjustment circuit 32 respectively receive the comparison signals from the comparison circuit 40 and respectively adjust the respective output voltages/currents according to the comparison signals, thereby respectively providing the driving stage and the output stage with appropriate bias voltages/currents.
For example, the power value corresponding to the P point position in fig. 2 is set as the threshold value P TH The power detection circuit 20 may be configured to detect the power of the signal output from the rf output terminal of the power amplifier 10, and the comparison circuit 40 may be configured to determine the magnitude of the signal power if the detected signal power is greater than the threshold value P TH The comparison signal may be made 1 (i.e., the second comparison signal is output) to indicate that the current output signal is a large signal. So that the bias of the amplifiers of the driving stage and the output stage in the power amplifier 10 can be adjusted to a large signal bias state. The large signal bias state specifically includes: the first bias adjustment circuit 31 adjusts the driving stage to a class a bias so that the driving stage operates under the class a bias; the second bias adjustment circuit 32 adjusts the output stage to a class AB bias such that the driver stage operates at the class AB bias. Thus, the driver stage and output stage of the power amplifier 10 operate in a class a operating region and a class AB operating region, respectively. The driving stage works under the class-A bias to provide the largest amplitude output signal as possible, and the output stage works under the class-AB bias to obtain more ideal output power with larger linearity, so that the whole power amplifier 10 can not only maintain larger output power, but also obtain better linearity.
The above-described embodiments may improve the linearity of the power amplifier 10 as a whole based on the existing poor linearity of the power amplifier. The power of the output signal of the power amplifier is detected, the detected power is compared with a set threshold value, and the bias mode is changed according to the comparison result. It is critical that the bias manner of the driver stage and the output stage remain different, i.e. the output stage needs to be set to a class AB bias when the driver stage is set to a class a bias or the output stage needs to be set to a class a bias when the driver stage is set to a class AB bias. Thus, the output stage and the driving stage always maintain the characteristic of high linearity and the characteristic of high gain, and the output stage and the driving stage are always complementary to each other, so that the defect of poor linearity of the conventional power amplifier can be overcome on the level of the power amplifier 10.
Fig. 4 shows a schematic diagram of the third order intermodulation distortion (IMD 3) versus output power (Pout) of the bias circuit of fig. 3. IMD3 curves of the power amplifier shown in fig. 3 are shown as curves shown by dotted lines. From an observation of the graph, the power threshold point P is used TH For the sake of limitation, the value of IMD3 in the smaller power region corresponds to the class a biased IMD3 curve shown in fig. 2, and the value of IMD3 in the larger power region corresponds to the class AB biased IMD3 curve shown in fig. 2, i.e., after adjustment by the bias adjustment circuit shown in fig. 3, the power amplifier shown in fig. 3 can obtain smaller IMD3 (i.e., better linearity) at different power points.
Fig. 5 shows a gain effect versus graph of the bias circuit of fig. 3. Those skilled in the art will appreciate that class a biases achieve relatively large gains and class AB biases achieve relatively small gains. In the embodiment shown in fig. 3, the driving stage and the output stage are defined to always keep different offsets, so that the gain of the driving stage and the gain of the output stage always keep one larger and one smaller (as shown by two dotted lines in fig. 5) in case of a large signal or in case of a small signal, and the resultant effect of the two (as shown by a solid line in fig. 5) can keep a stable gain at each power point, i.e. the power amplifier 10 can have better linearity and can realize power amplification with a stable gain.
Fig. 6 and 7 specifically show block diagrams of specific circuits that the first bias adjustment circuit 31 and the second bias adjustment circuit 32 can employ. Wherein fig. 6 shows a functional block diagram of a voltage bias adjustment circuit. Fig. 7 shows a functional block diagram of a current bias adjustment circuit.
As shown in fig. 6, the voltage bias adjustment circuit includes a first voltage source and a second voltage source, where the second voltage source can output a higher voltage (corresponding to a high voltage in the illustration) for setting the driving stage or the output stage to a class a bias. The first voltage source outputs a relatively low voltage (corresponding to the low voltage in the illustration) for setting the output stage or driver stage to a class AB bias. A gating switch K1 may also be included at the output of the two voltage sources. If the power detection logic signal indicates that the current signal is a large signal (i.e., a second comparison signal), the gating switch K1 in the first bias adjustment circuit 31 is connected to the second voltage source outputting the high voltage, so as to output the lower bias voltage to the driving stage, the driving stage is set to be a class-a bias, and the gating switch K1 in the second bias adjustment circuit 32 is connected to the first voltage source outputting the low voltage, so as to set the output stage to be a class-AB bias. The opposite is true if the power detection logic signal indicates that the current signal is a small signal (i.e., the first comparison signal).
As shown in fig. 7, the current bias adjustment circuit includes a first current source (corresponding to the current source 1 in the drawing), a second current source (corresponding to the current source 2 in the drawing), and a conducting switch K2, where the current source 1 (i.e., the first current source) always keeps outputting, and the current source 2 (i.e., the second current source) is overlapped or not overlapped to the bias current output terminal under the control of the conducting switch K2. Specifically, if the power detection logic signal indicates that the current signal is a small signal (i.e., the first comparison signal), the on switch K2 in the first bias adjustment circuit 31 is disconnected from the current source 2, so that only the current of the current source 1 is output to the driving stage, i.e., the driving stage is set to be biased in class AB, and the on switch K2 in the second bias adjustment circuit 33 is connected to the current source 2, so that the current source 1 is overlapped with the current source 2, and a larger bias current is output to the output stage, i.e., the output stage is set to be biased in class a. The opposite is true if the power detection logic signal indicates that the current signal is a large signal (i.e., the second comparison signal).
Fig. 8 and 9 show detailed circuits for setting a power amplifier using a current bias and a voltage bias, respectively. Fig. 8 shows a practical application circuit using the current bias adjustment circuit shown in fig. 7. Fig. 9 shows a practical application circuit using the voltage bias adjustment circuit shown in fig. 6.
An adaptive bias adjustment circuit for a single-pass power amplifier is shown in fig. 8. The single-path power amplifier comprises a driving stage 81 and an output stage 82, wherein a PA radio frequency input signal is input to the driving stage 81 through inductive coupling, the driving stage 81 can amplify the PA radio frequency input signal by adopting a common-source common-gate (or common-source) structure, the amplified PA radio frequency input signal is input to the output stage 82 again through inductive coupling, and the output stage 82 amplifies the power of the amplified PA radio frequency input signal by adopting a multilayer Stacked (Stacked) structure, so that a PA radio frequency output signal with enough power is obtained to meet the wireless transmission requirement. The driver stage 81 and the output stage 82 each comprise a controlled terminal for receiving a bias voltage/current, thereby determining under which bias the driver stage 81 and the output stage 82, respectively, are operated. The automatic bias adjusting circuit detects and compares the power of the PA radio frequency output signal, so as to adjust the output comparison signal according to the power of the PA radio frequency output signal, wherein the comparison signal is respectively connected with the controlled end of the driving stage 81 and the controlled end of the output stage 82, so that the bias voltage/current of the driving stage 81 and the output stage 82 can be adjusted. For a specific adjustment method, reference is made to what is described in connection with fig. 3.
Specifically, the automatic bias adjustment circuit includes a capacitive coupler 83 (coupling structure), a detector 84 (detection structure), a voltage comparator 85, the first bias adjustment circuit 31, and the second bias adjustment circuit 32.
The capacitive coupler 83 and the detector 84 constitute a power detection circuit for detecting the power of the PA radio frequency output signal and outputting a detection signal. The PA rf output signal is connected to a capacitive coupler 83, and the capacitive coupler 83 senses (or acquires) a coupling signal from the PA rf output signal through a capacitive partial pressure coupling structure, and outputs the coupling signal to a detector 84. The detector 84 performs a radio frequency-DC conversion process on the coupled signal and outputs a DC voltage signal (i.e., a detection signal) indicative of the magnitude of the coupled signal. Meanwhile, because the coupling signal and the PA radio frequency output signal are in coupling relation, the voltage of the direct-current voltage signal also indicates the power of the PA radio frequency output signal.
The voltage comparator 85 is a comparison circuit for comparing the detection signal (i.e. DC voltage signal) output from the detector 84 with a preset threshold value P TH The comparison is performed and a comparison signal is output. The comparison signal may be a logic signal, such as the power detection logic signal shown in the figure, with logic "0" and "1" indicating that the detection signal is greater than the threshold value P TH Or is smaller than the threshold value P TH . The comparison signal comprises a first comparison signal and a second comparison signal, and reference is made to what has been described in connection with fig. 3 for a specific description of the comparison signals.
The first bias adjustment circuit 31 and the second bias adjustment circuit 32 adjust bias voltages/currents of the driving stage 81 and the output stage 82, respectively, according to the comparison signals. An output of the first bias adjustment circuit 31 is connected to a controlled terminal of the driving stage 81 and an output of the second bias adjustment circuit 32 is connected to a controlled terminal of the output stage 82. And, the bias of the driving stage 81 and the output stage 82 are respectively adjusted under different bias types, so that the linearity and amplification gain of the driving stage 81 and the output stage 82 can be mutually complemented. For example, if the driving stage 81 is set to a class a bias, the output stage 82 is set to a class AB bias, so that the driving stage 81 has a good linearity, the output stage 82 has a large amplification gain, and a high gain and a high linearity can be obtained as a whole by combining the two.
The first bias adjustment circuit 31 and the second bias adjustment circuit 32 shown in fig. 8 are current bias adjustment circuits, and the relevant specific circuit can be referred to the relevant description of fig. 7. Specifically, the bias types of the driving stage 81 and the output stage 82 are set by the on-switch K2 in the first bias adjustment circuit 31 and the second bias adjustment circuit 32, respectively. In the case of a large signal (i.e., the second comparison signal), the on-switch K2 in the first bias adjustment circuit 31 is closed, the current I1 is output to the outside, superimposed with the current Iref1, and input to the driving stage 81At the control end, the bias current of the driving stage is Iref1+I1, and the bias type of the driving stage 81 is A type. The on-switch K2 in the second bias adjustment circuit 32 is turned off, the current I2 is not output to the outside, only the current Iref2 is input to the control terminal of the output stage 82, and the bias of the output stage 82 is set to class AB. By the above adjustment, the linearity of the output stage 82 is maintained at P shown in FIG. 4 out ＞P TH Is at a preferred level and the bias of the driver stage 81 is class AB, with a higher signal gain, which compensates for the lost gain of the output stage 82.
Fig. 9 shows an adaptive bias adjustment circuit for a balanced power amplifier. The power amplifier adopts a balanced architecture, i.e. an architecture including two paths of amplifiers of a PA branch I and a PA branch Q, and the power amplifier used in each path of the amplifier may also include a driving stage 81 and an output stage 82, respectively. In comparison with the single-pass PA shown in fig. 8, in the circuit diagram shown in fig. 9, the controlled end of the driving stage 81 in the PA branch I and the controlled end of the driving stage 81 in the PA branch Q are simultaneously connected to the output end of the first bias adjustment circuit 31, and the controlled end of the output stage 82 in the PA branch I and the controlled end of the output stage 82 in the PA branch Q are simultaneously connected to the second bias adjustment circuit 32. I.e. the drive stage in the two-way amplifier remains the same offset, as does the output stage. The connection relationship among the remaining detectors 84, voltage comparator 85, first bias adjustment circuit 31 and second bias adjustment circuit 32 is the same as that of fig. 8, and is not repeated here.
In fig. 9, the input and output of the PA are provided with quadrature couplers. At the input, the radio frequency input signal is split by the first quadrature coupler 91 and then input to the driving stage 81 of the PA branch I and the driving stage 81 of the PA branch Q, respectively. After the signal is amplified by the PA, the output end of the output stage 82 of the PA branch I and the output end of the output stage 82 of the PA branch Q are respectively connected to the input end of the second quadrature coupler 92, the two output ends of the second quadrature coupler 92 are respectively used for outputting a radio frequency output signal and a coupling signal, the coupling signal is output to the detector 84, the detector 84 outputs a direct current voltage signal after radio frequency-DC conversion processing, and the voltage of the direct current signal indicatesThe power of the PA rf output signal is taken (see fig. 8 for details). After the DC voltage signal is input into the voltage comparator 85, it is compared with a threshold value P set therein TH A comparison is made to derive a power detection logic signal (see also the description of the same section of fig. 8 for details).
The first bias adjustment circuit 31 and the second bias adjustment circuit 32 shown in fig. 9 are voltage bias adjustment circuits, and the relevant specific circuit can be referred to the relevant description of fig. 6. The bias kinds of the driving stage 81 and the output stage 82 can be set by the gate switch K1 in the first bias adjustment circuit 31 and the second bias adjustment circuit 32, respectively. In the case of a large signal (i.e., the second comparison signal), the gate switch K1 in the first bias adjustment circuit 31 is connected to the high voltage source, and the bias type of the driving stage 81 is a type. The gating switch K1 in the second bias adjustment circuit 32 communicates with a low voltage source to set the bias of the output stage 82 to class AB. By the above adjustment, the linearity of the output stage 82 is maintained at P shown in FIG. 4 out ＞P TH Is at a preferred level and the bias of the driver stage 81 is class a, with a higher signal gain, which compensates for the lost gain of the output stage.
The circuits of the above portions in fig. 8 and 9 are only one example of a plurality of implementations, and specific implementations of the functional portions such as the coupling structure, the detecting structure, the comparing circuit, and the bias adjusting circuit may be other circuits that implement the same functions.
Fig. 10 and 11 show schematic block diagrams of two power detection circuits and a comparison circuit.
Fig. 10 shows a coupling structure 301, a detector 302 and a voltage comparator 303. Wherein the coupling structure 301 and the detector 302 constitute a power detection circuit 30. The coupling structure 301 couples the signal at the radio frequency output to the power detection circuit 30 by means of capacitive coupling or the like and feeds the coupled signal to the detector 302. The detector 302 detects the coupled signal as a detection structure, and after detection, the detector 302 can output a DC voltage signal which can be mapped with the magnitude of the coupled signalThe dependence, for example, the greater the peak voltage of the coupled signal, the greater the DC signal; for another example, the dc signal is smaller as the average power of the coupled signal is larger. That is, the direct current signal may be used to indicate the magnitude of the coupled signal without actually reflecting the actual power value of the coupled signal. The voltage comparator 303 is a comparison circuit with one input set to the threshold value P TH The other input terminal is used to receive the dc voltage signal, so that the voltage comparator 303 can output a comparison signal, such as a power detection logic signal, to indicate whether the signal at the rf output terminal of the PA is a large signal or a small signal.
Fig. 11 shows a coupling structure 301, a mixer 402, a low pass filter 403, an analog to digital converter 404, and a digital signal processor 405. The mixer 402 and the low-pass filter 403 form a detection structure, the analog-to-digital converter 404 and the digital signal processor 405 form a comparison circuit, and the coupling structure 301 and the detection structure form the power detection circuit 30.
The coupling structure 301 is the coupling structure 301 shown in fig. 10, and functions to obtain a signal having a linear correspondence with the signal at the signal output end, i.e. a coupling signal. The coupled signal may be used to characterize some electrical characteristic of the output signal, such as signal strength.
The mixer 402 receives the above-described coupled signal and mixes it to obtain a low frequency signal corresponding to the baseband signal.
The low-pass filter 403 filters the low-frequency signal to remove out-of-band clutter. The low pass filter 403 and the mixer 402 together form a detection structure for outputting a signal that may reflect the magnitude of the coupled signal.
The output signal of the low-pass filter 403 is digitized by an analog-to-digital converter 404 and then input to a digital signal processor 405.
The digital signal processor 405 determines whether the current rf output signal is a large signal or a small signal (i.e., a first comparison signal or a second comparison signal) according to the digital signal, and then outputs a corresponding power detection logic signal.
The two power detection circuits and the comparison circuit shown in fig. 10 and 11 are only examples, and other circuits that can achieve the same effect can be equally applied to the present application.
It should be noted that numerous specific details are set forth in the description provided herein. It is understood, however, that embodiments of the application may be practiced without some or all of these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, in the above description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and arranged in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
Claims (10)
1. A power amplifier bias adjustment circuit, comprising:
the power detection circuit is arranged at the output end of the power amplifier, and is used for detecting the power of the output signal at the output end and outputting a detection signal;
the comparison circuit is used for receiving the detection signal, comparing the detection signal with a set threshold value and outputting a comparison signal, outputting a first comparison signal when the detection signal is smaller than the threshold value, and outputting a second comparison signal when the detection signal is larger than the threshold value;
the first bias adjustment circuit comprises a first class A bias circuit, a first class AB bias circuit and a first switch circuit, wherein the first switch circuit receives the comparison signal, when receiving the first comparison signal, the first switch circuit controls the first class AB bias circuit to work to bias the power amplifier input, and when receiving the second comparison signal, the first switch circuit controls the first class A bias circuit to work to bias the power amplifier input.
2. The bias adjustment circuit of claim 1,
the power amplifier comprises a driving stage and an output stage which are sequentially connected in series;
the first bias adjustment circuit is electrically connected with the control end of the driving stage; and
the bias adjustment circuit further comprises a second bias adjustment circuit electrically connected with the control end of the output stage, the second bias adjustment circuit comprises a second class A bias circuit, a second class AB bias circuit and a second switch circuit, the second switch circuit receives the comparison signal, when receiving the first comparison signal, the second switch circuit controls the second class A bias circuit to work so as to input bias to the output stage of the power amplifier, and when receiving the second comparison signal, the second switch circuit controls the second class AB bias circuit to work so as to input bias to the output stage of the power amplifier.
3. The bias adjustment circuit of claim 1, wherein the power detection circuit includes a coupling structure having one end connected to the output and the other end outputting a coupling signal for power detection.
4. The bias adjustment circuit of claim 3, wherein the power detection circuit further comprises: and the detection structure is connected with the coupling structure and outputs the detection signal.
5. The bias adjustment circuit of claim 4, wherein the detection structure comprises a detector, or wherein the detection structure comprises a mixer, a low pass filter coupled to the mixer.
6. The bias adjustment circuit of claim 1 or 5, wherein the comparison circuit comprises: and one path of input end of the voltage comparator is electrically connected with the power detection circuit, the set threshold value is a voltage threshold value, and the other path of input end of the voltage comparator is input.
7. The bias adjustment circuit of claim 1 or 5, wherein the comparison circuit comprises: and the digital signal processor is used for comparing the set threshold value with the detection signal and outputting a comparison signal.
8. The bias adjustment circuit of claim 2, wherein the first class a bias circuit and the second class a bias circuit comprise a first voltage source; the first class AB bias circuit and the second class AB bias circuit include a second voltage source,
when the first comparison signal is received, the first switch circuit causes the second voltage source in the first class AB bias circuit to operate to output a bias to the driver stage, and the second switch circuit causes the first voltage source in the second class a bias circuit to operate to output a bias to the output stage;
when the second comparison signal is received, the first switching circuit causes the first voltage source in the first class A bias circuit to operate to output a bias to the driver stage, and the second switching circuit causes the second voltage source in the second class AB bias circuit to operate to output a bias to the output stage.
9. The bias adjustment circuit of claim 2, wherein said first class A bias circuit and said second class A bias circuit comprise a first current source and a second current source, said first class AB bias circuit and said second class AB bias circuit comprise said first current source,
when the first comparison signal is received, the first switch circuit enables the first current source in the first class AB bias circuit to work so as to output bias to the driving stage, and the second switch circuit enables the first current source and the second current source in the second class A bias circuit to work so as to output bias to the output stage;
when the second comparison signal is received, the first switch circuit causes the first current source and the second current source in the first class A bias circuit to operate to output a bias to the driver stage, and the second switch circuit causes the first current source in the second class AB bias circuit to operate to output a bias to the output stage.
10. A power amplifier chip comprising a power amplifier bias adjustment circuit according to any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311139583.1A CN116915197B (en) | 2023-09-06 | 2023-09-06 | Power amplifier bias adjusting circuit and power amplifier chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311139583.1A CN116915197B (en) | 2023-09-06 | 2023-09-06 | Power amplifier bias adjusting circuit and power amplifier chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116915197A true CN116915197A (en) | 2023-10-20 |
| CN116915197B CN116915197B (en) | 2023-12-08 |
Family
ID=88351361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311139583.1A Active CN116915197B (en) | 2023-09-06 | 2023-09-06 | Power amplifier bias adjusting circuit and power amplifier chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116915197B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020132652A1 (en) * | 2001-03-16 | 2002-09-19 | Steel Victor E. | Segmented power amplifier and method of control |
| US20020146993A1 (en) * | 2001-04-04 | 2002-10-10 | Charles Persico | Bias adjustment for power amplifier |
| US20050270103A1 (en) * | 2004-04-09 | 2005-12-08 | Nicolas Constantin | Dynamic biasing system for an amplifier |
| CN101562425A (en) * | 2009-05-26 | 2009-10-21 | 惠州市正源微电子有限公司 | High-low power combining circuit for radio-frequency power amplifier |
| CN102801392A (en) * | 2012-09-13 | 2012-11-28 | 电子科技大学 | Radio frequency power amplification device |
| JP2013062728A (en) * | 2011-09-14 | 2013-04-04 | Renesas Electronics Corp | Rf power amplifier and method of operating the same |
| CN204721317U (en) * | 2015-07-08 | 2015-10-21 | 无锡中普微电子有限公司 | Circuit containing the power amplifier power supply under multimode condition |
| US20170005629A1 (en) * | 2015-06-30 | 2017-01-05 | Research & Business Foundation Sungkyunkwan University | Average power tracking mode power amplifier using dual bias voltage levels |
| US20180198424A1 (en) * | 2017-01-06 | 2018-07-12 | Skyworks Solutions, Inc. | Amplifier architecture using positive envelope feedback |
| US20190068124A1 (en) * | 2017-08-31 | 2019-02-28 | Airoha Technology Corp. | Bias circuit and power amplifier circuit |
| CN112260654A (en) * | 2020-10-30 | 2021-01-22 | 锐石创芯（深圳）科技有限公司 | Power amplifier system |
| CN113206643A (en) * | 2021-04-22 | 2021-08-03 | 晋江三伍微电子有限公司 | Power amplifier circuit and electronic device |
-
2023
- 2023-09-06 CN CN202311139583.1A patent/CN116915197B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020132652A1 (en) * | 2001-03-16 | 2002-09-19 | Steel Victor E. | Segmented power amplifier and method of control |
| US20020146993A1 (en) * | 2001-04-04 | 2002-10-10 | Charles Persico | Bias adjustment for power amplifier |
| CN1515069A (en) * | 2001-04-04 | 2004-07-21 | �����ɷ� | Bias adjustment for power amplifier |
| US20050270103A1 (en) * | 2004-04-09 | 2005-12-08 | Nicolas Constantin | Dynamic biasing system for an amplifier |
| CN101562425A (en) * | 2009-05-26 | 2009-10-21 | 惠州市正源微电子有限公司 | High-low power combining circuit for radio-frequency power amplifier |
| JP2013062728A (en) * | 2011-09-14 | 2013-04-04 | Renesas Electronics Corp | Rf power amplifier and method of operating the same |
| CN102801392A (en) * | 2012-09-13 | 2012-11-28 | 电子科技大学 | Radio frequency power amplification device |
| US20170005629A1 (en) * | 2015-06-30 | 2017-01-05 | Research & Business Foundation Sungkyunkwan University | Average power tracking mode power amplifier using dual bias voltage levels |
| CN204721317U (en) * | 2015-07-08 | 2015-10-21 | 无锡中普微电子有限公司 | Circuit containing the power amplifier power supply under multimode condition |
| US20180198424A1 (en) * | 2017-01-06 | 2018-07-12 | Skyworks Solutions, Inc. | Amplifier architecture using positive envelope feedback |
| US20190068124A1 (en) * | 2017-08-31 | 2019-02-28 | Airoha Technology Corp. | Bias circuit and power amplifier circuit |
| CN109428553A (en) * | 2017-08-31 | 2019-03-05 | 络达科技股份有限公司 | Bias circuit and power amplifier circuit |
| CN112260654A (en) * | 2020-10-30 | 2021-01-22 | 锐石创芯（深圳）科技有限公司 | Power amplifier system |
| CN113206643A (en) * | 2021-04-22 | 2021-08-03 | 晋江三伍微电子有限公司 | Power amplifier circuit and electronic device |
Non-Patent Citations (2)
| Title |
|---|
| ABBAS NASRI: "Linearity Improvement of the CMOS Power Amplifier with Auxiliary Path", 《2022 IRANIAN INTERNATIONAL CONFERENCE ON MICROELECTRONICS (IICM)》, pages 62 - 65 * |
| 何军: "级联放大器整体线性和效率设计方法研究", 《通信技术》, pages 1309 - 1314 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116915197B (en) | 2023-12-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Ali et al. | A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays | |
| US10298177B2 (en) | N-way doherty distributed power amplifier with power tracking | |
| US8180304B2 (en) | Efficient power amplifier | |
| US8872583B2 (en) | Power amplifier with advanced linearity | |
| KR101216562B1 (en) | Detector circuit and semiconductor device using the same | |
| US20110006846A1 (en) | High-frequency amplifier | |
| US20180026593A1 (en) | Doherty amplifier | |
| US20070298736A1 (en) | Rf power amplifier | |
| US20150236651A1 (en) | Multi-mode bias modulator and envelope tracking power amplifier using the same | |
| US9197465B2 (en) | Apparatus and method for a digital transmitter architecture with outphasing power amplifier | |
| US9787259B2 (en) | Outphasing power amplifier signal splitter using next stage input impedance and multiple biasing | |
| US20100081410A1 (en) | Radio frequency circuit, radio frequency power amplifier, and semiconductor device | |
| US7948324B2 (en) | Power efficient multistage amplifier and design method | |
| Barton et al. | An RF-input outphasing power amplifier with RF signal decomposition network | |
| US7768344B2 (en) | Power circuit and power amplifier and base station device using the same | |
| US8653886B2 (en) | Method and arrangement in a mobile communications system | |
| CN116915197B (en) | Power amplifier bias adjusting circuit and power amplifier chip | |
| US11936340B2 (en) | Dynamically biased power amplification | |
| US20150222230A1 (en) | Output power tuning using pulse position and pulse width control in a pulse position, pulse width modulation amplifier | |
| Tajima et al. | Improved efficiency in outphasing power amplifier by mixing outphasing and amplitude modulation | |
| JP2006148523A (en) | Doherty amplifier | |
| JP5389567B2 (en) | High frequency amplifier and high efficiency method | |
| KR101686351B1 (en) | 3-way doherty power amplifier | |
| Chen et al. | An asynchronous dual switch envelope tracking supply modulator with 86% efficiency | |
| KR20150060173A (en) | Power amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |