CN116913886A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Abstract

The present disclosure provides a semiconductor device, including: a capacitor disposed in a back end of line (BEOL) layer; and an inductor disposed in a Far back end of line (Far-BEOL) layer over the back end of line layer, wherein the inductor is stacked over and electrically connected to the capacitor. The semiconductor device realizes single-chip stacking integration of the capacitor and the inductor, wherein the capacitor and the inductor can occupy the same chip area, so that technical effects of compact design, high integration level, simple manufacturing process and the like can be obtained.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device having a capacitor and an inductor stacked integrated within a single chip.

Background

With the trend toward miniaturization of electronic devices such as cellular phones, tablet computers, etc., there is a demand for miniaturization of power supply systems. Rectifying circuits are an important component in power supply systems. However, the output voltage of the rectifying circuit is not a pure dc voltage, and in order to obtain a relatively ideal dc voltage, a filtering circuit composed of reactive elements (e.g., capacitors and inductors) having an energy storage function is required to filter out the pulsating component in the output voltage of the rectifying circuit to obtain the dc voltage. A common LC filter is a filter circuit formed by a combination of an inductor and a capacitor.

Therefore, achieving compact integration of high-density capacitors and inductors on chip is a necessary trend and means for miniaturization development of power supply systems. However, the fabrication process of high density inductors and capacitors is not easily compatible with conventional CMOS processes.

The above information disclosed in this background section is only for the understanding of the background of the inventive concept and thus may contain information that does not form the prior art.

Disclosure of Invention

In order to solve the above problems existing in the prior art, the present disclosure proposes a novel semiconductor device having a capacitor and an inductor stacked and integrated within a single chip.

According to an aspect of the present disclosure, there is provided a semiconductor device, which may include: a capacitor disposed in a back end of line (BEOL) layer; and an inductor disposed in a Far back end of line (Far-BEOL) layer over the back end of line layer, wherein the inductor is stacked over and electrically connected to the capacitor.

According to embodiments of the present disclosure, the magnetic field direction of the inductor may be parallel to the surface of the semiconductor device.

According to embodiments of the present disclosure, the back end of line layer may be separated from the far back end of line layer by a polyimide film.

According to embodiments of the present disclosure, the capacitor may be a metal-oxide-metal (MOM) capacitor or a metal-insulator-metal (MIM) capacitor disposed in a back-end-of-line layer.

According to embodiments of the present disclosure, the first electrode and the second electrode of the capacitor may be formed to have an interdigital structure.

According to embodiments of the present disclosure, the first electrode and the second electrode of the capacitor may be formed in one or more metal layers.

According to an embodiment of the present disclosure, an oxide selected from at least one of: silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, and aluminum oxide.

According to an embodiment of the present disclosure, an inductor may include: a first metal line; the second metal line is arranged above the first metal line; a dielectric layer disposed between the first metal line and the second metal line; a magnetic core disposed in the dielectric layer and electrically insulated from the first metal line and the second metal line; and a first contact plug disposed in the dielectric layer to connect the first metal line and the second metal line to form a spiral coil of the inductor.

According to embodiments of the present disclosure, the dielectric layer may be formed of polyimide.

According to an embodiment of the present disclosure, one end of the inductor may be electrically connected with the first electrode or the second electrode of the capacitor through the second contact plug, and the second contact plug may be disposed in the far back end process layer.

According to the semiconductor device, the capacitor and the inductor are stacked and integrated on one chip by arranging the capacitor in the back-end process layer and arranging the inductor in the far back-end process layer above the back-end process layer, wherein the capacitor and the inductor can occupy the same chip area, and therefore the technical effects of compact design, high integration level, simple manufacturing process and the like can be achieved.

However, the effects of the present disclosure are not limited to the above-described effects, and various extensions may be made without departing from the spirit and scope of the present disclosure. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the invention.

Fig. 1 is a partial cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

Fig. 2 is a top view illustrating a capacitor included in a semiconductor device according to an embodiment of the present disclosure.

Fig. 3 is a top view illustrating an inductor included in a semiconductor device according to an embodiment of the present disclosure.

Fig. 4A and 4B are schematic circuit diagrams illustrating LC filters according to embodiments of the present disclosure.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments of the present disclosure. As used herein, an "embodiment" is a non-limiting example of an apparatus or method employing one or more of the inventive concepts disclosed herein. It may be evident, however, that the exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, certain features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

Unless otherwise indicated, the described exemplary embodiments should be understood to provide exemplary features of varying detail in some ways that the inventive concept may be practiced. Thus, unless otherwise indicated, features, components, modules, regions, and/or aspects of the embodiments (hereinafter referred to individually or collectively as "elements") may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be construed as any combination of two or more of X only, Y only, Z only, or X, Y and Z, such as XYZ, XYY, YZ and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising," when used in this specification, mean that there are stated features, steps, operations, elements, components, and/or groups thereof, but that the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof is not precluded. It should also be noted that as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not degree terms and, thus, are used to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout. Also, in the drawings, the components are not necessarily drawn to scale and the ratio and size of the components may be exaggerated for clarity of illustration.

Fig. 1 illustrates a partial cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure.

According to embodiments of the present disclosure, the semiconductor device 100 may include a capacitor 101 disposed in a back end of line (BEOL) layer 110 and an inductor 102 disposed in a Far back end of line (Far-BEOL) layer 120 over the BEOL layer 110.

As known to those skilled in the art, integrated circuit fabrication processes may be generally divided into front-end-of-line (FEOL) processes for fabricating devices such as transistors, mainly including isolation, gate structure, source and drain regions, contact holes, etc., and back-end-of-line (BEOL) processes for forming interconnect lines for transmitting electrical signals to the respective devices fabricated by the front-end-of-line processes, mainly including interconnect line interlayer dielectric deposition, metal line formation, extraction pads, etc., according to the order of the process steps performed. In addition, the integrated circuit manufacturing process may further include a Far-back end of line (Far-BEOL) process for providing interconnection between a chip or a chip and a substrate (package), mainly including a formation process of an under-bump-metal (ubm), a re-wiring layer (RDL), a through-silicon via (TSV), etc.

As shown in fig. 1, the semiconductor device 100 may include a front-end process layer 130, a back-end process layer 110, and a far back-end process layer 120 in order from bottom to top according to an embodiment of the present disclosure. According to embodiments of the present disclosure, devices such as transistors may be disposed in the front-end-of-line layer 130, capacitors 101 may be disposed in the back-end-of-line layer 110, and inductors 102 may be disposed in the far-back-end-of-line layer 120.

Further, as shown in fig. 1, the back end of line layer 110 may be separated from the far back end of line layer 120 by a polyimide (polyimide) film 103, in accordance with embodiments of the present disclosure. As shown in fig. 1, according to an embodiment of the present disclosure, an insulating layer 104 may be provided between the polyimide film 103 and the second metal layer M2, wherein a re-wiring layer and a through-silicon via may be provided to achieve electrical extension in a direction parallel to the surface of the semiconductor device 100 and a direction perpendicular to the surface of the semiconductor device 100, respectively.

As shown in fig. 1, according to an embodiment of the present disclosure, an inductor 102 may be stacked over a capacitor 101 and electrically connected to the capacitor 101.

Fig. 2 shows a top view of a capacitor 101 included in the semiconductor device 100 according to an embodiment of the present disclosure.

According to embodiments of the present disclosure, the capacitor 101 may be a metal-oxide-metal (MOM) capacitor disposed in the back-end-of-line layer 110. Although embodiments of the present disclosure are described in fig. 1 and 2 using capacitor 101 as an MOM capacitor as an example, those skilled in the art will recognize that capacitor 101 may also be a metal-insulator-metal (MIM) capacitor disposed in back-end-of-line layer 110, in accordance with alternative embodiments of the present disclosure. The MOM capacitor forms two electrodes with opposite polarities at the same time by using the metal pattern of the same layer, so that the capacitance value can comprise the capacitance formed by the same conductor layer. In contrast, the MIM capacitor is formed by using metal patterns on the same layer or on different layers to form the same electrode, and the capacitance value of the MIM capacitor is mainly formed by capacitors formed by different conductor layers.

As shown in fig. 2, the capacitor 101 may include a first electrode 1011 and a second electrode 1012 formed in the same metal layer (e.g., the first metal layer M1 and the second metal layer M2 shown in fig. 1). That is, the first electrode 1011 and the second electrode 1012 of the capacitor 101 may be formed of metal.

Further, as shown in fig. 2, according to an embodiment of the present disclosure, the first electrode 1011 and the second electrode 1012 of the capacitor 101 may be formed to have comb-shaped structures, respectively, in the same metal layer (e.g., the first metal layer M1 and the second metal layer M2 shown in fig. 1), so that the first electrode 1011 and the second electrode 1012 may together form an inter-digitated structure. According to embodiments of the present disclosure, the polarities of the first electrode 1011 and the second electrode 1012 of the capacitor 101 may be opposite, and the electrode bars of the respective comb structures of the first electrode 1011 and the second electrode 1012 may be oppositely staggered, thereby forming a capacitance between the electrode bars of the first electrode 1011 and the second electrode 1012. According to embodiments of the present disclosure, the capacitance value of capacitor 101 may be equal to the sum of the capacitances formed by the electrode strips. This design of the capacitor 101 helps to increase the capacitance per unit area, thereby helping to reduce the area occupied by the capacitor 101 and thus helping to increase the integration of the semiconductor device 100.

In addition, in order to increase the capacitance value, as shown in fig. 1, the capacitor 101 may have a stacked structure such that the total capacitance thereof may be equal to the sum of the capacitance of the same layer, the capacitance between different layers, and the capacitance between each electrode bar and the via hole. In other words, according to embodiments of the present disclosure, the first electrode 1011 of the capacitor 101 may be formed in one or more metal layers (e.g., the first metal layer M1 and the second metal layer M2 shown in fig. 1), and the second electrode 1012 of the capacitor 101 may also be formed in one or more same metal layers (e.g., the first metal layer M1 and the second metal layer M2 shown in fig. 1). Although the embodiments of the present disclosure are described in fig. 1 by taking the example that the first electrode 1011 and the second electrode 1012 of the capacitor 101 are formed in two metal layers M1 and M2, those skilled in the art will recognize that the first electrode 1011 and the second electrode 1012 of the capacitor 101 may be formed in one metal layer or three or more metal layers according to alternative embodiments of the present disclosure.

According to an embodiment of the present disclosure, an oxide selected from at least one of the following may be filled between the first electrode 1011 and the second electrode 1012 of the capacitor 101: silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, and aluminum oxide as the capacitance medium 1013 of the capacitor 101. Further, when the capacitor 101 has a stacked structure, an insulating layer 1014 is provided between metal layers (e.g., a first metal layer M1 and a second metal layer M2 shown in fig. 1) in which the first electrode 1011 and the second electrode 1012 are formed. Further, according to an embodiment of the present disclosure, when among the first electrode 1011 and the second electrode 1012 formed in different metal layers (for example, the first metal layer M1 and the second metal layer M2 shown in fig. 1), the first electrode 1011 and the second electrode 1012 in the different metal layers may be connected to each other through the metal via 1015. Those skilled in the art will recognize that although in fig. 1 and 2, the metal via 1015 is formed only between the first metal layer M1 and the second metal layer M2 of the electrode portions of the first electrode 1011 and the second electrode 1012 except for the electrode bars (i.e., the interdigital portions), the present disclosure is not limited thereto. According to an embodiment of the present disclosure, the metal via 1015 may also be formed between the first metal layer M1 and the second metal layer M2 of the electrode bars (i.e., the interdigital portions) of the first electrode 1011 and the second electrode 1012, which are alternately arranged.

Fig. 3 is a top view illustrating an inductor 102 included in the semiconductor device 100 according to an embodiment of the present disclosure.

As shown in fig. 1 and 3, according to an embodiment of the present disclosure, the inductor 102 may include a first metal line 1021 patterned in the third metal layer M3 (light-colored line shown in fig. 3) and a second metal line 1022 patterned in the fourth metal layer M4 over the third metal layer M3 (dark-colored line shown in fig. 3). As shown in fig. 3, according to an embodiment of the present disclosure, the first metal line 1021 and the second metal line 1022 of the inductor 102 may be formed in a pattern having a plurality of lines parallel to each other.

Further, as shown in fig. 1, according to an embodiment of the present disclosure, the inductor 102 may include a dielectric layer 1023 disposed between the first metal line 1021 and the second metal line 1022. According to embodiments of the present disclosure, the dielectric layer 1023 may be formed of, for example, polyimide.

Further, as shown in fig. 1 and 3, according to an embodiment of the present disclosure, the inductor 102 may include a magnetic core 1024 disposed in the dielectric layer 1023 and electrically insulated from the first metal line 1021 and the second metal line 1022. According to embodiments of the present disclosure, the magnetic core 1024 may be formed of, for example, cobalt Zirconium Tantalum (CZT), nickel iron (NiFe), or iron nitride (FeN).

Further, as shown in fig. 1 and 3, according to an embodiment of the present disclosure, the inductor 102 may include a first contact plug 1025 disposed in the dielectric layer 1023 to connect the first metal line 1021 and the second metal line 1022, so that a spiral coil of the inductor 102 may be formed by interconnecting the first metal line 1021 and the second metal line 1022 with each other.

As shown in fig. 1 and 3, according to an embodiment of the present disclosure, a magnetic field direction of an inductor may be parallel to a surface of a semiconductor device.

As described above, according to embodiments of the present disclosure, the inductor 102 may be stacked over the capacitor 101. Specifically, as shown in fig. 1, according to an embodiment of the present disclosure, one end of the inductor 102 (e.g., an end of the first metal line 1021 of the inductor 102 disposed in the third metal layer M3 as shown in fig. 1) may be electrically connected with the second electrode 1012 of the capacitor 101 through the second contact plug 1026. As shown in fig. 1, a second contact plug 1026 may also be disposed in the far back end of line layer 120, in accordance with embodiments of the present disclosure.

In fact, according to an embodiment of the present disclosure, either end of the inductor 102 (which may be the end of the first metal line 1021 or the end of the second metal line 1022) disposed in the far back end process layer 120 may be electrically connected to either one of the first electrode 1011 and the second electrode 1012 of the capacitor 101 through the second contact plug 1026, thereby forming different circuit topologies of the LC filter.

Fig. 4A and 4B are schematic circuit diagrams illustrating LC filters according to embodiments of the present disclosure. The LC filter as shown in fig. 4A and 4B may include the capacitor 101 and the inductor 102 described above with reference to fig. 1 to 3.

Fig. 4A shows a circuit diagram of an LC filter used as a low pass filter according to an embodiment of the present disclosure. As shown in fig. 4A, the node N1 may refer to a second contact plug 1026, i.e., a connection point of the capacitor 101 and the inductor 102. The load resistor R may be electrically connected to the node N1 and connected in parallel with the capacitor 101.

Fig. 4B shows a circuit diagram of an LC filter used as a high pass filter according to another embodiment of the present disclosure. As shown in fig. 4B, the node N1 may refer to a second contact plug 1026, i.e., a connection point of the capacitor 101 and the inductor 102. The load resistor R may be electrically connected to the node N1 and connected in parallel with the inductor 102.

According to the semiconductor device, the capacitor and the inductor are stacked and integrated on one chip by arranging the capacitor in the back-end process layer and arranging the inductor in the far back-end process layer above the back-end process layer, wherein the capacitor and the inductor can occupy the same chip area, and therefore the technical effects of compact design, high integration level, simple manufacturing process and the like can be achieved. Furthermore, according to embodiments of the present disclosure, the fabrication process of the inductor and capacitor is easily compatible with conventional CMOS processes.

The foregoing has been presented for purposes of illustration a limited number of possible embodiments of the present disclosure. Although the present disclosure has been described with reference to embodiments thereof, those skilled in the art will appreciate that various modifications and changes can be made to the embodiments of the disclosure without departing from the spirit and scope of the disclosure as disclosed in the appended claims.

Although numerous details are contained herein, these details should not be construed as limitations on the scope of the disclosure or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Claims (10)

1. A semiconductor device, comprising:

a capacitor disposed in the back-end-of-line BEOL layer; and

an inductor disposed in a Far back end of line Far-BEOL layer above the back end of line layer,

wherein the inductor is stacked over and electrically connected to the capacitor.

2. The semiconductor device according to claim 1, wherein a magnetic field direction of the inductor is parallel to a surface of the semiconductor device.

3. The semiconductor device of claim 1, wherein the back end of line layer is separated from the far back end of line layer by a polyimide film.

4. A semiconductor device according to any one of claims 1 to 3, wherein the capacitor is a metal-oxide-metal MOM capacitor or a metal-insulator-metal MIM capacitor provided in the back-end-of-line layer.

5. A semiconductor device according to any one of claims 1 to 3, wherein the first electrode and the second electrode of the capacitor are formed to have an interdigital structure.

6. A semiconductor device according to any one of claims 1 to 3, wherein the first and second electrodes of the capacitor are formed in one or more metal layers.

7. The semiconductor device according to claim 4, wherein an oxide selected from at least one of: silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, and aluminum oxide.

8. A semiconductor device according to any one of claims 1 to 3, wherein the inductor comprises:

a first metal line;

the second metal line is arranged above the first metal line;

a dielectric layer disposed between the first metal line and the second metal line;

a magnetic core disposed in the dielectric layer and electrically insulated from the first metal line and the second metal line; and

and a first contact plug disposed in the dielectric layer to connect the first metal line and the second metal line to form a spiral coil of the inductor.

9. The semiconductor device according to claim 8, wherein the dielectric layer is formed of polyimide.

10. The semiconductor device according to claim 8, wherein one end of the inductor is electrically connected to the first electrode or the second electrode of the capacitor through a second contact plug, and

wherein the second contact plug is arranged in the far back end process layer.