CN116895697A

CN116895697A - Semiconductor device and method of forming the same

Info

Publication number: CN116895697A
Application number: CN202310744230.8A
Authority: CN
Inventors: 庄宗翰; 林志昌; 陈仕承; 张荣宏; 姚茜甯; 庄凯麟; 江国诚; 王志豪
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-06-22
Filing date: 2023-06-21
Publication date: 2023-10-17

Abstract

In an embodiment, a semiconductor device includes: a first nanostructure; a first undoped semiconductor layer contacting a first dummy region of the first nanostructure; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructure; and a first gate structure surrounding the first channel region and the first dummy region of the first nanostructure. Embodiments of the present invention also provide methods of forming semiconductor devices.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present invention relate to semiconductor devices and methods of forming the same.

Background

Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the individual material layers using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum component size decreases, additional problems that should be solved arise.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor device including: a first nanostructure; a first source/drain region adjacent to the first nanostructure, a top surface of the first source/drain region extending over the top surface of the first nanostructure, the first source/drain region contacting a first number of the first nanostructures; a second nanostructure having the same size as the first nanostructure; and a second source/drain region adjacent to the second nanostructure, a top surface of the second source/drain region extending over the top surface of the second nanostructure, the second source/drain region contacting a second number of second nanostructures, the second number of second nanostructures being greater than the first number of first nanostructures.

Further embodiments of the present invention provide a semiconductor device including: a first nanostructure; a first undoped semiconductor layer contacting the first dummy region of the first nanostructure; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructure; and a first gate structure surrounding the first channel region and the first dummy region of the first nanostructure.

Still further embodiments of the present invention provide a method of forming a semiconductor device, the method comprising: patterning a first source/drain recess and a second source/drain recess in a first nanostructure and a second nanostructure, respectively, the first nanostructure having the same dimensions as the second nanostructure; growing a first semiconductor layer and a second semiconductor layer in the first source/drain recess and the second source/drain recess, respectively; increasing the first height of the first semiconductor layer compared to the second height of the second semiconductor layer; and growing a first source/drain region and a second source/drain region over the first semiconductor layer and the second semiconductor layer, respectively.

Drawings

Aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawing figures. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates an example of a nanostructured field effect transistor (nanostructured FET) in a three-dimensional view according to some embodiments.

Fig. 2-26C are views of intermediate stages in the fabrication of a nanostructured FET according to some embodiments.

Fig. 27A-27C are views of nanostructured FETs according to some embodiments.

Fig. 28A-28C are views of nanostructured FETs according to some embodiments.

Fig. 29A-29C are views of nanostructured FETs according to some embodiments.

Fig. 30A-30C are views of nanostructured FETs according to some embodiments.

Fig. 31A-31C are views of nanostructured FETs according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, of different components for use with the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "under …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to various embodiments, the nanostructure FET includes source/drain regions having various heights. Some source/drain regions contact more adjacent nanostructures than others. In this way, devices formed in the first region have a different number of channel regions than devices formed in the second region. Devices in different regions have different effective work functions, which can be advantageous to balance performance and efficiency. Because the effective work function of the device can be controlled based on the height of the source/drain regions, the nanostructures of the device can be of the same size. Accordingly, pattern loading effects can be avoided during processing, which can improve the manufacturing yield of the resulting device.

Fig. 1 illustrates examples of nanostructured FETs (e.g., nanowire FETs, nanoplatelet FETs, multi-bridge channel (MBC) FETs, nanoribbon FETs, full-gate-all-around (GAA) FETs, etc.) according to some embodiments. Fig. 1 is a three-dimensional view in which some components of the nanostructure FET are omitted for clarity of illustration.

The nanostructure FET includes a nanostructure 66 (e.g., a nanoplatelet, nanowire, etc.) located over a fin 62 on a substrate 50 (e.g., a semiconductor substrate), where the nanostructure 66 is a semiconductor component that serves as a channel region for the nanostructure FET. Isolation regions 70, such as Shallow Trench Isolation (STI) regions, are disposed between adjacent fins 62, and the fins 62 may overlie adjacent isolation regions 70 and protrude from between adjacent isolation regions 70. The nanostructures 66 are disposed over adjacent isolation regions 70 and between adjacent isolation regions 70. Although isolation region 70 is depicted/shown as being separate from substrate 50, as used herein, the term "substrate" may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fin 62 is shown as a single continuous material with the substrate 50, the bottom portion of the fin 62 and/or the substrate 50 may comprise a single material or multiple materials. In this case, the fin 62 refers to a portion extending between adjacent isolation regions 70.

Gate dielectric 132 is located over the top surface of fin 62 and along the top, sidewalls, and bottom surfaces of nanostructure 66. A gate electrode 134 is located over the gate dielectric 132. Source/drain regions 118 are disposed on fin 62 at opposite sides of gate dielectric 132 and gate electrode 134. The source/drain regions 118 may be referred to as sources or drains, individually or collectively depending on the context. An interlayer dielectric (ILD) 124 is formed over the source/drain regions 118. Contacts (described later) to the source/drain regions 118 will be formed through the ILD 124. The source/drain regions 118 may be shared between individual nanostructures 66. For example, adjacent source/drain regions 118 may be electrically connected, such as by epitaxially growing the source/drain regions 118 in combination, or by coupling the source/drain regions 118 to the same contacts.

Fig. 1 further shows the reference cross section used in the following figures. The cross-section A-A' is along the longitudinal axis of the fin 62 of the nanostructure FET and in the direction of current flow, for example, between the source/drain regions 118 of the nanostructure FET. Section B-B 'is perpendicular to section A-A' and extends through the source/drain regions 118 of the nanostructure FET. Section C-C 'is parallel to section B-B' and is along the longitudinal axis of gate electrode 134. For clarity, subsequent figures refer to these reference sections.

Some embodiments discussed herein are discussed in the context of a nanostructured FET formed using a back gate process. In other embodiments, a gate-first process may be used. Moreover, some embodiments contemplate aspects used in planar devices such as planar FETs or in fin field effect transistors (finfets) in place of or in combination with nanostructure FETs. For example, a FinFET may include a semiconductor fin on a substrate, where the semiconductor fin is a semiconductor feature that serves as a channel region of the FinFET. Similarly, a planar FET may include a substrate, the planar portion of which is a semiconductor component that serves as the channel region of the planar FET.

Fig. 2-26C are views of intermediate stages in the fabrication of a nanostructured FET according to some embodiments. Fig. 2, 3, 4, 5, 6 and 7 are three-dimensional views showing a three-dimensional view similar to fig. 1. Fig. 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 20B, 21A, 22A, 23A, 24A, 25A and 26A show cross-sectional views along similar cross-sections as the reference section A-A' in fig. 1. Fig. 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18, 19, 21B, 22B, 23B, 24B, 25B, and 26B show cross-sectional views along a similar cross-section as the reference section B-B' in fig. 1. Fig. 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, 21C, 22C, 23C, 24C, 25C and 26C show cross-sectional views along a similar cross-section to the reference section C-C' in fig. 1.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, the SOI substrate is a layer of semiconductor material formed on an insulator layer. For example, the insulator layer may be a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multi-layer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 50 may comprise silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof.

The substrate 50 has an N-type region 50N and a P-type region 50P. The N-type region 50N may be used to form an N-type device, such as an NMOS transistor, e.g., an N-type nanostructured FET, while the P-type region 50P may be used to form a P-type device, such as a PMOS transistor, e.g., a P-type nanostructured FET. The N-type region 50N may (or may not) be physically separated from the P-type region 50P (not separately shown), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the N-type region 50N and the P-type region 50P. Although one N-type region 50N and one P-type region 50P are shown, any number of N-type regions 50N and P-type regions 50P may be provided.

A multi-layer stack 52 is formed over the substrate 50. The multi-layer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layer 54 is formed of a first semiconductor material, and the second semiconductor layer 56 is formed of a second semiconductor material. The semiconductor materials may each be selected from candidate semiconductor materials of the substrate 50.

In the illustrated embodiment, as described in more detail later, the first semiconductor layer 54 will be removed and the second semiconductor layer 56 will be patterned to form a channel region of the nanostructure FET in both the N-type region 50N and the P-type region 50P. In such embodiments, the channel regions in both the N-type region 50N and the P-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously. The first semiconductor layer 54 is a dummy layer that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material having a high etching selectivity with respect to the etching of the second semiconductor layer 56, for example, silicon germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

In another embodiment (not separately shown), the first semiconductor layer 54 will be patterned to form a channel region for the nanostructure FET in one region (e.g., P-type region 50P), while the second semiconductor layer 56 will be patterned to form a channel region for the nanostructure FET in another region (e.g., N-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., si _x Ge _1-x Wherein x may be in the range of 0 to 1), pure germanium, a group III-V compound semiconductor, a group II-VI compound semiconductor, and the like. The second semiconductor material of the second semiconductor layer 56 may be a material suitable for an n-type device, such as silicon, silicon carbide, a group III-V compound semiconductor, a group II-VI compound semiconductor, or the like. The etching of the first semiconductor material and the second semiconductor material relative to each other may have a high etch selectivity, such that the first semiconductor material may be removed in the N-type region 50NThe semiconductor layer 54 is not significantly removed from the second semiconductor layer 56, and the second semiconductor layer 56 may be removed from the P-type region 50P without significantly removing the first semiconductor layer 54.

The multi-layer stack 52 is shown to include three first semiconductor layers 54 and three second semiconductor layers 56. It should be appreciated that the multi-layer stack 52 may include any number of first and second semiconductor layers 54, 56. Each layer of the multi-layer stack 52 may be grown by a process such as Vapor Phase Epitaxy (VPE) or Molecular Beam Epitaxy (MBE), deposited by a process such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), or the like. In some embodiments, some layers of the multi-layer stack 52 are formed thinner than other layers of the multi-layer stack 52.

In fig. 3, fins 62 are formed in substrate 50 and nanostructures 64, 66 are formed in multilayer stack 52. In some embodiments, nanostructures 64, 66 and fins 62 may be formed in multilayer stack 52 and substrate 50, respectively, by etching trenches in multilayer stack 52 and substrate 50. The etching may be any acceptable etching process, such as Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. The formation of the nanostructures 64, 66 by etching the multilayer stack 52 may further define a first nanostructure 64 from the first semiconductor layer 54 and a second nanostructure 66 from the second semiconductor layer 56.

The fins 62 and nanostructures 64, 66 may be patterned by any suitable method. For example, the fin 62 and the nanostructures 64, 66 may be patterned using one or more photolithographic processes including a double patterning process or a multiple patterning process. Typically, a double patterning process or multiple patterning process combines lithography and self-aligned processes, allowing creation of patterns with, for example, smaller pitches than those obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed beside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins 62 and nanostructures 64, 66.

Fin 62 is shown as having substantially equal widths in both N-type region 50N and P-type region 50P. In some embodiments, the width of fin 62 in N-type region 50N may be greater than or less than the width of fin 62 in P-type region 50P. Furthermore, while each of the fins 62 and/or nanostructures 64, 66 are shown as always having a constant width, in other embodiments, the fins 62 and/or nanostructures 64, 66 may have tapered sidewalls such that the width of each of the fins 62 and/or nanostructures 64, 66 continuously increases in a direction toward the substrate 50. In such embodiments, each of the nanostructures 64, 66 may have a different width and be trapezoidal in shape.

In fig. 4, an insulating material 68 is formed over the substrate 50 and between adjacent fins 62 and adjacent nanostructures 64, 66. The insulating material 68 may be an oxide such as silicon oxide, nitride, or the like, or a combination thereof, and the insulating material 68 may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In some embodiments, insulating material 68 comprises silicon oxide formed by an FCVD process. Once the insulating material 68 is formed, an annealing process may be performed. Although insulating material 68 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not separately shown) may first be formed along the surfaces of the substrate 50, fin 62, and nanostructures 64, 66. Thereafter, a filler material, such as one of the insulating materials described hereinabove, may be formed over the liner.

An insulating material 68 may be deposited over the fin 62 and the nanostructures 64, 66 such that excess insulating material 68 covers the nanostructures 64 and 66. A removal process is then applied to the insulating material 68 to remove excess insulating material 68 over the nanostructures 64, 66. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like may be utilized. The planarization process exposes the nanostructures 64, 66 such that after the planarization process is completed, the insulating material 68 and the top surfaces of the nanostructures 64, 66 are flush.

In fig. 5, insulating material 68 is recessed to form STI regions 70.STI region 70 is adjacent fin 62. The insulating material 68 is recessed such that the nanostructures 64, 66 and/or upper portions of the fins 62 protrude from between adjacent STI regions 70. The nanostructures 64, 66 and/or the upper portion of the fin 62 are located above the STI region 70. Further, the top surface of STI region 70 may have a planar surface, a convex surface, a concave surface (such as a dish), or a combination thereof, as shown. The top surface of STI region 70 may be formed flat, raised, and/or recessed by a suitable etch. STI regions 70 may be recessed using an acceptable etching process, such as an etching process selective to the material of insulating material 68 (e.g., etching the material of insulating material 68 at a faster rate than the material of fin 62 and nanostructures 64, 66). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) may be used.

The process described hereinabove is just one example of how the fin 62 and nanostructures 64, 66 may be formed. In some embodiments, a mask and epitaxial growth process may be used to form the fins 62 and/or nanostructures 64, 66. For example, a dielectric layer may be formed over the top surface of the substrate 50, and trenches through the dielectric layer may be etched to expose the underlying substrate 50. An epitaxial structure may be epitaxially grown in the trench and the dielectric layer may be recessed such that the epitaxial structure protrudes from the dielectric layer to form fin 62 and/or nanostructures 64, 66. The epitaxial structure may comprise alternating semiconductor materials as previously described, such as a first semiconductor material and a second semiconductor material. In some embodiments where the epitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid previous and/or subsequent implants, however in situ and implant doping may be used together.

Furthermore, suitable wells (not separately shown) may be formed in fin 62, nanostructures 64, 66, and/or STI region 70. In embodiments with different well types, different implantation steps of N-type region 50N and P-type region 50P may be implemented using photoresist or other masks (not separately shown). For example, the N-type region 50N and the p-type region may be formed The fin 62, nanostructures 64, 66 and STI region 70 in 50P form a photoresist. The photoresist is patterned to expose the P-type region 50P. The photoresist may be formed by using a spin-coating technique, and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an N-type dopant implantation is performed in the P-type region 50P, and the photoresist may act as a mask to substantially prevent the N-type dopant from being implanted into the N-type region 50N. The n-type dopant may be implanted into the region at a concentration of 10 ¹³ Atoms/cm ³ To 10 ¹⁴ Atoms/cm ³ Phosphorus, arsenic, antimony, etc. in the range of (a). After implantation, the photoresist is removed, such as by an acceptable ashing process.

After or before implantation of the P-type region 50P, a photoresist or other mask (not separately shown) is formed over the fins 62, nanostructures 64, 66, and STI regions 70 in the P-type region 50P and N-type region 50N. The photoresist is patterned to expose the N-type region 50N. The photoresist may be formed by using a spin-coating technique, and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a P-type dopant implantation may be performed in the N-type region 50N, and the photoresist may act as a mask to substantially prevent the P-type dopant from being implanted into the P-type region 50P. The p-type dopant may be implanted into the region at a concentration of 10 ¹³ Atoms/cm ³ To 10 ¹⁴ Atoms/cm ³ Boron, boron fluoride, indium, etc. within the range of (2). After implantation, the photoresist may be removed, such as by an acceptable ashing process.

After implantation of N-type region 50N and P-type region 50P, an anneal may be performed to repair the implant damage and activate the implanted P-type and/or N-type dopants. In some embodiments, the growth material of the epitaxial fin may be doped in situ during growth, which may avoid implantation, however in situ doping and implant doping may be used together.

In fig. 6, a dummy dielectric layer 72 is formed over the fin 62 and/or the nanostructures 64, 66. The dummy dielectric layer 72 may be formed of silicon oxide, silicon nitride, combinations thereof, or the like, which may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 74 is formed over the dummy dielectric layer 72, and a mask layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 may be deposited over the dummy dielectric layer 72 and then the dummy gate layer 74 is planarized, such as by CMP. The dummy gate layer 74 may be formed of a conductive or nonconductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polycrystalline silicon), polycrystalline silicon germanium (polycrystalline silicon germanium), metal nitride, metal silicide, metal oxide, and metal. The material of dummy gate layer 74 may be deposited by CVD, physical Vapor Deposition (PVD), sputter deposition, or other techniques for depositing the selected material. The dummy gate layer 74 may be formed of other materials having a high etch selectivity with respect to the etching of the insulating material (e.g., STI region 70 and/or dummy dielectric layer 72). A mask layer 76 may be deposited over the dummy gate layer 74. The mask layer 76 may be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the N-type region 50N and the P-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 overlies the STI region 70 such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the STI region 70. In another embodiment, the dummy dielectric layer 72 covers only the fin 62 and the nanostructures 64, 66.

In fig. 7, mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 may then be transferred to dummy gate layer 74 and dummy dielectric layer 72 to form dummy gate 84 and dummy dielectric 82, respectively. The dummy gate 84 overlies the respective channel regions of the nanostructures 64, 66. The pattern of the mask 86 may be used to physically separate each dummy gate 84 from an adjacent dummy gate 84. The dummy gate 84 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding fin 62. After patterning, the mask 86 may optionally be removed, such as by any acceptable etching technique.

Fig. 8A through 26C illustrate various additional steps in the fabrication of the embodiment device. Fig. 8A to 17C and fig. 21A to 26C show components in either of the N-type region 50N and the P-type region 50P. For example, the illustrated structure may be applicable to both N-type region 50N and P-type region 50P. The differences in the structure of N-type region 50N and P-type region 50P, if any, are explained in the text attached to each figure.

Further, fig. 8A to 26C show components in the high-efficiency region 50E and the high-speed region 50S. The devices formed in the high-efficiency region 50E will have a smaller effective work function, while the devices formed in the high-speed region 50S will have a larger effective work function. Accordingly, the devices formed in the high-efficiency region 50E have greater power efficiency than the devices formed in the high-speed region 50S, and the devices formed in the high-speed region 50S have higher performance than the devices formed in the high-efficiency region 50E. The same logic cells ("hybrid logic cells") of an integrated circuit die may include both high-efficiency and high-speed devices. The use of hybrid logic cells may allow for more flexibility in considering performance, power efficiency, and cell area when designing integrated circuits. Each of the high-efficiency region 50E and the high-speed region 50S may include devices from both the N-type region 50N and the P-type region 50P. In other words, the high-efficiency region 50E and the high-speed region 50S may each include an n-type device and a p-type device.

The nanostructures 64, 66 in the high-efficiency region 50E have the same dimensions (e.g., width and thickness) as the nanostructures 64, 66 in the high-speed region 50S. Accordingly, pattern loading effects such as during an etching process can be avoided. In addition, a processing window may be added. And thus the manufacturing yield of the resulting device can be improved.

In fig. 8A-8C, a spacer layer 90 is conformally formed over the nanostructures 64, 66 and STI region 70, over mask 86 (if present), dummy gate 84, dummy dielectric 82, nanostructures 64, 66, and exposed sidewalls of fin 62. Spacer layer 90 may be formed from one or more dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like, which may be formed by deposition processes such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like. Other insulating materials formed by any acceptable process may be used. The spacer layer 90 will then be etched to form spacers.

In fig. 9A-9C, spacer layer 90 is patterned to form gate spacers 92 and fin spacers 94. Any acceptable etching process, such as dry etching, wet etching, or the like, or combinations thereof, may be performed to pattern the spacer layer 90. The etching may be anisotropic. When the spacer layer 90 is etched, the spacer layer 90 has portions left on the sidewalls of the dummy gate 84 (thus forming gate spacers 92) and has portions left on the sidewalls of the fins 62 and/or nanostructures 64, 66 (thus forming fin spacers 94). After etching, fin spacers 94 and/or gate spacers 92 may have straight sidewalls or may have curved sidewalls. In addition, STI regions 70 may also be etched when patterning spacer layer 90. The etching may recess portions of STI regions 70 between fins 62.

As described above, since the nanostructures 64, 66 in the high-efficiency region 50E have the same dimensions (e.g., width and thickness) as the nanostructures 64, 66 in the high-speed region 50S, the pattern loading effect can be avoided. As a result, the fin spacers 94 in the high-efficiency region 50E may have the same dimensions (e.g., width and thickness) as the fin spacers 94 in the high-speed region 50S. In some embodiments, fin spacers 94 in high-efficiency region 50E and high-speed region 50S have a height in the range of 15nm to 30nm and have a width in the range of 5nm to 10 nm.

In addition, implantation may be performed for lightly doped source/drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the implantation for wells described previously, a mask such as photoresist may be formed over the N-type region 50N while exposing the P-type region 50P, and dopants of the appropriate type (e.g., P-type) may be implanted into the exposed fin 62 and/or nanostructures 64, 66 in the P-type region 50P. The mask may then be removed. Subsequently, a mask, such as photoresist, may be formed over the P-type region 50P while exposing the N-type region 50N, and an appropriate type (e.g., N-type) of dopant may be implanted into the exposed fin 62 and/or nanostructures 64, 66 in the N-type region 50N. The mask may then be removed. The n-type dopant may be any of the n-type dopants previously discussed, and the p-type dopant may be any of the p-type dopants previously described. Lightly doped source/drain regions may have a thickness of 10 ¹⁵ Atoms/cm ³ To 10 ¹⁹ Atoms/cm ³ RangeDopant concentration within. Annealing may be used to repair implant damage and activate the implanted dopants.

It should be noted that the previous disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, a different sequence of steps may be utilized, additional spacers may be formed and removed, and so forth. In addition, the n-type device and the p-type device may be formed using different structures and steps.

Source/drain recesses 96 (including source/drain recesses 96E in high-efficiency region 50E and source/drain recesses 96S in high-speed region 50S) are patterned in fin 62, nanostructures 64, 66, and substrate 50. Epitaxial source/drain regions will then be formed in the source/drain recesses 96. Source/drain recesses 96 may extend through nanostructures 64, 66 and into substrate 50. In some embodiments, fin 62 may be etched such that the bottom surface of source/drain recess 96 is disposed below the top surface of STI region 70. The source/drain recesses 96 may be formed by etching the fin 62, the nanostructures 64, 66, and the substrate 50 using an anisotropic etching process (such as RIE, NBE, etc.). During the etching process for forming the source/drain recesses 96, the gate spacers 92 and dummy gates 84 mask portions of the fin 62, nanostructures 64, 66, and substrate 50. A single etching process or multiple etching processes may be used to etch each layer of nanostructures 64, 66 and/or fin 62. After the source/drain recesses 96 reach the desired depth, a timed etch process may be used to stop etching of the source/drain recesses 96.

In fig. 10A-10C, an internal spacer 98 is formed on sidewalls of the remaining portion of the first nanostructure 64 (e.g., sidewalls exposed by the source/drain recesses 96). As will be described in more detail later, then source/drain regions will be formed in the source/drain recesses 96, and then the first nanostructures 64 will be replaced by corresponding gate structures. The internal spacers 98 act as isolation features between subsequently formed source/drain regions and subsequently formed gate structures. In addition, the internal spacers 98 may be used to prevent damage to subsequently formed source/drain regions from a subsequent etching process, such as a subsequent etching process for removing the first nanostructures 64.

As an example of forming the internal spacers 98, the source/drain recesses 96 may be laterally expanded. In particular, portions of the sidewalls of the first nanostructures 64 exposed by the source/drain recesses 96 may be recessed to form sidewall recesses. Although the sidewalls of the first nanostructures 64 are shown as being straight, the sidewalls may be concave or convex. The sidewalls may be recessed by any acceptable etching process, such as an etching process that is selective to the material of the first nanostructures 64 (e.g., etching the material of the first nanostructures 64 selectively at a faster rate than the material of the second nanostructures 66). The etching may be isotropic. For example, when the second nanostructures 66 are formed of silicon and the first nanostructures 64 are formed of silicon germanium, the etching process may be using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH) ₄ OH), and the like. In another embodiment, the etching process may be a dry etching using a fluorine-based gas, such as Hydrogen Fluoride (HF) gas. In some embodiments, the same etching process may be performed consecutively to form the source/drain recesses 96 and recess the sidewalls of the first nanostructures 64. Then, the inner spacers 98 may be formed by conformally forming an insulating material in the source/drain recesses 96, and then etching the insulating material. The insulating material may be silicon nitride or silicon oxynitride, but any suitable material may be utilized, such as a low dielectric constant (low-k) material having a dielectric constant less than about 3.5. The insulating material may be formed by a deposition process such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etching such as RIE, NBE, or the like.

Although the outer sidewalls of the inner spacers 98 are shown as being planar with the sidewalls of the second nanostructures 66, the outer sidewalls of the inner spacers 98 may extend beyond the sidewalls of the second nanostructures 66 or be recessed from the sidewalls of the second nanostructures 66. In other words, the inner spacer 98 may partially fill, completely fill, or overfill the sidewall recess. In addition, although the sidewalls of the inner spacer 98 are shown as straight, the sidewalls of the inner spacer 98 may be concave or convex.

In fig. 11A to 11C, a semiconductor layer 102 (including the semiconductor layer 102E in the high-efficiency region 50E and the semiconductor layer 102S in the high-speed region 50S) is formed in the source/drain groove 96. The semiconductor layer 102 may be formed of a semiconductor material selected from candidate semiconductor materials of the substrate 50, which may be grown by an epitaxial growth process such as Vapor Phase Epitaxy (VPE), molecular Beam Epitaxy (MBE), or the like. The semiconductor layer 102 may be an undoped semiconductor layer. In some embodiments, the semiconductor layer 102 is formed of undoped silicon or undoped silicon germanium. In this embodiment, the top surface of the semiconductor layer 102 is a planar top surface. In another embodiment (described later), the top surface of the semiconductor layer 102 is a raised top surface. The semiconductor layer 102 provides a non-recessed (e.g., planar or raised) top surface upon which subsequently formed spacers will be formed.

Semiconductor layer 102 may be epitaxially grown by flowing a semiconductor-containing precursor and an etchant-containing precursor in source/drain recesses 96. The semiconductor-containing precursor may be a silicon-containing precursor, such as silane, e.g., monosilane (SiH) ₄ ) Dichlorosilane (H) ₂ SiCl ₂ ) Disilane (Si) ₂ H ₆ ) Etc.; germanium-containing precursors, e.g. germane (GeH) ₄ ) Etc.; combinations thereof, and the like. The etchant-containing precursor may be a chlorine-containing precursor, such as hydrogen chloride (HCl) gas, chlorine (Cl) ₂ ) Gas, etc. Flowing the etchant-containing precursor at a fast flow rate may cause the semiconductor layer 102 to be grown in a more bottom-up manner than in a lateral manner. In some embodiments, the semiconductor-containing precursor is flowed at a flow rate in the range of 0sccm to 1000sccm and the etchant-containing precursor is flowed at a flow rate in the range of 0sccm to 1000 sccm. In this way, semiconductor layer 102 may be grown from fin 62 rather than from nanostructures 66. In some embodiments, the epitaxial growth is performed at a temperature in the range of 500 ℃ to 900 ℃ and at a pressure in the range of 1 torr to 150 torr. The semiconductor layer 102 may be formed to have a flat or convex top surface by controlling the flow rate of the etchant-containing precursor during deposition.

The semiconductor layer 102 may be partially filled and completely filledFilling or overfilling portions of the source/drain recesses 96 in the fin 62. At this processing step, semiconductor layer 102 may be in contact with the sidewalls of some of the internal spacers 98, but semiconductor layer 102 is not in contact with the sidewalls of nanostructures 66. Height H of semiconductor layer 102 ₁ Less than the distance between fin 62 and lower nanostructure 66. In some embodiments, the height H of the semiconductor layer 102 ₁ In the range of 10nm to 15 nm. The timed epitaxial growth process may be used to stop the growth of the semiconductor layer 102 after the semiconductor layer 102 reaches a desired height. At this processing step, the semiconductor layer 102E has the same height H as the semiconductor layer 102S ₁ . As described in more detail later, an additional epitaxial growth process will be performed to increase the height of the semiconductor layer 102E compared to the semiconductor layer 102S.

In fig. 12A-12C, a mask layer 104 is conformally formed over semiconductor layer 102, fin spacers 94, gate spacers 92, STI regions 70 and mask 86 (if present) or dummy gate 84, and sidewalls of nanostructures 66 and inner spacers 98 in source/drain recesses 96. The mask layer 104 may be formed of a hard mask material such as aluminum oxide, silicon carbide, titanium nitride, or the like, which may be formed by a deposition process such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or the like. The mask layer 104 is formed in both the high-efficiency region 50E and the high-speed region 50S.

In fig. 13A-13C, the mask layer 104 is patterned to remove portions of the mask layer 104 in the high-efficiency region 50E, thereby forming a mask 106. The mask layer 104 may be patterned with any acceptable etching process that is selective to the mask layer 104 (e.g., selectively etching the material of the mask layer 104 at a faster rate than the material of the semiconductor layer 102). The etching process may be isotropic. Photoresist 108 may be formed over semiconductor layer 102, fin spacers 94, gate spacers 92, STI regions 70 and mask 86 (if present) or dummy gate 84 in high-efficiency region 50E and high-speed region 50S. Photoresist 108 is patterned to expose high efficiency region 50E. The photoresist 108 may be formed by using a spin-coating technique, and the photoresist 108 may be patterned using an acceptable photolithography technique. Once the photoresist 108 is patterned, the mask layer 104 may be etched in the high-efficiency region 50E, and the photoresist 108 may act as an etch mask to substantially prevent etching of the mask layer 104 in the high-speed region 50S. After etching, the photoresist 108 is removed, for example, by an acceptable ashing process. The mask 106 covers the semiconductor layer 102S and exposes the semiconductor layer 102E.

In fig. 14A to 14C, the height of the semiconductor layer 102E is increased as compared with the semiconductor layer 102S. The height of the semiconductor layer 102E may be increased by repeating the epitaxial growth process for forming the semiconductor layer 102 previously described, thereby growing more semiconductor material of the semiconductor layer 102E. In performing the additional epitaxial growth of the semiconductor layer 102E, the mask 106 covers the semiconductor layer 102S during the growth period to substantially prevent the additional epitaxial growth of the semiconductor layer 102S.

At this processing step, the semiconductor layer 102E is in contact with the sidewalls of some of the nanostructures 66. Semiconductor layer 102E covers some of the sidewalls of nanostructures 66, while semiconductor layer 102S may not cover the sidewalls of nanostructures 66. Height H of semiconductor layer 102E ₂ Height H greater than semiconductor layer 102S ₁ . In some embodiments, the height H of the semiconductor layer 102E ₂ In the range of 25nm to 32 nm. The timed epitaxial growth process may be used to stop additional growth of the semiconductor layer 102E after the semiconductor layer 102E reaches a desired height.

The height H of the semiconductor layer 102E is increased compared to the depth of the source/drain recesses 96S ₂ The depth of the source/drain recesses 96E is reduced. The depth of the source/drain recesses 96S is greater than the depth of the source/drain recesses 96E. As described in greater detail later, the source/drain recesses 96E having a smaller depth than the source/drain recesses 96S allow the source/drain regions subsequently formed in the high-efficiency region 50E to couple to fewer nanostructures 66 than the source/drain regions subsequently formed in the high-speed region 50S.

In fig. 15A to 15C, the mask 106 is removed to expose the semiconductor layer 102S. The mask 106 may be removed using any acceptable etching process that is selective to the mask 106 (e.g., selectively etching the material of the mask 106 at a faster rate than the material of the semiconductor layer 102).The etching process may be isotropic. For example, when the mask 106 is formed of aluminum oxide, the etching process may be using ammonium hydroxide (NH ₄ OH), dilute hydrofluoric acid (dHF), and the like.

In fig. 16A to 16C, a bottom spacer 110 (including a bottom spacer 110E in the high-efficiency region 50E and a bottom spacer 110S in the high-speed region 50S) is formed on the semiconductor layer 102 (including the semiconductor layer 102E and the semiconductor layer 102S). In addition, bottom spacers 112 may also be formed on other horizontal surfaces, such as on portions of STI regions 70 between source/drain recesses 96. In some embodiments in which the semiconductor layer 102S is not in contact with the sidewalls of the nanostructures 66, the bottom spacer 110S is disposed below the top surface of the lower interior spacer 98 (e.g., the interior spacer 98 disposed closest to the substrate 50). Further, bottom spacer 110E may be disposed above the top surface of lower inner spacer 98. The bottom spacers 110, 112 may be formed by conformally forming one or more dielectric materials over the semiconductor layer 102, fin spacers 94, gate spacers 92, STI regions 70 and mask 86 (if present) or dummy gate 84, and then subsequently etching the dielectric material. Acceptable dielectric materials may include silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, silicon carbonitride, silicon oxides, aluminum oxides, hafnium oxides, and the like, which may be formed by deposition processes such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like. Any acceptable etching process (such as dry etching, wet etching, etc., or combinations thereof) may be performed to pattern the dielectric material. The etching may be anisotropic. The vertical portions of the dielectric material are etched away. When etched, the dielectric material has horizontal portions (thereby forming bottom spacers 112 and/or bottom spacers 110) that remain on the top surfaces of STI regions 70 and/or semiconductor layer 102. The bottom spacer 110 may be thin so as not to occupy too much space in the source/drain recess 96. In some embodiments, the thickness of the bottom spacer 110 is in the range of 3nm to 5 nm.

In fig. 17A-17C, epitaxial source/drain regions 118 (including epitaxial source/drain regions 118S in high-speed region 50S and epitaxial source/drain regions 118E in high-efficiency region 50E) are formed in source/drain recesses 96. In some embodiments, the epitaxial source/drain regions 118 stress the corresponding channel regions of the second nanostructures 66, thereby improving performance. Epitaxial source/drain regions 118 are formed in source/drain recesses 96 such that each dummy gate 84 is disposed between an adjacent pair of corresponding epitaxial source/drain regions 118. In some embodiments, gate spacers 92 are used to separate the epitaxial source/drain regions 118 from the dummy gate 84, and the internal spacers 98 are used to separate the epitaxial drain/source regions 118 from the nanostructures 64 by an appropriate lateral distance so that the epitaxial source/drain regions 118 are not shorted to the gates of the resulting nanostructure FET that is subsequently formed.

The epitaxial source/drain regions 118 in the N-type region 50N may be formed by an epitaxial process (described later). The epitaxial source/drain regions 118 may comprise any acceptable material suitable for an n-type nanostructured FET. For example, if the second nanostructures 66 are formed of silicon, the epitaxial source/drain regions 118 may comprise a material that imparts a tensile strain to the second nanostructures 66, such as silicon, silicon carbide, phosphorus doped silicon carbide, silicon phosphide, and the like. The epitaxial source/drain regions 118 in the N-type region 50N may be referred to as "N-type source/drain regions". The epitaxial source/drain regions 118 may have surfaces raised from the respective upper surfaces of the nanostructures 64, 66, and may have facets.

The epitaxial source/drain regions 118 in the P-type region 50P may be formed by an epitaxial process (described later). The epitaxial source/drain regions 118 may comprise any acceptable material suitable for p-type nanostructured FETs. For example, if the second nanostructure 66 is formed of silicon, the epitaxial source/drain regions 118 may comprise a material that applies compressive strain to the first nanostructure 64, such as silicon germanium, boron doped silicon germanium, germanium tin, and the like. The epitaxial source/drain regions 118 in the P-type region 50P may be referred to as "P-type source/drain regions". The epitaxial source/drain regions 118 may have surfaces raised from the respective surfaces of the nanostructures 64, 66, and may have facets.

Epitaxial sourceThe pole/drain regions 118, nanostructures 64, 66, and/or fin 62 may be implanted with dopants to form source/drain regions, similar to the process of forming lightly doped source/drain regions and subsequent annealing as previously discussed. The source/drain regions may have 10 ¹⁹ Atoms/cm ³ And 10 ²¹ Atoms/cm ³ Dopant concentration between. The n-type and/or p-type dopants of the source/drain regions may be any of the dopants previously discussed. In some embodiments, the epitaxial source/drain regions 118 may be doped in-situ during growth.

As a result of the epitaxial process used to form the epitaxial source/drain regions 118, the upper surface of the epitaxial source/drain regions 118 has facets that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, these facets cause adjacent epitaxial source/drain regions 118 of the same nanostructure FET to merge, as shown in fig. 1. In other embodiments, adjacent epitaxial source/drain regions 118 remain separated after the epitaxial process is completed, as shown in fig. 17B. In the illustrated embodiment, fin spacers 94 are formed on the top surfaces of STI regions 70, thereby blocking epitaxial growth. In some other embodiments, fin spacers 94 may cover portions of the sidewalls of fin 62 and/or nanostructures 64, 66, thereby further blocking epitaxial growth. In another embodiment, the spacer etch used to form gate spacers 92 is adjusted so as not to form fin spacers 94, so as to allow epitaxial source/drain regions 118 to extend to the surface of STI regions 70.

Epitaxial source/drain regions 118 (including epitaxial source/drain regions 118S in high-speed region 50S and epitaxial source/drain regions 118E in high-efficiency region 50E) extend over the top surface of nanostructures 66. As a result, the top surfaces of the epitaxial source/drain regions 118 are disposed farther from the substrate 50 than the top surfaces of adjacent nanostructures 66. In some embodiments, the top surface of epitaxial source/drain regions 118S is substantially coplanar (within process variations) with the top surface of epitaxial source/drain regions 1180E.

The bottom spacer 110 covers the semiconductor layer 102 so that the epitaxial source/drain regions 118 do not grow from the semiconductor layer 102. Corresponding toThe epitaxial source/drain regions 118 are electrically isolated from the semiconductor layer 102. The semiconductor layer 102 and bottom spacers 110 underlie the epitaxial source/drain regions 118. The bottom spacer 110 is located between the semiconductor layer 102 and the epitaxial source/drain regions 118. Further, because the source/drain recesses 96S are deeper than the source/drain recesses 96E, the epitaxial source/drain regions 118S in the high-speed region 50S have a greater height than the epitaxial source/drain regions 118E in the high-efficiency region 50E. Height H of epitaxial source/drain regions 118S ₃ Height H greater than epitaxial source/drain regions 118E ₄ . In some embodiments, the height H of the epitaxial source/drain regions 118S ₃ In the range of 40nm to 60nm, and the height H of the epitaxial source/drain regions 118E ₄ In the range of 25nm to 45 nm.

Since the epitaxial source/drain regions 118S have a greater height than the epitaxial source/drain regions 118E, the epitaxial source/drain regions 118S contact a greater number of sidewalls of the nanostructures 66 than the epitaxial source/drain regions 118E. In this example, each epitaxial source/drain region 118S contacts a sidewall of three nanostructures 66 under the dummy gate 84, while each epitaxial source/drain region 118E contacts a sidewall of two nanostructures under the dummy gate 84. Accordingly, the devices formed in the high-speed region 50S have more channel regions than the devices formed in the high-efficiency region 50E. As a result, the devices in the high-speed region 50S have a greater effective work function than the devices in the high-efficiency region 50E, even though the nanostructures 64, 66 of the devices in the high-speed region 50S have the same dimensions (e.g., width and thickness) as the nanostructures 64, 66 of the devices in the high-efficiency region 50E. Thus, the hybrid logic cell can be formed while avoiding the pattern loading effect. The nanostructures 64, 66 that are located below the channel region and do not contact the epitaxial source/drain regions 118 are unused dummy regions. The subsequently formed gate structure will surround the channel region and the dummy region of the nanostructure.

In this embodiment, the epitaxial source/drain regions 118 extend across the entire top surface of the bottom spacer 110. In another embodiment (described later), a void is formed under the epitaxial source/drain regions 118 such that a portion of the top surface of the bottom spacer 110 is exposed to the void. When the epitaxial source/drain regions 118 merge before the lower portions of the source/drain recesses 96 are completely filled, voids may be formed during epitaxial growth.

Fig. 18-19 illustrate steps of forming epitaxial source/drain regions 118 in source/drain recesses 96. The formation of epitaxial source/drain regions 118E in N-type region 50N, the formation of extrinsic pole/drain regions 118S in N-type region 50N, the formation of epitaxial source/drain regions 118E in P-type region 50P, and the formation of epitaxial source/drain regions 118S in P-type region 50P are shown.

In fig. 18, a mask 114 is formed to mask the P-type region 50P. For example, a mask layer may be formed over bottom spacers 110, fin spacers 94, gate spacers 92, STI regions 70, and mask 86 (if present) or dummy gate 84 in N-type region 50N and P-type region 50P. The mask layer is patterned to expose the N-type region 50N. The mask layer may be formed of a hard mask material such as aluminum oxide, silicon carbide, titanium nitride, or the like, which may be formed by a deposition process such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or the like. The mask layer may be patterned using acceptable photolithography and etching techniques to form the mask 114. In other embodiments, another type of mask, such as photoresist, may be utilized.

Epitaxial source/drain regions 118 are then epitaxially grown in source/drain recesses 96 in N-type region 50N. Mask 114 substantially prevents growth in P-type region 50P. An epitaxial process for forming the epitaxial source/drain regions 118 is performed such that the epitaxial source/drain regions 118 are selectively grown from the semiconductor features (e.g., the nanostructures 66) but not from the dielectric features (e.g., the bottom spacers 110). Epitaxial source/drain regions 118 may be grown by flowing a semiconductor-containing precursor, an etchant-containing precursor, and a dopant-containing precursor in source/drain recesses 96. The semiconductor-containing precursor and the etchant-containing precursor may be selected from the same semiconductor-containing precursor and etchant-containing precursor, respectively, used to grow the semiconductor layer 102, or the semiconductor-containing precursor and etchant-containing precursor may include different precursors. Before containing dopantThe body contains a suitable dopant for the n-type source/drain regions, such as an arsenic-containing precursor (such as arsenic trioxide (AsH) ₃ ) A phosphorus-containing precursor (such as phosphorus (P) ₂ H ₆ ) Or Phosphane (PH) ₃ ) And the like. When growing the epitaxial source/drain regions 118, the etchant-containing precursor may be flowed at a slower flow rate than when growing the semiconductor layer 102, which may cause the epitaxial source/drain regions 118 to grow in a more lateral manner than in a bottom-up manner. In some embodiments, the semiconductor-containing precursor is flowed at a flow rate in the range of 0sccm to 1000sccm, the etchant-containing precursor is flowed at a flow rate in the range of 0sccm to 1000sccm, and the dopant-containing precursor is flowed at a flow rate in the range of 0sccm to 1000 sccm. The epitaxial process of epitaxial source/drain regions 118 may have a faster lateral growth rate and a slower bottom-up growth rate than the epitaxial process of semiconductor layer 102. In this way, epitaxial source/drain regions 118 may be laterally grown from nanostructures 66. In some embodiments, the epitaxial growth is performed at a temperature in the range of 400 ℃ to 900 ℃ and a pressure in the range of 1 torr to 500 torr.

After epitaxial source/drain regions 118 are grown in N-type region 50N, mask 114 is removed. Mask 114 may be removed by any acceptable etching process that is selective to mask 114 (e.g., selectively etching the material of mask 114 at a faster rate than the material of epitaxial source/drain regions 118). The etching process may be isotropic. For example, when the mask 114 is formed of aluminum oxide, the etching process may be using ammonium hydroxide (NH ₄ OH), dilute hydrofluoric acid (dHF), and the like.

In fig. 19, a mask 116 is formed to mask the N-type region 50N. For example, a mask layer may be formed over the epitaxial source/drain regions 118, bottom spacers 110, fin spacers 94, gate spacers 92, STI regions 70, and mask 86 (if present), or dummy gate 84 in P-type region 50P and N-type region 50N. The mask layer is patterned to expose the P-type region 50P. The mask layer may be formed of a hard mask material such as aluminum oxide, silicon carbide, titanium nitride, or the like, which may be formed by a deposition process such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or the like. The mask layer may be patterned using acceptable photolithography and etching techniques to form mask 116. In other embodiments, another type of mask, such as photoresist, may be utilized.

Epitaxial source/drain regions 118 are then epitaxially grown in source/drain recesses 96 in P-type region 50P. Mask 116 substantially prevents growth in N-type region 50N. An epitaxial process for forming the epitaxial source/drain regions 118 is performed such that the epitaxial source/drain regions 118 are selectively grown from the semiconductor features (e.g., the nanostructures 66) but not from the dielectric features (e.g., the bottom spacers 110). Epitaxial source/drain regions 118 may be grown by flowing a semiconductor-containing precursor, an etchant-containing precursor, and a dopant-containing precursor in source/drain recesses 96. The semiconductor-containing precursor and the etchant-containing precursor may be selected from the same semiconductor-containing precursor and etchant-containing precursor, respectively, used to grow the semiconductor layer 102, or the semiconductor-containing precursor and etchant-containing precursor may include different precursors. The dopant-containing precursor comprises a suitable dopant for the p-type source/drain regions, such as a boron-containing precursor, such as diborane (B ₂ H ₆ ) Borane (BH) ₃ ) Etc. When growing the epitaxial source/drain regions 118, the etchant-containing precursor may be flowed at a slower flow rate than when growing the semiconductor layer 102, which may cause the epitaxial source/drain regions 118 to grow in a more lateral manner than in a bottom-up manner. In some embodiments, the semiconductor-containing precursor is flowed at a flow rate in the range of 0sccm to 1000sccm, the etchant-containing precursor is flowed at a flow rate in the range of 0sccm to 1000sccm, and the dopant-containing precursor is flowed at a flow rate in the range of 0sccm to 1000 sccm. The epitaxial process of epitaxial source/drain regions 118 may have a faster lateral growth rate and a slower bottom-up growth rate than the epitaxial process of semiconductor layer 102. In this way, epitaxial source/drain regions 118 may be laterally grown from nanostructures 66. In some embodiments, the epitaxial growth is performed at a temperature in the range of 400 ℃ to 900 ℃ and a pressure in the range of 1 torr to 150 torr.

After epitaxial source/drain regions 118 are grown in P-type region 50P, mask 116 is removed. Any acceptable etch selective to mask 116 may be usedAn etching process (e.g., selectively etching the material of mask 116 at a faster rate than the material of epitaxial source/drain regions 118) removes mask 116. The etching process may be isotropic. For example, when the mask 116 is formed of aluminum oxide, the etching process may be using ammonium hydroxide (NH ₄ OH), dilute hydrofluoric acid (dHF), and the like.

The epitaxial source/drain regions 118 may include one or more layers of semiconductor material. For example, the epitaxial source/drain regions 118 may include a liner layer, a main layer, and a finish layer (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Each of the cushion layer, the main layer, and the finishing layer may be formed of different semiconductor materials, and may be doped to different dopant concentrations. In some embodiments, the backing layer may have a dopant concentration that is less than the main layer and greater than the finish layer. In embodiments where the epitaxial source/drain regions 118 comprise three layers of semiconductor material, a liner layer may be grown in the source/drain recesses 96, a main layer may be grown over the liner layer, and a finish layer may be grown over the main layer. Any number of layers of semiconductor material may be used for epitaxial source/drain regions 118. In some embodiments, the epitaxial source/drain regions 118 in the N-type region 50N include a liner layer 118A on the nanostructures 66 and a fill layer 118C on the liner layer 118A, as shown in fig. 20A-20B. In some embodiments, the epitaxial source/drain regions 118 in the P-type region 50P include a liner layer 118A on the nanostructure 66, a liner layer 118B on the liner layer 118A, and a fill layer 118C on the liner layer 118B, as shown in fig. 20A-20B.

In fig. 21A-21C, a first ILD 124 is deposited over epitaxial source/drain regions 118, bottom spacers 112, fin spacers 94, gate spacers 92, and mask 86 (if present) or dummy gate 84. The first ILD 124 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma Enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), and the like. Other insulating materials formed by any acceptable process may be used.

In some embodiments, a Contact Etch Stop Layer (CESL) 122 is formed between the first ILD 124 and the epitaxial source/drain regions 118, the bottom spacers 112, the fin spacers 94, the gate spacers 92, and the mask 86 (if present) or dummy gate 84. The CESL 122 may be formed of a dielectric material having a high etch selectivity with respect to the etching of the first ILD 124, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the CESL 122 may be formed by any suitable deposition process, such as CVD, ALD, etc.

In fig. 22A-22C, a removal process is performed to bring the top surface of the first ILD 124 flush with the top surfaces of the gate spacers 92 and mask 86 (if present) or dummy gate 84. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like may be utilized. The planarization process may also remove the mask 86 on the dummy gate 84, as well as portions of the gate spacers 92 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the first ILD 124, gate spacers 92, and mask 86 (if present) or dummy gate 84 are substantially coplanar (within process variations). Accordingly, the top surface of mask 86 (if present) or dummy gate 84 is exposed through first ILD 124.

In fig. 23A-23C, mask 86 (if present) and dummy gate 84 are removed in one or more etching steps such that recess 126 is formed between gate spacers 92. Portions of dummy dielectric 82 in recess 126 are also removed. In some embodiments, dummy gate 84 and dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of the dummy gate 84 at a faster rate than the material of the first ILD 124 or the gate spacer 92. Each recess 126 exposes a portion of the nanostructures 64, 66 and/or overlies a portion of the nanostructures 64, 66, which portion of the nanostructures 64, 66 serves as a channel region in a subsequently completed nanostructure FET. Portions of the nanostructures 64, 66 that serve as channel regions are disposed between adjacent pairs of epitaxial source/drain regions 118. Portions of the nanostructures 64, 66 that are dummy regions are disposed between adjacent pairs of the semiconductor layer 102. During removal, the dummy dielectric 82 may act as an etch stop layer when the dummy gate 84 is etched. The dummy dielectric 82 may then be removed after the dummy gate 84 is removed.

The remaining portions of the first nanostructures 64 are then removed to form openings 128 in the regions between the second nanostructures 66. The remainder of the first nanostructures 64 may be removed by any acceptable etching process that selectively etches the material of the first nanostructures 64 at a faster rate than the material of the second nanostructures 66. The etching may be isotropic. For example, when the first nanostructures 64 are formed of silicon germanium and the second nanostructures 66 are formed of silicon, the etching process may be using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH) ₄ OH), and the like. In some embodiments, a trimming process (not separately shown) is performed to reduce the thickness of the exposed portions of the second nanostructures 66 and expand the openings 128.

In fig. 24A to 24C, a gate dielectric 132 and a gate electrode 134 are formed for the replacement gate. Each respective pair of gate dielectric 132 and gate electrode 134 may be collectively referred to as a "gate structure". Each gate structure surrounds the channel region of the nanostructure 66 such that the gate structure extends along the sidewalls, bottom surface, and top surface of the nanostructure 66. Some gate structures also extend along the sidewalls and/or top surface of fin 62.

Gate dielectric 132 includes sidewalls and/or a top surface disposed on fin 62; disposed on the top, sidewalls, and bottom surfaces of the channel region of the nanostructure 66; disposed on the sidewalls of the inner spacers 98 adjacent to the epitaxial source/drain regions 118; and one or more gate dielectric layers disposed on sidewalls of gate spacers 92. The gate dielectric 132 may be formed of an oxide (such as silicon oxide or metal oxide), a silicate (such as metal silicate), a combination thereof, a multilayer thereof, or the like. Additionally or alternatively, the gate dielectric 132 may be formed of a high-k dielectric material (e.g., a dielectric material having a k value greater than about 7.0), such as a silicate or metal oxide of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric material of gate dielectric 132 may be formed by Molecular Beam Deposition (MBD), ALD, PECVD, or the like. Although a single layer of gate dielectric 132 is shown, the gate dielectric 132 may include any number of interface layers and any number of main layers. For example, gate dielectric 132 may include an interfacial layer and an overlying high-k dielectric layer.

The gate electrode 134 includes one or more gate electrode layers disposed over the gate dielectric 132. The gate electrode 134 may be formed of a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multilayers thereof, or the like. Although a single layer gate electrode 134 is shown, the gate electrode 134 may include any number of work function modifying layers, any number of barrier layers, any number of glue layers, and filler materials.

As an example of forming a gate structure, one or more gate dielectric layers may be deposited in recess 126 and opening 128. A gate dielectric layer may also be deposited on top surfaces of the first ILD 124, cesl 122 and gate spacers 92. One or more gate electrode layers may then be deposited over the gate dielectric layer and in the remainder of recess 126 and opening 128. A removal process may then be performed to remove the excess portions of the gate dielectric layer and gate electrode layer that are over the top surfaces of the first ILD 124, CESL 122, and gate spacers 92. In some embodiments, a planarization process, such as Chemical Mechanical Polishing (CMP), an etch back process, combinations thereof, and the like, may be utilized. After the removal process, the gate dielectric layer has portions left in the recess 126 and the opening 128 (thus forming the gate dielectric 132). After the removal process, the gate electrode layer has portions left in the recess 126 and the opening 128 (thus forming the gate electrode 134). When a planarization process is utilized, the top surfaces of gate spacer 92, CESL 122, first ILD 124, gate dielectric 132, and gate electrode 134 are coplanar (within process variations).

In fig. 25A-25C, a second ILD 144 is deposited over the gate spacer 92, CESL 122, first ILD 124, gate dielectric 132, and gate electrode 134. In some embodiments, the second ILD 144 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 144 is formed of a dielectric material such as PSG, BSG, BPSG, USG, which may be formed by any suitable deposition process such as CVD, PECVD, or the like.

In some embodiments, an Etch Stop Layer (ESL) 142 is formed between the second ILD 144 and the gate spacers 92, CESL 122, first ILD 124, gate dielectric 132, and gate electrode 134. The ESL 142 may be formed of a dielectric material having a high etch selectivity relative to the etch of the second ILD 144, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the ESL 142 may be formed by any suitable deposition process, such as CVD, ALD, etc.

In fig. 26A-26C, gate contacts 152 and source/drain contacts 154 are formed to contact the gate electrode 134 and the epitaxial source/drain regions 118, respectively. The gate contact 152 may be physically and electrically coupled to the gate electrode 134. Source/drain contacts 154 may be physically and electrically coupled to epitaxial source/drain regions 118.

As an example of forming the gate contact 152 and the source/drain contact 154, an opening for the gate contact 152 is formed through the second ILD 144 and ESL 142, and an opening for the source/drain contact 154 is formed through the second IL 144, ESL 142, the first ILD 124, and the CESL 122. Acceptable photolithography and etching techniques may be used to form the openings. A liner (not separately shown) such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 144. The remaining liner and conductive material form gate contacts 152 and source/drain contacts 154 in the openings. The gate contact 152 and the source/drain contact 154 may be formed in different processes, or the gate contact 152 and the source/drain contact 154 may be formed in the same process. Although the gate contact 152 and the source/drain contact 154 are shown as being formed in the same cross-section, it should be understood that each of the gate contact 152 and the source/drain contact 154 may be formed in different cross-sections, which may avoid shorting of the contacts.

Optionally, a metal semiconductor alloy region 156 is formed at the interface between the epitaxial source/drain regions 118 and the source/drain contacts 154. The metal semiconductor alloy region 156 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a germanide region formed of a metal silicide and a metal germanide, etc. The metal semiconductor alloy region 156 may be formed by depositing a metal in the opening for the source/drain contact 154 before the material of the source/drain contact 154, and then performing a thermal annealing process. The metal may be any metal capable of reacting with the semiconductor material (e.g., silicon carbide, silicon germanium, etc.) of the epitaxial source/drain regions 118 to form a low resistance metal semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be formed by a deposition process such as ALD, CVD, PVD. After the thermal annealing process, a cleaning process, such as a wet clean, may be performed to remove any remaining metal from the openings for the source/drain contacts 154 (e.g., from the surface of the metal semiconductor alloy regions 156). The material of the source/drain contacts 154 may then be formed on the metal semiconductor alloy regions 156.

Embodiments may realize advantages. Forming the semiconductor layer 102E to a greater height than the semiconductor layer 102S allows the epitaxial source/drain regions 118E to have a smaller height than the epitaxial source/drain regions 118S. In this way, the devices formed in the high-speed region 50S have a different number of channel regions than the devices formed in the high-efficiency region 50E. Devices in different regions have different effective work functions, which can be advantageous to balance performance and efficiency. Because the effective work function of the device can be controlled based on the height of the epitaxial source/drain regions 118, the nanostructures 66 of the device can be the same size. Accordingly, pattern loading effects can be avoided during processing, which can improve the manufacturing yield of the resulting device.

Fig. 27A-27C are views of nanostructure FETs according to some embodiments. Fig. 27A-27C are additional views of the nanostructure FET of fig. 26A-26C. Fig. 27A shows a cross-sectional view of the high efficiency region 50E along a cross-section similar to the reference section A-A' in fig. 1. Fig. 27B shows a sectional view of the high-speed region 50S along a section similar to the reference section A-A' in fig. 1. Fig. 27C shows a cross-sectional view of the high-efficiency region 50E and the high-speed region 50S in a similar cross-section to the reference section B-B' in fig. 1.

Fig. 28A-28C are views of nanostructured FETs according to some embodiments. This embodiment is similar to the embodiment of fig. 27A to 27C except that the top surface of the semiconductor layer 102 is a convex top surface. As a result, the epitaxial source/drain regions 118 have a recessed bottom surface.

Fig. 29A-29C are views of nanostructure FETs according to some embodiments. This embodiment is similar to the embodiment of fig. 27A-27C except that a void 162 is formed beneath the epitaxial source/drain regions 118. As a result, portions of the top surface of the bottom spacer 110 are exposed to the void 162. Although not shown separately, it should be understood that in this embodiment, the top surface of the semiconductor layer 102 may also be a raised top surface.

Fig. 30A-30C are views of a nanostructured FET according to some embodiments. This embodiment is similar to the embodiment of fig. 27A-27C except that the bottom spacer 110 is omitted from underneath the p-type epitaxial source/drain regions 118S. The bottom spacer 110 may be formed in other regions than the high-speed region 50S in the p-type region. By masking those regions during the process of forming the bottom spacers 110, the bottom spacers 110 may be omitted from the desired regions. The p-type epitaxial source/drain regions 118S may be grown from the semiconductor layer 102S (in addition to grown from the nanostructures 66). Although not shown separately, it should be understood that in this embodiment, the top surface of the semiconductor layer 102 may also be a raised top surface.

Fig. 31A-31C are views of nanostructured FETs according to some embodiments. This embodiment is similar to the embodiment of fig. 27A-27C, except that the semiconductor layer 102S is also located on the sidewalls of some of the nanostructures 66. By forming the semiconductor layer 102S to a greater height than in the embodiment of fig. 27A to 27C, the semiconductor layer 102S is formed on the sidewalls of some of the nanostructures 66. Semiconductor layer 102E still has a greater height than semiconductor layer 102S such that epitaxial source/drain regions 118S contact a greater number of sidewalls of nanostructures 66 than epitaxial source/drain regions 1180E. Semiconductor layer 102E contacts a first subset of nanostructures 66 and semiconductor layer 102S contacts a second subset of nanostructures 66. Although not shown separately, it should be understood that in this embodiment, the top surface of the semiconductor layer 102 may also be a raised top surface.

In an embodiment, a device includes: a first nanostructure; a first source/drain region adjacent to the first nanostructure, a top surface of the first source/drain region extending above the top surface of the first nanostructure, the first source/drain region contacting the first number of first nanostructures; a second nanostructure having the same size as the first nanostructure; and a second source/drain region adjacent to the second nanostructure, a top surface of the second source/drain region extending over the top surface of the second nanostructure, the second source/drain region contacting a second number of second nanostructures, the second number of second nanostructures being greater than the first number of first nanostructures. In some embodiments of the device, the first source/drain region has a first height, the second source/drain region has a second height, and the second height is greater than the first height. In some embodiments of the device, the first source/drain region contacts a subset of the first nanostructures and the second source/drain region contacts each of the second nanostructures. In some embodiments of the device, the first source/drain region contacts a first subset of the first nanostructures and the second source/drain region contacts a second subset of the second nanostructures. In some embodiments, the device further comprises: a first undoped semiconductor layer under the first source/drain region; and a second undoped semiconductor layer under the second source/drain region. In some embodiments of the device, the first undoped semiconductor layer has a first height, the second undoped semiconductor has a second height, and the first height is greater than the second height. In some embodiments of the device, the first undoped semiconductor layer contacts a subset of the first nanostructures and the second undoped semiconductor layer does not contact the second nanostructures. In some embodiments of the device, the first undoped semiconductor layer contacts a first subset of the first nanostructures and the second undoped semiconductor layer contacts a second subset of the second nanostructures.

In an embodiment, a device includes: a first nanostructure; a first undoped semiconductor layer contacting the first dummy region of the first nanostructure; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructure; and a first gate structure surrounding the first channel region and the first dummy region of the first nanostructure. In some embodiments of the device, the first undoped semiconductor layer has a raised top surface. In some embodiments of the device, the first undoped semiconductor layer has a planar top surface. In some embodiments, the device further comprises: a second nanostructure having the same size as the first nanostructure; a second undoped semiconductor layer adjacent to the second nanostructure, the second undoped semiconductor layer having a smaller height than the first undoped semiconductor layer; a second spacer on the second undoped semiconductor layer; a second source/drain region on the second spacer, the second source/drain region contacting a second channel region of the second nanostructure; and a second gate structure surrounding a second channel region of the second nanostructure.

In an embodiment, a method includes: patterning a first source/drain recess and a second source/drain recess in a first nanostructure and a second nanostructure, respectively, the first nanostructure having the same dimensions as the second nanostructure; growing a first semiconductor layer and a second semiconductor layer in the first source/drain recess and the second source/drain recess, respectively; increasing the first height of the first semiconductor layer compared to the second height of the second semiconductor layer; and growing a first source/drain region and a second source/drain region over the first semiconductor layer and the second semiconductor layer, respectively. In some embodiments of the method, the first and second source/drain regions are grown at a faster lateral growth rate than the first and second semiconductor layers. In some embodiments of the method, the first and second source/drain regions are grown at a slower bottom-up growth rate than the first and second semiconductor layers. In some embodiments, the method further comprises: first and second spacers are formed on the first and second semiconductor layers, respectively, and first and second source/drain regions are formed on the first and second spacers, respectively. In some embodiments, the method further comprises: a first spacer is formed on the first semiconductor layer, a first source/drain region is grown on the first spacer, and a second source/drain region is grown from the second semiconductor layer. In some embodiments of the method, growing the first semiconductor layer and the second semiconductor layer comprises growing a semiconductor material, and increasing the first height of the first semiconductor layer comprises: forming a mask covering the second semiconductor layer, the mask exposing the first semiconductor layer; growing more semiconductor material from the first semiconductor layer while the second semiconductor layer is covered by the mask; and removing the mask from the second semiconductor layer. In some embodiments of the method, the semiconductor material is undoped silicon. In some embodiments of the method, the semiconductor material is undoped silicon germanium.

The foregoing outlines features of a drop-on embodiment so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising:

a first nanostructure;

a first source/drain region adjacent to the first nanostructure, a top surface of the first source/drain region extending over a top surface of the first nanostructure, the first source/drain region contacting a first number of the first nanostructures;

a second nanostructure having the same dimensions as the first nanostructure; and

a second source/drain region adjacent to the second nanostructure, a top surface of the second source/drain region extending over a top surface of the second nanostructure, the second source/drain region contacting a second number of the second nanostructures, the second number of the second nanostructures being greater than the first number of the first nanostructures.

2. The semiconductor device of claim 1, wherein the first source/drain region has a first height, the second source/drain region has a second height, and the second height is greater than the first height.

3. The semiconductor device of claim 1, wherein the first source/drain region contacts a subset of the first nanostructures and the second source/drain region contacts each of the second nanostructures.

4. The semiconductor device of claim 1, wherein the first source/drain region contacts a first subset of the first nanostructures and the second source/drain region contacts a second subset of the second nanostructures.

5. The semiconductor device of claim 1, further comprising:

a first undoped semiconductor layer under the first source/drain region; and

a second undoped semiconductor layer located under the second source/drain region.

6. The semiconductor device of claim 5, wherein the first undoped semiconductor layer has a first height, the second undoped semiconductor layer has a second height, and the first height is greater than the second height.

7. The semiconductor device of claim 5, wherein the first undoped semiconductor layer contacts a subset of the first nanostructures and the second undoped semiconductor layer does not contact the second nanostructures.

8. The semiconductor device of claim 5, wherein the first undoped semiconductor layer contacts a first subset of the first nanostructures and the second undoped semiconductor layer contacts a second subset of the second nanostructures.

9. A semiconductor device, comprising:

a first nanostructure;

a first undoped semiconductor layer contacting a first dummy region of the first nanostructure;

a first spacer on the first undoped semiconductor layer;

a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructure; and

a first gate structure surrounding the first channel region and the first dummy region of the first nanostructure.

10. A method of forming a semiconductor device, comprising:

patterning a first source/drain recess and a second source/drain recess in a first nanostructure and a second nanostructure, respectively, the first nanostructure having the same dimensions as the second nanostructure;

Growing a first semiconductor layer and a second semiconductor layer in the first source/drain recess and the second source/drain recess, respectively;

increasing a first height of the first semiconductor layer compared to a second height of the second semiconductor layer; and

first and second source/drain regions are grown over the first and second semiconductor layers, respectively.